Array substrate, manufacturing method thereof and display device

Abstract

The application discloses an array substrate, a preparation method thereof and a display device. The array substrate comprises a substrate, an active layer and a plurality of metal layers. The active layer and the plurality of metal layers form a pixel circuit. A first end of a driving transistor is connected with a second end of a compensation transistor, a first end of the compensation transistor is connected with a second end of a first reset transistor, and a second end of the driving transistor is connected with a second end of a first light-emitting control transistor. In the active layer in one pixel circuit, the first end of the driving transistor and the second end of the compensation transistor and the second end of the first light-emitting control transistor are arranged at intervals to form a first active part, a second active part and a third active part arranged at intervals. The driving transistor is located in the first active part, the compensation transistor and the first reset transistor are located in the second active part, and the first light-emitting control transistor is located in the third active part. The above scheme can improve the problem of leakage current and improve the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a method for fabricating the same, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the display performance of current OLED display products needs improvement. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide an array substrate and its fabrication method, as well as a display device, to improve leakage current and enhance display performance.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing an array substrate, including a substrate, an active layer, and multiple metal layers; the active layer is disposed on one side of the substrate; the multiple metal layers are disposed on the side of the active layer away from the substrate; the active layer and the multiple metal layers form a pixel circuit, the pixel circuit including a driving transistor, a compensation transistor, a first reset transistor, and a first light-emitting control transistor, wherein the subthreshold swing of the driving transistor is greater than the subthreshold swing of the compensation transistor and the first reset transistor; a first terminal of the driving transistor is electrically connected to a second terminal of the compensation transistor, a first terminal of the compensation transistor is electrically connected to a second terminal of the first reset transistor, and a second terminal of the driving transistor is electrically connected to a second terminal of the first light-emitting control transistor; in the active layer of the pixel circuit, the first terminal of the driving transistor is spaced apart from the second terminal of the compensation transistor and the second terminal of the first light-emitting control transistor to form a spaced-apart first active portion, a second active portion, and a third active portion, wherein the driving transistor is located in the first active portion, the compensation transistor and the first reset transistor are located in the second active portion, and the first light-emitting control transistor is located in the third active portion.

[0006] Preferably, the plurality of metal layers includes a first metal layer, and at least one insulating layer is provided between the first metal layer and the active layer. The at least one insulating layer is provided with a first via, a second via, and a third via. The first via connects the first metal layer and a first terminal of the driving transistor in the active layer. The second via connects the first metal layer and a second terminal of the first reset transistor in the active layer. The third via connects the first metal layer and a second terminal of the first light-emitting control transistor in the active layer. The first metal layer fills at least a portion of the first via, the second via, and the third via, so that the first active portion is electrically connected to the second active portion and the third active portion.

[0007] Preferably, the at least one insulating layer includes a first insulating layer stacked on the side of the first metal layer facing the substrate, the first insulating layer including a first sub-insulating layer and a second sub-insulating layer stacked on the side of the first sub-insulating layer facing the substrate, the second sub-insulating layer being located on the side of the first sub-insulating layer facing the substrate, and the first via, the second via, and the third via all penetrating the first sub-insulating layer and the second sub-insulating layer; wherein, the first sub-insulating layer is formed after the dehydrogenation treatment of the active layer, and the second sub-insulating layer is formed before the dehydrogenation treatment.

[0008] Preferably, the at least one insulating layer is further provided with a plurality of fourth vias and a plurality of fifth vias, the first metal layer fills at least part of the fourth vias and the fifth vias, the fourth vias connect the first metal layer and the first active part, and the fifth vias connect the first metal layer and the second active part / the third active part.

[0009] Preferably, the active layer is made of a semiconductor material.

[0010] Preferably, the active layer is made of polycrystalline silicon.

[0011] To solve the above-mentioned technical problems, another technical solution adopted in this application is: a method for fabricating an array substrate, comprising: forming an active layer on one side of a substrate, the active layer including a first active portion, a second active portion, and a third active portion disposed at intervals; forming a plurality of metal layers on the side of the active layer away from the substrate, the active layer and the multiple metal layers forming a pixel circuit, the pixel circuit including a driving transistor, a compensation transistor, a first reset transistor, and a first light-emitting control transistor, wherein the subthreshold swing of the driving transistor is greater than the subthreshold swing of the compensation transistor and the first reset transistor; wherein, in the active layer, the first end of the driving transistor is located in the first active portion, the second end of the compensation transistor is located in the second active portion, and the second end of the first light-emitting control transistor is located in the third active portion; the first end of the driving transistor is electrically connected to the second end of the compensation transistor, the first end of the compensation transistor is electrically connected to the second end of the first reset transistor, and the second end of the driving transistor is electrically connected to the second end of the first light-emitting control transistor.

[0012] Preferably, the step of forming multiple metal layers on the side of the active layer away from the substrate further includes: forming multiple insulating layers on one side of the active layer, the insulating layers including a first insulating layer; forming a first via, a second via, and a third via on the insulating layer, wherein the first via connects to a first terminal of the driving transistor in the active layer, the second via connects to a second terminal of the first reset transistor in the active layer, and the third via connects to a second terminal of the first light-emitting control transistor; forming a first metal layer on the side of the first insulating layer away from the substrate, wherein the first metal layer fills at least a portion of the first via, the second via, and the third via, so that the first active portion is electrically connected to the second active portion and the third active portion.

[0013] Preferably, the step of forming at least one insulating layer on one side of the active layer, the insulating layer including a first insulating layer, includes: forming a second sub-insulating layer; hydrogenating the second sub-insulating layer; exposing the first terminal of the driving transistor in the active layer through a first temporary via, and dehydrogenating the active layer; forming a first sub-insulating layer on the side of the second sub-insulating layer opposite to the substrate to form the first insulating layer; and forming the first via, the second via, and the third via on the first insulating layer.

[0014] Preferably, after the step of hydrogenating the second sub-insulating layer, the method further includes: exposing the first active portion through a second temporary via; after the step of forming a first sub-insulating layer on the side of the second sub-insulating layer away from the substrate to form the first insulating layer, the method further includes: forming a plurality of fourth vias and a plurality of fifth vias on the first insulating layer, the fourth vias communicating with the first active portion, and the fifth vias communicating with the second active portion / the third active portion; the step of forming a first metal layer on the side of the first insulating layer away from the substrate further includes: the first metal layer filling at least a portion of the fourth vias and the fifth vias, such that the first metal layer is electrically connected to the second active portion / the third active portion.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a display device, including the array substrate described in any embodiment or the array substrate prepared by the preparation method described in any embodiment.

[0016] The beneficial effects of this application are as follows: Unlike the prior art, the first active portion of the active layer in the array substrate of this application is physically disconnected from the second and third active portions. The movement path of hydrogen ions generated during the hydrogen removal process is blocked. During the hydrogen removal process of the driving transistor, free hydrogen ions are difficult to move from the surface of the first active portion across the disconnection to the surface of the second and third active portions. This greatly avoids hydrogen ion intrusion into the interface between the second active portion and the third insulating layer where the compensation transistor and the first reset transistor are located, thereby ensuring the device quality of the compensation transistor and the first reset transistor, ensuring that the compensation transistor and the first reset transistor have small leakage current, and making the display panel have a good display effect. Attached Figure Description

[0017] Figure 1 This is a top view of one embodiment of the array substrate of this application;

[0018] Figure 2 This is a cross-sectional view of one embodiment of the array substrate of this application;

[0019] Figure 3 This is a schematic diagram of the pixel circuit P of this application;

[0020] Figure 4 yes Figure 1 Sectional view along the middle AA direction;

[0021] Figure 5a This is a top view of the active layer in this application;

[0022] Figure 5b This is a top view of the array substrate after the third metal layer has been formed;

[0023] Figure 5c This is a top view of the array substrate after the second metal layer has been formed;

[0024] Figure 5d This is a top view of the array substrate of this application after the first temporary via and the second temporary via are formed;

[0025] Figure 5e This is a top view of the array substrate before the formation of the first metal layer in this application;

[0026] Figure 6 This is a schematic flowchart of one embodiment of the preparation method of this application;

[0027] Figure 7 This is a flowchart illustrating step S120 of this application;

[0028] Figure 8 This is a flowchart illustrating step S121 of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description is provided with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] Existing display devices typically suffer from poor display quality when displaying black levels and screen flicker, severely impacting their display performance. The inventors' research revealed the following reasons for these problems: Existing display devices generally use thin-film transistors (TFTs) made of low-temperature polysilicon (LTPS) to drive light-emitting devices in their pixel circuits. Due to manufacturing limitations, LTPS TFTs generate significant leakage current. This affects the voltage retention of the storage capacitors in the pixel circuit, thus impacting the display's performance when displaying black levels, reducing contrast, and affecting display quality. Furthermore, the high leakage current from LTPS TFTs exacerbates screen flicker, severely impacting the display's overall performance.

[0031] In view of this, please provide an array substrate 100, see reference. Figure 1The array substrate 100 includes a substrate (not shown), an active layer 21, and multiple metal layers (not shown). The active layer 21 is disposed on one side of the substrate; the multiple metal layers are disposed on the side of the active layer 21 facing away from the substrate; the active layer 21 and the multiple metal layers form a pixel circuit P, which includes a driving transistor T1, a compensation transistor T3, a first reset transistor T4, and a first light-emitting control transistor T6, wherein the subthreshold swing (SS) of the driving transistor T1 is greater than the subthreshold swing of the compensation transistor T3 and the first reset transistor T4.

[0032] Specifically, see Figure 2 The substrate 10 includes a substrate 11 and a buffer layer 12 stacked together. The buffer layer 12 has an array layer 20 on the side facing away from the substrate 11. The array layer 20 includes an active layer 21, multiple insulating layers (not shown), and multiple metal layers (not shown). Specifically, the array layer 20 includes an active layer 21, a third insulating layer 22, a third metal layer 23, a second insulating layer 24, a second metal layer 25, a first insulating layer 26, and a first metal layer 27 stacked sequentially. In the thin-film transistor (TFT) made of low-temperature polycrystalline silicon (PTS), the active layer 21 can be made of polycrystalline silicon (P-Si) or other semiconductor materials. The gate 231 of the TFT is located on the third metal layer 23 and is insulated from the active layer 21 by the third insulating layer 22. The source 271 and drain 272 of the TFT are located on the first metal layer 27 and are insulated from the active layer 21 by the first insulating layer 26, the second insulating layer 24, and the third insulating layer 22. An insulating layer is provided with a via 261 that passes through the first insulating layer 26, the second insulating layer 24 and the third insulating layer 22. The via 261 connects the first metal layer 27 and the active layer 21. The source electrode 271 and the drain electrode 272 are electrically connected to the active layer 21 after filling the via 261.

[0033] The pixel circuit P includes various structures, such as "3T1C", "4T1C", "7T1C" or "7T2C", where "T" represents a thin-film transistor (TFT) and "C" represents a storage capacitor (Cst). The numbers indicate the number of components following the numbers.

[0034] Specifically, see Figure 3This application uses a pixel circuit P with a "7T1C" structure as an example for illustration. A pixel circuit P includes seven thin-film transistors (TFTs) and a storage capacitor Cst. Specifically, the seven TFTs include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first reset transistor T4, a second light-emitting control transistor T5, a first light-emitting control transistor T6, and a second reset transistor T7. The first terminal of the driving transistor T1 is connected to the second terminal of the compensation transistor T3 and the second terminal of the second reset transistor T7. The second terminal of the driving transistor T1 is connected to the second terminal of the first light-emitting control transistor T6. The first terminal of the compensation transistor T3 is connected to the second terminal of the first reset transistor T4.

[0035] In the fabrication process of thin-film transistors (TFTs) using low-temperature polycrystalline silicon, in order to make the driving transistor T1 have a more stable threshold voltage Vth and a higher subthreshold swing SS compared to other transistors, it is usually necessary to electrically regulate the driving transistor T1. Specifically, after the first insulating layer 26 is formed, hydrogenation is performed, and after etching to form vias 261, hydrogen removal is performed on the exposed active layer 21 through the vias 261. The inventors discovered that during the dehydrogenation process, free hydrogen ions move violently along the surface of the active layer 21 toward the third insulating layer 22, leading to an increase in interface defects between the active layer 21 and the third insulating layer 22. This results in an increase in the leakage current of the transistor. Since the leakage current generated by the compensation transistor T3 and the first reset transistor T4 flows to the gate of the driving transistor T1, the voltage of the storage capacitor Cst connected to the gate of the driving transistor T1 increases, and the driving current of the driving transistor T1 decreases. As a result, the brightness of the display screen continues to decrease, especially in low-frequency display modes, such as always-on display (AOD) mode, where the display screen is prone to flickering, which seriously affects the display effect.

[0036] See Figure 5aIn the active layer 21 of a pixel circuit P, the first terminal of the driving transistor T1 (shown as D1 in the figure), the second terminal of the compensation transistor T3 (shown as D2 in the figure), and the second terminal of the first light-emitting control transistor T6 (shown as D3 in the figure) are spaced apart to form a first active portion 211, a second active portion 212, and a third active portion 213 spaced apart. The driving transistor T1 is located in the first active portion 211, the compensation transistor T3 and the first reset transistor T4 are located in the second active portion 212, and the first light-emitting control transistor T6 is located in the third active portion 213. It should be noted that the array substrate 100 has multiple pixel circuits P, which are arrayed along a first direction X and a second direction Y. In the first direction X, the second active portion 212 of one pixel circuit P and the third active portion 213 of another adjacent pixel circuit P are interconnected. Therefore, when the first active part 211 is physically disconnected from the second active part 212 and the third active part 213, the movement path of hydrogen ions is blocked. During the dehydrogenation process of the active layer 21, free hydrogen ions are difficult to move from the surface of the first active part 211 across the disconnection point to the surface of the second active part 212 and the third active part 213. This greatly avoids hydrogen ions invading the interface between the second active part 212 and the third insulating layer 22 where the compensation transistor T3 and the first reset transistor T4 are located. This ensures the device quality of the compensation transistor T3 and the first reset transistor T4, and ensures that the compensation transistor T3 and the first reset transistor T4 have small leakage current, so that the display panel has a good display effect.

[0037] It should be noted that the driving transistor T1, compensation transistor T3, and first light-emitting control transistor T6 in a pixel circuit P are only physically disconnected on the active layer 21. Other metal layers are needed to reconnect the disconnected driving transistor T1, compensation transistor T3, and first light-emitting control transistor T6 to ensure the normal conduction of the pixel circuit P.

[0038] In one specific implementation, see further details. Figure 1 and Figure 4Via 261 includes a first via 2611, a second via 2612, and a third via 2613, all of which penetrate the first insulating layer 26, the second insulating layer 24, and the third insulating layer 22. The first via 2611 connects the first metal layer 27 and the first terminal D1 of the driving transistor T1 in the active layer 21. The second via 2612 connects the first metal layer 27 and the second terminal D2 of the first reset transistor T4 in the active layer 21. The third via 2613 connects the first metal layer 27 and the second terminal D3 of the first light-emitting control transistor in the active layer 21. The first metal layer 27 fills a portion of the first via 2611, the second via 2612, and the third via 2613, so that the first active part 211 is electrically connected to the second active part 212 and the third active part 213. In this embodiment, the first metal layer 27 reconnects the originally disconnected driving transistor T1, compensation transistor T3, and first light-emitting control transistor T6, ensuring the normal conduction of the pixel circuit P. Since the metal layer where the source 271 and drain 272 of the thin-film transistor TFT are located is the first metal layer 27, the source 271, drain 272 and the metal filling the first via 2611, the second via 2612 and the third via 2613 can be formed simultaneously.

[0039] Optionally, the first insulating layer 26 includes a second sub-insulating layer and a first sub-insulating layer (not shown) stacked together, with the second sub-insulating layer located on the side of the first sub-insulating layer facing the substrate. The first and second sub-insulating layers are made of the same material, but the two layers are formed sequentially, with the second sub-insulating layer formed before the dehydrogenation treatment and the first sub-insulating layer formed after the dehydrogenation treatment. Specifically, firstly, a complete second sub-insulating layer is formed on the surface of the second metal layer 25 by chemical vapor deposition (CVD), and this insulating layer is hydrogenated; then, a first temporary via is formed, which penetrates the second sub-insulating layer, the second insulating layer 24, and the third insulating layer 22, exposing the first active portion 211 corresponding to the first end of the driving transistor T1 through the first temporary via; then, the exposed active layer 21 is dehydrogenated through the first temporary via. Since the first temporary via only connects to the first active portion 211, and the second active portion 212 and the third active portion 213 are completely covered by the insulating layer at this time, the dehydrogenation treatment can only affect the first active portion 211. This allows the electrical properties of the driving transistor T1 corresponding to the first active part 211 to be adjusted. After the electrical adjustment is completed, the first sub-insulating layer is formed to form a complete first insulating layer 26. Since the first sub-insulating layer fills the first temporary via, a first via 2611 needs to be formed at the position of the first temporary via, and a second via 2612 and a third via 2613 need to be formed. All three types of vias penetrate the first insulating layer 26, the second insulating layer 24 and the third insulating layer 22, making it difficult for the hydrogen ions generated in this dehydrogenation process to affect the second active part 212 and the third active part 213, thereby reducing the possibility of leakage current generated by the compensation transistor T3 and the first reset transistor T4.

[0040] Optionally, such as Figure 5eAs shown, the array substrate 100 is also provided with a plurality of fourth vias 2614 and a plurality of fifth vias 2615, all of which are used for electrical connection between the first metal layer 27 and the active layer 21. The first metal layer 27 fills at least part of the fourth vias 2614 and the fifth vias 2615. The plurality of fourth vias 2614 are connected to the first metal layer 27 and the first active part 211, and the plurality of fifth vias 2615 are connected to the first metal layer 27 and the second active part 212 / third active part 213. Specifically, a second temporary via is formed simultaneously with the formation of the first temporary via. The second temporary via penetrates the second sub-insulating layer, the second insulating layer 24, and the third insulating layer 22, exposing the first active part 211. A fourth via 2614 and a fifth via 2615 are formed simultaneously with the first via 2611, the second via 2612, and the third via 2613, with the fourth via 2614 forming at the position corresponding to the second temporary via. All vias penetrate the first insulating layer 26, the second insulating layer 24, and the third insulating layer 22. That is, all vias 261 communicating with the first active part 211 are formed before the dehydrogenation treatment. After the first active part 211 is dehydrogenated through the first and second temporary vias, the second via 2612, the third via 2613, and the fifth via 2615 communicating with the second active part 212 / third active part 213 are formed. Further reducing the impact of dehydrogenation on the second active section 212 / third active section 213 reduces the possibility of leakage current generated by the compensation transistor T3 and the first reset transistor T4.

[0041] See Figure 6 This application also provides a method for fabricating an array substrate, the method comprising:

[0042] Step S110: As Figure 5a As shown, an active layer 21 is formed on one side of the substrate 10. The active layer 21 includes a first active portion 211, a second active portion 212, and a third active portion 213 spaced apart. Specifically, the disconnected end of the first active portion 211 corresponds to the first end of the driving transistor T1 in the active layer 21, the disconnected end of the second active portion 212 corresponds to the second end of the compensation transistor T3 in the active layer 21, and the disconnected end of the third active portion 213 corresponds to the second end of the first light-emitting control transistor T6 in the active layer 21. The active layer 21 can be made of polysilicon, and this step can be achieved by etching the active layer 21 to form patterned first active portions 211, second active portions 212, and third active portions 213.

[0043] Step S120: Multiple metal layers are formed on the side of the active layer 21 facing away from the substrate 10. The active layer 21 and the multiple metal layers form a pixel circuit P. The pixel circuit P includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first reset transistor T4, a second light-emitting control transistor T5, a first light-emitting control transistor T6, and a second reset transistor T7, as shown below. Figure 1 As shown.

[0044] See Figure 7 Specifically, step S120 further includes:

[0045] Step S121: As Figure 5b and Figure 5c As shown, multiple insulating layers are formed on one side of the active layer 21, including a first insulating layer 26, a second insulating layer 24, and a third insulating layer 22. Specifically, this step involves sequentially forming a third insulating layer 22, a third metal layer 23, a second insulating layer 24, a second metal layer 25, and a first insulating layer 26 on one side of the active layer 21.

[0046] Step S122: As Figure 5e As shown, a first via 2611, a second via 2612, and a third via 2613 are formed on the insulating layer. Optionally, multiple fourth vias 2614 and fifth vias 2615 can also be formed in this step, all for connecting the first metal layer 27 and the active layer 21. The fourth via 2614 can be understood as all vias 261 connecting the first active portion 211 and the first metal layer 27 except for the first via 2611. The fifth via 2615 can be understood as all vias 261 connecting the second active portion 212 / third active portion 213 and the first metal layer 27 except for the second via 2612 and the third via 2613. Among them, the first via 2611 connects to the first terminal D1 of the driving transistor T1 in the active layer 21, the second via 2612 connects to the second terminal D2 of the first reset transistor T4 in the active layer 21, and the third via 2613 connects to the second terminal D3 of the first light-emitting control transistor T6.

[0047] Step S123: As Figure 1 and Figure 4 As shown, a first metal layer 27 is formed on the side of the first insulating layer 26 facing away from the substrate 10. The first metal layer 27 fills at least a portion of the first via 2611, the second via 2612, and the third via 2613, so that the first active portion 211 is electrically connected to the second active portion 212 and the third active portion 213. Optionally, the first metal layer 27 may also fill at least a portion of the fourth via 2614 and the fifth via 2615, so that the first metal layer 27 is electrically connected to the second active portion 212 / the third active portion 213.

[0048] See Figure 8 Specifically, step S121 may also include:

[0049] Step S1211: Form the second sub-insulating layer. The second sub-insulating layer is formed after the second metal layer.

[0050] Step S1212: Hydrogenation treatment is performed on the second sub-insulating layer. Hydrogenation can greatly reduce dangling bonds and interface defects.

[0051] Step S1213: As Figure 5d As shown, the first end of the driving transistor in the active layer is exposed through the first temporary via 2161a, and the active layer is subjected to hydrogen removal treatment. The first temporary via 2161a corresponds to the subsequent first via 2161. Optionally, multiple second temporary vias 2614a can also be formed simultaneously in this step. This exposes the corresponding active layer, i.e., the first active portion, through the first temporary via 2161a and the second temporary via 2614a, enabling subsequent electrical connection with the first metal layer. The hydrogen removal treatment can reduce defects or traps in the active layer. Specifically, the hydrogen removal treatment can only reach the first active portion 211 through the first temporary via 2161a and the second temporary via 2614a to perform hydrogen removal treatment on the first active portion 211. This hydrogen removal treatment is unlikely to affect the second active portion 212 / third active portion 213 covered by the insulating layer.

[0052] Step S1214: A first sub-insulating layer is formed on the side of the second sub-insulating layer facing away from the substrate to form the first insulating layer. Since the first temporary via 2161a and the second temporary via 2614a are formed before the first sub-insulating layer, the two vias are filled by the first sub-insulating layer. Therefore, a first via 2611 penetrating all insulating layers needs to be formed corresponding to the first temporary via 2161a, and a fourth via 2614 penetrating all insulating layers needs to be formed corresponding to the second temporary via 2614a to expose the first active portion. Since the second via 2612, the third via 2613, and the fifth via 2615 are formed after the dehydrogenation process, the hydrogen ions generated during the dehydrogenation process are unlikely to affect the second active portion 212 / third active portion 213.

[0053] The fabrication method provided in this application ensures that the driving transistor T1 has good electrical properties while reducing the impact of electrical adjustment on the performance of other thin-film transistors (TFTs) in the pixel circuit P, thereby improving the display effect.

[0054] This application also provides a display device, including an array substrate according to any embodiment, and further including a light-emitting layer and an encapsulation layer sequentially stacked on the array substrate. The display device can be a mobile phone, tablet computer, television, or wearable display device, etc.

[0055] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate; an active layer arranged on one side of the substrate; a plurality of metal layers arranged on the side of the active layer away from the substrate; the active layer and the plurality of metal layers form a pixel circuit, the pixel circuit comprising a driving transistor, a compensation transistor, a first reset transistor and a first light-emitting control transistor, wherein the subthreshold swing of the driving transistor is greater than the subthreshold swings of the compensation transistor and the first reset transistor; a first end of the driving transistor is electrically connected to a second end of the compensation transistor, a first end of the compensation transistor is electrically connected to a second end of the first reset transistor, and a second end of the driving transistor is electrically connected to a second end of the first light-emitting control transistor; in the active layer in one of the pixel circuits, the first end of the driving transistor is arranged apart from the second end of the compensation transistor and the second end of the first light-emitting control transistor to form first, second and third active parts arranged apart, wherein the driving transistor is located in the first active part, the compensation transistor and the first reset transistor are located in the second active part, and the first light-emitting control transistor is located in the third active part.

2. The array substrate according to claim 1, wherein the plurality of metal layers comprises a first metal layer, at least one insulating layer is arranged between the first metal layer and the active layer, the at least one insulating layer is provided with a first via, a second via and a third via, the first via communicates the first metal layer with the first end of the driving transistor in the active layer, the second via communicates the first metal layer with the second end of the first reset transistor in the active layer, and the third via communicates the first metal layer with the second end of the first light-emitting control transistor in the active layer, and the first metal layer fills at least part of the first via, the second via and the third via to electrically connect the first active part to the second active part and electrically connect the first active part to the third active part.

3. The array substrate according to claim 2, wherein the at least one insulating layer comprises a first insulating layer arranged on the side of the first metal layer facing the substrate, the first insulating layer comprises a first sub-insulating layer and a second sub-insulating layer arranged in layers, the second sub-insulating layer is located on the side of the first sub-insulating layer facing the substrate, and the first via, the second via and the third via all penetrate the first sub-insulating layer and the second sub-insulating layer; wherein the first sub-insulating layer is formed after dehydrogenation treatment of the active layer, and the second sub-insulating layer is formed before the dehydrogenation treatment.

4. The array substrate according to claim 2, wherein the at least one insulating layer is further provided with a plurality of fourth vias and a plurality of fifth vias, the first metal layer fills at least part of the fourth vias and the fifth vias, the fourth vias communicate the first metal layer with the first active part, and the fifth vias communicate the first metal layer with the second active part / the third active part.

5. The array substrate according to claim 1, characterized in that, The active layer is made of semiconductor material.

6. The array substrate according to claim 5, characterized in that, The active layer is made of polycrystalline silicon.

7. A method for fabricating an array substrate, characterized in that, An active layer is formed on one side of the substrate, the active layer including a first active portion, a second active portion and a third active portion disposed at intervals; A multilayer metal layer is formed on the side of the active layer away from the substrate. The active layer and the multilayer metal layers form a pixel circuit. The pixel circuit includes a driving transistor, a compensation transistor, a first reset transistor, and a first light-emitting control transistor. The subthreshold swing of the driving transistor is greater than that of the compensation transistor and the first reset transistor. In the active layer, the driving transistor is located in the first active portion, the compensation transistor is located in the second active portion, and the first light-emitting control transistor is located in the third active portion. The first terminal of the driving transistor is electrically connected to the second terminal of the compensation transistor, the first terminal of the compensation transistor is electrically connected to the second terminal of the first reset transistor, and the second terminal of the driving transistor is electrically connected to the second terminal of the first light-emitting control transistor.

8. The production method according to claim 7, characterized by, The step of forming a multilayer metal layer on the side of the active layer opposite to the substrate further includes: At least one insulating layer is formed on the side of the active layer away from the substrate, the at least one insulating layer including a first insulating layer; A first via, a second via, and a third via are formed on at least one of the insulating layers, wherein the first via connects to a first terminal of the driving transistor in the active layer, the second via connects to a second terminal of the first reset transistor in the active layer, and the third via connects to a second terminal of the first light-emitting control transistor. A first metal layer is formed on the side of the first insulating layer away from the substrate, wherein the first metal layer fills at least a portion of the first via, the second via, and the third via, such that the first active portion is electrically connected to the second active portion, and the first active portion is electrically connected to the third active portion.

9. The production method according to claim 8, characterized by, The step of forming at least one insulating layer on the side of the active layer opposite to the substrate, wherein the at least one insulating layer includes a first insulating layer, comprises: Forming a second insulating layer; The second sub-insulating layer is hydrogenated; The first end of the driving transistor in the active layer is exposed through the first temporary via, and the active layer is subjected to hydrogen removal treatment. A first sub-insulating layer is formed on the side of the second sub-insulating layer opposite to the substrate to form the first insulating layer.

10. The method of claim 9, wherein, Following the step of hydrogenating the second sub-insulating layer, the method further includes: The first active part is exposed through the second temporary via; The step of forming a first sub-insulating layer on the side of the second sub-insulating layer opposite to the substrate to form the first insulating layer further includes: A plurality of fourth vias and a plurality of fifth vias are formed on the at least one insulating layer, wherein the fourth vias are connected to the first active part, and the fifth vias are connected to the second active part / the third active part; The step of forming a first metal layer on the side of the first insulating layer opposite to the substrate further includes: The first metal layer fills at least a portion of the fourth and fifth vias to make the first metal layer electrically connected to the second active portion / the third active portion.

11. A display device, characterized in that, The array substrate includes any one of the array substrates as described in claims 1-6 or any one of the preparation methods described in claims 7-10.

Images