Display panel and display device

Abstract

The application relates to a display panel and a display device; the display panel comprises an array substrate and a pixel definition layer; the pixel definition layer is arranged on the array substrate, a plurality of pixel openings are arranged in the pixel definition layer, the pixel definition layer comprises a barrier wall arranged between adjacent pixel openings, a side surface of the barrier wall close to the pixel opening comprises a first sub-surface and a second sub-surface, the first sub-surface is located between the array substrate and the second sub-surface, the contact angle of the first sub-surface is smaller than that of the second sub-surface; wherein the first sub-surface has a first height in the thickness direction of the display panel, the barrier wall has a second height in the thickness direction of the display panel, and the ratio of the first height to the second height is greater than or equal to 0.5; the application can prolong the electric leakage path, increase the resistance, reduce the electric leakage current, and then be beneficial to improving the performance and display effect of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] An organic light-emitting diode (OLED) display panel has the advantages of low cost, wide viewing angle, high contrast, and bendability, and has achieved remarkable results in small and large size applications.

[0003] Inkjet printing technology can be used in the preparation of the organic functional layer of the OLED display panel. The inkjet printing technology is to directly drop the ink containing OLED materials to the pixel definition layer prepared in advance, and the required pattern is formed after the solvent is volatilized. For example, the hole injection layer, the hole transport layer, and the light emitting layer can all be prepared by using the inkjet printing process.

[0004] Generally, a hydrophobic surface is formed on the upper side of the dam in the pixel definition layer, so that the ink is more easily flowed into the pixel opening; wherein the film layer climbing point of the hole injection layer, the hole transport layer and the light emitting layer on the side wall of the dam is below the hydrophobic surface, and the climbing height is not much different, so that at the side wall of the dam, the hole injection layer is easily exposed and not wrapped, which leads to the hole injection layer easily contacting the cathode layer above the light emitting layer, thereby causing electric leakage, affecting the device performance and display effect. SUMMARY

[0005] Embodiments of the present application provide a display panel and a display device, which can prolong the electric leakage path between the short circuit film layers, increase the resistance, and reduce the leakage current.

[0006] Embodiments of the present application provide a display panel, which comprises:

[0007] An array substrate;

[0008] A pixel definition layer is arranged on the array substrate, and a plurality of pixel openings are arranged in the pixel definition layer. The pixel definition layer comprises a barrier wall arranged between adjacent pixel openings. The side surface of the barrier wall close to the pixel opening comprises a first sub-surface and a second sub-surface. The first sub-surface is located between the array substrate and the second sub-surface. The contact angle of the first sub-surface is smaller than that of the second sub-surface.

[0009] The first sub-surface has a first height in the thickness direction of the display panel, and the barrier wall has a second height in the thickness direction of the display panel. The ratio of the first height to the second height is greater than or equal to 0.5.

[0010] In an embodiment of the present application, the display panel further comprises:

[0011] a hole injection layer comprising a hole injection portion disposed in the pixel opening;

[0012] a light emitting layer comprising a light emitting portion disposed in the pixel opening and located on a side of the hole injection portion away from the array substrate;

[0013] a functional electrode layer disposed on the pixel defining layer and extending into the pixel opening, and the functional electrode layer located in the pixel opening is located on a side of the light emitting portion away from the hole injection portion;

[0014] wherein an edge of the hole injection portion extends onto the side surface, and the functional electrode layer extends onto the side surface and connects with the hole injection portion.

[0015] In an embodiment of the present application, the connection between the hole injection portion and the functional electrode layer is located on the first sub-surface and on a side of the first sub-surface close to the second sub-surface.

[0016] In an embodiment of the present application, a normal projection of the light emitting portion on the array substrate is located within a normal projection of the hole injection portion on the array substrate.

[0017] In an embodiment of the present application, in the pixel opening, an edge of at least one side of the light emitting portion is disposed apart from the side surface, and the functional electrode layer covers the light emitting portion and extends to the side surface and connects with the hole injection portion.

[0018] In an embodiment of the present application, the functional electrode layer comprises a cathode layer, and at the side surface, the hole injection portion connects with the cathode layer.

[0019] Alternatively, the functional electrode layer comprises an electron transport layer and the cathode layer, and the electron transport layer is located between the light emitting portion and the cathode layer, and at the side surface, the hole injection portion connects with the electron transport layer.

[0020] In an embodiment of the present application, the display panel further comprises a hole transport layer disposed between the hole injection layer and the light emitting layer, and the hole transport layer comprises a hole transport portion disposed between the hole injection portion and the light emitting portion and located in the pixel opening.

[0021] In the pixel opening, an edge of at least one side of the hole transport portion is disposed apart from the side surface, and the functional electrode layer covers the light emitting portion and the hole transport portion and extends to the side surface and connects with the hole injection portion.

[0022] In an embodiment of the present application, the display panel further comprises:

[0023] a hole injection layer comprising a hole injection portion disposed in the pixel opening;

[0024] a light emitting layer comprising a light emitting portion disposed in the pixel opening and located on a side of the hole injection portion away from the array substrate;

[0025] a functional electrode layer disposed on the pixel defining layer and extending into the pixel opening, and the functional electrode layer located in the pixel opening is located on a side of the light emitting portion away from the hole injection portion;

[0026] wherein the hole injection portion and the functional electrode layer are spaced apart.

[0027] In an embodiment of the present application, the first sub-surface and the second sub-surface are connected, and the first sub-surface and the second sub-surface intersect at a preset included angle at the connection, and the preset included angle is less than or equal to 180°.

[0028] In an embodiment of the present application, the first sub-surface comprises a first side close to the array substrate and a second side away from the array substrate, the second sub-surface comprises a third side close to the array substrate and a fourth side away from the array substrate, the first side and the second side have a first distance, the third side and the fourth side have a second distance, and the ratio of the first distance to the second distance is greater than or equal to 1.

[0029] In an embodiment of the present application, the first sub-surface is hydrophilic, and the second sub-surface is hydrophobic.

[0030] In an embodiment of the present application, a plurality of the pixel openings are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect;

[0031] The barrier wall comprises a first sub-portion and a plurality of second sub-portions arranged in layers, the first sub-portion is located between the array substrate and the second sub-portion, the first sub-portion extends along the first direction and the second direction, and is arranged around each of the pixel openings;

[0032] The second sub-portion extends along the second direction, a plurality of the second sub-portions are arranged along the first direction, a plurality of the pixel openings arranged along the second direction are arranged between adjacent two of the second sub-portions, and the second sub-portion has the first sub-surface and the second sub-surface on a side close to the pixel opening.

[0033] According to the above purposes of the present application, the display device provided by the embodiments of the present application comprises the display panel.

[0034] The display panel and the display device provided by the present application can increase the proportion of the part with a smaller contact angle in the side surface of the retaining wall by increasing the height of the first sub-surface, so that the climbing height of the ink on the side surface is increased in the process of the display panel, the position connected by the short-circuit film layer is also increased, the leakage path is lengthened, the resistance is increased, the leakage current is reduced, and the performance and the display effect of the display panel are improved.

[0035] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the following embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0037] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0038] Figure 1 The structural schematic diagram of the display panel provided by an embodiment is shown in the figure.

[0039] Figure 2 The structural schematic diagram of the display panel provided by an embodiment is shown in the figure. Figure 1 The enlarged structural schematic diagram of a in the figure.

[0040] Figure 3 The first structural schematic diagram of the display panel provided by an embodiment of the present application is shown in the figure.

[0041] Figure 4 The structural schematic diagram of the display panel provided by an embodiment of the present application is shown in the figure. Figure 3 The enlarged structural schematic diagram of A in the figure.

[0042] Figure 5 The detection schematic diagram of the hydrophobic material in the side surface of the retaining wall provided by an embodiment of the present application is shown in the figure.

[0043] Figure 6 The second structural schematic diagram of the display panel provided by an embodiment of the present application is shown in the figure.

[0044] Figure 7 The structural schematic diagram of the pixel definition layer provided by an embodiment of the present application is shown in the figure.

[0045] Figure 8Another structure schematic view of the pixel definition layer provided by the embodiment of the present application;

[0046] Figure 9 The third structure schematic view of the display panel provided by the embodiment of the present application;

[0047] Figure 10 The plane distribution schematic view of the pixel definition layer provided by the embodiment of the present application;

[0048] Figures 11-12 The manufacturing process structure schematic view of the pixel definition layer provided by the embodiment of the present application.

[0049] Explanation of the reference signs:

[0050] 1, anode electrode; 2, pixel definition layer; 3, hole injection film layer; 4, hole transport film layer; 5, organic light emitting layer; 6, cathode electrode;

[0051] 10, array substrate;

[0052] 20, pixel definition layer; 21, barrier wall; 211, first sub-part; 212, second sub-part; 201, pixel opening; 202, top surface; 203, side surface; 2031, first sub-surface; 2032, second sub-surface; 23, barrier wall intermediate body; 204, first surface; 205, second surface;

[0053] 30, anode layer; 31, anode;

[0054] 40, hole injection layer; 41, hole injection part;

[0055] 50, light emitting layer; 51, light emitting part;

[0056] 60, functional electrode layer; 61, cathode layer; 62, electron transport layer;

[0057] 70, hole transport layer; 71, hole transport part. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.

[0059] Please refer to Figure 1 and Figure 2The display panel comprises a positive electrode 1, a pixel definition layer 2 arranged on the positive electrode 1, a hole injection film layer 3, a hole transport film layer 4, an organic light-emitting layer 5, and a negative electrode 6 arranged on the pixel definition layer 2 and the organic light-emitting layer 5. The pixel definition layer 2 is provided with a pixel opening, and the hole injection film layer 3, the hole transport film layer 4, and the organic light-emitting layer 5 can be arranged in the pixel opening. The hole injection film layer 3, the hole transport film layer 4, and the organic light-emitting layer 5 can be prepared by using an inkjet printing process. In the inkjet printing process, a hydrophobic surface is usually formed on the dam side of the pixel definition layer 2, so that the ink of the hole injection film layer 3, the hole transport film layer 4, and the organic light-emitting layer 5 can flow into the pixel opening more easily. The film layer climbing point of the hole injection film layer 3, the hole transport film layer 4, and the organic light-emitting layer 5 on the side wall of the dam is below the hydrophobic surface, and the climbing height difference is small. Therefore, at the side wall of the dam, the hole injection film layer 3 is easy to be exposed and not wrapped, which causes the hole injection film layer 3 to be easy to contact with the negative electrode 6 above the light-emitting layer, for example Figure 1 As shown by the leakage current a in the middle, the leakage current is generated, which affects the performance and display effect of the device.

[0060] Please refer to Figure 3 and Figure 4 The display panel provided by the embodiments of the present application comprises an array substrate 10 and a pixel definition layer 20. The pixel definition layer 20 is arranged on the array substrate 10, and a plurality of pixel openings 201 are arranged in the pixel definition layer 20. The pixel definition layer 20 comprises a dam 21 arranged between adjacent pixel openings 201. The side surface 203 of the dam 21 close to the pixel opening 201 comprises a first sub-surface 2031 and a second sub-surface 2032. The first sub-surface 2031 is located between the array substrate 10 and the second sub-surface 2032. The contact angle of the first sub-surface 2031 is smaller than that of the second sub-surface 2032.

[0061] The first sub-surface 2031 has a first height H1 along the thickness direction of the display panel. The dam 21 has a second height H2 along the thickness direction of the display panel. The ratio of the first height H1 to the second height H2 is greater than or equal to 0.5.

[0062] In the implementation process, the height of the first sub-surface 2031 is increased, so that the proportion of the part with a smaller contact angle in the side surface 203 of the dam 21 is increased. In the process of manufacturing the display panel, the climbing height of the ink on the side surface 203 is increased, the position connected by the short-circuit film layer is also increased, the leakage path is lengthened, the resistance is increased, the leakage current is reduced, and the performance and display effect of the display panel are improved.

[0063] In particular, please continue to refer to Figure 3 and Figure 4 The display panel comprises an array substrate 10, an anode layer 30 disposed on the array substrate 10, a pixel definition layer 20 disposed on the anode layer 30, a hole injection layer 40, a light-emitting layer 50, and a functional electrode layer 60.

[0064] In some embodiments, the array substrate 10 comprises a substrate and a thin-film transistor layer disposed on the substrate.

[0065] In some embodiments, the substrate can be a hard substrate, such as a glass substrate, or the substrate can be a flexible substrate, such as a substrate formed of polyimide. When the substrate is a flexible substrate, the substrate can be formed of multiple sub-substrates of the same material, such as polyimide, and adjacent sub-substrates are bonded by an adhesive sub-layer.

[0066] In some embodiments, the thin-film transistor layer comprises a thin-film transistor comprising a semiconductor on the substrate, which can be formed of polycrystalline silicon or metal oxide (such as indium gallium zinc oxide). The semiconductor is divided into a channel region and source and drain regions formed on both sides of the channel region. The thin-film transistor layer further comprises a first gate insulating layer covering the semiconductor. The thin-film transistor further comprises a first gate formed on the first gate insulating layer, which overlaps the channel region. The first gate can be formed of multiple layers or a single layer comprising a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high corrosion resistance. The thin-film transistor layer further comprises a second gate insulating layer covering the first gate. The thin-film transistor further comprises a second gate on the second gate insulating layer, which overlaps the first gate, and the second gate can be formed of multiple layers or a single layer comprising a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high corrosion resistance. The thin-film transistor layer further comprises a first interlayer insulating layer formed on the second gate. The first interlayer insulating layer and the first gate insulating layer and the second gate insulating layer comprise source and drain contact holes, and the source and drain regions are exposed through the source and drain contact holes, respectively.

[0067] The thin film transistor further comprises a source electrode and a drain electrode arranged in the same layer, both of which are formed on the first interlayer insulating layer, the source electrode is connected with the source region through the source contact hole, and the drain electrode is connected with the drain region through the drain contact hole. The source electrode and the drain electrode can be multiple layers or a single layer formed by low-resistance materials such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or materials with high corrosion resistance. For example, the source electrode and the drain electrode can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, or other single layer or multiple layer structures.

[0068] In some embodiments, the thin film transistor layer further comprises a planarization layer on the side of the first interlayer insulating layer away from the substrate, which covers the source electrode and the drain electrode.

[0069] In some embodiments, the anode layer 30 is arranged on the planarization layer, and the anode layer 30 comprises a plurality of anodes 31; the pixel definition layer 20 is arranged on the planarization layer, and the pixel definition layer 20 is provided with a plurality of pixel openings 201, and the plurality of pixel openings 201 are arranged corresponding to the plurality of anodes 31; for example, the plurality of pixel openings 201 and the plurality of anodes 31 can be arranged one-to-one, and each pixel opening 201 exposes the surface of the corresponding anode 31 away from the array substrate 10.

[0070] Further, the hole injection layer 40 is arranged on the pixel definition layer 20, and the hole injection layer 40 comprises a hole injection part 41 arranged in the pixel opening 201 and located on the side of the anode 31 away from the array substrate 10.

[0071] The light-emitting layer 50 is arranged on the hole injection layer 40, and the light-emitting layer 50 comprises a light-emitting part 51 arranged in the pixel opening 201 and located on the side of the hole injection part 41 away from the anode 31.

[0072] The functional electrode layer 60 is arranged on the pixel definition layer 20, and the functional electrode layer 60 is further arranged on the side of the light-emitting layer 50 away from the hole injection layer 40, the functional electrode layer 60 extends into the pixel opening 201, and the functional electrode layer 60 located in the pixel opening 201 is located on the side of the light-emitting part 51 away from the hole injection part 41.

[0073] In some embodiments, the pixel definition layer 20 includes a barrier wall 21 disposed between adjacent pixel openings 201, and the barrier wall 21 includes a top surface 202 away from the array substrate 10 and a side surface 203 close to the pixel openings 201, and the side surface 203 is connected to the top surface 202; wherein the side surface 203 includes a first sub-surface 2031 and a second sub-surface 2032, the first sub-surface 2031 is located between the second sub-surface 2032 and the array substrate 10, the contact angle of the first sub-surface 2031 is smaller than the contact angle of the second sub-surface 2032, and the contact angle of the first sub-surface 2031 is smaller than the contact angle of the top surface 202.

[0074] In some embodiments, the first sub-surface 2031 can be hydrophilic, the second sub-surface 2032 and the top surface 202 can be hydrophobic; further, the contact angle of the first sub-surface 2031 can be less than 90°, the contact angle of the second sub-surface 2032 can be greater than 90°, and the contact angle of the top surface 202 can be greater than 90°.

[0075] It should be noted that the hole injection layer 40 and the light-emitting layer 50 in the display panel provided by the embodiments of the present application can be prepared by an inkjet printing process, and in the process of the display panel, since the top surface 202 and the second sub-surface 2032 are hydrophobic, the ink will flow into the pixel openings 201 and form a film in the range of the first sub-surface 2031, and the hole injection layer 40 and the light-emitting layer 50 will form a climbing at the first sub-surface 2031; since the climbing heights of the hole injection layer 40 and the light-emitting layer 50 are not much different, the hole injection layer 40 is easy to be exposed and not wrapped by the light-emitting layer 50 at the side surface 203 of the barrier wall 21, and thus the hole injection layer 40 is easy to contact with the functional electrode layer 60 above the light-emitting layer 50, thereby causing a leakage current, affecting the device performance and display effect.

[0076] In some embodiments, the hydrophilic and hydrophobic properties of the top surface 202 and the side surface 203 can be achieved by forming a thin film with hydrophilic or hydrophobic properties on the surface of the barrier wall 21, or by adding a hydrophobic material, such as fluorine, to the material of the barrier wall 21, and making the hydrophobic material mainly distributed on the side of the barrier wall 21 away from the array substrate 10, for example, by making the concentration of the hydrophobic material on the side of the barrier wall 21 away from the array substrate 10 greater than the concentration of the hydrophobic material on the side of the barrier wall 21 close to the array substrate 10, so as to make the top surface 202 and the second sub-surface 2032 on the side of the barrier wall 21 away from the array substrate 10 hydrophobic, and make the first sub-surface 2031 on the side of the barrier wall 21 close to the array substrate 10 hydrophilic.

[0077] In some embodiments, the ratio of the concentration of the hydrophobic material on the second sub-surface 2032 to the concentration of the hydrophobic material on the first sub-surface 2031 is greater than or equal to 3; for example Figure 5 When the hydrophobic material is fluorine, the content of fluorine on the first sub-surface 2031 and the second sub-surface 2032 can be detected.

[0078] In the embodiments of the present application, the first sub-surface 2031 has a first height H1 in the thickness direction of the display panel, the barrier wall 21 has a second height H2 in the thickness direction of the display panel, and the ratio of the first height H1 to the second height H2 is greater than or equal to 0.5; that is, the height of the first sub-surface 2031 is increased in the embodiments of the present application, so as to increase the climbing distance of the hole injection part 41 and the light emitting part 51 at the side surface 203, even if the hole injection part 41 and the functional electrode layer 60 are connected at the climbing position, the position where the hole injection part 41 and the functional electrode 60 are connected can be moved away from the anode 31, so that the short-circuit position is farther away from the center of the hole injection part 41, the leakage path is lengthened, the resistance is increased, and thus the leakage current can be effectively reduced, and the performance and display effect of the display panel are improved.

[0079] In some embodiments, the ratio of the first height H1 to the second height H2 can be 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95 or 1.

[0080] In an embodiment of the present application, please refer to Figure 3 and Figure 4 The edge of the hole injection part 41 extends to the side surface 203, and the functional electrode layer 60 extends to the side surface 203 and is connected to the hole injection part 41.

[0081] Among them, since the contact angle of the first sub-surface 2031 is smaller than the contact angle of the second sub-surface 2032, for example, the first sub-surface 2031 is hydrophilic and the second sub-surface 2032 is hydrophobic; the ink in the process will be restricted to the first sub-surface 2031; therefore, the climbing edges of the hole injection portion 41 and the light-emitting portion 51 should not exceed the range of the first sub-surface 2031.

[0082] In some embodiments, the connection between the hole injection portion 41 and the functional electrode layer 60 is located on the first sub-surface 2031, and is located on the side of the first sub-surface 2031 close to the second sub-surface 2032; thus, in the present application, by increasing the height of the first sub-surface 2031, the position where the hole injection portion 41 and the functional electrode 60 are connected can be effectively moved in a direction away from the anode 31, so that the short-circuit is farther away from the center of the hole injection portion 41, extending the leakage path, increasing the resistance, and thus effectively reducing the leakage current and improving the performance and display effect of the display panel.

[0083] In some embodiments, within the pixel opening 201 , an edge of at least one side of the light-emitting portion 51 is spaced apart from the side surface 203 , and the functional electrode layer 60 covers the light-emitting portion 51 and extends to the side surface 203 to connect with the hole injection portion 41 .

[0084] In some embodiments, the orthographic projection of the light emitting portion 51 on the array substrate 10 is located within the orthographic projection of the hole injection portion 41 on the array substrate 10 .

[0085] In some embodiments, the display panel also includes a hole transport layer 70 arranged between the hole injection layer 40 and the light-emitting layer 50, and the hole transport layer 70 includes a hole transport portion 71 arranged between the hole injection portion 41 and the light-emitting portion 51 and located within the pixel opening 201; within the pixel opening 201, the edge of at least one side of the hole transport portion 71 is spaced apart from the side surface 203, and the functional electrode layer 60 covers the light-emitting portion 51 and the hole transport portion 71 and extends to the side surface 203 to be connected to the hole injection portion 41.

[0086] In some embodiments, the orthographic projection of the hole transport portion 71 on the array substrate 10 is located within the orthographic projection of the hole injection portion 41 on the array substrate 10 .

[0087] In some embodiments, as Figure 3 and Figure 4As shown, the functional electrode layer 60 includes a cathode layer 61, and at the side surface 203, the hole injection part 41 is connected with the cathode layer 61.

[0088] In some embodiments, as shown in Figure 6 As shown, the functional electrode layer 60 includes an electron transport layer 62 and the cathode layer 61, and the electron transport layer 62 is located between the light emitting part 51 and the cathode layer 61, and at the side surface 203, the hole injection part 41 is connected with the electron transport layer 62.

[0089] It can be understood that, by increasing the height of the first sub-surface 2031, the present application can reduce the leakage current between the hole injection part 41 and the cathode layer 61, or reduce the leakage current between the hole injection part 41 and the electron transport layer 62.

[0090] In some embodiments, as shown in Figure 3 and Figure 7 , the first sub-surface 2031 is connected with the second sub-surface 2032, and the first sub-surface 2031 and the second sub-surface 2032 intersect at a preset included angle B at the connection, and the preset included angle B is less than or equal to 180°.

[0091] Further, the first sub-surface 2031 includes a first side close to the array substrate 10 and a second side away from the array substrate 10, and the second sub-surface 2032 includes a third side close to the array substrate 10 and a fourth side away from the array substrate 10, and the first side and the second side have a first distance L1, and the third side and the fourth side have a second distance L2, and the ratio of the first distance L1 to the sum of the first distance L1 and the second distance L2 is greater than or equal to 1.

[0092] It should be noted that, when the preset included angle B is equal to 180°, the first sub-surface 2031 and the second sub-surface 2032 are coplanar, and at this time, the ratio of the first height H1 to the second height H2 is equal to the ratio of the first distance L1 to the sum of the first distance L1 and the second distance L2.

[0093] In some embodiments, the corner where the second sub-surface 2032 is connected with the top surface 202 can be a rounded corner, as shown in Figure 8 .

[0094] Further, in the present application, as shown in Figure 9 and Figure 10 , the barrier wall 21 includes a first sub-part 211 and a second sub-part 212 which are stacked, and the first sub-part 211 is located between the second sub-part 212 and the array substrate 10.

[0095] In some embodiments, the plurality of pixel openings 201 are arranged in an array along a first direction X and a second direction Y, the first direction X and the second direction Y being perpendicular to each other.

[0096] In some embodiments, the first sub-section 211 extends along the first direction X and the second direction Y, and is arranged around each pixel opening 201; the second sub-section 212 extends along the second direction Y, and a plurality of second sub-sections 212 are arranged along the first direction X, i.e., the second sub-section 212 is located on a side of the first sub-section 211 extending along the second direction Y, away from the array substrate 10.

[0097] In some embodiments, a plurality of pixel openings 201 are arranged along the second direction Y between two adjacent second sub-sections 212, and the side of the second sub-section 212 close to the pixel opening 201 has the first sub-surface 2031 and the second sub-surface 2032.

[0098] In the embodiments of the present application, the first sub-section 211 and the second sub-section 212 are stacked between two pixel openings 201 adjacent along the first direction X, and the first sub-section 211 is arranged between two pixel openings 201 adjacent along the second direction Y, i.e., the height of the barrier wall 21 between two pixel openings 201 adjacent along the first direction X is greater than the height of the barrier wall 21 between two pixel openings 201 adjacent along the second direction Y; therefore, in the inkjet printing process of the display panel, the hole injection layer 40 and the light-emitting layer 50 are continuously arranged along the second direction Y, and the hole injection layer 40 and the light-emitting layer 50 are arranged at intervals along the first direction X, i.e., the hole injection layer 40 and the light-emitting layer 50 along the first direction X are separated by the second sub-section 212, and the hole injection section 41 and the light-emitting section 51 will climb on the side surface 203 of the second sub-section 212.

[0099] As mentioned above, by increasing the height of the first sub-surface 2031, the proportion of the part of the side surface 203 of the barrier wall 21 with a smaller contact angle can be increased, and in the process of the display panel, the climbing height of the ink on the side surface 203 is increased, and the position where the hole injection section 41 and the functional electrode layer 60 are connected is also increased, so that the leakage path is lengthened, the resistance is increased, the leakage current is reduced, and the performance and display effect of the display panel are improved.

[0100] In other embodiments of the present application, the hole injection portion 41 and the functional electrode layer 60 can also be spaced apart, i.e., not short-circuited.

[0101] The orthographic projection of the hole injection portion 41 on the array substrate 10 is within the orthographic projection of the light emitting portion 51 on the array substrate 10, and / or the orthographic projection of the hole injection portion 41 on the array substrate 10 is within the orthographic projection of the hole transport portion 71 on the array substrate 10.

[0102] In addition, the embodiments of the present application also provide a manufacturing method of the display panel described in the above embodiments, and specifically include how to control the height of the first sub-surface 2031.

[0103] Please refer to Figure 3 , Figure 11 and Figure 12 , first, the barrier wall intermediate body 23 is formed on the anode layer 30, and the barrier wall intermediate body 23 has a first surface 204 away from the side of the anode layer 30 and a second surface 205 connected to the first surface 204, as shown in Figure 11 .

[0104] In some embodiments, the contact angle of the first surface 204 is greater than the contact angle of the second surface 205; further, the first surface 204 is hydrophobic, and the second surface 205 is hydrophilic, i.e., the contact angle of the first surface 204 is greater than 90°, and the contact angle of the second surface 205 is less than 90°.

[0105] In some embodiments, regarding the hydrophilicity and hydrophobicity of the first surface 204 and the second surface 205, a thin film with hydrophilicity or hydrophobicity can be formed on the surface of the barrier wall intermediate body 23; or, a hydrophobic material, such as fluorine element, can be added to the material of the barrier wall intermediate body 23, and the hydrophobic material is mainly distributed on the side of the barrier wall intermediate body 23 away from the anode layer 30, for example, the concentration of the hydrophobic material on the side of the barrier wall intermediate body 23 away from the anode layer 30 is greater than the concentration of the hydrophobic material on the side of the barrier wall intermediate body 23 close to the anode layer 30, so as to realize that the first surface 204 on the side of the barrier wall intermediate body 23 away from the anode layer 30 is hydrophobic, and the second surface 205 on the side of the barrier wall intermediate body 23 close to the anode layer 30 is hydrophilic.

[0106] Next, the retaining wall intermediate 23 is baked and cured. During the baking process of the retaining wall intermediate 23, the retaining wall intermediate 23 will soften and flow, so that a portion of the first surface 204 flows to the side of the retaining wall intermediate 23, thereby making the portion of the side of the retaining wall intermediate 23 away from the anode layer 30 hydrophobic.

[0107] Then we can get Figure 12 The structure of the pixel definition layer 20 is shown, wherein, in the retaining wall 21 of the pixel definition layer 20, the top surface 202 and the second sub-surface 2032 of the side surface 203 away from the anode layer 30 are hydrophobic, while the first sub-surface 2031 of the side surface 203 close to the anode layer 30 is hydrophilic.

[0108] It should be noted that the area of ​​the first surface 204 flowing to the side of the retaining wall intermediate 23 can be controlled by controlling the baking time of the retaining wall intermediate 23, and then the height or length ratio of the first sub-surface 2031 can be controlled; for example, the shorter the baking time, the smaller the height and length ratio of the second sub-surface 2032, the larger the height or length ratio of the first sub-surface 2031, the smaller the leakage current generated between the hole injection part 41 and the functional electrode layer 60, and the more beneficial it is to the performance improvement of the display panel.

[0109] In other embodiments of the present application, the height or length ratio of the first sub-surface 2031 can also be controlled by controlling the height of the retaining wall 21. For example, the higher the height of the retaining wall 21, the greater the height or length ratio of the first sub-surface 2031. Specifically, the height of the second retaining wall 212 can be increased, and / or the height of the first retaining wall 211 can be increased.

[0110] In addition, an embodiment of the present application further provides a display device, which includes the display panel described in the above embodiment.

[0111] It can be understood that, since the display device has the same beneficial effects as the display panel, the display device has the same beneficial effects as the display panel, and therefore, details thereof will not be repeated here.

[0112] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0113] In the above embodiments, the description of each embodiment is focused on, and the part not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0114] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0115] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment without departing from the technical solution content of the present application and in accordance with the technical essence of the present application still belongs to the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: array substrate; a pixel definition layer disposed on the array substrate, the pixel definition layer having a plurality of pixel openings formed therein, the pixel definition layer including a retaining wall disposed between adjacent pixel openings, the side surface of the retaining wall adjacent to the pixel openings including a first subsurface and a second subsurface, the first subsurface being located between the array substrate and the second subsurface, and the contact angle of the first subsurface being smaller than the contact angle of the second subsurface; a hole injection layer, comprising a hole injection portion disposed within the pixel opening; a light-emitting layer, comprising a light-emitting portion disposed in the pixel opening and located on a side of the hole injection portion away from the array substrate; a functional electrode layer, disposed on the pixel definition layer and extending into the pixel opening, wherein the functional electrode layer located in the pixel opening is located on a side of the light-emitting portion away from the hole injection portion; In which, the first sub-surface has a first height along the thickness direction of the display panel, the retaining wall has a second height along the thickness direction of the display panel, and the ratio of the first height to the second height is greater than or equal to 0.5; the edge of the hole injection part extends to the side surface, the functional electrode layer extends to the side surface and is connected to the hole injection part, and the connection between the hole injection part and the functional electrode layer is located on the first sub-surface and on the side of the first sub-surface close to the second sub-surface.

2. The display panel according to claim 1, wherein: The orthographic projection of the light emitting portion on the array substrate is located within the orthographic projection of the hole injection portion on the array substrate.

3. The display panel according to claim 1, wherein: In the pixel opening, an edge of at least one side of the light-emitting portion is spaced apart from the side surface, and the functional electrode layer covers the light-emitting portion and extends to the side surface to be connected to the hole injection portion.

4. The display panel according to claim 1, wherein: The functional electrode layer includes a cathode layer, and the hole injection portion is connected to the cathode layer at the side surface; Alternatively, the functional electrode layer includes an electron transport layer and the cathode layer, and the electron transport layer is located between the light-emitting portion and the cathode layer, and at the side surface, the hole injection portion is connected to the electron transport layer.

5. The display panel according to claim 1, wherein: The display panel further includes a hole transport layer disposed between the hole injection layer and the light emitting layer, the hole transport layer including a hole transport portion disposed between the hole injection portion and the light emitting portion and located within the pixel opening; In the pixel opening, an edge of at least one side of the hole transport portion is spaced apart from the side surface, and the functional electrode layer covers the light emitting portion and the hole transport portion and extends to the side surface to connect with the hole injection portion.

6. The display panel according to claim 1, wherein: The display panel further includes: a hole injection layer, comprising a hole injection portion disposed within the pixel opening; a light-emitting layer, comprising a light-emitting portion disposed in the pixel opening and located on a side of the hole injection portion away from the array substrate; a functional electrode layer, disposed on the pixel definition layer and extending into the pixel opening, wherein the functional electrode layer located in the pixel opening is located on a side of the light-emitting portion away from the hole injection portion; Wherein, the hole injection portion is spaced apart from the functional electrode layer.

7. The display panel according to any one of claims 1 to 6, characterized in that: The first sub-surface is connected to the second sub-surface, and the first sub-surface and the second sub-surface intersect at a predetermined angle at the connection point, and the predetermined angle is less than or equal to 180°.

8. The display panel according to any one of claims 1 to 6, characterized in that: The first sub-surface includes a first side close to the array substrate and a second side away from the array substrate, the second sub-surface includes a third side close to the array substrate and a fourth side away from the array substrate, a first distance is between the first side and the second side, a second distance is between the third side and the fourth side, and a ratio of the first distance to the second distance is greater than or equal to 1.

9. The display panel according to any one of claims 1 to 6, characterized in that: The first sub-surface is hydrophilic, and the second sub-surface is hydrophobic.

10. The display panel according to any one of claims 1 to 6, characterized in that: The plurality of pixel openings are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect; The retaining wall includes a first sub-portion and a plurality of second sub-portions stacked together, wherein the first sub-portion is located between the array substrate and the second sub-portions, and the first sub-portion extends along the first direction and the second direction and is arranged around each of the pixel openings; The second sub-section extends along the second direction, multiple second sub-sections are arranged along the first direction, multiple pixel openings arranged along the second direction are arranged between two adjacent second sub-sections, and the second sub-section has the first sub-surface and the second sub-surface on the side close to the pixel opening.

11. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 10.

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