Chip for perfecting function safety mechanism and capacitance detection circuit thereof

Abstract

The embodiment of the invention provides a chip for perfecting a function safety mechanism and a capacitance detection circuit thereof. The capacitance detection circuit comprises a detection module and a logic processing module, the detection module detects an output current of a power tube in a soft start process of a chip to obtain an output detection current and determines a current detection signal according to whether the output detection current is greater than a preset current, and the logic processing module outputs a current detection signal after the soft start of the chip is finished. According to whether the current detection signal is greater than the preset voltage or not, the capacitor state indication signal is determined, an off-chip capacitor can be indicated to be abnormal when the output current of the power tube is abnormal, and the off-chip capacitor can be indicated to be normal when the output current of the power tube is normal, so that indication can be performed when the off-chip capacitor is abnormal so as to perfect a function safety mechanism of a chip; and meanwhile, the output voltage of the power tube is not influenced, so that the normal starting of the chip is not influenced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and more particularly to a chip and a capacitance detection circuit thereof for improving a functional safety mechanism. Background Art

[0002] Linear regulators are widely used in power supply systems in various fields due to their simple structure, easy application, small area, low cost and no switching noise. For example, in consumer electronics such as household appliances and mobile communication devices, industrial electronics such as server memory and motor drive control, and automotive electronics such as vehicle-mounted millimeter-wave radar and vehicle-mounted cameras, linear regulators are used as post-stage regulators in switching power supply circuits in power supply systems. A large capacitor is usually set at the output end of the linear regulator as an output capacitor to play a role in voltage stabilization and filtering. If the output capacitor is placed outside the chip, it is called an off-chip capacitor. If the output capacitor is placed inside the chip, it is called an on-chip capacitor. The number of products and application scenarios of off-chip capacitor linear regulators are far greater than those of on-chip capacitor linear regulators.

[0003] In the linear regulator, the off-chip capacitor needs to be connected to the pin of the off-chip capacitor through the bonding wire and the chip pin. The abnormality of the off-chip capacitor connection includes the breakage of the bonding wire and the cold soldering of the pin. The abnormality of the off-chip capacitor itself includes the abnormal capacitance of the off-chip capacitor. The above-mentioned abnormality of the off-chip capacitor will affect the normal operation of the linear regulator. However, the above-mentioned abnormality of the off-chip capacitor is unpredictable during the chip manufacturing and use process. For users, it is expected that they can get corresponding prompts when the off-chip capacitor is abnormal, so as to improve the functional safety mechanism of the chip. Summary of the invention

[0004] The present disclosure provides a chip for improving the functional safety mechanism and a capacitance detection circuit thereof, which can indicate when the off-chip capacitance is abnormal, so as to improve the functional safety mechanism of the chip without affecting the normal startup of the chip.

[0005] In a first aspect, the present disclosure provides a capacitance detection circuit of a chip for improving a functional safety mechanism, wherein the chip includes a power tube and an output pin, and the output end of the power tube is connected to an off-chip capacitor through the output pin. The capacitance detection circuit includes a detection module and a logic processing module, wherein the input end of the detection module is connected to the output end of the power tube, the control end of the detection module is connected to the control end of the power tube, and the output end of the detection module is connected to the input end of the logic processing module.

[0006] The detection module is configured to detect the output current of the power tube during the soft start process of the chip to obtain the output detection current, and determine the current detection signal according to whether the output detection current is greater than a preset current, wherein the preset current is used to characterize the critical current of the abnormal capacitor connected to the output end of the power tube.

[0007] The logic processing module is configured to determine a capacitance state indication signal according to whether the current detection signal is greater than a preset voltage after the chip soft start is completed, and the capacitance state indication signal includes a capacitance normal signal and a capacitance abnormal signal.

[0008] In some embodiments of the present disclosure, the detection module includes a current generating unit and a current mirror unit, the first output end of the current generating unit is connected to the first bias end of the current mirror unit, the second output end of the current generating unit is connected to the output end of the current mirror unit and the input end of the logic processing module, the input end of the current mirror unit is connected to the output end of the power tube, and the second bias end of the current mirror unit is connected to the control end of the power tube.

[0009] The current generating unit is configured to generate a bias current and the preset current according to a constant current during the soft start process of the chip, and provide the bias current to the current mirror unit; when the output detection current is less than the preset current, pull down the input end of the logic processing module to a first level to obtain the current detection signal.

[0010] The current mirror unit is configured to, during the soft start process of the chip, mirror the output current into the output detection current, and when the output detection current is greater than or equal to the preset current, pull up the input end of the logic processing module to a second level to obtain the current detection signal.

[0011] In some embodiments of the present disclosure, the current generating unit includes a first current source, a first transistor, a second transistor and a third transistor, the second transistor and the third transistor are matched, the power supply end of the first current source is connected to an external power supply, the output end of the first current source is connected to the second end of the first transistor, the control end of the first transistor, the control end of the second transistor and the control end of the third transistor, the first end of the first transistor, the first end of the second transistor and the first end of the third transistor are grounded, the second end of the second transistor is connected to the first bias end of the current mirror unit, and the second end of the third transistor is connected to the input end of the logic processing module.

[0012] The first current source is configured to provide the constant current during the soft start of the chip. The current generating unit is further configured to mirror the constant current into the bias current and the preset current during the soft start of the chip, and the bias current and the preset current are equal.

[0013] In some embodiments of the present disclosure, the current mirror unit includes a fourth transistor, a fifth transistor, a sixth transistor, a first resistor and a second resistor, the first resistor and the second resistor are matched, the fourth transistor and the fifth transistor are matched, and the preset current is equal to the bias current.

[0014] The first end of the fourth transistor is connected to the output end of the power tube through the first resistor, the first end of the fifth transistor is connected to the second end of the sixth transistor through the second resistor, the control end of the sixth transistor is connected to the control end of the power tube, the first end of the sixth transistor is connected to an external power supply, the control end of the fourth transistor is connected to the second end of the fourth transistor, the control end of the fifth transistor and the first output end of the current generating unit, and the second end of the fifth transistor is connected to the second output end of the current generating unit and the input end of the logic processing module.

[0015] In some embodiments of the present disclosure, the logic processing module includes a comparison unit and a logic unit, the input end of the comparison unit is connected to the output end of the detection module, the output end of the comparison unit is connected to the input end of the logic unit, and the output end of the logic unit is connected to the output end of the capacitance detection circuit.

[0016] The comparison unit is configured to output a first level when the current detection signal is greater than or equal to the preset voltage during the soft start of the chip, and output a second level when the current detection signal is less than the preset voltage.

[0017] The logic unit is configured to, after the chip soft start ends, generate the normal capacitance signal according to the first level when the current detection signal is greater than or equal to the preset voltage, and generate the abnormal capacitance signal according to the second level when the current detection signal is less than the preset voltage.

[0018] In some embodiments of the present disclosure, the logic unit includes an inverting Schmitt trigger, a D flip-flop and an AND gate, the input end of the inverting Schmitt trigger is connected to the output end of the comparison unit, the output end of the inverting Schmitt trigger is connected to the clock end of the D flip-flop, the input end of the D flip-flop is used to receive an inverted signal of a soft start process signal, the reset end of the D flip-flop is used to receive a chip enable signal, the inverting output end of the D flip-flop is connected to the first input end of the AND gate, and the second input end of the AND gate is used to receive the soft start process signal.

[0019] In some embodiments of the present disclosure, the comparison unit includes a second current source, a seventh transistor, an eighth transistor and a ninth transistor, the first end of the seventh transistor and the first end of the eighth transistor are connected to an external power supply, the control end of the seventh transistor is connected to the second end of the seventh transistor, the control end of the eighth transistor and the output end of the second current source, the power supply end of the second current source is grounded, the second end of the eighth transistor is connected to the second end of the ninth transistor and the input end of the logic unit, the control end of the ninth transistor is connected to the output end of the detection module, and the first end of the ninth transistor is grounded.

[0020] In some embodiments of the present disclosure, the logic unit further includes a delay device, an input end of the delay device is connected to an output end of the inverting Schmitt trigger, and an output end of the delay device is connected to a clock end of the D flip-flop.

[0021] In some embodiments of the present disclosure, the comparison unit further includes a capacitor, a first plate of the capacitor is connected to an input terminal of the logic unit, and a second plate of the capacitor is grounded.

[0022] In a second aspect, the present disclosure provides a chip for improving a functional safety mechanism, comprising a power tube, an output pin, and any capacitance detection circuit provided in the first aspect, wherein the output end of the power tube is connected to an off-chip capacitor through the output pin.

[0023] The technical solution disclosed in the present invention provides a capacitance detection circuit of a chip, including a detection module and a logic processing module. During the soft start process of the chip, the detection module detects the output current of the power tube to obtain the output detection current, and determines the current detection signal according to whether the output detection current is greater than the preset current. After the soft start of the chip is completed, the logic processing module determines the capacitance state indication signal according to whether the current detection signal is greater than the preset voltage. When the output current of the power tube is abnormal, it can indicate that the off-chip capacitance is abnormal, and when the output current of the power tube is normal, it can indicate that the off-chip capacitance is normal. Therefore, it can indicate when the off-chip capacitance is abnormal, so as to improve the functional safety mechanism of the chip, and at the same time will not affect the output voltage of the power tube, and thus will not affect the normal startup of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure, wherein:

[0025] Figure 1 A schematic diagram of the internal structure of a chip provided in an embodiment of the present disclosure.

[0026] Figure 2 A schematic diagram of the external structure of a chip provided in an embodiment of the present disclosure.

[0027] Figure 3 A schematic diagram of the structure of a capacitance detection circuit provided in an embodiment of the present disclosure.

[0028] Figure 4 A schematic diagram of the structure of another capacitance detection circuit provided in an embodiment of the present disclosure.

[0029] Figure 5 A schematic diagram of the structure of another capacitance detection circuit provided in an embodiment of the present disclosure.

[0030] Figure 6 A timing diagram of a D flip-flop provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0033] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0034] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0035] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0036] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two), and similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0037] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0038] The chip provided in the present disclosure may be an off-chip capacitor linear regulator, or may be other chips connected to an off-chip capacitor. The present disclosure does not impose any specific limitation on this. The embodiments of the present disclosure are only described by taking an off-chip capacitor linear regulator as an example.

[0039] Figure 1 A schematic diagram of the internal structure of a chip provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the chip 10 includes an error amplifier EA, a power tube M_Power and a feedback network 11, wherein the inverting input terminal of the error amplifier EA receives a reference voltage Vref, the non-inverting input terminal of the error amplifier EA is connected to the output terminal of the feedback network 11 to receive the feedback voltage Vfb provided by the feedback network 11, and the output terminal of the error amplifier EA is connected to the control terminal of the power tube M_Power, and the control voltage of the power tube M_Power can be determined according to the reference voltage Vref and the feedback voltage Vfb.

[0040] The input end of the power tube M_Power is connected to an external power supply to receive the power supply voltage Vcc provided by the external power supply. The output end of the power tube M_Power is connected to the input end of the feedback network 11 and the output end of the chip 10. The power tube M_Power can adjust the output voltage of the chip 10 according to the control voltage to suppress the input voltage ripple noise of the chip 10 and the influence of load changes on the output voltage of the chip 10, thereby stabilizing the output voltage of the chip 10.

[0041] For example, Figure 2 A schematic diagram of the external structure of a chip provided in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the chip 10 also includes an output pin Pin_out, the output end of the power tube M_Power is connected to one end of the output pin Pin_out through a bonding line, the other end of the output pin Pin_out is connected to the first plate of the off-chip capacitor Coff, and the second plate of the off-chip capacitor Coff is grounded.

[0042] During chip manufacturing and use, the off-chip capacitor Coff may have random failures, for example, the off-chip capacitor Coff has an abnormal capacitance, such as Figure 2 The bonding line between the output end of the power tube M_Power and the output pin Pin_out shown in part (a) is broken and Figure 2 A poor solder joint between the output pin Pin_out and the external capacitor Coff shown in part (b) may cause an abnormal connection of the external capacitor Coff or an abnormality of the external capacitor Coff itself.

[0043] Since the capacitance of the capacitor connected to the output end of the power tube M_Power will affect multiple index parameters such as the stability of the internal loop of the chip 10, loop bandwidth, surge voltage, overshoot voltage and undershoot voltage during load step, the random failure of the off-chip capacitor Coff will affect the capacitance of the capacitor connected to the output end of the power tube M_Power, thereby affecting the normal operation of the chip 10. However, the random failure of the off-chip capacitor Coff is unpredictable, which brings difficulties to chip design. For users, it is expected that corresponding prompts can be obtained when the off-chip capacitor is abnormal.

[0044] Usually, the current I provided by the fixed current source can flow into the output end of the power tube M_Power within a fixed time T, and the output voltage V of the power tube M_Power can be detected. According to C'V=IT, C'=IT / V can be obtained, where C' is the capacitance of the capacitor connected to the output end of the power tube M_Power. However, if the above solution is adopted, in the case of abnormal connection of the off-chip capacitor Coff, the output voltage V of the power tube M_Power will rise rapidly, affecting the normal startup process of the chip 10.

[0045] In view of this, the chip 10 provided in the embodiment of the present disclosure also includes a capacitor detection circuit. During the soft start process of the chip, the capacitor detection circuit determines a current detection signal based on whether the output detection current is greater than a preset current. After the chip soft start is completed, the capacitor detection circuit determines a capacitor status indication signal based on whether the current detection signal is greater than a preset voltage. It can indicate that the off-chip capacitor is abnormal when the output current of the power tube is abnormal, and indicate that the off-chip capacitor is normal when the output current of the power tube is normal. Therefore, it can indicate when the off-chip capacitor is abnormal, so as to improve the functional safety mechanism of the chip, and at the same time will not affect the output voltage of the power tube, and thus will not affect the normal startup of the chip.

[0046] The capacitance detection circuit provided by the present disclosure is described in detail below with reference to several specific embodiments.

[0047] Figure 3 A schematic diagram of a capacitance detection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the capacitance detection circuit 100 includes a detection module 110 and a logic processing module 120, wherein the input end of the detection module 110 is connected to the output end of the power tube M_Power, the control end of the detection module 110 is connected to the control end of the power tube M_Power, and the output end of the detection module 110 is connected to the input end of the logic processing module 120.

[0048] The detection module 110 is configured to detect the output current Ids of the power tube M_Power during the soft start process of the chip 10 to obtain the output detection current Ids', and determine the current detection signal Vpre according to whether the output detection current Ids' is greater than the preset current Ith. The preset current Ith is used to characterize the critical current of the abnormal capacitor connected to the output end of the power tube M_Power.

[0049] The logic processing module 120 is configured to determine the capacitance state indication signal Si_Coff according to whether Vpre is greater than a preset voltage Vth after the soft start of the chip 10 is completed. The capacitance state indication signal Si_Coff includes a capacitance normal signal and a capacitance abnormal signal.

[0050] For example, Figure 3 As shown, during the soft start process of the chip 10, the output voltage V of the power tube M_Power will rise linearly within the set soft start time t. According to C'*V=Ids*t, when the soft start time t and the output voltage V of the power tube M_Power are determined, the output current Ids of the power tube M_Power is proportional to the capacitance of the capacitor connected to the output end of the power tube M_Power. Therefore, the output current Ids of the power tube M_Power can be used to determine whether the capacitor connected to the output end of the power tube M_Power is abnormal, that is, whether the off-chip capacitor Coff is abnormal.

[0051] Continue to see Figure 3 The detection module 110 includes a current generating unit 111 and a current mirror unit 112, wherein a first output end of the current generating unit 111 is connected to a first bias end of the current mirror unit 112, a second output end of the current generating unit 111 is connected to an output end of the current mirror unit 112 and an input end of the logic processing module 120, an input end of the current mirror unit 112 is connected to an output end of the power tube M_Power, and a second bias end of the current mirror unit 112 is connected to a control end of the power tube M_Power.

[0052] For example, Figure 4 A schematic diagram of another capacitance detection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the current generating unit 111 includes a first current source IB1 , a first transistor M1 , a second transistor M2 , and a third transistor M3 , wherein the second transistor M2 and the third transistor M3 are matched.

[0053] A power supply end of the first current source IB1 is connected to an external power supply, an output end of the first current source IB1 is connected to a second end of the first transistor M1, a control end of the first transistor M1, a control end of the second transistor M2, and a control end of the third transistor M3, a first end of the first transistor M1, a first end of the second transistor M2, and a first end of the third transistor M3 are grounded, a second end of the second transistor M2 is connected to a first bias end of the current mirror unit 112, and a second end of the third transistor M3 is connected to an input end of the logic processing module 120.

[0054] Exemplarily, the first transistor M1, the second transistor M2 and the third transistor M3 are N-metal oxide semiconductor field effect transistors (NMOS), the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3 are grounded, and the drain of the first transistor M1 and the gate of the first transistor M1 are connected to the output end of the first current source IB1 to receive the constant current Icc provided by the first current source during the soft start process of the chip 10.

[0055] The gate of the second transistor M2 is connected to the gate of the first transistor M1 and the drain of the first transistor M1, and the drain of the second transistor M2 is connected to the first bias end of the current mirror unit 112. During the soft start process of the chip 10, the second transistor M2 can mirror the constant current Icc into a bias current Ibia and provide the bias current Ibia to the current mirror unit 112.

[0056] The gate of the third transistor M3 is connected to the gate of the first transistor M1 and the drain of the first transistor M1, and the drain of the third transistor M3 is connected to the output end of the detection module 110. During the soft start process of the chip 10, the third transistor M3 can mirror the constant current Icc into a preset current Ith and provide it to the output end of the detection module 110.

[0057] Exemplarily, the second transistor M2 and the third transistor M3 are matched, which means that the width-to-length ratio of the second transistor M2 and the third transistor M3 is equal and the external environment of the second transistor M2 and the third transistor M3 is the same, so the bias current Ibia is equal to the preset current Ith, that is, Ibia=Ith. Since the first transistor M1, the second transistor M2 and the third transistor M3 form a current mirror structure, the first transistor M1, the second transistor M2 and the third transistor M3 all work in the saturation region, so the preset current Ith can be understood as the current when the third transistor M3 works in the saturation region.

[0058] In this way, during the soft start process of the chip 10, the current generating unit 111 can mirror the constant current Icc into a bias current Ibia and a preset current Ith, and the bias current Ibia and the preset current Ith are equal, so as to generate equal bias current Ibia and preset current Ith according to the constant current Icc, and provide the bias current Ibia to the current mirror unit 112, and the preset current Ith is provided to the output end of the detection module 110.

[0059] Continue to see Figure 4 The current mirror unit 112 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first resistor R1 and a second resistor R2, wherein the first resistor R1 and the second resistor R2 match, the fourth transistor M4 and the fifth transistor M5 match, and the bias current Ibia is equal to the preset current Ith.

[0060] The first end of the fourth transistor M4 is connected to the output end of the power tube M_Power through the first resistor R1, the first end of the fifth transistor M5 is connected to the second end of the sixth transistor M6 through the second resistor R2, the control end of the sixth transistor M6 is connected to the control end of the power tube M_Power, the first end of the sixth transistor M6 is connected to an external power supply, the control end of the fourth transistor M4 is connected to the second end of the fourth transistor M4, the control end of the fifth transistor M5 and the first output end of the current generating unit 111, and the second end of the fifth transistor M5 is connected to the second output end of the current generating unit 111 and the input end of the logic processing module 120.

[0061] Exemplarily, the power transistor M_Power, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are PMOS, and the gate of the fourth transistor M4 is connected to the drain of the fourth transistor and the drain of the second transistor M2 to receive the bias current Ibia provided by the second transistor M2.

[0062] The gate of the fifth transistor M5 is connected to the gate of the fourth transistor M4 and the drain of the fourth transistor, the fourth transistor M4 and the fifth transistor M5 are matched, the current flowing through the fourth transistor M4 is equal to the current flowing through the fifth transistor M5, the source of the fourth transistor M4 is connected to the drain of the power tube M_Power through the first resistor R1, the source of the fifth transistor M5 is connected to the drain of the sixth transistor M6 through the second resistor R2, and the current flowing through the first resistor R1 is equal to the current flowing through the second resistor R2.

[0063] The first resistor R1 matches the second resistor R2, which means that the resistance values ​​of the first resistor R1 and the second resistor R2 are equal, the sizes of the first resistor R1 and the second resistor R2 are equal, and the external environments of the first resistor R1 and the second resistor R2 are the same, so the output voltage V of the power tube M_Power is equal to the drain voltage of the sixth transistor M6, that is, the drain voltage of the power tube M_Power is equal to the drain voltage of the sixth transistor M6.

[0064] The gate of the power tube M_Power is connected to the gate of the sixth transistor M6, and the gate voltage of the power tube M_Power is equal to the gate voltage of the sixth transistor M6. The source of the power tube M_Power and the source of the sixth transistor M6 are connected to an external power supply, and the source voltage of the power tube M_Power is equal to the source voltage of the sixth transistor M6. Therefore, during the soft start process of the chip 10, no matter whether the power tube M_Power works in the saturation region or the linear region, the sixth transistor M6 can mirror the output current Ids of the power tube M_Power to obtain the output detection current Ids'.

[0065] In this way, during the soft start process of the chip 10 , the current mirror unit 112 can mirror the output current Ids of the power tube M_Power into the output detection current Ids′.

[0066] During the soft start process of the chip 10, when the off-chip capacitor Coff is abnormal, the capacitance of the capacitor connected to the output end of the power tube M_Power is small, and the output current Ids of the power tube M_Power is small, then the output detection current Ids' is also small, and is smaller than the current when the third transistor M3 works in the saturation region, that is, the output detection current Ids' is smaller than the preset current Ith.

[0067] At this time, the third transistor M3 can pull down the input terminal of the logic processing module 120 to the first level, and the obtained current detection signal Vpre is the first level, for example, the first level is a low level.

[0068] When the off-chip capacitor Coff is normal, the capacitance of the capacitor connected to the output end of the power tube M_Power is large, the output current Ids of the power tube M_Power is large, and the output detection current Ids' is also large and greater than or equal to the preset current Ith.

[0069] At this time, the sixth transistor M6 can pull up the input terminal of the logic processing module 120 to the second level, and the obtained current detection signal Vpre is the second level, for example, the second level is a high level.

[0070] In this way, during the soft start process of the chip 10, when the output detection current Ids' is less than the preset current Ith, the current generating unit 111 pulls down the input end of the logic processing module 120 to a low level to obtain the current detection signal Vpre; when the output detection current Ids' is greater than or equal to the preset current Ith, the current mirror unit 112 pulls up the input end of the logic processing module 120 to a high level to obtain the current detection signal Vpre.

[0071] For example, see Figure 3 The logic processing module 120 includes a comparison unit 121 and a logic unit 122. The input end of the comparison unit 121 is connected to the output end of the detection module 110, the output end of the comparison unit 121 is connected to the input end of the logic unit 122, and the output end of the logic unit 122 is connected to the output end of the capacitance detection circuit 100.

[0072] During the soft start process of the chip 10, the comparison unit 121 can receive the current detection signal Vpre, and compare the current detection signal Vpre with the internal preset voltage Vth. When the off-chip capacitor Coff is abnormal, the current detection signal Vpre is at a low level, and the low level is less than the preset voltage Vth, then the current detection signal Vpre is less than the preset voltage Vth, and the comparison unit 121 outputs a high level. After the soft start of the chip 10 is completed, the logic unit 122 can generate a capacitance abnormality signal according to the high level, for example, the capacitance abnormality signal is a high level.

[0073] When the off-chip capacitor Coff is normal, the current detection signal Vpre is at a high level, and the high level is greater than or equal to the preset voltage Vth, then the current detection signal Vpre is greater than or equal to the preset voltage Vth, and the comparison unit 121 outputs a low level. After the soft start of the chip 10 ends, the logic unit 122 can generate a capacitor normal signal according to the low level, for example, the capacitor normal signal is a low level.

[0074] In the disclosed embodiment, the capacitor detection circuit includes a detection module and a logic processing module. During the soft start process of the chip, the detection module detects the output current of the power tube to obtain the output detection current, and determines the current detection signal according to whether the output detection current is greater than the preset current. After the soft start of the chip is completed, the logic processing module determines the capacitor status indication signal according to whether the current detection signal is greater than the preset voltage. When the output current of the power tube is abnormal, it can indicate that the off-chip capacitor is abnormal, and when the output current of the power tube is normal, it can indicate that the off-chip capacitor is normal, so as to improve the functional safety mechanism of the chip. Therefore, it can indicate when the off-chip capacitor is abnormal, and at the same time will not affect the output voltage of the power tube, and thus will not affect the normal startup of the chip.

[0075] In some embodiments, Figure 5 A structural diagram of another capacitance detection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the comparison unit 121 includes a second current source IB2, a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9.

[0076] Among them, the first end of the seventh transistor M7 and the first end of the eighth transistor M8 are connected to an external power supply, the control end of the seventh transistor M7 is connected to the second end of the seventh transistor M7, the control end of the eighth transistor M8 and the output end of the second current source IB2, the power supply end of the second current source IB2 is grounded, the second end of the eighth transistor M8 is connected to the second end of the ninth transistor M9 and the input end of the logic unit 122, the control end of the ninth transistor M9 is connected to the output end of the detection module 110, and the first end of the ninth transistor M9 is grounded.

[0077] Exemplarily, the seventh transistor M7 and the eighth transistor M8 are PMOS, the ninth transistor M9 is NMOS, the source of the seventh transistor M7 and the source of the eighth transistor M8 are connected to an external power supply, and the gate of the seventh transistor M7 and the drain of the seventh transistor M7 are connected to the second current source IB2 to receive the current provided by the second current source IB2.

[0078] The gate of the eighth transistor M8 is connected to the gate of the seventh transistor M7 and the drain of the seventh transistor M7, and the drain of the eighth transistor M8 is connected to the drain of the ninth transistor M9 and the input end of the logic unit 122. During the soft start process of the chip 10, the eighth transistor M8 can mirror the current provided by the second current source IB2 to the drain of the ninth transistor M9.

[0079] The gate of the ninth transistor M9 is connected to the output end of the detection module 110, the source of the ninth transistor M9 is grounded, the gate voltage of the ninth transistor M9 is equal to the current detection signal Vpre, the gate-source voltage of the ninth transistor M9 is equal to the gate voltage of the ninth transistor M9, and the gate-source voltage of the ninth transistor M9 is equal to the current detection signal Vpre.

[0080] When the off-chip capacitor Coff is abnormal, the current detection signal Vpre is at a low level, and the low level is less than the threshold voltage of the ninth transistor M9, then the gate-source voltage of the ninth transistor M9 is less than the threshold voltage of the ninth transistor M9, and the ninth transistor M9 is turned off. The threshold voltage of the ninth transistor M9 is defined as a preset voltage Vth, at which time the current detection signal Vpre is less than the preset voltage Vth, and the eighth transistor M8 pulls the drain of the ninth transistor M9 to a high level, that is, pulls the input end of the logic unit 122 to a high level.

[0081] When the off-chip capacitor Coff is normal, the current detection signal Vpre is at a high level, and the high level is greater than or equal to the threshold voltage of the ninth transistor M9. The gate-source voltage of the ninth transistor M9 is greater than or equal to the threshold voltage of the ninth transistor M9, and the ninth transistor M9 is turned on. At this time, the current detection signal Vpre is greater than or equal to the preset voltage Vth, and the ninth transistor M9 pulls the drain of the ninth transistor M9 down to a low level, that is, pulls the input end of the logic unit 122 down to a low level.

[0082] In some embodiments, see Figure 5 , the logic unit 122 includes an inverting Schmitt trigger 1221, a D flip-flop 1222 and an AND gate AND.

[0083] Among them, the input end of the inverting Schmitt trigger 1221 is connected to the output end of the comparison unit 121, the output end of the inverting Schmitt trigger 1221 is connected to the clock end of the D flip-flop 1222, the input end of the D flip-flop 1222 is used to receive the inverted signal SSOK_B of the soft start process signal, the reset end of the D flip-flop 1222 is used to receive the chip enable signal ICEN, the inverting output end of the D flip-flop 1222 is connected to the first input end of the AND gate AND, and the second input end of the AND gate AND is used to receive the soft start process signal SSOK.

[0084] Exemplarily, the soft start process signal SSOK is used to indicate whether the soft start is completed. For example, if the soft start process signal SSOK is at a low level, the inverted signal SSOK_B of the soft start process signal is at a high level, indicating that the soft start is not completed. If the soft start process signal SSOK is at a high level, the inverted signal SSOK_B of the soft start process signal is at a low level, indicating that the soft start is completed.

[0085] The chip enable signal ICEN is used to indicate whether the chip is working. For example, if the chip enable signal ICEN is at a high level, it indicates that the chip is in a working state. If the chip enable signal ICEN is at a low level, it indicates that the chip is in a stopped working state.

[0086] Figure 6A timing diagram of a D flip-flop provided in an embodiment of the present disclosure, such as Figure 6 As shown, before time T1, the chip 10 has not started working, the chip enable signal ICEN is at a low level, the D flip-flop 1222 is in an initial state, and the output signal of the inverting output terminal of the D flip-flop 1222 is is high level, at this time the chip 10 has not started soft start, the soft start process signal SSOK is low level, and the capacitor state indication signal Si_Coff output by the AND gate AND is low level, that is, the output capacitor is normal signal.

[0087] At time T1, the chip 10 starts to work, the chip enable signal ICEN flips from low level to high level, and the chip 10 starts soft start. Obviously, the soft start of the chip 10 has not ended yet, so the soft start process signal SSOK maintains a low level, and the capacitor state indication signal Si_Coff maintains a low level.

[0088] At this time, when the off-chip capacitor Coff is abnormal, the comparison unit 121 outputs a high level, and the inverting Schmitt trigger 1221 outputs a low level, that is, the clock signal CLK of the D flip-flop 1222 is a low level, then the output signal of the inverting output terminal of the D flip-flop 1222 is When the off-chip capacitor Coff is normal, the comparison unit 121 outputs a low level, and the inverting Schmitt trigger 1221 outputs a high level, that is, the clock signal CLK of the D flip-flop 1222 is a high level, then the output signal of the inverting output terminal of the D flip-flop 1222 is Flips from high to low.

[0089] The soft start process of the chip 10 lasts from time T1 to time T2. During the time period T1-T2, when the off-chip capacitor Coff is abnormal, the clock signal CLK of the D flip-flop 1222 maintains a low level, and the output signal of the inverting output terminal of the D flip-flop 1222 is Maintaining a high level, when the off-chip capacitor Coff is normal, the clock signal CLK of the D flip-flop 1222 maintains a high level, then the output signal of the inverting output terminal of the D flip-flop 1222 Maintain low level.

[0090] At time T2, the soft start of chip 10 ends, and the soft start process signal SSOK flips from low level to high level. When the off-chip capacitor Coff is abnormal, the output signal of the inverting output terminal of the D flip-flop 1222 When the capacitor state indication signal Si_Coff output by the AND gate AND is high, it turns from low level to high level, that is, the output capacitor abnormality signal is turned on. When the off-chip capacitor Coff is normal, the output signal of the inverting output terminal of the D flip-flop 1222 is is at a low level, the capacitance state indication signal Si_Coff output by the AND gate AND maintains a low level.

[0091] In some embodiments, see Figure 5 The logic unit 122 further includes a delay device Delay, an input end of the delay device Delay is connected to the output end of the inverting Schmitt trigger 1221, and an output end of the delay device Delay is connected to the clock end of the D flip-flop 1222.

[0092] Exemplarily, the delay device Delay can delay the level output by the inverting Schmitt trigger 1221 to avoid the influence of the unstable external power supply on the capacitor state indication signal Si_Coff, thereby improving the accuracy of the capacitor state indication signal Si_Coff.

[0093] In some embodiments, see Figure 5 The comparison unit 121 further includes a capacitor C, a first plate of the capacitor C is connected to the input end of the logic unit 122, and a second plate of the capacitor C is grounded.

[0094] Exemplarily, the capacitor C is connected between the input terminal of the logic unit 122 and the ground, and the circuit noise can be filtered out to stabilize the voltage at the output terminal of the comparison unit 121, thereby avoiding the instantaneous mutation introduced by the circuit noise from affecting the output of the comparison unit 121, and further avoiding the instantaneous mutation introduced by the circuit noise from affecting the capacitor state indication signal Si_Coff, so as to improve the accuracy of the capacitor state indication signal Si_Coff.

[0095] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural form and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0096] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A capacitance detection circuit for a chip for improving a functional safety mechanism, characterized in that: The chip includes a power tube and an output pin, the output end of the power tube is connected to an off-chip capacitor through the output pin, and the capacitance detection circuit includes a detection module and a logic processing module; The input end of the detection module is connected to the output end of the power tube, the control end of the detection module is connected to the control end of the power tube, and the output end of the detection module is connected to the input end of the logic processing module; The detection module is configured to detect the output current of the power tube during the soft start process of the chip to obtain the output detection current, and determine the current detection signal according to whether the output detection current is greater than a preset current, wherein the preset current is used to characterize the critical current of the abnormal capacitor connected to the output end of the power tube; The logic processing module is configured to determine a capacitance state indication signal according to whether the current detection signal is greater than a preset voltage after the chip soft start is completed, and the capacitance state indication signal includes a capacitance normal signal and a capacitance abnormal signal.

2. The capacitance detection circuit according to claim 1, characterized in that: The detection module includes a current generating unit and a current mirror unit; The first output end of the current generating unit is connected to the first bias end of the current mirror unit, the second output end of the current generating unit is connected to the output end of the current mirror unit and the input end of the logic processing module, the input end of the current mirror unit is connected to the output end of the power tube, and the second bias end of the current mirror unit is connected to the control end of the power tube; The current generating unit is configured to generate a bias current and the preset current according to a constant current during the soft start process of the chip, and provide the bias current to the current mirror unit; When the output detection current is less than the preset current, the input terminal of the logic processing module is pulled down to a first level to obtain the current detection signal; The current mirror unit is configured to, during the soft start process of the chip, mirror the output current into the output detection current, and when the output detection current is greater than or equal to the preset current, pull up the input end of the logic processing module to a second level to obtain the current detection signal.

3. The capacitance detection circuit according to claim 2, characterized in that: The current generating unit comprises a first current source, a first transistor, a second transistor and a third transistor, wherein the second transistor matches the third transistor; A power supply terminal of the first current source is connected to an external power supply, an output terminal of the first current source is connected to a second terminal of the first transistor, a control terminal of the first transistor, a control terminal of the second transistor, and a control terminal of the third transistor, a first terminal of the first transistor, a first terminal of the second transistor, and a first terminal of the third transistor are grounded, a second terminal of the second transistor is connected to a first bias terminal of the current mirror unit, and a second terminal of the third transistor is connected to an input terminal of the logic processing module; The first current source is configured to provide the constant current during the soft start process of the chip; The current generating unit is further configured to, during the soft start process of the chip, mirror the constant current into the bias current and the preset current, wherein the bias current and the preset current are equal.

4. The capacitance detection circuit according to claim 2, characterized in that: The current mirror unit includes a fourth transistor, a fifth transistor, a sixth transistor, a first resistor and a second resistor, the first resistor matches the second resistor, the fourth transistor matches the fifth transistor, and the preset current is equal to the bias current; The first end of the fourth transistor is connected to the output end of the power tube through the first resistor, the first end of the fifth transistor is connected to the second end of the sixth transistor through the second resistor, the control end of the sixth transistor is connected to the control end of the power tube, the first end of the sixth transistor is connected to an external power supply, the control end of the fourth transistor is connected to the second end of the fourth transistor, the control end of the fifth transistor and the first output end of the current generating unit, and the second end of the fifth transistor is connected to the second output end of the current generating unit and the input end of the logic processing module.

5. The capacitance detection circuit according to any one of claims 1 to 4, characterized in that: The logic processing module includes a comparison unit and a logic unit; The input end of the comparison unit is connected to the output end of the detection module, the output end of the comparison unit is connected to the input end of the logic unit, and the output end of the logic unit is connected to the output end of the capacitance detection circuit; The comparison unit is configured to output a first level when the current detection signal is greater than or equal to the preset voltage during the soft start of the chip, and output a second level when the current detection signal is less than the preset voltage; The logic unit is configured to, after the chip soft start ends, generate the normal capacitance signal according to the first level when the current detection signal is greater than or equal to the preset voltage, and generate the abnormal capacitance signal according to the second level when the current detection signal is less than the preset voltage.

6. The capacitance detection circuit according to claim 5, characterized in that: The logic unit includes an inverting Schmitt trigger, a D flip-flop and an AND gate; The input end of the inverting Schmitt trigger is connected to the output end of the comparison unit, the output end of the inverting Schmitt trigger is connected to the clock end of the D trigger, the input end of the D trigger is used to receive the inverted signal of the soft start process signal, the reset end of the D trigger is used to receive the chip enable signal, the inverting output end of the D trigger is connected to the first input end of the AND gate, and the second input end of the AND gate is used to receive the soft start process signal.

7. The capacitance detection circuit according to claim 5, characterized in that: The comparison unit includes a second current source, a seventh transistor, an eighth transistor and a ninth transistor; The first end of the seventh transistor and the first end of the eighth transistor are connected to an external power supply, the control end of the seventh transistor is connected to the second end of the seventh transistor, the control end of the eighth transistor and the output end of the second current source, the power supply end of the second current source is grounded, the second end of the eighth transistor is connected to the second end of the ninth transistor and the input end of the logic unit, the control end of the ninth transistor is connected to the output end of the detection module, and the first end of the ninth transistor is grounded.

8. The capacitance detection circuit according to claim 6, characterized in that: The logic unit also includes a delay device; The input end of the delay device is connected to the output end of the inverting Schmitt trigger, and the output end of the delay device is connected to the clock end of the D flip-flop.

9. The capacitance detection circuit according to claim 5, characterized in that: The comparison unit also includes a capacitor; The first plate of the capacitor is connected to the input end of the logic unit, and the second plate of the capacitor is grounded.

10. A chip for improving functional safety mechanism, characterized in that: The invention comprises a power tube, an output pin and the capacitance detection circuit according to any one of claims 1 to 9, wherein the output end of the power tube is connected to an off-chip capacitor through the output pin.

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