System and method for constructing airborne intelligent calculation model

Abstract

The invention relates to the technical field of computers, in particular to a system and method for constructing an airborne intelligent calculation model. The system comprises a base layer used for generating an executable file corresponding to a target task; the operation scheduling layer is used for executing the executable file and scheduling computing resources; the execution framework layer is used for executing generation, loading and reasoning processing of a data processing model corresponding to the executable file; and the model layer is used for deploying the executable data processing model. The scheme can be applied to development of airborne intelligent applications.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a system and method for building an airborne intelligent computing model, a storage medium, a computer program product, and an electronic device. Background Art

[0002] In the relevant technologies, many application scenarios in the airborne field have application requirements for intelligent computing technology, such as radar obstacle target recognition, optoelectronic obstacle recognition, image stitching, map data processing, voice interaction, intelligent decision-making, etc. Currently, mature intelligent computing technologies and intelligent computing frameworks are applied on PCs and servers, and there is currently no intelligent computing framework available for airborne applications in the airborne field.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The present invention provides a system and method for constructing an airborne intelligent computing model, a computer program product, and an electronic device, which can be applied to the development of airborne intelligent applications, thereby overcoming the defects existing in the prior art to a certain extent.

[0005] Other features and advantages of the present invention will become apparent from the following detailed description, or may be learned in part by practice of the present invention.

[0006] According to a first aspect of the present invention, a system for constructing an airborne intelligent computing model is provided, the system comprising:

[0007] The basic layer is used to generate executable files corresponding to the target tasks;

[0008] The operation scheduling layer is used to execute the executable file and schedule computing resources;

[0009] An execution framework layer, used to generate, load and infer the data processing model corresponding to the executable file;

[0010] The model layer is used to deploy the executable data processing model.

[0011] In some exemplary embodiments, the base layer includes:

[0012] The programming development layer is used to provide a callable programming interface for building a data processing model corresponding to the target task;

[0013] A compilation optimization layer, used for scheduling hardware resources to compile and optimize the constructed data processing model;

[0014] The hardware enablement layer is used to provide schedulable hardware resources for the compilation optimization layer and the programming development layer.

[0015] In some exemplary embodiments, the operation scheduling layer includes:

[0016] Tensor acceleration engine, which provides a standard operator library that can be directly called;

[0017] An operation manager, configured to provide resource management functions for task allocation of intelligent applications; wherein the intelligent applications perform business data processing based on the data processing model;

[0018] The task scheduler is used to configure tasks for intelligent applications and collaborate with the operation manager to complete the task scheduling process.

[0019] In some exemplary embodiments, the task scheduler includes:

[0020] Scheduling interface, used for communication and data exchange with the operation manager and driver;

[0021] The scheduling engine is used to control the execution process of the task scheduling CPU;

[0022] The scheduling logic processing module is used to call the corresponding task module according to the task type corresponding to the current task to process the current task;

[0023] AI CPU scheduler, used for AI CPU status management and task scheduling;

[0024] The task block scheduler is used to distribute tasks processed by the task scheduling CPU to the AI ​​computing core;

[0025] System control module, used to configure the system and initialize chip functions;

[0026] Performance analysis module, used to monitor the execution process of tasks;

[0027] The log module is used to record the log data of the task scheduler.

[0028] In some exemplary embodiments, the scheduling logic processing module includes:

[0029] A kernel function execution module is used to schedule kernel functions to process corresponding computing tasks;

[0030] Direct storage access execution module, used to implement the scheduling logic of storage tasks;

[0031] The event execution module is used to implement the scheduling logic of synchronous control tasks and realize the logical processing of event dependencies between execution flows.

[0032] In some exemplary embodiments, the execution framework layer includes:

[0033] Offline model generator, used to convert model files and weight files into corresponding offline model files;

[0034] Offline model executor, used to load / unload offline models and compile programs for loaded offline models;

[0035] The process orchestrator is used to configure the process of the computing engine corresponding to the offline model;

[0036] AI model manager is used to control the initialization management and offline model loading of the corresponding processes on the device side.

[0037] According to a second aspect of the present invention, there is provided a method for constructing an onboard intelligent computing model, the method comprising:

[0038] Generate an executable file corresponding to the target task at the base layer, and send the executable file to the operation scheduling layer;

[0039] Executing the executable file in the operation scheduling layer and scheduling computing resources;

[0040] Using the execution framework layer to perform generation, loading and reasoning processing of the data processing model corresponding to the executable file;

[0041] The executable data processing model is deployed at the model layer.

[0042] According to a third aspect of the present invention, there is provided a computer program product having a computer program stored thereon, which implements the above-mentioned method for constructing an airborne intelligent computing model when the computer program is executed by a processor.

[0043] According to a fourth aspect of the present invention, there is provided an electronic device, comprising:

[0044] Processor; and

[0045] A memory, configured to store executable instructions of the processor;

[0046] Wherein, the processor is configured to implement the above-mentioned method for constructing an airborne intelligent computing model by executing the executable instructions.

[0047] According to a fifth aspect of the present invention, there is provided a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-mentioned method for constructing an airborne intelligent computing model.

[0048] The system for building an airborne intelligent computing model provided by the embodiment of the present invention sets a system architecture of a basic layer, an operation scheduling layer, an execution framework layer, and a model layer, uses the basic layer to generate an executable file corresponding to a target task, and sends the executable file to the operation scheduling layer; executes the executable file in the operation scheduling layer, and schedules computing resources; uses the execution framework layer to perform generation, loading, and reasoning processing of a data processing model corresponding to the executable file; and deploys the executable data processing model in the model layer. This enables the system to implement a layered airborne intelligent computing software stack structure, which can support mainstream computing frameworks such as TensorFlow, Caffe, and MindSpore, can support the development of airborne special operators, and can meet the needs of intelligent applications such as radar obstacle target recognition, optoelectronic obstacle recognition, image stitching, map data processing, voice interaction, and intelligent decision-making.

[0049] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0051] Figure 1 A schematic diagram of a hierarchical structure of a system for constructing an airborne intelligent computing model according to an exemplary embodiment of the present invention is schematically shown;

[0052] Figure 2 A schematic diagram of a system architecture of a system for constructing an airborne intelligent computing model according to an exemplary embodiment of the present invention is schematically shown;

[0053] Figure 3 A schematic diagram schematically illustrates a framework of an operation manager according to an exemplary embodiment of the present invention;

[0054] Figure 4 A schematic diagram schematically illustrates a functional framework of a task scheduler according to an exemplary embodiment of the present invention;

[0055] Figure 5 A schematic diagram schematically illustrating the working principle of an offline model generator according to an exemplary embodiment of the present invention;

[0056] Figure 6A schematic diagram schematically shows an exemplary embodiment of the present invention in which a process scheduler coordinates the entire computing engine process;

[0057] Figure 7 A schematic diagram schematically illustrates a method flow of an offline model management according to an exemplary embodiment of the present invention;

[0058] Figure 8 A schematic diagram schematically illustrates a method for constructing an airborne intelligent computing model according to an exemplary embodiment of the present invention;

[0059] Fig. 9 The figure schematically shows the composition of an electronic device in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present invention will be more comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0061] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0062] In view of the shortcomings and deficiencies of the prior art, a system and method for constructing an airborne intelligent computing model are provided in this example implementation. Below, the system for constructing an airborne intelligent computing model in this example implementation and each step of the corresponding method will be described in more detail in conjunction with the accompanying drawings and embodiments.

[0063] refer to Figure 1 As shown, the hierarchical architecture of the system may include: a basic layer 14, an operation scheduling layer 13, an execution framework layer 12 and a model layer 11, which are arranged in sequence.

[0064] Specifically, the basic layer 14 can be used to generate an executable file corresponding to the target task. The operation scheduling layer 13 can be used to execute the executable file and schedule computing resources. The execution framework layer 12 can be used to generate, load and reason about the data processing model corresponding to the executable file. The model layer 11 can be used to deploy the executable data processing model.

[0065] In this example implementation, reference Figure 2 As shown, the basic layer 11 includes: a programming development layer, a compilation optimization layer, and a hardware enabling layer which are arranged in sequence.

[0066] Specifically, the programming development layer can be used to provide a callable programming interface for building a data processing model corresponding to the target task. The compilation optimization layer can be used to schedule hardware resources to compile and optimize the constructed data processing model. The hardware enablement layer can be used to provide schedulable hardware resources for the compilation optimization layer and the programming development layer.

[0067] Exemplarily, the basic layer implements the basic core functions of the system framework, specifically including three sub-layers: programming development, compilation optimization, and hardware enablement. Among them, the programming development layer can serve as a window for developers to interact with the framework, providing developers with an API interface for building AI models. In addition, a graphical user interface can be configured in the programming development layer to facilitate users to enter code data, use programming languages ​​to edit the code data corresponding to the data processing model corresponding to the target task, and select the API interface to call. For example, the above-mentioned target tasks can be editing tasks for image recognition models and target tracking models. The compilation optimization layer is a key part of the system framework, responsible for compiling and optimizing the model and scheduling hardware resources to complete the calculation. The hardware enablement layer is a channel for the system framework to connect with the computing power hardware, helping developers shield the underlying hardware technology details.

[0068] In this example implementation, reference Figure 2 As shown, the operation scheduling layer 13 includes: a tensor acceleration engine, an operation manager, and a task scheduler. Among them, the tensor acceleration engine can be used to provide a standard operator library that can be directly called. The operation manager can be used to provide resource management functions for task allocation of intelligent applications; wherein, the intelligent application performs business data processing based on the data processing model. The task scheduler can be used to configure the tasks of the intelligent application and collaborate with the operation manager to complete the task scheduling process.

[0069] Specifically, in the construction of neural networks, operators are used to form network structures with different application functions. The tensor acceleration engine provides the intelligent computing platform with a standard operator library that is directly called by the application program. In addition, the tensor acceleration engine can be configured with an operator custom processing interface for user-defined operators. If an operator other than the standard operator library is called in the program, the custom operator development function provided by the tensor acceleration engine can be called to customize the operator and use the custom operator.

[0070] For example, the intelligent computing software stack can directly use the operators that have been developed internally. At the same time, the intelligent computing software stack also allows developers to develop custom operators according to their own needs. These operators can run on the AI ​​CPU or the AI ​​Core. At the same time, developers can develop operators through the C++ or TVM mechanism.

[0071] The development process of a custom operator mainly includes the following steps:

[0072] (1) Create a custom operator development project. This step can be done by quickly creating a new project directly through the integrated development environment, or by modifying the sample project that comes with the DDK.

[0073] (2) Custom operator development: Different types of operators can be developed in different ways.

[0074] (3) Custom plug-in development. It is called by the offline model generator and provides functions such as parameter parsing, shape inference, and kernel compilation.

[0075] (4) Load the plug-in to convert the model. When the offline model generator converts the model, it calls the plug-in to parse the parameters, infer the tensor shape, compile the operator provided in step (2) into a kernel, and insert it into the offline model.

[0076] Among them, developers need to program themselves: custom operator logic development and custom operator plug-in development.

[0077] Exemplarily, the operation manager can be used to provide resource management functions for task allocation of intelligent applications, and provide storage management, device management, execution flow management, event management and kernel function execution functions for intelligent applications, such as Figure 3 As shown in the figure. The upper layer of the operation manager provides the tensor acceleration engine with a standard arithmetic library and an offline model executor. The lower layer of the operation manager is a driver that interacts with the hardware of the intelligent computing platform. The operation manager provides various calling interfaces, such as storage interface, device interface, execution flow interface, event interface, and execution control interface. Different interfaces are controlled by the operation management engine to perform different functions.

[0078] In this example implementation, the task scheduler includes: a scheduling interface for communicating and exchanging data with the operation manager and the driver; a scheduling engine for controlling the execution process of the task scheduling CPU; a scheduling logic processing module for calling the corresponding task module according to the task type corresponding to the current task to process the current task; an AI CPU scheduler for state management and task scheduling of the AI ​​CPU; a task block scheduler for distributing tasks processed by the task scheduling CPU to the AI ​​computing core; a system control module for configuring the system and initializing chip functions; a performance analysis module for data monitoring of the execution process of the task; and a log module for recording log data of the task scheduler.

[0079] Specifically, refer to Figure 4 As shown in the figure, the task scheduler is usually located on the device side, and its functions are completed by the task scheduling CPU. The task scheduling CPU consists of a scheduling interface (Interface), a scheduling engine (Engine), a scheduling logic processing module, an AI CPU scheduler, a task block scheduler, a system control (SysCtrl) module, a performance analysis (Profile) and a log (Log) module.

[0080] The task scheduling CPU implements communication and interaction with the operation manager and driver through the scheduling interface. The task results are transmitted to the task scheduling engine. As the main body of task scheduling, the task scheduling engine is responsible for implementing the processes such as task organization, task dependency and task scheduling control, and manages the execution process of the entire task scheduling CPU. The task scheduling engine divides tasks into three types: computing, storage and control according to the specific type of tasks, distributes them to different scheduling logic processing modules, and starts the management and scheduling of specific kernel function tasks, storage tasks, and event dependencies between execution flows.

[0081] In this example implementation, the scheduling logic processing module includes: a kernel function execution module, which is used to schedule kernel functions to process corresponding computing tasks; a direct storage access execution module, which is used to implement the scheduling logic of storage tasks; and an event execution module, which is used to implement the scheduling logic of synchronous control tasks and realize the logical processing of event dependencies between execution flows.

[0082] Exemplarily, the logic processing module is divided into a kernel execution module (Kernel Execute), a direct memory access execution module (DMA Execute) and an event execution module (Event Execute). The kernel execution module performs scheduling processing for computing tasks, implements the scheduling logic of tasks on the AI ​​CPU and AI Core, and schedules specific kernel functions. The direct memory access execution module implements the scheduling logic of storage tasks and schedules memory copies, etc. The event execution module is responsible for implementing the scheduling logic of synchronous control tasks and implementing the logic processing of event dependencies between execution flows. After completing the scheduling logic processing of different types of tasks, it is directly handed over to the corresponding control unit for hardware execution.

[0083] Specifically, the kernel execution module (Kernel Execute) can be used to schedule computing tasks, implement the scheduling logic of tasks on the AI ​​CPU and AI Core, and schedule specific kernel functions. The direct memory access execution module (DMA Execute) is used to implement the scheduling logic of storage tasks and schedule memory copies, etc. The event execution module (Event Execute) is responsible for implementing the scheduling logic of synchronous control tasks and implementing the logic processing of event dependencies between execution flows. After completing the scheduling logic processing of different types of tasks, they are directly handed over to the corresponding control unit for hardware execution.

[0084] For example, for the AI ​​CPU task execution, the AI ​​CPU scheduler in the task scheduling CPU uses software to manage the AI ​​CPU state and schedule tasks. For the AI ​​Core task execution, the task scheduling CPU distributes the processed tasks to the AI ​​Core through a separate task block scheduler hardware, and the AI ​​Core performs specific calculations, and the calculation results are also returned to the task scheduling CPU by the task block scheduler.

[0085] During the task scheduling process, the system control configures the system and initializes the chip functions. At the same time, the performance analysis and log modules monitor the entire execution process, record key execution parameters and specific execution details, and perform specific performance analysis or error location when the entire execution ends or an error is reported, providing a basis for detailed evaluation and analysis of the correctness and efficiency of the execution process.

[0086] In the software flow, the onboard intelligent computing framework manager collaborates with the tensor acceleration engine to generate executable offline models for intelligent applications. Before the intelligent application is executed, the onboard intelligent computing framework manager is closely integrated with the onboard intelligent hardware platform to generate a high-efficiency offline model that matches the hardware, and connects the process orchestrator and the operation manager to achieve a deep integration of the offline model and the intelligent computing platform. When the intelligent application is executed, the onboard intelligent computing framework manager works with the process orchestrator, the operation manager, the task scheduler and the underlying hardware resources to combine the offline model, data and the intelligent computing platform to optimize the execution process and obtain the results of the intelligent application.

[0087] In this example implementation, the execution framework layer includes: an offline model generator, an offline model executor, a process scheduler, and an AI model manager. The offline model generator can be used to convert the model file and the weight file into the corresponding offline model file; the offline model executor can be used to load / unload the offline model and compile the loaded offline model; the process scheduler is used to configure the process for the computing engine corresponding to the offline model; the AI ​​model manager is used to control the initialization management of the process corresponding to the device end and the loading of the offline model.

[0088] Specifically, the offline model generator is mainly responsible for converting the model files and weight files that have been generated under the Caffe or TensorFlow framework into offline model files, which can be executed independently on the AI ​​processor. Taking the convolutional neural network as an example, the offline model generation constructs the corresponding network model under the deep learning framework, and trains the original data. Then, the offline model generator is used to perform operator scheduling optimization, weight data rearrangement and compression, memory optimization, etc., and finally generates a tuned offline model. The offline model generator is mainly used to generate offline models that can be efficiently executed on the AI ​​processor. The working principle of the offline model generator is as follows: Figure 5 As shown in the figure, after receiving the original model, the convolutional neural network model is subjected to four steps: model parsing, quantization, compilation, and serialization.

[0089] The offline model executor is responsible for loading and unloading offline models, and converting the successfully loaded model files into instruction sequences that can be executed on the AI ​​processor, completing the program compilation work before execution.

[0090] The AI ​​model manager inference interface is responsible for process initialization and offline model loading on the device side.

[0091] The role of the process orchestrator is to coordinate offline models and provide developers with a development platform for deep learning computing, including computing resources, operating frameworks, and related supporting tools, so that developers can easily and efficiently write artificial intelligence applications that run on specific hardware devices, and are responsible for the generation, loading, and scheduling of operations of models. Through the unified management of the process orchestrator, the entire intelligent computing includes four engines: data engine, preprocessing engine, model inference engine, and post-processing engine. The process orchestrator is responsible for the creation, destruction, and recycling of computing resources of the entire computing engine flowchart. The intelligent computing platform uses the cooperation of the computing engine and the process orchestrator to realize the orchestration and execution of intelligent application neural networks. The process orchestrator coordinates the entire computing engine flowchart implementation process such as Figure 6 shown.

[0092] For example, refer to Figure 7 As shown, users can use the offline model generator to generate the corresponding offline model, and use the process orchestrator to call the AI ​​model manager to manage the offline model; and call the offline model executor to load and execute the offline model.

[0093] Exemplarily, the executable data processing model deployed by the model layer 11 may be an offline model that has been processed by the execution framework layer and can be directly called.

[0094] Furthermore, the implementation of this example also provides a method for constructing an airborne intelligent computing model, which can be applied to the above-mentioned system for constructing an airborne intelligent computing model. Figure 8 As shown, the method includes:

[0095] Step S81, generating an executable file corresponding to the target task in the base layer, and sending the executable file to the operation scheduling layer;

[0096] Step S82, executing the executable file in the operation scheduling layer and scheduling computing resources;

[0097] Step S83, using the execution framework layer to generate, load and infer the data processing model corresponding to the executable file;

[0098] Step S84, deploying the executable data processing model at the model layer.

[0099] The specific functions implemented by each functional layer in the above steps have been described in detail in the corresponding system embodiments and will not be repeated here.

[0100] The system and corresponding method provided in the embodiment of the present invention, the integrated development environment corresponding to the system is a set of AI full-stack development platform that can be developed based on NPU (Neural-network Processing Unit). For operator development, it provides a full set of operator development and tuning capabilities, and supports the operation of simulation operators in a real chip operating environment; for network model development, it integrates offline model conversion tools, model quantization tools, model accuracy comparison tools, and model operation performance analysis tools to improve the efficiency of network model transplantation, analysis and optimization; for computing engine development, it provides computing engine visualization programming technology to lower the development threshold; for application development, it integrates tools such as analyzers and compilers to provide developers with a graphical integrated development environment, through which the entire process development such as project management, compilation, debugging, simulation performance analysis, etc. can be carried out, and the development efficiency can be greatly improved.

[0101] The system and method provided by the present invention have the following advantages:

[0102] 1) This method supports mainstream computing frameworks such as TensorFlow, Caffe, and MindSpore;

[0103] 2) This method supports the operation of algorithms such as image screening / detection / recognition, speech recognition, and intelligent decision-making;

[0104] 3) This method supports model conversion and optimization, and has functions such as operator scheduling optimization, weight data rearrangement and compression, and memory optimization;

[0105] 4) This method supports the development of airborne dedicated operators, and has functions such as operator analysis, operator compilation and deployment, and network operation verification;

[0106] 5) This method supports domestically produced NPU processors and has the ability to aggregate computing power;

[0107] 6) This method supports the performance analysis and evaluation of the intelligent application execution process, and has the functions of pre-processing performance, inference execution, and post-processing performance analysis.

[0108] It should be noted that the above figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0109] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to an embodiment of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0110] Fig. 9 A schematic diagram of an electronic device suitable for implementing an embodiment of the present invention is shown.

[0111] It should be noted that Fig. 9 The electronic device 1000 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0112] like Fig. 9 As shown, the electronic device 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage part 1008 to the random access memory (RAM) 1003. In the RAM 1003, various programs and data required for system operation are also stored. The CPU 1001, ROM 1002 and RAM 1003 are connected to each other through a bus 1004. The input / output (I / O) interface 1005 is also connected to the bus 1004. In addition, the electronic device 1000 also includes: FPGA devices, SOC devices.

[0113] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, etc.; an output section 1007 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage section 1008 as needed.

[0114] In particular, according to an embodiment of the present invention, the process described below with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a storage medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 1009, and / or installed from a removable medium 1011. When the computer program is executed by a central processing unit (CPU) 1001, various functions defined in the system of the present application are executed.

[0115] Specifically, the above-mentioned electronic device may be an airborne intelligent electronic device.

[0116] It should be noted that the storage medium shown in the embodiment of the present invention may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In the present invention, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any storage medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the storage medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0117] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0118] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0119] It should be noted that, as another aspect, the present application also provides a storage medium, which can be included in an electronic device; or it can exist independently without being installed in the electronic device. The above storage medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the following embodiments. For example, the electronic device can implement the following Figure 8 The individual steps of the method are shown.

[0120] In one embodiment, the present application provides a computer program product, including a computer program, which implements the steps in the above-mentioned method embodiments when executed by a processor.

[0121] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0122] Other embodiments of the invention will readily occur to those skilled in the art after considering the specification and practicing the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0123] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A system for constructing an airborne intelligent computing model, characterized in that: The system comprises: The basic layer is used to generate executable files corresponding to the target tasks; The operation scheduling layer is used to execute the executable file and schedule computing resources; An execution framework layer, used to generate, load and infer the data processing model corresponding to the executable file; The model layer is used to deploy the executable data processing model.

2. The system according to claim 1, characterized in that The base layer includes: The programming development layer is used to provide a callable programming interface for building a data processing model corresponding to the target task; A compilation optimization layer, used for scheduling hardware resources to compile and optimize the constructed data processing model; The hardware enablement layer is used to provide schedulable hardware resources for the compilation optimization layer and the programming development layer.

3. The system according to claim 1, characterized in that The operation scheduling layer includes: Tensor acceleration engine, which provides a standard operator library that can be directly called; An operation manager, configured to provide resource management functions for task allocation of intelligent applications; wherein the intelligent applications perform business data processing based on the data processing model; The task scheduler is used to configure tasks for intelligent applications and collaborate with the operation manager to complete the task scheduling process.

4. The system according to claim 3, characterized in that The task scheduler comprises: Scheduling interface, used for communication and data exchange with the operation manager and driver; The scheduling engine is used to control the execution process of the task scheduling CPU; The scheduling logic processing module is used to call the corresponding task module according to the task type corresponding to the current task to process the current task; AI CPU scheduler, used for AI CPU status management and task scheduling; The task block scheduler is used to distribute tasks processed by the task scheduling CPU to the AI ​​computing core; System control module, used to configure the system and initialize chip functions; Performance analysis module, used to monitor the execution process of tasks; The log module is used to record the log data of the task scheduler.

5. The system according to claim 4, characterized in that The scheduling logic processing module includes: A kernel function execution module is used to schedule kernel functions to process corresponding computing tasks; Direct storage access execution module, used to implement the scheduling logic of storage tasks; The event execution module is used to implement the scheduling logic of synchronous control tasks and realize the logical processing of event dependencies between execution flows.

6. The system according to claim 1, characterized in that The execution framework layer includes: Offline model generator, used to convert model files and weight files into corresponding offline model files; Offline model executor, used to load / unload offline models and compile programs for loaded offline models; The process orchestrator is used to configure the process of the computing engine corresponding to the offline model; AI model manager is used to control the initialization management and offline model loading of the corresponding processes on the device side.

7. A method for constructing an airborne intelligent computing model, characterized in that: The method comprises: Generate an executable file corresponding to the target task at the base layer, and send the executable file to the operation scheduling layer; Executing the executable file in the operation scheduling layer and scheduling computing resources; Using the execution framework layer to perform generation, loading and reasoning processing of the data processing model corresponding to the executable file; The executable data processing model is deployed at the model layer.

8. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method for constructing an airborne intelligent computing model described in claim 7 is implemented.

9. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for constructing an airborne intelligent computing model described in claim 7 is implemented.

10. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; Wherein, the processor is configured to execute the method for constructing an airborne intelligent computing model as described in claim 7 by executing the executable instructions.

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