Cache and operation method, processor core, instruction processing method, device and medium

Abstract

Embodiments of the present disclosure relate to a cache and an operating method thereof, a microinstruction cache, a processor core, an instruction processing method, an electronic device, and a computer-readable storage medium. The cache includes a plurality of cache entries, each of which is configured to store information related to a microinstruction group, and each cache entry includes an address field corresponding to the corresponding microinstruction group; in response to a target microinstruction group being filled in the microinstruction cache, address information of the microinstruction address of the target microinstruction group in the microinstruction cache is stored in the address field of the cache entry corresponding to the target microinstruction group. By setting an address field in the cache entry included in the cache and storing the address information of the microinstruction group, the address information of the microinstruction group can be used to perform operations such as parallel reading of subsequent microinstruction groups.

Description

Technical Field

[0001] The present disclosure relates to a cache and an operating method thereof, a microinstruction cache, a processor core, an instruction processing method, an electronic device, and a computer-readable storage medium. Background Art

[0002] A processor core (or simply "CPU core") is a core that independently completes the operations of a central processing unit (CPU). For example, a CPU may contain at least one CPU core. Depending on the number of CPU cores, a CPU may be a single-core processor (CPU) or a multi-core processor (CPU). Each CPU core typically includes a three-level cache (if available).

[0003] The processor core translates each architectural instruction (instruction, referred to as "instruction") into one or more micro-instructions (micro-op, uop) within the microarchitecture. Each microinstruction only performs a limited number of operations, which ensures that each pipeline stage is very short, thereby increasing the operating frequency of the processor core. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a cache comprising a plurality of cache entries, wherein each cache entry is configured to store information associated with a microinstruction group, and each cache entry comprises an address field corresponding to the corresponding microinstruction group; in response to an object microinstruction group being filled in the microinstruction cache, address information of a microinstruction address of the object microinstruction group in the microinstruction cache is stored in the address field of the cache entry corresponding to the object microinstruction group.

[0005] At least one embodiment of the present disclosure provides a microinstruction cache, comprising: a first sub-cache, configured to provide a microinstruction group storage space; and a second sub-cache, comprising a plurality of cache entries, each cache entry being configured to store information related to a microinstruction group, each cache entry including an address field corresponding to a corresponding microinstruction group; in response to an object microinstruction group being filled in the microinstruction cache, address information of a microinstruction address of the object microinstruction group in the microinstruction cache is stored in the address field of the cache entry corresponding to the object microinstruction group.

[0006] At least one embodiment of the present disclosure provides a processor core, comprising: a first sub-cache, configured to provide a microinstruction group storage space; a second sub-cache, comprising a plurality of cache entries, each cache entry being configured to store information related to a microinstruction group, each cache entry including an address field corresponding to a corresponding microinstruction group; and a cache operation module, configured to: in response to an object microinstruction group being filled in the first sub-cache, obtain a microinstruction address of the object microinstruction group in the first sub-cache; and store the address information of the microinstruction address in the address field of the cache entry corresponding to the object microinstruction group in the second sub-cache.

[0007] At least one embodiment of the present disclosure provides a cache operating method, comprising: in response to an object microinstruction group being filled in a microinstruction cache, selecting a target cache entry from a plurality of cache entries included in the cache; and storing address information of a microinstruction address of the object microinstruction group in the microinstruction cache in an address field included in the target cache entry.

[0008] At least one embodiment of the present disclosure provides an instruction processing method, comprising: in response to an object microinstruction group being filled in a first sub-cache, obtaining a microinstruction address of the object microinstruction group in the first sub-cache; and storing address information of the microinstruction address in an address field of a cache entry corresponding to the object microinstruction group in a second sub-cache.

[0009] At least one embodiment of the present disclosure provides an electronic device, comprising: a processor; and a memory, comprising one or more computer program instructions; wherein the one or more computer program instructions, when executed by the processor, execute the method provided by at least one embodiment of the present disclosure.

[0010] At least one embodiment of the present disclosure provides a computer-readable storage medium that non-transitorily stores computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the method provided by at least one embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0012] Figure 1 A schematic diagram of a pipeline of a processor core is shown;

[0013] Figure 2 A schematic diagram showing the basic structural division of a processor is shown;

[0014] Figure 3 A schematic diagram showing an example of a front-end structure of a CPU core;

[0015] Figure 4 shows a schematic diagram of a branch prediction module;

[0016] Figure 5 A schematic diagram illustrating the operation of decoding instructions in a processor core;

[0017] Figure 6 A schematic diagram showing an operation of accessing a microinstruction cache to obtain corresponding microinstruction group data;

[0018] Figure 7 A schematic diagram showing the alignment relationship between microinstruction groups and cache blocks is shown;

[0019] Figure 8 A schematic diagram illustrating a cache according to at least one embodiment of the present disclosure is shown;

[0020] Figure 9 A schematic flow chart illustrating a cache operation method according to at least one embodiment of the present disclosure is shown;

[0021] Figure 10 A schematic diagram illustrating a cache according to at least another embodiment of the present disclosure is shown;

[0022] Figure 11 A schematic diagram illustrating a cache according to at least another embodiment of the present disclosure is shown;

[0023] Figure 12 A schematic diagram illustrating a microinstruction cache according to at least one embodiment of the present disclosure is shown;

[0024] Figure 13 A schematic diagram showing the structure of a processor core according to at least one embodiment of the present disclosure is shown;

[0025] Figure 14 A schematic flow chart illustrating an instruction processing method according to at least one embodiment of the present disclosure is shown;

[0026] Figure 15 A schematic flow chart illustrating an instruction processing method according to at least another embodiment of the present disclosure is shown;

[0027] Figure 16 A schematic diagram showing the principle of storing address information in the address field included in a cache entry;

[0028] Figure 17 A schematic diagram illustrating the principle of reading multiple microinstruction groups in parallel according to at least one embodiment of the present disclosure is shown;

[0029] Figure 18 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown;

[0030] Figure 19A schematic diagram showing the structure of a computer-readable storage medium according to at least one embodiment of the present disclosure; and

[0031] Figure 20 A schematic block diagram of an electronic device according to at least another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure pertains. The terms "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are merely used to distinguish between different components. Similarly, terms such as "include" or "comprise" and the like mean that the elements or objects preceding the term encompass the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0034] The processor cores (CPU cores) of single-core or multi-core processors use pipelining to improve instruction execution efficiency. Pipelining divides the complete operation steps of the CPU core into multiple sub-steps and executes these sub-steps in a pipelined manner to improve efficiency.

[0035] Figure 1 FIG. 1 shows an exemplary scalar central processing unit (CPU) instruction pipeline comprising a five-stage pipeline. Figure 1As shown, each instruction can be issued every clock cycle and executed within a fixed time (e.g., five clock cycles). The execution of each instruction is divided into five steps: instruction fetch (IF) stage 1001, decode (ID) stage 1002, execute (EX) stage 1003, memory access (MEM) stage 1004, and writeback (WB) stage 1005. In IF stage 1001, a specified instruction is fetched from the instruction cache. A portion of the fetched instruction specifies the source register that can be used for instruction execution. In ID stage 1002, the instruction is decoded and control logic is generated to fetch the contents of the specified source register. Based on the control logic, an arithmetic or logical operation is performed on the fetched contents in EX stage 1003. In MEM stage 1004, the executed instruction can read or write to the memory in the data cache. Finally, in WB stage 1005, the value obtained by executing the instruction can be written back to a register.

[0036] Usually, the earlier pipeline steps in the CPU are classified as the front end. For example, taking a five-stage pipeline as an example, the modules used for the instruction fetch stage and the decoding stage are classified as the CPU front end. Correspondingly, the later pipeline steps in the CPU are classified as the back end. For example, taking a five-stage pipeline as an example, the modules used for the execution stage, memory access stage and write-back stage are classified as the CPU back end.

[0037] To support high operating frequencies, each pipeline stage may contain multiple (sub-)pipeline stages (clock cycles). Although each pipeline stage performs a limited number of operations, this minimizes the time required for each clock cycle, thereby improving CPU core performance by increasing the CPU's operating frequency. Each pipeline stage can also further enhance processor core performance by accommodating more instructions (i.e., superscalar technology). Superscalar refers to the method of executing multiple instructions in parallel within a single cycle. Processors with increased instruction-level parallelism and the ability to process multiple instructions within a single cycle are called superscalar processors. For example, superscalar processors can further support out-of-order execution. Out-of-order execution refers to the CPU's use of technology that allows multiple instructions to be sent separately to the corresponding circuit units for processing, not in the order specified by the program.

[0038] Within the microarchitecture, the processor core translates each architectural instruction ("instruction") into one or more microinstructions. Each microinstruction performs only a limited number of operations, keeping each pipeline stage short and increasing the processor core's operating frequency. For example, a memory read instruction (load) can be translated into an address generation microinstruction and a memory read microinstruction. The second microinstruction depends on the result of the first microinstruction, so the second microinstruction will not execute until the first microinstruction completes. Microinstructions contain multiple microarchitecture-related fields used to pass relevant information between pipeline stages.

[0039] Speculative execution is another technique for improving processor performance. This technique executes the instructions following an instruction before it has completed execution. One speculative execution technique is branch prediction. As mentioned above, the instruction fetch unit is responsible for providing the processor with the next instruction to execute. During the instruction fetch stage, in addition to fetching multiple instructions, the address for the next instruction fetch must also be determined. Therefore, this stage determines whether a conditional branch instruction exists, if so, whether the branch will take place (in which direction), and the target address. The instruction fetch unit includes a branch prediction unit (branch predictor) to perform branch prediction. The branch prediction unit (branch predictor) at the front end of the processor core predicts the direction of a conditional branch instruction, prefetches, and executes instructions in that direction. Another speculative execution technique involves executing a memory read instruction before the addresses of all preceding memory write instructions are known.

[0040] Speculative execution further increases inter-instruction parallelism, significantly improving processor core performance. When a speculative execution error occurs, such as a branch prediction error or a write instruction preceding a memory read overwriting the same address, all instructions in the pipeline following the erroneous instruction must be flushed (or "cleared"), and the program then jumps to the error point and re-executes to ensure correct execution.

[0041] Figure 2 A schematic diagram of the basic structure of a processor is shown. Processor 200 includes at least one CPU core (processor core) and at least one level of cache. For example, the CPU core includes a front-end 201 and a back-end 202. For example, the at least one level of cache includes a level 1 cache (not shown) within the CPU core and a level 2 cache 203 outside the CPU core. Here, the level 2 cache 203 is a separate structure.

[0042] Figure 3A schematic diagram of an example of the front-end structure of a CPU core is shown. The front-end 201 of the CPU core includes an instruction fetch unit, a decoding unit, and a transmitting unit. The instruction fetch unit includes a branch prediction 301 and a selection logic 302; the decoding unit includes an instruction cache 303, an instruction decode 304, a microinstruction cache 305, and a microinstruction queue 306; and the transmitting unit 307 is connected to the microinstruction queue 306. The CPU core has both an instruction cache and a microinstruction cache, so it has micro-architecture optimization. The instruction address obtained by the instruction fetch unit (which can be a program counter address, referred to as a PC address) is predicted through the branch prediction 301 to obtain the instruction address to be executed next. At the same time, the instruction address passes through the selection logic 302 to determine whether the instruction corresponding to the instruction address needs to be decoded. If "yes", then go to step 1. Figure 3 The left path in the middle needs to decode the instruction; if "no", then go to Figure 3 The path on the right does not need to decode the instruction, but accesses the microinstruction cache to obtain the corresponding microinstruction group data.

[0043] Figure 4 A schematic diagram of a branch prediction module is shown. Figure 3 , the instruction address enters the branch prediction (301) module, and accesses the branch predictor 401 and other functional modules 402 respectively. The purpose of accessing the branch predictor 301 is to determine whether there is a branch instruction within a range starting from the instruction address (for example, the range from the instruction address to the first subsequent alignment address, for example, the processor alignment address can be 64 bytes), the branch direction and jump address when there is a branch instruction. The purpose of accessing other functional modules is to obtain some key information to facilitate access to subsequent modules. Among them, other functional modules may include, for example, a micro-tag cache of microinstructions and a micro-tag cache of instructions. If a branch that can be jumped is predicted, the next instruction address is the jump address of the branch. If no branch that can be jumped is predicted, the next instruction address is the starting address of the next alignment address.

[0044] Figure 5 A schematic diagram showing the operation of decoding instructions in a processor core is shown. Figure 3Based on instruction address A, the instruction cache 303 is queried to obtain the undecoded instruction data (e.g., one or more instructions) corresponding to instruction address A. The instruction data is then decoded into multiple microinstructions (these microinstructions may be referred to as microinstruction groups, e.g., including microinstruction 1, microinstruction 2, microinstruction 3, etc.) by instruction decoding 304. The resulting microinstruction groups are sent to the microinstruction queue 306 to await allocation and issuance by the issue unit 307 to the corresponding execution unit in the backend of the CPU core for execution. Alternatively, if certain conditions are met (e.g., the microinstruction group is a frequently used microinstruction group), the microinstruction group is saved to the microinstruction cache 305, awaiting possible future access.

[0045] In one embodiment, the processor core may update the micro tag caches of the micro instructions in other functional modules 402 while saving the micro instruction group into the micro instruction cache 305 .

[0046] Figure 6 A schematic diagram showing the operation of accessing the microinstruction cache to obtain the corresponding microinstruction group data. Figure 3 Based on the instruction address, microinstruction cache 305 is accessed to obtain the corresponding microinstruction group data (e.g., including microinstructions 1, 2, and 3). The obtained microinstruction group data is directly sent to microinstruction queue 306, where it awaits allocation and issuance by issue unit 307 to the corresponding execution unit in the backend of the CPU core for execution. Because accessing the microinstruction cache has low latency and reduces power consumption associated with decoding, selection logic 302 prefers accessing microinstruction cache 305 whenever possible.

[0047] Typically, cache capacity is very small, storing only a subset of main memory's contents. Data exchange between cache and main memory is performed in blocks, with main memory blocks and cache lines (or cache blocks) being the same size. To cache data from main memory, a function must be applied to locate the main memory address in the cache; this is called address mapping. After the instruction data in main memory is cached in the cache (instruction cache) according to this mapping, the CPU core converts the main memory address in the program's instructions into a cache address when executing the program. Cache address mapping methods typically include direct mapping, fully associative mapping, and set associative mapping.

[0048] Each cache item includes a cache block, that is, it corresponds to a cache block; each cache item also includes a valid bit (Valid), a tag (Tag) field and a data field, etc., among which the data field includes a cache block, which is used to store cached data (such as instruction data or operated data), and the tag field stores the tag part of the memory address of the cached data.

[0049] For fully associative mapping, all cache entries in the cache are organized into multiple sets. When the processor core accesses the cache using a memory address, it compares the tag sum with the tag in the cache entry one by one. Upon a hit, it uses the offset to locate the corresponding byte in the cache block. For direct mapping, all cache entries in the cache are organized into multiple sets, but each set contains only one cache entry, meaning there is only one "way." When the processor core accesses the cache using a memory address, it first finds the corresponding "set" using the index portion of the memory address. It then compares the tag sum with the tag in the cache entry within that set. Upon a hit, it uses the offset to locate the corresponding byte in the cache block. For set-associative mapping, all cache items in the cache are organized into multiple groups, each group includes multiple cache items, and each cache item in the group occupies a "way", that is, there are multiple ways. When the processor core uses the memory address to access the cache, it first finds the corresponding "group" through the index part of the memory address, and then within the "group", uses the tag to compare with the tag in the cache item stored in each "way". If the same tag is found in a certain way, the cache query hits, otherwise, the cache query misses, and when it hits, the offset is used to locate the corresponding byte in the cache block.

[0050] As described above, in the case of fully associative mapping, the memory address includes two parts: a tag and an offset but does not include an index; in the case of direct mapping and set associative mapping, the memory address includes three parts: a tag, an index, and an offset.

[0051] Figure 7 Figure 2 shows the alignment relationship between microinstruction groups and cache blocks. Figure 7 As shown, a cache block 700 is a cache block whose first and last addresses are aligned with the memory blocks of the main memory. The first address of the cache block 700 is set to be the microinstruction starting address of a microinstruction group, and the last address is set to be the microinstruction ending address of a microinstruction group. The cache block 700 can store at least a microinstruction group 711 and a microinstruction group 712. It is understood that, depending on the actual situation, a cache block can also store only one microinstruction group, or it can store two or more microinstruction groups.

[0052] If a cache block stores at least two microinstruction groups, the X86 architecture serially accesses the microinstruction cache to read these multiple microinstruction groups. For example, it is necessary to first read a microinstruction group based on the instruction address. Then, based on the obtained microinstruction end address of the microinstruction group, the microinstruction start address of the next microinstruction group can be obtained. Because multiple microinstruction groups stored in a cache block need to be read serially, the read bandwidth of the microinstruction cache is relatively low.

[0053] At least one embodiment of the present disclosure provides a cache and a corresponding operating method. The cache provided by at least one embodiment can be used as a microtag cache of a microinstruction, or as a sub-cache in a microinstruction cache, and the embodiments of the present disclosure are not limited to this. The cache sets an address field corresponding to the microinstruction group and stores the address information of the microinstruction group in the microinstruction cache. For example, before reading the microinstruction group from the microinstruction cache, the address information of the microinstruction group can be obtained in advance, for example, to facilitate the execution of an operation of determining the address of at least one subsequent microinstruction group based on the address information.

[0054] The following will be combined Figures 8 to 11 The cache and its operation method provided by at least one embodiment of the present disclosure are described in detail.

[0055] Figure 8 A schematic diagram of a cache according to at least one embodiment of the present disclosure is shown.

[0056] like Figure 8 As shown, the cache 800 of this embodiment includes a plurality of cache entries, each cache entry corresponding to a microinstruction group and configured to store information related to a microinstruction group. Figure 8 The description is made by taking an example where each row corresponds to one cache entry, but the embodiments of the present disclosure do not limit this.

[0057] Each cache entry includes an address field 801 corresponding to a corresponding microinstruction group. The address field 801 is used to store address information of a microinstruction address of the corresponding microinstruction group in the microinstruction cache.

[0058] For example, the microinstruction address of the corresponding microinstruction group in the microinstruction cache can be stored in address field 801, or the microinstruction ending address of the corresponding microinstruction group in the microinstruction cache can be stored in address field 801, or the microinstruction starting address and address offset of the corresponding microinstruction group in the microinstruction cache can be stored in address field 801. The microinstruction ending address of the microinstruction group can be the address of the last microinstruction in the microinstruction group. The microinstruction starting address of the microinstruction group can be the address of the first microinstruction in the microinstruction group. The address offset of the microinstruction group can be the offset of the microinstruction receiving address relative to the microinstruction starting address.

[0059] For example, if the microinstruction group includes five microinstructions, the addresses of the five microinstructions in the microinstruction cache are: 0x1000, 0x1001, 0x1002, 0x1003, 0x1004, then the microinstruction starting address is 0x1000, the microinstruction ending address is 0x1004, and the address offset is 4.

[0060] In at least one embodiment of the present disclosure, the address information of the microinstruction address of the microinstruction group in the microinstruction cache may be any information capable of indicating the end address of the microinstruction, and the present disclosure is not limited thereto. For example, if the processor alignment address is 64 bytes (e.g., the system bus width is 64 bytes), the last 6 bits of the microinstruction address of the microinstruction group in the microinstruction cache may be used as the address information.

[0061] At least one embodiment of the present disclosure can store the address information of the microinstruction address of the object microinstruction group in the microinstruction cache in the address field of the cache entry corresponding to the object microinstruction group when the acquired instruction is decoded (decoded) by the decoding unit to obtain the object microinstruction group and the object microinstruction group is filled in the microinstruction cache.

[0062] At least one embodiment of the present disclosure sets an address field in a cache and stores address information in the address field. For example, the address information of the microinstruction group can be obtained before the microinstruction group is read from the microinstruction cache, so as to improve the efficiency of obtaining the address information in a scenario where the address information needs to be obtained.

[0063] For example, in at least one application scenario, before reading a specified microinstruction group based on a received instruction fetch address, address information can be first obtained from a cache entry corresponding to the specified microinstruction group in the cache. Based on the address information, the instruction fetch address of the next microinstruction group following the specified microinstruction group can be derived. Subsequently, based on the received instruction fetch address and the derived instruction fetch address, the specified microinstruction group and the next microinstruction group can be read in parallel, thereby increasing the read bandwidth of the microinstruction cache and improving microinstruction reading efficiency.

[0064] Based on the cache provided by at least one embodiment of the present disclosure, the present disclosure also provides an operation method of the cache. Figure 9 Provide a detailed description.

[0065] Figure 9 A schematic flowchart of a cache operation method according to at least one embodiment of the present disclosure is shown.

[0066] In at least one embodiment of the present disclosure, Figure 9 As shown, the cache operation method 900 provided by at least one embodiment of the present disclosure may include operations S910 to S920.

[0067] In operation S910 , in response to a target microinstruction group being filled in a microinstruction cache, a target cache entry is selected from a plurality of cache entries included in the cache.

[0068] In operation S920 , address information of a microinstruction address of a target microinstruction group in the microinstruction cache is stored in an address field included in a target cache entry.

[0069] For example, if the cache already contains a cache entry corresponding to the target microinstruction group, the corresponding cache entry can be used as the target cache entry. If the cache does not contain a cache entry corresponding to the target microinstruction group, for example, a cache entry can be selected as the target cache entry from cache entries that do not correspond to the target microinstruction group, or a cache entry can be determined as the target cache entry based on a cache replacement algorithm.

[0070] For example, whether the cache includes a cache entry corresponding to the object microinstruction group can be located based on the tag of the object microinstruction group. Alternatively, whether the cache includes a cache entry corresponding to the object microinstruction group can be located based on the microtag of the object microinstruction group. Among them, the tag of the microinstruction group can be obtained based on the address of the first microinstruction in the microinstruction group, for example, the tag of the microinstruction group can be composed of other parts of the address of the first microinstruction except the index part. The microtag of the microinstruction group can be a part of the tag of the microinstruction group or information obtained by compressing the tag of the microinstruction group.

[0071] After the target cache entry is determined, the address information of the microinstruction address of the target microinstruction group in the microinstruction cache may be stored in the address field included in the target cache entry, ie, the address information may be written to the address field.

[0072] For example, the operation method may be executed by an instruction fetch unit in a processor core, or by a decoding unit in a processor core, or by other functional units with processing functions in a processor core, and the embodiments of the present disclosure do not limit this.

[0073] In at least one embodiment of the present disclosure, the address information of the microinstruction group stored in the address field may include a microinstruction end address. For example, the microinstruction end address can be operated on to conveniently obtain the starting address of the next microinstruction group of the target microinstruction group. In this way, the next microinstruction group can be read based on the obtained starting address without having to read the target microinstruction group before reading the next microinstruction group. In one embodiment, the next microinstruction group can be read in parallel with the target microinstruction group.

[0074] Figure 10 A schematic diagram of a cache according to at least another embodiment of the present disclosure is shown.

[0075] In at least one embodiment of the present disclosure, Figure 10 As shown, each of the multiple cache entries included in the cache 1000 may include, in addition to the address field 1001 , a microtag field 1002 , for example, in which the microtag field 1002 stores the microtag of the corresponding microinstruction group.

[0076] For example, the microtag can be determined based on the microinstruction start address of the microinstruction group in the microinstruction cache. For example, the microtag can be a portion of the microinstruction start address, or can be information obtained by compressing the microinstruction start address. Based on the microtag, the target cache entry can be quickly selected.

[0077] For example, when performing the aforementioned operation of selecting a target cache entry, the microtag of the target microinstruction group can be first determined based on the microinstruction starting address of the target microinstruction group in the microinstruction cache. Subsequently, the determined microtag can be compared with the microtag stored in the microtag field of each cache entry in cache 1000. If a cache entry exists whose stored microtag matches the determined microtag, then that cache entry is determined as the target cache entry.

[0078] In at least one embodiment of the present disclosure, Figure 10 As shown, each cache entry included in cache 1000 may further include a valid bit 1003, which stores validity information of the corresponding microinstruction group to indicate whether the corresponding microinstruction group is valid. Based on the valid bit, for example, a target cache entry may be selected.

[0079] For example, the information stored in the valid bit 1003 can be a binary number. If the value of the stored binary number is 0, the corresponding micro-instruction group is invalid. If the value of the stored binary number is 1, the corresponding micro-instruction group is valid.

[0080] For example, when performing the aforementioned operation of selecting a target cache entry, the microtag of the target microinstruction group can be first determined based on the microinstruction starting address of the target microinstruction group in the microinstruction cache. Subsequently, the determined microtag can be compared with the microtag stored in the microtag field of each cache entry in cache 1000. If no cache entry exists whose stored microtag matches the determined microtag, a cache entry whose valid bit stores validity information indicating invalidity can be selected from the cache as the target cache entry.

[0081] In one embodiment, the address field can be added to the micro-tag cache of the micro-instruction with the micro-tag field and the valid bit to obtain the following: Figure 10 Cache 1000 is shown.

[0082] Figure 11 A schematic diagram of a cache according to at least another embodiment of the present disclosure is shown.

[0083] In at least one embodiment of the present disclosure, Figure 11As shown, the address field 1101 included in each cache entry in the cache 1100 may include, for example, at least two address subfields, such as two address subfields, namely, the address subfield 1111 and the address subfield 1121. It should be noted that, Figure 11 The embodiment in which the address field includes two address subfields is described only as an example to facilitate understanding of the present disclosure. According to actual needs, the address field may also include three or more address subfields, which is not limited in the embodiments of the present disclosure.

[0084] Exemplarily, the number of address subfields included in the address field can be determined based on the number of microinstruction groups that a cache block in the microinstruction cache can store. For example, if a cache block can store N microinstruction groups, the number of address subfields included in the address field in each cache entry can be N-1, where N is an integer greater than or equal to 2.

[0085] Illustratively, the at least two address subfields included in the address field of each cache entry may sequentially store address information of the microinstruction addresses of the target microinstruction group and the subsequent microinstruction group of the target microinstruction group in the microinstruction cache. For example, the subsequent microinstruction group of the target microinstruction group may be a microinstruction group stored in the same cache block as the target microinstruction group and stored in the microinstruction cache after the target microinstruction group.

[0086] For example, in response to a next microinstruction group immediately adjacent to the target microinstruction group being filled in the microinstruction cache and being in the same cache block as the target microinstruction, address information of the microinstruction address of the next microinstruction in the microinstruction cache may be stored in the address subfield of the cache entry corresponding to the target microinstruction group. For example, the next microinstruction group may be understood as the first microinstruction group decoded by the decoding unit after the target microinstruction group is decoded.

[0087] For example, the order in which the at least two address subfields included in the address field of each cache entry store the at least two pieces of address information may correspond to the order in which the microinstruction groups corresponding to the at least two pieces of address information are stored in the microinstruction cache. For example, if microinstruction group 1, microinstruction group 2, and microinstruction group 3 are sequentially stored in a cache block, then the two subfields included in the cache entry corresponding to microinstruction group 1 sequentially store the address information of the microinstruction address of microinstruction group 1 in the microinstruction cache and the address information of the microinstruction address of microinstruction group 2 in the microinstruction cache.

[0088] For example, at least two address subfields obtained in time sequence may be written into the at least two address subfields according to the front-to-back sequence of the at least two address subfields in the cache.

[0089] By providing at least two address subfields in a cache entry and storing the address information of a corresponding microinstruction group and a subsequent microinstruction group stored in the same cache block as the corresponding microinstruction group, it is possible, for example, to derive the value addresses of at least two subsequent microinstruction groups based on the at least two stored address information and the value address of the target microinstruction group. Furthermore, it is possible to read the target microinstruction group and the subsequent at least two microinstruction groups in parallel from the microinstruction cache based on the value address of the target microinstruction group and the derived value addresses of the subsequent at least two microinstruction groups.

[0090] Based on the cache provided by at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a microinstruction cache. Figure 12 The microinstruction cache is described in detail.

[0091] Figure 12 A schematic diagram of a microinstruction cache according to at least one embodiment of the present disclosure is shown.

[0092] like Figure 12 As shown, the microinstruction cache 1200 of this embodiment includes a first sub-cache 1201 and a second sub-cache 1202 .

[0093] The first sub-cache 1201 is configured to provide a microinstruction group storage space. For example, the first sub-cache 1201 stores microinstructions (microinstruction groups) in blocks. Each cache block can store one microinstruction group, or two or more microinstruction groups.

[0094] The second sub-cache 1202 may include a plurality of cache entries, each cache entry storing information associated with a microinstruction group, and each cache entry including an address field corresponding to a corresponding microinstruction group.

[0095] For example, in response to the target microinstruction group being filled in the first sub-cache 1201 , the address information of the microinstruction address of the target microinstruction group in the first sub-cache 1201 may be stored in the address field of the cache entry corresponding to the target microinstruction group included in the second sub-cache 1202 .

[0096] For example, the cache entries included in the second sub-cache 1202 are similar to the cache entries included in the cache in at least one embodiment described above, and are not described again here.

[0097] In at least one embodiment of the present disclosure, for example, a portion of the storage space in the existing microinstruction cache can be divided into multiple cache entries to store information related to the microinstruction group, and the remaining storage space except the multiple cache entries is used as the microinstruction group storage space to obtain the following: Figure 12The microinstruction cache of at least one embodiment of the present disclosure can store address information of microinstruction addresses of microinstruction groups in the microinstruction cache without providing an additional cache. In specific application scenarios, the read bandwidth of the microinstruction cache can be increased without increasing hardware costs.

[0098] Based on the cache provided by at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a processor core. Figures 13 to 17 A processor core and a method for processing instructions thereof provided by at least one embodiment of the present disclosure are described in detail.

[0099] Figure 13 A schematic structural diagram of a processor core according to at least one embodiment of the present disclosure is shown.

[0100] like Figure 13 As shown, the processor core 1300 of this embodiment includes a first sub-cache 1301, a second sub-cache 1302, and a cache operation module 1303. The cache operation module 1303 can be in communication with the first sub-cache 1301 and the second sub-cache 1302. For example, the cache operation module 1303 can at least access the second sub-cache 1302 to perform read and write operations on the second sub-cache 1302.

[0101] The first sub-cache 1301 is configured to provide a microinstruction group storage space. For example, the first sub-cache 1301 can be a microinstruction cache, or it can be combined with the second sub-cache 1302 as two parts of a microinstruction cache to form a microinstruction cache.

[0102] The second sub-cache 1302 includes multiple cache entries, each of which is configured to store information related to a microinstruction group, and each cache entry includes an address field corresponding to the corresponding microinstruction group. For example, the second sub-cache 1302 can be the cache provided by any of the aforementioned embodiments of the present disclosure, or it can be combined with the first sub-cache 1301 as two parts of the microinstruction cache to form a microinstruction cache.

[0103] Cache operation module 1303 is configured to, in response to the target microinstruction group being populated into first sub-cache 1301, obtain the microinstruction address of the target microinstruction group in the first sub-cache. The address information of the microinstruction address is then stored in the address field of the cache entry corresponding to the target microinstruction group in second sub-cache 1302. For example, cache operation module 1303 may employ the aforementioned instruction fetch unit or decode unit, or any other unit in the processor core having processing functionality, and this disclosure is not limited thereto.

[0104] In at least one embodiment of the present disclosure, the cache operation module 1302 can write the acquired microinstruction address as address information into the address field of the cache entry corresponding to the object microinstruction group, or can write the microinstruction end address of the object microinstruction group included in the microinstruction address as address information into the address field of the cache entry corresponding to the object microinstruction group, or can write the microinstruction start address of the object microinstruction group included in the microinstruction address and the address offset determined based on the microinstruction start address and the microinstruction end address as address information into the address field of the cache entry corresponding to the object microinstruction group.

[0105] For example, the address information written by the cache operation module 1302 in the address field of the cache entry corresponding to the target microinstruction group may be any information that can indicate the end address of the microinstructions of the target microinstruction group, and this disclosure does not limit this.

[0106] Based on the processor core of at least one embodiment, at least one embodiment of the present disclosure further provides an instruction processing method. Figure 14 A schematic flow chart of an instruction processing method according to at least one embodiment of the present disclosure is shown.

[0107] like Figure 14 As shown, the instruction processing method 1400 of this embodiment includes operations S1410 to S1420. This instruction processing method can be executed by, for example, a cache operation module in the processor core provided by at least one of the aforementioned embodiments.

[0108] In operation S1410 , in response to a target microinstruction group being filled in a first sub-cache, a microinstruction address of the target microinstruction group in the first sub-cache is obtained.

[0109] In operation S1420 , address information of the microinstruction address is stored in the address field of the cache entry corresponding to the target microinstruction group in the second sub-cache.

[0110] It is understandable that the implementation principles of each operation in the instruction processing method are similar to the implementation principles of the operations performed after the cache operation module in the processor core provided in at least one embodiment above is configured, and will not be repeated here.

[0111] In at least one embodiment of the present disclosure, in a specific application scenario, the processor core provided by at least one embodiment of the present disclosure can derive, based on address information stored in an address field of a cache entry corresponding to a microinstruction group, the instruction fetch address of a microinstruction group that is stored in the same cache block as the microinstruction group corresponding to the current instruction fetch address and is immediately adjacent to the microinstruction group corresponding to the current instruction fetch address, and read at least two microinstruction groups stored in the same cache block in parallel based on the current instruction fetch address and the derived instruction fetch address. This improves the read bandwidth of the microinstruction cache and enhances microinstruction read efficiency.

[0112] For example, the cache operation module in the processor core provided by at least one embodiment of the present disclosure is further configured to obtain the first instruction fetch address of the object microinstruction group in response to receiving an instruction fetch request for the object microinstruction group. The cache operation module is further configured to obtain the address information stored in the address field of the cache entry corresponding to the object microinstruction group from the second sub-cache at the same time as obtaining the first instruction fetch address or at any time after receiving the instruction fetch request. After obtaining the address information, the cache operation module is further configured to obtain the second instruction fetch address of the first microinstruction group based on the obtained address information. After obtaining the first instruction fetch address and the second instruction fetch address, the cache operation module is further configured to read the object microinstruction group and the first microinstruction group in parallel from the first sub-cache based on the first instruction fetch address and the second instruction fetch address. For example, the first microinstruction group and the object microinstruction group are stored in the same cache block of the first sub-cache, and the first microinstruction group is stored in the first sub-cache immediately after the object microinstruction group.

[0113] Accordingly, the instruction processing method provided by at least one embodiment of the present disclosure includes, in addition to the stage of storing address information through the aforementioned operations S1410 to S1420, a stage of reading address information and reading microinstruction groups in parallel. Figure 15 An instruction processing method provided by at least another embodiment of the present disclosure is described in detail to further describe the operations that the cache operation module is configured to perform.

[0114] Figure 15 A schematic flowchart of an instruction processing method according to at least another embodiment of the present disclosure is shown.

[0115] like Figure 15 As shown, the instruction processing method 1500 of this embodiment includes at least operations S1530 to S1560. For example, the instruction processing method 1500 may also include the aforementioned operations S1410 to S1420. For the same microinstruction group, operations S1530 to S1560 should be executed after operations S1410 to S1420. For different microinstruction groups, operations S1530 to S1560 and operations S1410 to S1420 can be executed in parallel or in any execution order, and the embodiments of the present disclosure are not limited to this.

[0116] Operation S1530 : In response to receiving an instruction fetch request for a target microinstruction group, obtaining a first instruction fetch address of the target microinstruction group.

[0117] In operation S1540 , address information stored in an address field of a cache entry corresponding to the target microinstruction group is obtained from the second sub-cache.

[0118] Operation S1550: Obtain a second instruction fetch address of the first microinstruction group based on the obtained address information.

[0119] In operation S1560 , the target microinstruction group and the first microinstruction group are read in parallel from the first sub-cache based on the first instruction fetch address and the second instruction fetch address.

[0120] For example, the instruction fetch unit at the front end of the processor core obtains the instruction address based on the program counter (PC), saves the instruction fetch address to the instruction fetch queue, and generates an instruction fetch request. If the current processor core is in microinstruction fetch mode and the instruction fetch address hits the microinstruction cache (which may be the first sub-cache included in the processor core in at least one of the aforementioned embodiments), the cache operation module can parse the instruction fetch request to obtain the instruction fetch address and use this instruction fetch address as the first instruction fetch address.

[0121] It is understandable that the target microinstruction group is any microinstruction group stored in the microinstruction cache, and the embodiments of the present disclosure are not limited to this.

[0122] In at least one embodiment of the present disclosure, after obtaining the first instruction fetch address, the cache entry corresponding to the target microinstruction group in the second sub-cache can be determined based on the first instruction fetch address. For example, the cache entry corresponding to the target microinstruction group in the second sub-cache can be determined by matching a tag or microtag, or the cache entry corresponding to the target microinstruction group can be determined by an index or the like. Tags, microtags, indexes, etc. are associated with the instruction fetch address of the microinstruction group, for example. After determining the corresponding cache entry, the address information stored in the address field in the corresponding cache entry is obtained.

[0123] In at least one embodiment of the present disclosure, after obtaining the address information, the second instruction fetch address of the first microinstruction group can be calculated based on the address information. For example, if the address information is the microinstruction end address, the second instruction fetch address can be obtained by adding 1 to the microinstruction end address. For example, if the address information is the microinstruction start address and address offset, the second instruction fetch address can be obtained by adding the address offset to the microinstruction start address and then adding 1. For example, if the address information is a microinstruction address, the second instruction fetch address can be obtained by adding 1 to the end address in the microinstruction address. For example, if the address information is the last few bytes (e.g., 6 bytes) of the microinstruction address of the last microinstruction in the microinstruction group, the second instruction fetch address can be obtained by adding the high-order address of the first instruction fetch address to the address information and then adding 1. It will be understood that the above-mentioned calculation method for obtaining the second instruction fetch address is merely an example to facilitate understanding of the present disclosure, and the embodiments of the present disclosure are not limited thereto.

[0124] Through the processor core of at least one embodiment of the present disclosure and the instruction processing method of at least one embodiment, parallel reading of two microinstruction groups in the same cache block can be achieved, the reading bandwidth of the microinstruction cache can be improved, and the reading efficiency of the microinstruction group can be improved.

[0125] In at least one embodiment of the present disclosure, the first sub-cache included in the processor core may include at least two read ports, and the cache operation module may read the target microinstruction group and the first microinstruction group in parallel through two of the at least two read ports corresponding to the target microinstruction group and the first microinstruction group. This embodiment provides the hardware conditions for parallel reading of microinstruction groups.

[0126] For example, compared to a solution of serially reading the microinstruction cache using a single microinstruction cache read port, at least one embodiment of the present disclosure can read at least two microinstruction groups in parallel by adding at least one microinstruction cache read port.

[0127] In at least one embodiment of the present disclosure, the processor core may include a microinstruction queue in addition to the first sub-cache, the second sub-cache and the cache operation module. Figure 3 The microinstruction queue described is similar and is used to store microinstruction groups read from the microinstruction cache and the parsed microinstruction groups.

[0128] For example, the microinstruction queue includes a write port. Figure 3 In at least one embodiment of the present disclosure, the write port of the microinstruction queue can be expanded at least twice to write at least two microinstruction groups read in parallel to the microinstruction queue. For example, the write port can write the target microinstruction group and the first microinstruction group read in parallel to the microinstruction queue in parallel. Through this embodiment, the instruction fetch efficiency of the processor core front end can be improved.

[0129] In at least one embodiment of the present disclosure, after reading the target microinstruction group and the first microinstruction group in parallel, the cache operation module may further compare address information determined based on the read target microinstruction group with address information obtained from an address field in a cache entry corresponding to the target microinstruction group in the second sub-cache to determine whether the address information is consistent. If the address information and the address field are inconsistent, the first microinstruction group read in parallel with the target microinstruction group is discarded.

[0130] For example, considering that the microtag is part of the tag of the microinstruction group or is obtained by compressing the tag of the microinstruction group, in an embodiment in which the microtag is used as the basis for determining the cache entry corresponding to the target microinstruction group, there may be a situation in which the cache entry corresponding to the target microinstruction group is incorrectly determined. In this case, the address information of the target microinstruction group read from the microinstruction cache may be inconsistent with the address information stored in the address field included in the cache entry in the incorrectly determined second sub-cache. If they are inconsistent, the first microinstruction group can be abandoned to facilitate ensuring the execution accuracy of the microinstructions.

[0131] For example, even if the cache entry corresponding to the target microinstruction group is determined more accurately, as a fallback strategy, the address information determined based on the read target microinstruction group can be compared with the address information obtained from the address field in the cache entry corresponding to the target microinstruction group in the second sub-cache to determine whether the two are consistent. In this way, the execution accuracy of the microinstructions can be effectively guaranteed.

[0132] Figure 16 A schematic diagram showing the principle of storing address information in the address field included in the cache entry.

[0133] In at least one embodiment of the present disclosure, the address field included in each cache entry may include at least two address subfields. At least one embodiment of the present disclosure may store at least two address information in the at least two address subfields to correspond to at least the first (N-1) microinstruction groups in the N microinstruction groups stored in the same cache block in the microinstruction cache (for example, it may also be the first sub-cache). For example, based on the at least two address information and the instruction fetch address of the first microinstruction group in the N microinstruction groups, the instruction fetch address of each microinstruction group in the N microinstruction groups can be derived. In this way, it is convenient to read the N microinstruction groups stored in the same cache block in parallel, further improve the read bandwidth of the microinstruction cache, and improve the read efficiency of the microinstruction groups.

[0134] For example, in response to a first microinstruction group that is immediately adjacent to the target microinstruction group being filled in the first sub-cache and stored in the same cache block as the target microinstruction group, the cache operation module can store the address information of the microinstruction address of the first microinstruction group in the first sub-cache in the address subfield of the cache entry corresponding to the target microinstruction group. The cache operation module can also store the address information of the microinstruction address of the second microinstruction group in the first sub-cache in the address subfield of the cache entry corresponding to the target microinstruction group in response to a second microinstruction group that is immediately adjacent to the first microinstruction group being also filled in the first sub-cache and stored in the same cache block as the target microinstruction group. This can be deduced by analogy until at least two address subfields included in the address field of the cache entry corresponding to the target microinstruction group store address information.

[0135] In at least one embodiment of the present disclosure, the index of the microinstruction group corresponding to the last updated cache entry in the second sub-cache can be recorded as the target index, and information indicating whether the address subfield in the last updated cache entry is full can be recorded. This embodiment can use the target index as a determination criterion for determining whether the next microinstruction group and the microinstruction group corresponding to the last updated cache entry are stored in the same cache block. This is because, under normal circumstances, the indexes of different microinstruction groups stored in the same cache block are the same.

[0136] In at least one embodiment of the present disclosure, in addition to recording the target index and information indicating whether the address subfield is full, the microtag of the microinstruction group corresponding to the last updated cache entry in the second sub-cache may also be recorded as the target tag. This target tag can be used to quickly locate the last updated cache entry.

[0137] Exemplarily, the target microinstruction group is set to the first microinstruction group filled in a cache block, such as Figure 16 As shown, after the address information of the object microinstruction group is stored in the address field of the corresponding cache entry, when the third microinstruction group adjacent to the object microinstruction group is filled in the first sub-cache, the address information of the microinstruction address of the third microinstruction group in the microinstruction cache can be stored in the second sub-cache by the logic described in operations S1612 to S1662. It should be noted that, in this embodiment, it can be assumed that it is not determined in advance whether the third microinstruction group is stored in a cache block with the object microinstruction group. The object microinstruction group and the third microinstruction group can be understood as two microinstruction groups arranged in close proximity among the multiple microinstruction groups decoded by the decoding unit.

[0138] Operation S1612: Obtain an index of the third microinstruction group based on the microinstruction address of the third microinstruction group. For example, the index included in the microinstruction address of the first microinstruction in the third microinstruction group may be used as the index of the third microinstruction group.

[0139] Operation S1622 determines whether the index of the third microinstruction group is the same as the target index. It is understandable that since the third microinstruction group is the microinstruction group adjacent to the target microinstruction group, the target index is the index of the microinstruction group corresponding to the cache entry storing the address information of the target microinstruction group, for example, it can be an index obtained based on the microinstruction address of the target microinstruction group. If the two indexes are the same, operation S1632 is performed, otherwise it is determined that the third microinstruction group and the target microinstruction group are stored in different cache blocks of the first sub-cache, and operation S1652 is performed.

[0140] Operation S1632 determines whether the address subfield of the target cache entry is full. For example, the target cache entry is a cache entry that stores address information of the target microinstruction group, such as the cache entry corresponding to the target microinstruction group. It can be determined whether all address subfields included in the target cache entry store address information. If all address subfields store address information, it is determined that the address subfield of the target cache entry is full. If not, operation S1642 is executed; otherwise, operation S1662 is executed.

[0141] Operation S1642 : Store address information of the microinstruction address of the third microinstruction group in the first sub-cache in an address subfield of the target cache entry where address information is not stored.

[0142] Operation S1652: Update the target index. For example, the target index may be updated to the index of the third microinstruction group.

[0143] In operation S1662 , cache entries other than the target cache entry are selected, and address information of the microinstruction addresses of the third microinstruction group in the first sub-cache is stored in the address fields of the selected cache entries.

[0144] In operation S1672, the target cache entry is updated. For example, the target cache entry may be updated to the selected cache entry.

[0145] In at least one embodiment of the present disclosure, operation S1662 may select any cache entry that does not store information other than the target cache entry, or may select any cache entry whose valid bit information indicates invalidity, or may select a cache entry from cache entries other than the target cache entry based on a least recently used (LRU) strategy, a random replacement strategy, or a first in first out (First In First Out) strategy, etc., and the present disclosure does not limit this.

[0146] According to at least one embodiment of the present disclosure, when a cache entry also includes a micro-tag field, the embodiment may further, in the logic for storing address information, obtain the micro-tag of the third micro-instruction group based on the micro-instruction start address included in the micro-instruction address of the third micro-instruction group in the first sub-cache. After selecting and obtaining a cache entry in operation S1662, the micro-tag of the third micro-instruction group may be stored in the micro-tag field included in the selected cache entry. For example, the micro-tag may be obtained by compressing (e.g., performing a hash operation on) the tag portion of the micro-instruction start address, or a portion of the tag may be intercepted from the tag portion of the micro-instruction start address as the micro-tag.

[0147] According to an embodiment of the present disclosure, when the address field includes at least two address subfields, the address information obtained by the aforementioned operation S1540 can be at least two. This embodiment can, for example, obtain at least two instruction fetch addresses based on the at least two address information obtained, and based on the first instruction fetch address of the target microinstruction group and the at least two instruction fetch addresses obtained, read the target microinstruction group and the at least two microinstruction groups corresponding to the at least two instruction fetch addresses in parallel. It is understandable that the principle of obtaining at least two instruction fetch addresses is similar to the principle of obtaining the second instruction fetch address in the aforementioned operation S1550, and will not be repeated here.

[0148] The following will be combined Figure 17 The principle of reading multiple microinstruction groups in parallel in at least one embodiment of the present disclosure is described in detail, taking the example of an address field including two address subfields (i.e., the aforementioned value of N is 3). It is understood that when N is greater than 3, the principle of reading multiple microinstruction groups in parallel can be derived from the principle of reading multiple microinstruction groups in parallel when N is 3.

[0149] Figure 17 A schematic diagram illustrating the principle of reading multiple microinstruction groups in parallel according to at least one embodiment of the present disclosure is shown.

[0150] like Figure 17 As shown, in at least one embodiment of the present disclosure, when reading a microinstruction group, in response to receiving an instruction fetch request for a target microinstruction group, a first instruction fetch address of the target microinstruction group can be first obtained. The first instruction fetch address can be, for example, an instruction address obtained according to a program counter. After obtaining the first instruction fetch address, the first instruction fetch address can be placed in an instruction fetch queue. After traversing to the first instruction fetch address in the instruction fetch queue, operation S1701 can be performed.

[0151] Operation S1701 determines whether a hit occurs in the microinstruction cache (e.g., the first sub-cache) based on the first instruction fetch address. If a hit occurs in the microinstruction cache, operation S1702 is executed. If a hit does not occur in the microinstruction cache, the instruction cache is accessed based on the first instruction fetch address, and the read instruction is decoded to obtain a microinstruction. After obtaining the microinstruction, the microinstruction can be written to a microinstruction queue to wait for the aforementioned issue unit to allocate and issue it to the corresponding execution unit in the back end of the CPU core for execution.

[0152] For example, after obtaining the first instruction fetch address, the corresponding address information can be obtained from the second sub-cache based on the first instruction fetch address. Alternatively, after determining a hit in the microinstruction cache in operation S1701, the corresponding address information can be obtained from the second sub-cache based on the first instruction fetch address. For example, the address information stored in the address subfield of the cache entry corresponding to the target microinstruction group can be obtained from the second sub-cache.

[0153] Operation S1702 determines whether there is first address information. For example, the operation S1702 can determine whether an address information is obtained based on the first instruction fetch address. If so, any address information obtained can be used as the first address information. For example, the operation S1702 can also determine whether the address information stored in the first address subfield in the cache entry corresponding to the object microinstruction group is obtained from the second sub-cache based on the first instruction fetch address. If so, the address information stored in the first address subfield is used as the first address information. If there is first address information, perform operation S1703. If there is no first address information, access the first sub-cache based on the first instruction fetch address to read the object microinstruction group from the first sub-cache.

[0154] Operation S1703: Calculate a second instruction fetch address based on the first address information and the first instruction fetch address. For example, the principle of obtaining the second instruction fetch address in operation S1703 is similar to the principle of obtaining the second instruction fetch address in operation S1550, which will not be repeated here.

[0155] In operation S1704, it is determined whether there is second address information. For example, operation S1704 can determine whether two pieces of address information are obtained based on the first instruction fetch address. If two pieces of address information are obtained, the other piece of address information other than the first piece of address information can be used as the second address information. For example, operation S1704 can also determine whether the address information stored in the second address subfield of the cache entry corresponding to the target microinstruction group is obtained from the second sub-cache based on the first instruction fetch address. If so, the address information stored in the second address subfield is used as the second address information. If there is second address information, operation S1706 is executed. If there is no second address information, operation S1705 is executed.

[0156] In operation S1705 , the second sub-cache is accessed based on the first instruction fetch address and the second instruction fetch address to read the target microinstruction group and the microinstruction group corresponding to the second instruction fetch address in parallel. After operation S1705 , operation S1707 is performed.

[0157] In operation S1706, a third instruction fetch address is calculated based on the first instruction fetch address and the second address information, and the second sub-cache is accessed based on the first instruction fetch address, the second instruction fetch address, and the third instruction fetch address to read three microinstruction groups in parallel. After operation S1706, operation S1707 is performed.

[0158] For example, if the address information stored in the address subfield is the end address of the microinstruction, then the second address information can be added by 1 to obtain the third instruction fetch address. If the address information stored in the address subfield is the last few bytes of the microinstruction address of the last microinstruction in the microinstruction group, then the high-order address of the first instruction fetch address can be added to the second address information, and then added by 1 to obtain the third instruction fetch address. It will be understood that the above calculation method for obtaining the second instruction fetch address is only used as an example to facilitate understanding of the present disclosure, and the embodiments of the present disclosure are not limited thereto.

[0159] Operation S1707: Determine whether the address information of the microinstruction group read based on the first instruction fetch address is consistent with the first address information. If consistent, execute operation S1709; if inconsistent, execute operation S1708.

[0160] In operation S1708, the microinstruction group read based on the second instruction fetch address and the third instruction fetch address is discarded. After operation S1708, operation S1712 is performed.

[0161] Operation S1709: Determine whether there is a third instruction fetch address. If yes, execute operation S1710; if not, execute operation S1712.

[0162] Operation S1710: Check whether the address information of the microinstruction group read based on the second instruction fetch address is consistent with the second address information. If they are consistent, execute operation S1712; if they are inconsistent, execute operation S1711.

[0163] In operation S1711, the microinstruction group read based on the third instruction fetch address is discarded. After operation S1711, operation S1712 is performed.

[0164] Operation S1712: Write the read microinstruction groups into the microinstruction queue. Operation S1712 writes the unabandoned microinstruction groups of the three read microinstruction groups into the microinstruction queue in parallel through the write port of the microinstruction queue, waiting for the aforementioned issue unit to allocate and issue them to the corresponding execution unit in the back end of the CPU core for execution.

[0165] Through the technical solution of at least one embodiment of the present disclosure, parallel reading of at least two microinstruction groups can be achieved, the reading bandwidth of the microinstruction cache can be improved, and the reading efficiency of the microinstruction groups can be improved.

[0166] Based on the cache operation method provided by at least one embodiment of the present disclosure and the instruction processing method provided by at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides an electronic device. Figure 18 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown.

[0167] For example, Figure 18As shown, the electronic device 1800 includes a processor 1810 and a memory 1820. The memory 1820 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 1810 is used to execute the computer program instructions. When executed by the processor 1810, the computer program instructions implement the cache operation method and / or instruction processing method provided by any embodiment of the present disclosure. The memory 1820 and the processor 1810 can be interconnected via a bus system and / or other form of connection mechanism (not shown).

[0168] Processor 1810 may be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU). It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. For example, the central processing unit (CPU) may be an X86 or ARM architecture. Processor 1810 may be a general-purpose processor or a dedicated processor, and may control other components in electronic device 1800 to perform desired functions.

[0169] For example, memory 1820 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 1810 may execute one or more computer program modules to implement various functions of the electronic device 1800. The computer-readable storage medium may also store various applications and data, as well as data used and / or generated by the applications.

[0170] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 1800 can refer to the above description of the cache operation method and / or instruction processing method, which will not be repeated here.

[0171] At least some embodiments of the present disclosure also provide a non-transitory storage medium. Figure 19 A schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 19As shown, the storage medium 1900 non-temporarily stores computer executable instructions 1901. When the non-temporary computer executable instructions 1901 are executed by a computer (including a processor), the cache operation method and / or instruction processing method provided by any embodiment of the present disclosure can be executed.

[0172] For example, one or more computer instructions may be stored on the storage medium 1900. Some of the computer instructions stored on the storage medium 1900 may be, for example, instructions for implementing one or more steps in the above-mentioned cache operation method and / or instruction processing method.

[0173] For example, the storage medium may include a tablet computer storage component, a personal computer hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), flash memory, or any combination thereof, or other suitable storage media. For example, the storage medium 1900 may include the memory 1920 in the aforementioned electronic device 1900.

[0174] The technical effects of the storage medium provided by the embodiments of the present disclosure can be referred to the corresponding descriptions of the cache operation method and / or instruction processing method in the above embodiments, which will not be repeated here.

[0175] Figure 20 A schematic block diagram of an electronic device according to at least another embodiment of the present disclosure is shown.

[0176] At least some embodiments of the present disclosure further provide an electronic device comprising the processor core of any of the aforementioned embodiments. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 20 The electronic device 2000 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0177] For example, Figure 20As shown, in some examples, electronic device 2000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 2001. This processing device may include a processor core according to any of the above-described embodiments. It can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 2002 or programs loaded from a storage device 2008 into a random access memory (RAM) 2003. RAM 2003 also stores various programs and data required for the operation of the computer system. Processor 2001, ROM 2002, and RAM 2003 are connected to each other via a bus 2004. An input / output (I / O) interface 2005 is also connected to bus 2004.

[0178] For example, the following components may be connected to the I / O interface 2005: an input device 2006 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 2007 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; a storage device 2008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 2009, which may also include, for example, a network interface card such as a LAN card or modem. The communication device 2009 may allow the electronic device 2000 to communicate with other devices wirelessly or wired to exchange data, performing communication processing via a network such as the Internet. A drive 2010 is also connected to the I / O interface 2005 as needed. Removable media 2011, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in the drive 2010 as needed, so that computer programs read from the removable media can be installed into the storage device 2008 as needed.

[0179] Although Figure 20 The electronic device 2000 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0180] For example, the electronic device 2000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 2009 may communicate with a network and other devices via wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0181] For example, the electronic device 2000 may include any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or may be any combination of data processing devices and hardware, which is not limited in the embodiments of the present disclosure.

[0182] Regarding this disclosure, the following points need to be explained:

[0183] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design.

[0184] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0185] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A cache, including multiple cache entries, in, Each of the cache entries is configured to store information associated with a microinstruction group, each of the cache entries includes an address field corresponding to the corresponding microinstruction group, wherein the address field includes at least two address subfields; each of the address subfields is used to store address information of a microinstruction address of a microinstruction group; In response to the target microinstruction group being filled in the microinstruction cache, storing address information of a microinstruction address of the target microinstruction group in the microinstruction cache in an address field of a cache entry corresponding to the target microinstruction group; In response to the next microinstruction group immediately following the target microinstruction group being filled in the microinstruction cache and being in the same cache block as the target microinstruction, address information of the microinstruction address of the next microinstruction group in the microinstruction cache is stored in the address subfield of the cache entry corresponding to the target microinstruction group.

2. The cache according to claim 1, wherein: The address information includes the microinstruction end address.

3. The cache according to claim 1 or 2, wherein: Each of the cache entries also includes a microtag field and a valid bit, The microtag field stores a microtag of the corresponding microinstruction group; the microtag is determined based on a microinstruction start address of the microinstruction group in the microinstruction cache; The validity information of the corresponding microinstruction group is stored in the valid bit.

4. A microinstruction cache comprising: A first sub-cache is configured to provide a microinstruction group storage space; as well as a second sub-cache comprising a plurality of cache entries, wherein each of the cache entries is configured to store information associated with a microinstruction group, each of the cache entries comprising an address field corresponding to the corresponding microinstruction group, wherein the address field comprises at least two address sub-fields; each of the address sub-fields is used to store address information of a microinstruction address of a microinstruction group, and in response to a target microinstruction group being filled in the first sub-cache, the address information of the microinstruction address of the target microinstruction group in the first sub-cache is stored in the address field of the cache entry corresponding to the target microinstruction group; In response to the next microinstruction group immediately following the target microinstruction group being filled in the first sub-cache and in the same cache block as the target microinstruction, address information of the microinstruction address of the next microinstruction group in the first sub-cache is stored in the address subfield of the cache entry corresponding to the target microinstruction group.

5. A processor core comprising: A first sub-cache is configured to provide a microinstruction group storage space; a second sub-cache, comprising a plurality of cache entries, each of the cache entries being configured to store information associated with a microinstruction group, each of the cache entries comprising an address field corresponding to the corresponding microinstruction group, wherein the address field comprises at least two address subfields; each of the address subfields being used to store address information of a microinstruction address of a microinstruction group; and The cache operation module is configured as follows: In response to the target microinstruction group being filled in the first sub-cache, obtaining a microinstruction address of the target microinstruction group in the first sub-cache; and storing the address information of the microinstruction address into the address field of the cache entry corresponding to the target microinstruction group in the second sub-cache; In response to the next microinstruction group immediately following the target microinstruction group being filled in the first sub-cache and in the same cache block as the target microinstruction, address information of the microinstruction address of the next microinstruction group in the first sub-cache is stored in the address subfield of the cache entry corresponding to the target microinstruction group. The processor core according to claim 5 , wherein: The address information includes the microinstruction end address.

7. The processor core according to claim 5 or 6, wherein: The cache operation module is further configured to: In response to receiving an instruction fetch request for the target microinstruction group, obtaining a first instruction fetch address of the target microinstruction group; Acquire, from the second sub-cache, address information stored in an address field of a cache entry corresponding to the target microinstruction group, wherein the address information is provided for obtaining an instruction fetch address of the next microinstruction group of the target microinstruction group; Obtaining a second instruction fetch address of a first microinstruction group based on the obtained address information, wherein the first microinstruction group and the target microinstruction group are stored in the same cache block of the first sub-cache and are immediately after the target microinstruction group; and Based on the first instruction fetch address and the second instruction fetch address, the target microinstruction group and the first microinstruction group are read from the first sub-cache in parallel.

8. The processor core according to claim 7, wherein: The first sub-cache includes at least two read ports; The cache operation module is further configured to: Based on the first instruction fetch address and the second instruction fetch address, the target microinstruction group and the first microinstruction group are read in parallel through the at least two read ports.

9. The processor core according to claim 7, wherein: The cache operation module is further configured to: Obtaining a third instruction fetch address of a second microinstruction group based on the obtained address information, wherein the second microinstruction group and the target microinstruction group are stored in the same cache block of the microinstruction cache and are immediately after the first microinstruction group; and Based on the third instruction fetch address, the second microinstruction group is read in parallel with the target microinstruction group and the first microinstruction group.

10. The processor core according to claim 7, wherein the cache operation module is further configured to: In response to the address information of the microinstruction address of the target microinstruction group in the first sub-cache determined based on the target microinstruction group being different from the address information obtained from the address field in the cache entry corresponding to the target microinstruction group in the second sub-cache, the read first microinstruction group is abandoned.

11. The processor core according to claim 7, further comprising a microinstruction queue, wherein the microinstruction queue comprises a write port; wherein: The write port is configured to write the target microinstruction group and the first microinstruction group to the microinstruction queue in parallel.

12. The processor core according to claim 5, wherein: The address field includes at least two address subfields; each of the address subfields is used to store address information of a microinstruction address; The cache operation module is further configured to: In response to a first microinstruction group adjacent to the target microinstruction group being filled in the first sub-cache and in the same cache block as the target microinstruction group, address information of the microinstruction address of the first microinstruction group in the first sub-cache is stored in the address subfield of the cache entry corresponding to the target microinstruction group.

13. The processor core according to claim 12, wherein: The cache operation module is further configured to: In response to the third microinstruction group being filled in the first sub-cache, obtaining an index of the third microinstruction group based on a microinstruction address of the third microinstruction group; and In response to the index of the third microinstruction group being the same as the target index and the address subfield of the target cache entry being not fully stored, storing address information of the microinstruction address of the third microinstruction group in the first sub-cache in the address subfield that does not store address information, The target index is the index of the microinstruction group corresponding to the cache entry updated last time, and the target cache entry is the cache entry updated last time.

14. The processor core according to claim 13, wherein: The cache operation module is further configured to: In response to the index of the third microinstruction group being the same as the target index and the address subfield of the target cache entry being full, selecting a first cache entry other than the target cache entry, and storing address information of a microinstruction address of the third microinstruction group in the first sub-cache in the address field of the first cache entry; and The target cache entry is updated to the first cache entry.

15. The processor core according to claim 14, wherein: Each of the cache entries also includes a microtag field; The cache operation module is further configured to: Obtaining a microtag of the second microinstruction group based on a microinstruction start address of the third microinstruction group; as well as In response to storing address information of the microinstruction address of the third microinstruction group in the first sub-cache in the address field of the first cache entry, storing a microtag of the third microinstruction group in the microtag field of the first cache entry.

16. The processor core according to claim 13, wherein: The cache operation module is further configured to: In response to the index of the third microinstruction group being different from the target index, selecting a second cache entry other than the target cache entry, and storing address information of a microinstruction address of the third microinstruction group in the first sub-cache in an address field of the second cache entry; as well as The target index is updated to the index of the third microinstruction group, and the target cache entry is updated to the second cache entry.

17. The processor core according to claim 16, wherein: Each of the cache entries also includes a microtag field; The cache operation module is further configured to: Acquire a microtag of the third microinstruction group based on a microinstruction start address of the third microinstruction group; as well as In response to storing address information of the microinstruction address of the third microinstruction group in the first sub-cache in the address field of the second cache entry, storing the microtag of the third microinstruction group in the microtag field of the second cache entry.

18. A cache operation method, comprising: In response to the target microinstruction group being populated in the microinstruction cache, selecting a target cache entry among a plurality of cache entries included in the cache; as well as Storing address information of a microinstruction address of the target microinstruction group in the microinstruction cache in an address field included in the target cache entry, wherein the address field includes at least two address subfields; each of the address subfields is used to store address information of a microinstruction address of a microinstruction group; In response to the next microinstruction group immediately following the target microinstruction group being filled in the microinstruction cache and being in the same cache block as the target microinstruction, address information of the microinstruction address of the next microinstruction group in the microinstruction cache is stored in the address subfield of the cache entry corresponding to the target microinstruction group.

19. A method for processing an instruction, comprising: In response to the target microinstruction group being filled in the first sub-cache, obtaining a microinstruction address of the target microinstruction group in the first sub-cache; as well as storing the address information of the microinstruction address in an address field of a cache entry corresponding to the target microinstruction group in the second sub-cache, wherein the address field includes at least two address sub-fields; each of the address sub-fields is used to store the address information of the microinstruction address of a microinstruction group; In response to the next microinstruction group immediately following the target microinstruction group being filled in the microinstruction cache and being in the same cache block as the target microinstruction, address information of the microinstruction address of the next microinstruction group in the microinstruction cache is stored in the address subfield of the cache entry corresponding to the target microinstruction group.

20. The method according to claim 19, further comprising: In response to receiving an instruction fetch request for the target microinstruction group, obtaining a first instruction fetch address of the target microinstruction group; Acquire, from the second sub-cache, address information stored in an address field of a cache entry corresponding to the target microinstruction group, wherein the address information is provided for obtaining an instruction fetch address of the next microinstruction group of the target microinstruction group; Obtaining a second instruction fetch address of a first microinstruction group based on the obtained address information, wherein the first microinstruction group and the target microinstruction group are stored in the same cache block of the first sub-cache and are immediately after the target microinstruction group; and Based on the first instruction fetch address and the second instruction fetch address, the target microinstruction group and the first microinstruction group are read from the first sub-cache in parallel.

21. An electronic device comprising: processor; as well as a memory comprising one or more computer program instructions; The one or more computer program instructions are executed by the processor to perform the method according to any one of claims 18 to 20.

22. A computer-readable storage medium non-transitorily storing computer-readable instructions, wherein: When the computer-readable instructions are executed by a processor, the method according to any one of claims 18 to 20 is implemented.

Images