CMOS inverter performance evaluation method, electronic equipment and readable storage medium

Abstract

The invention provides a CMOS (complementary metal oxide semiconductor) inverter performance evaluation method, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining the width size information of a target PMOS (P-channel metal oxide semiconductor) of a CMOS inverter, and enabling the threshold voltage of the CMOS inverter to be equal to half of the operation voltage when the width size of a PMOS tube in the CMOS inverter is the width size of the target PMOS; according to the target PMOS width size information, performing circuit simulation on the CMOS phase inverter to obtain target performance parameter information of the CMOS phase inverter under the target PMOS width size; and according to the target performance parameter information, carrying out Monte Carlo simulation on the CMOS inverter for a preset number of times to obtain performance parameter distribution information of the CMOS inverter under the target PMOS width size. According to the method, the performance parameter distribution characteristics of the CMOS phase inverter during mass production can be known in advance, so that the resource investment for performance analysis of the CMOS phase inverter at the initial stage of production and manufacturing can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a CMOS inverter performance evaluation method, electronic equipment and a readable storage medium. Background Art

[0002] The CMOS inverter is composed of two enhancement mode MOS (Metal Oxide Semiconductor), namely NMOS (N-Metal-Oxide-Semiconductor) and PMOS (P-Metal-Oxide-Semiconductor).

[0003] In the prior art, when analyzing the performance of CMOS inverters in the early stage of CMOS inverter production and manufacturing, a large amount of test data is required to support the judgment, so more resources need to be invested in the early stage of CMOS inverter production and manufacturing. Therefore, how to reduce the resource investment in CMOS inverter performance analysis in the early stage of CMOS inverter production and manufacturing has become one of the problems that technicians in this field need to solve urgently.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide a CMOS inverter performance evaluation method, an electronic device and a readable storage medium. By performing a preset number of Monte Carlo simulations on the CMOS inverter before mass production of the CMOS inverter product, the performance parameter distribution characteristics of the CMOS inverter during mass production can be known in advance, thereby effectively reducing the resource investment in CMOS inverter performance analysis in the early stage of production.

[0006] To achieve the above object, the present invention provides a CMOS inverter performance evaluation method, the evaluation method comprising:

[0007] Acquiring target PMOS width size information of a CMOS inverter, wherein when the width size of a PMOS tube in the CMOS inverter is the target PMOS width size, a threshold voltage of the CMOS inverter is equal to half of an operating voltage;

[0008] According to the target PMOS width size information, circuit simulation is performed on the CMOS inverter to obtain target performance parameter information of the CMOS inverter under the target PMOS width size;

[0009] A preset number of Monte Carlo simulations are performed on the CMOS inverter according to the target performance parameter information to obtain performance parameter distribution information of the CMOS inverter under the target PMOS width size.

[0010] Optionally, the step of obtaining target PMOS width size information of the CMOS inverter includes:

[0011] Obtaining voltage transfer characteristic curves of the CMOS inverter under different PMOS width sizes;

[0012] For each PMOS width, determining a threshold voltage of the CMOS inverter at the PMOS width according to a voltage transfer characteristic curve of the CMOS inverter at the PMOS width;

[0013] A PMOS width dimension that makes the threshold voltage of the CMOS inverter equal to half of the operating voltage is used as a target PMOS width dimension of the CMOS inverter.

[0014] Optionally, the obtaining of the voltage transfer characteristic curve of the CMOS inverter under different PMOS width sizes includes:

[0015] A direct current simulation is performed on the CMOS inverter according to different PMOS width size information to obtain a voltage transfer characteristic curve of the CMOS inverter under different PMOS width sizes.

[0016] Optionally, the target performance parameter information includes target transient energy consumption information and target propagation delay time information;

[0017] The performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target performance parameter information to obtain performance parameter distribution information of the CMOS inverter under the target PMOS width size includes:

[0018] Performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information to obtain transient energy consumption distribution information of the CMOS inverter under the target PMOS width size; and

[0019] A preset number of Monte Carlo simulations are performed on the CMOS inverter according to the target propagation delay time information to obtain propagation delay time distribution information of the CMOS inverter under the target PMOS width size.

[0020] Optionally, performing circuit simulation on the CMOS inverter according to the target PMOS width size information to obtain target performance parameter information of the CMOS inverter under the target PMOS width size includes:

[0021] According to the target PMOS width size information, a transient simulation is performed on the CMOS inverter to obtain a transient energy consumption simulation result and a propagation delay time simulation result of the CMOS inverter under the target PMOS width size;

[0022] According to the average value of the transient energy consumption simulation results, obtaining target transient energy consumption information of the CMOS inverter at the target PMOS width size; and

[0023] According to the average value of the propagation delay time simulation results, target propagation delay time information of the CMOS inverter under the target PMOS width size is obtained.

[0024] Optionally, the propagation delay time simulation result includes a rising propagation delay time simulation result and a falling propagation delay time simulation result;

[0025] The step of obtaining target propagation delay time information of the CMOS inverter at the target PMOS width size according to the average value of the propagation delay time simulation result includes:

[0026] According to an average value of the rising propagation delay time simulation result and the falling propagation delay time simulation result, target propagation delay time information of the CMOS inverter at the target PMOS width size is obtained.

[0027] Optionally, performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information to obtain transient energy consumption distribution information of the CMOS inverter under the target PMOS width size includes:

[0028] Performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information to obtain a plurality of transient energy consumption sample values ​​of the CMOS inverter under the target PMOS width size;

[0029] Frequency statistics and Gaussian curve fitting are performed according to a plurality of transient energy consumption sample values ​​of the CMOS inverter under the target PMOS width size, so as to obtain transient energy consumption distribution information of the CMOS inverter under the target PMOS width size.

[0030] Optionally, performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target propagation delay time information to obtain propagation delay time distribution information of the CMOS inverter under the target PMOS width size includes:

[0031] Performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target propagation delay time information to obtain a plurality of propagation delay time sample values ​​of the CMOS inverter under the target PMOS width size;

[0032] Frequency statistics and Gaussian curve fitting are performed according to a plurality of propagation delay time sample values ​​of the CMOS inverter under the target PMOS width size, so as to obtain propagation delay time distribution information of the CMOS inverter under the target PMOS width size.

[0033] Optionally, the preset number of times is greater than or equal to 5000 times.

[0034] To achieve the above object, the present invention further provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the CMOS inverter performance evaluation method described above is implemented.

[0035] To achieve the above object, the present invention further provides a readable storage medium, wherein the readable storage medium stores a computer program, and when the computer program is executed by a processor, the CMOS inverter performance evaluation method described above is implemented.

[0036] Compared with the prior art, the CMOS inverter performance evaluation method, electronic device and readable storage medium provided by the present invention have the following beneficial effects:

[0037] The CMOS inverter performance evaluation method provided by the present invention first obtains the target PMOS width size information of the CMOS inverter; then, according to the target PMOS width size information, the circuit simulation of the CMOS inverter is performed to obtain the target performance parameter information of the CMOS inverter under the target PMOS width size; finally, according to the target performance parameter information, the CMOS inverter is subjected to a preset number of Monte Carlo simulations to obtain the performance parameter distribution information of the CMOS inverter under the target PMOS width size. It can be seen that the CMOS inverter performance evaluation method provided by the present invention performs a preset number of Monte Carlo simulations on the CMOS inverter before the mass production of the CMOS inverter product, so that the performance parameter distribution characteristics of the CMOS inverter during mass production can be known in advance, thereby effectively reducing the resource investment in the performance analysis of the CMOS inverter in the early stage of product production. In addition, the CMOS inverter performance evaluation method provided by the present invention can obtain the performance parameter distribution information of the CMOS inverter under the target PMOS width size, so as to implement the product process level of the CMOS inverter. In addition, since the current intensity of the NMOS tube is generally greater than that of the PMOS tube under the same size (width W / length L), the CMOS inverter performance evaluation method provided by the present invention can obtain the simplest control result by controlling the width size of the PMOS tube, thereby effectively simplifying the optimization process of the CMOS inverter.

[0038] Since the electronic device and the readable storage medium provided by the present invention belong to the same inventive concept as the CMOS inverter performance evaluation method provided by the present invention, the electronic device and the readable storage medium provided by the present invention at least have all the beneficial effects of the CMOS inverter performance evaluation method provided by the present invention. For details, please refer to the relevant description of the beneficial effects of the CMOS inverter performance evaluation method provided by the present invention in the above text. Therefore, the beneficial effects of the electronic device and the readable storage medium provided by the present invention will not be described one by one here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A flow chart of a CMOS inverter performance evaluation method provided by one embodiment of the present invention;

[0040] Figure 2 A schematic diagram of a DC simulation circuit of a CMOS inverter provided in one embodiment of the present invention;

[0041] Figure 3 A voltage transfer characteristic curve diagram of a CMOS inverter provided in one embodiment of the present invention under different PMOS widths;

[0042] Figure 4 A schematic diagram of a transient simulation circuit of a CMOS inverter provided in one embodiment of the present invention;

[0043] Figure 5 A schematic diagram of transient energy consumption simulation results of a CMOS inverter provided in an embodiment of the present invention at a target PMOS width size;

[0044] Figure 6 A schematic diagram of propagation delay time simulation results of a CMOS inverter under a target PMOS width size provided by one embodiment of the present invention;

[0045] Figure 7 A schematic diagram of transient energy consumption distribution information of a CMOS inverter under a target PMOS width size provided by one embodiment of the present invention;

[0046] Figure 8 A schematic diagram of propagation delay time distribution information of a CMOS inverter under a target PMOS width size provided by one embodiment of the present invention;

[0047] Fig. 9 A schematic diagram of the block structure of an electronic device provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0048] The CMOS inverter performance evaluation method, electronic device and readable storage medium proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose provided by the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Any structural modification, change in proportional relationship or adjustment of size, under the same or similar conditions as the effects that can be produced by the present invention and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present invention.

[0049] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. The singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features.

[0050] In addition, in the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0051] The core idea of ​​the present invention is to provide a CMOS inverter performance evaluation method, an electronic device and a readable storage medium. By performing a preset number of Monte Carlo simulations on the CMOS inverter before mass production of the CMOS inverter product, the performance parameter distribution characteristics of the CMOS inverter during mass production can be known in advance, thereby effectively reducing the resource investment in CMOS inverter performance analysis in the early stage of product production.

[0052] It should be noted that the CMOS inverter performance evaluation method provided by the present invention can be applied to the electronic device provided by the present invention, wherein the electronic device can be a personal computer, a mobile terminal, etc., and the mobile terminal can be a mobile phone, a tablet computer, and other hardware devices with various operating systems.

[0053] To realize the above idea, the present invention provides a CMOS inverter performance evaluation method, please refer to Figure 1 , which is a flow chart of a CMOS inverter performance evaluation method provided by one embodiment of the present invention, such as Figure 1 As shown, the CMOS inverter performance evaluation method provided by the present invention comprises the following steps:

[0054] Step S100, obtaining target PMOS width size information of a CMOS inverter, wherein when the width size of a PMOS tube in the CMOS inverter is the target PMOS width size, the threshold voltage of the CMOS inverter is equal to half of the operating voltage.

[0055] Step S200: performing circuit simulation on the CMOS inverter according to the target PMOS width size information to obtain target performance parameter information of the CMOS inverter under the target PMOS width size.

[0056] Step S300: performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target performance parameter information to obtain performance parameter distribution information of the CMOS inverter at the target PMOS width size.

[0057] It can be seen that the CMOS inverter performance evaluation method provided by the present invention can know in advance the performance parameter distribution characteristics of the CMOS inverter during mass production by performing a preset number of Monte Carlo simulations on the CMOS inverter before the mass production of the CMOS inverter product, thereby effectively reducing the resource investment in the performance analysis of the CMOS inverter in the early stage of product production. In addition, the CMOS inverter performance evaluation method provided by the present invention can know in advance the performance optimization degree of the CMOS inverter under the target PMOS width size by obtaining the performance parameter distribution information of the CMOS inverter under the target PMOS width size, and implement the product process level of the CMOS inverter. In addition, since the current intensity of the NMOS tube is generally greater than the current intensity of the PMOS tube under the same size (width W / length L), the CMOS inverter performance evaluation method provided by the present invention can obtain the simplest control result by controlling the width size of the PMOS tube, thereby effectively simplifying the optimization process of the CMOS inverter.

[0058] It should be noted that, as can be understood by those skilled in the art, "the threshold voltage of the CMOS inverter is equal to half of the operating voltage" referred to in this article means that the threshold voltage of the CMOS inverter is equal to or approximately equal to (close to) half of the operating voltage.

[0059] In some exemplary embodiments, the step of obtaining target PMOS width size information of a CMOS inverter includes:

[0060] Obtaining voltage transfer characteristic curves of the CMOS inverter under different PMOS width sizes;

[0061] For each PMOS width, determining a threshold voltage of the CMOS inverter at the PMOS width according to a voltage transfer characteristic curve of the CMOS inverter at the PMOS width;

[0062] A PMOS width dimension that makes the threshold voltage of the CMOS inverter equal to half of the operating voltage is used as a target PMOS width dimension of the CMOS inverter.

[0063] Therefore, by selecting the PMOS width size that makes the threshold voltage of the CMOS inverter equal to half of the operating voltage as the target PMOS width size of the CMOS inverter, the CMOS inverter can have the best performance, that is, the propagation delay time of the CMOS inverter can be effectively reduced.

[0064] Specifically, please refer to Figure 2 , which is a schematic diagram of a DC simulation circuit of a CMOS inverter provided by an embodiment of the present invention. Figure 2 As shown, when the CMOS inverter is subjected to DC simulation, the voltage VDC output by the DC power supply varies in the range of 0V to 0.9V (that is, the operating voltage VDD varies in the range of 0V to 0.9V). It should be noted that, as can be understood by those skilled in the art, the capacitance of the external capacitor CL in the simulation circuit can be set to 1pf.

[0065] Please continue to refer to Figure 3 , which is a voltage transfer characteristic curve diagram of a CMOS inverter provided by an embodiment of the present invention under different PMOS width sizes. Figure 3 As shown, the PMOS width size (Wp=500nm) that makes the intersection point (threshold voltage) of the input voltage VIN and the output voltage VOUT of the CMOS inverter near VDD / 2 (VDD is the operating voltage) is the ideal PMOS width size (target PMOS width size) of the CMOS inverter.

[0066] In some exemplary embodiments, obtaining the voltage transfer characteristic curve of the CMOS inverter under different PMOS width sizes includes:

[0067] A direct current simulation is performed on the CMOS inverter according to different PMOS width size information to obtain a voltage transfer characteristic curve of the CMOS inverter under different PMOS width sizes.

[0068] Specifically, when DC simulation is performed on the CMOS inverter according to different PMOS width size information, the size of the NMOS tube of the CMOS inverter (including the NMOS width size and the NMOS length size, where the NMOS width size can be 100nm and the NMOS length size can be 30nm) and the length size of the PMOS tube (PMOS length size, the PMOS length size can be 30nm) should be kept unchanged.

[0069] In some exemplary embodiments, the target performance parameter information includes target transient energy consumption information and target propagation delay time information.

[0070] Correspondingly, performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target performance parameter information to obtain performance parameter distribution information of the CMOS inverter under the target PMOS width size includes:

[0071] Performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information to obtain transient energy consumption distribution information of the CMOS inverter under the target PMOS width size; and

[0072] A preset number of Monte Carlo simulations are performed on the CMOS inverter according to the target propagation delay time information to obtain propagation delay time distribution information of the CMOS inverter under the target PMOS width size.

[0073] Therefore, by performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information and the target propagation delay time information of the CMOS inverter at the target PMOS width size, the transient energy consumption distribution information and the propagation delay time distribution information of the CMOS inverter at the target PMOS width size are obtained. The energy consumption distribution characteristics and the performance distribution characteristics of the CMOS inverter during mass production can be known in advance, so that the designer can know in advance the energy consumption optimization degree and the performance optimization degree of the CMOS inverter at the target PMOS width size.

[0074] In some exemplary embodiments, the performing circuit simulation on the CMOS inverter according to the target PMOS width size information to obtain target performance parameter information of the CMOS inverter under the target PMOS width size includes:

[0075] According to the target PMOS width size information, a transient simulation is performed on the CMOS inverter to obtain a transient energy consumption simulation result and a propagation delay time simulation result of the CMOS inverter under the target PMOS width size;

[0076] According to the average value of the transient energy consumption simulation results, obtaining target transient energy consumption information of the CMOS inverter at the target PMOS width size; and

[0077] According to the average value of the propagation delay time simulation results, target propagation delay time information of the CMOS inverter under the target PMOS width size is obtained.

[0078] Thus, by taking the average value (total transient energy consumption / total time) of the transient energy consumption simulation results of the CMOS inverter at the target PMOS width size as the target transient energy consumption value of the CMOS inverter at the target PMOS width size, the transient energy consumption distribution information obtained by performing a preset number of Monte Carlo simulations based on the target transient energy consumption value can more accurately reflect the transient energy consumption distribution characteristics of the CMOS inverter at the target PMOS width size. By taking the average value of the propagation delay time simulation results of the CMOS inverter at the target PMOS width size as the target propagation delay time of the CMOS inverter at the target PMOS width size, the propagation delay time distribution information obtained by performing a preset number of Monte Carlo simulations based on the target propagation delay time can more accurately reflect the propagation delay time distribution characteristics of the CMOS inverter at the target PMOS width size.

[0079] Please continue to refer to Figure 4 , which is a schematic diagram of a transient simulation circuit of a CMOS inverter provided by an embodiment of the present invention. Specifically, when performing transient simulation on the CMOS inverter, the transient energy consumption simulation result of the CMOS inverter under the target PMOS width size can be obtained under the condition that the voltage VDC output by the DC power supply is fixed at 0.9V (that is, VDD is fixed at 0.9V) and the input voltage VIN varies in the range of 0V to 1V; the propagation delay time simulation result of the CMOS inverter under the target PMOS width size can be obtained under the condition that the voltage VDC output by the DC power supply varies in the range of 0V to 0.9V (that is, the operating voltage VDD varies in the range of 0V to 0.9V).

[0080] Please continue to refer to 5 and Figure 6 ,in, Figure 5 A schematic diagram of transient energy consumption simulation results of a CMOS inverter provided in an embodiment of the present invention at a target PMOS width size; Figure 6 This is a schematic diagram of the propagation delay time simulation results of a CMOS inverter under a target PMOS width size provided by one embodiment of the present invention. Figure 5 The transient energy consumption simulation results shown in FIG. 1 can calculate that the target transient energy consumption (Power) value of the CMOS inverter at the target PMOS width size (eg, 500 nm) is 72.2288 nW; Figure 6 The propagation delay time simulation results shown in FIG. 1 can calculate that the target propagation delay time Tpd of the CMOS inverter under the target PMOS width size is 13.6563ps. By performing transient simulation on the CMOS inverter of the original PMOS width size (e.g., 100nm), it can be calculated that the transient energy consumption (Powe) value of the CMOS inverter under the original PMOS width size (e.g., 100nm) is 53.5717nW, and the propagation delay time Tpd is 17.3663ps. By comparison, it can be seen that the transient power consumption of the CMOS inverter under the target PMOS width size is increased compared with the transient power consumption of the CMOS inverter under the original PMOS width size, but the propagation delay time of the CMOS inverter under the target PMOS width size is reduced by 21.3% compared with the propagation delay time of the CMOS inverter under the original PMOS width size. It can be seen that by increasing the width size of the PMOS tube of the CMOS inverter, the performance of the CMOS inverter can be effectively improved.

[0081] In some exemplary embodiments, the propagation delay time simulation result includes a rising propagation delay time simulation result and a falling propagation delay time simulation result;

[0082] The step of obtaining target propagation delay time information of the CMOS inverter at the target PMOS width size according to the average value of the propagation delay time simulation result includes:

[0083] According to an average value of the rising propagation delay time simulation result and the falling propagation delay time simulation result, target propagation delay time information of the CMOS inverter at the target PMOS width size is obtained.

[0084] Specifically, the average rising propagation delay time can be calculated according to the simulation result of the rising propagation delay time, and the average falling propagation delay time can be calculated according to the simulation result of the falling propagation delay time. The target propagation delay time of the CMOS inverter at the target PMOS width size can be obtained according to the average value of the average rising propagation delay time and the average falling propagation delay time.

[0085] For example, assuming that the average rising propagation delay time Tpdr is 16.6746 ps and the average falling propagation delay time Tpdf is 10.6377 ps, the target propagation delay time Tpd of the CMOS inverter at the target PMOS width size is = (Tpdr+Tpdf) / 2 = 13.6563 ps.

[0086] In some exemplary embodiments, performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information to obtain transient energy consumption distribution information of the CMOS inverter at the target PMOS width size includes:

[0087] Performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information to obtain a plurality of transient energy consumption sample values ​​of the CMOS inverter under the target PMOS width size;

[0088] Frequency statistics and Gaussian curve fitting are performed according to a plurality of transient energy consumption sample values ​​of the CMOS inverter under the target PMOS width size, so as to obtain transient energy consumption distribution information of the CMOS inverter under the target PMOS width size.

[0089] Therefore, by performing a preset number of Monte Carlo simulations (e.g., 8000 times) on the CMOS inverter according to the target transient energy consumption value (e.g., 72.2288 nW), 8000 transient energy consumption sample values ​​of the CMOS inverter at the target PMOS width size can be obtained, and by performing frequency statistics and Gaussian curve fitting on these 8000 transient energy consumption sample values, the transient energy consumption distribution information of the CMOS inverter at the target PMOS width size can be obtained.

[0090] For example, please refer to Figure 7 , which is a schematic diagram of transient energy consumption distribution information of a CMOS inverter under a target PMOS width size provided by an embodiment of the present invention. Figure 7As shown, the average transient energy consumption (Mean, i.e., μ) of the CMOS inverter at the target PMOS width size is 73.5203 ​​nW, and the standard deviation (StdDev, i.e., σ) is 1.16862 nW. It can be seen that in actual mass production, the transient energy consumption of CMOS inverter products should be between [70.0145 nW, 77.0262 nW].

[0091] It should be noted that, as can be understood by those skilled in the art, Figure 7 Skewness in the equation represents skewness (Skewness = 957.516m = 957.516 × 10 -3 ), Kurtosis represents kurtosis, Number represents the number of transient energy consumption sample values, and Jarque-Bera represents JB statistic (Jarque-Bera = 1.75923k = 1.75923 × 10 3 ).

[0092] In some exemplary embodiments, performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target propagation delay time information to obtain propagation delay time distribution information of the CMOS inverter at the target PMOS width size includes:

[0093] Performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target propagation delay time information to obtain a plurality of propagation delay time sample values ​​of the CMOS inverter under the target PMOS width size;

[0094] Frequency statistics and Gaussian curve fitting are performed according to a plurality of propagation delay time sample values ​​of the CMOS inverter under the target PMOS width size, so as to obtain propagation delay time distribution information of the CMOS inverter under the target PMOS width size.

[0095] Therefore, by performing a preset number of (e.g., 8000) Monte Carlo simulations on the CMOS inverter according to the target propagation delay time information, 8000 propagation delay time sample values ​​of the CMOS inverter at the target PMOS width size can be obtained, and by performing frequency statistics and Gaussian curve fitting on these 8000 propagation delay time sample values, the propagation delay time distribution information of the CMOS inverter at the target PMOS width size can be obtained.

[0096] For example, please refer to Figure 8 , which is a schematic diagram of the propagation delay time distribution information of a CMOS inverter under a target PMOS width size provided by an embodiment of the present invention. Figure 8As shown, the average propagation delay time (Mean, i.e., μ) of the CMOS inverter at the target PMOS width size is 13.6653 ps, and the standard deviation (Std Dev, i.e., σ) is 630.262 fs. It can be seen that in actual mass production, the propagation delay time of the CMOS inverter product should be between [11.7745 ps, 15.5561 ps].

[0097] It should be noted that, as can be understood by those skilled in the art, Figure 8 Skewness in the equation represents skewness (Skewness = 55.3426m = 55.3426 × 10 -3 ), Kurtosis represents kurtosis (Kurtosis = -8.59823m = -8.59823×10 -3 ), Number represents the number of propagation delay time sample values, and Jarque-Bera represents the JB statistic.

[0098] In some exemplary embodiments, the preset number of times is greater than or equal to 5000. Thus, by performing at least 5000 Monte Carlo simulations on the CMOS inverter according to the target performance parameter information (including target transient energy consumption information and target propagation delay time information) of the CMOS inverter at the target PMOS width size, the accuracy of the obtained performance parameter distribution information (including transient energy consumption distribution information and propagation delay time distribution information) of the CMOS inverter at the target PMOS width size can be effectively guaranteed.

[0099] Based on the same inventive concept, the present invention also provides an electronic device, please refer to Fig. 9 , which is a schematic diagram of a block structure of an electronic device provided by an embodiment of the present invention. Fig. 9 As shown, the electronic device includes a processor 101 and a memory 103, and a computer program is stored in the memory 103. When the computer program is executed by the processor 101, the CMOS inverter performance evaluation method described above is implemented. Since the electronic device provided by the present invention and the CMOS inverter performance evaluation method provided by the present invention belong to the same inventive concept, the electronic device provided by the present invention at least has all the beneficial effects of the CMOS inverter performance evaluation method provided by the present invention. For details, reference can be made to the relevant description of the beneficial effects of the CMOS inverter performance evaluation method provided by the present invention in the above text, and no further description will be given here.

[0100] Please continue to refer to Fig. 9 ,like Fig. 9As shown, the electronic device also includes a communication interface 102 and a communication bus 104, wherein the processor 101, the communication interface 102, and the memory 103 communicate with each other through the communication bus 104. The communication bus 104 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus 104 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The communication interface 102 is used for communication between the above-mentioned electronic device and other devices.

[0101] Furthermore, the processor 101 referred to in the present invention may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor 101 is the control center of the electronic device, and various interfaces and lines are used to connect various parts of the entire electronic device.

[0102] Further, the memory 103 can be used to store the computer program, and the processor 101 implements various functions of the electronic device by running or executing the computer program stored in the memory 103 and calling the data stored in the memory 103. The memory 103 may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable memory (PROM), electrically programmable memory (EPROM), electrically erasable programmable memory (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, random access memory is available in a variety of forms, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous random access memory (SDRAM), double data rate synchronous random access memory (DDRSDRAM), enhanced synchronous random access memory (ESDRAM), synchronous link (Synchlink) dynamic random access memory (SLDRAM), memory bus (Rambus) direct random access memory (RDRAM), direct memory bus dynamic random access memory (DRDRAM), and memory bus dynamic random access memory (RDRAM), etc.

[0103] The present invention also provides a readable storage medium, wherein a computer program is stored in the readable storage medium, and when the computer program is executed by a processor, the CMOS inverter performance evaluation method described above can be implemented. Since the readable storage medium provided by the present invention and the CMOS inverter performance evaluation method provided by the present invention belong to the same inventive concept, the readable storage medium provided by the present invention at least has all the beneficial effects of the CMOS inverter performance evaluation method provided by the present invention. For details, reference can be made to the above description of the beneficial effects of the CMOS inverter performance evaluation method provided by the present invention, and no further description will be given here.

[0104] Specifically, the readable storage medium provided by the present invention can adopt any combination of one or more computer-readable media. The readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, a system, device or component of electricity, magnetism, light, electromagnetic, infrared or semiconductor, or any combination of the above. More specific examples (non-exhaustive enumeration) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer hard disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this article, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, a device or a device or used in combination with it.

[0105] Further, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0106] In summary, compared with the prior art, the CMOS inverter performance evaluation method, electronic device and readable storage medium provided by the present invention have the following beneficial effects:

[0107] The present invention performs a preset number of Monte Carlo simulations on the CMOS inverter before the mass production of the CMOS inverter product, so that the performance parameter distribution characteristics of the CMOS inverter during mass production can be known in advance, thereby effectively reducing the resource investment in the performance analysis of the CMOS inverter in the early stage of product production. In addition, by obtaining the performance parameter distribution information of the CMOS inverter under the target PMOS width size, the present invention can know in advance the performance optimization degree of the CMOS inverter under the target PMOS width size, and implement the product process level of the CMOS inverter. In addition, since the current intensity of the NMOS tube is generally greater than the current intensity of the PMOS tube under the same size (width W / length L), the present invention can obtain the simplest control result by controlling the width size of the PMOS tube, thereby effectively simplifying the optimization process of the CMOS inverter.

[0108] It should be noted that the computer program code for performing the operation of the present invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages-such as Java, Smalltalk, C++, and also conventional procedural programming languages-such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network-including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0109] It should be noted that the devices and methods disclosed in the embodiments of this article can also be implemented in other ways. The device implementation described above is only schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of this article. In this regard, each box in the flowchart or block diagram can represent a part of a module, program or code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented by a dedicated hardware-based system for performing a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0110] It should also be noted that the above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of the present invention. Any changes and modifications made by a person skilled in the art in the field of the present invention based on the above disclosure are within the scope of protection of the present invention. Obviously, a person skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A CMOS inverter performance evaluation method, characterized in that: include: Acquiring target PMOS width size information of a CMOS inverter, wherein when the width size of a PMOS tube in the CMOS inverter is the target PMOS width size, a threshold voltage of the CMOS inverter is equal to half of an operating voltage; According to the target PMOS width size information, circuit simulation is performed on the CMOS inverter to obtain target performance parameter information of the CMOS inverter under the target PMOS width size; as well as A preset number of Monte Carlo simulations are performed on the CMOS inverter according to the target performance parameter information to obtain performance parameter distribution information of the CMOS inverter under the target PMOS width size.

2. The CMOS inverter performance evaluation method according to claim 1, characterized in that: The step of obtaining target PMOS width size information of the CMOS inverter includes: Obtaining voltage transfer characteristic curves of the CMOS inverter under different PMOS width sizes; For each PMOS width, determining a threshold voltage of the CMOS inverter at the PMOS width according to a voltage transfer characteristic curve of the CMOS inverter at the PMOS width; and A PMOS width dimension that makes the threshold voltage of the CMOS inverter equal to half of the operating voltage is used as a target PMOS width dimension of the CMOS inverter.

3. The CMOS inverter performance evaluation method according to claim 2, characterized in that: The step of obtaining a voltage transfer characteristic curve of the CMOS inverter under different PMOS widths includes: A direct current simulation is performed on the CMOS inverter according to different PMOS width size information to obtain a voltage transfer characteristic curve of the CMOS inverter under different PMOS width sizes.

4. The CMOS inverter performance evaluation method according to claim 1, characterized in that: The target performance parameter information includes target transient energy consumption information and target propagation delay time information; The performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target performance parameter information to obtain performance parameter distribution information of the CMOS inverter under the target PMOS width size includes: Performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information to obtain transient energy consumption distribution information of the CMOS inverter under the target PMOS width size; and A preset number of Monte Carlo simulations are performed on the CMOS inverter according to the target propagation delay time information to obtain propagation delay time distribution information of the CMOS inverter under the target PMOS width size.

5. The CMOS inverter performance evaluation method according to claim 4, characterized in that: The circuit simulation of the CMOS inverter is performed according to the target PMOS width size information to obtain target performance parameter information of the CMOS inverter under the target PMOS width size, including: According to the target PMOS width size information, a transient simulation is performed on the CMOS inverter to obtain a transient energy consumption simulation result and a propagation delay time simulation result of the CMOS inverter under the target PMOS width size; According to the average value of the transient energy consumption simulation results, obtaining target transient energy consumption information of the CMOS inverter at the target PMOS width size; and According to the average value of the propagation delay time simulation results, target propagation delay time information of the CMOS inverter under the target PMOS width size is obtained.

6. The CMOS inverter performance evaluation method according to claim 5, characterized in that: The propagation delay time simulation result includes a rising propagation delay time simulation result and a falling propagation delay time simulation result; The step of obtaining target propagation delay time information of the CMOS inverter at the target PMOS width size according to the average value of the propagation delay time simulation result includes: According to an average value of the rising propagation delay time simulation result and the falling propagation delay time simulation result, target propagation delay time information of the CMOS inverter at the target PMOS width size is obtained.

7. The CMOS inverter performance evaluation method according to claim 4, characterized in that: The performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information to obtain transient energy consumption distribution information of the CMOS inverter under the target PMOS width size includes: Performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target transient energy consumption information to obtain a plurality of transient energy consumption sample values ​​of the CMOS inverter under the target PMOS width size; and Perform frequency statistics and Gaussian curve fitting according to a plurality of transient energy consumption sample values ​​of the CMOS inverter under the target PMOS width size, so as to obtain transient energy consumption distribution information of the CMOS inverter under the target PMOS width size; The performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target propagation delay time information to obtain propagation delay time distribution information of the CMOS inverter under the target PMOS width size includes: Performing a preset number of Monte Carlo simulations on the CMOS inverter according to the target propagation delay time information to obtain a plurality of propagation delay time sample values ​​of the CMOS inverter under the target PMOS width size; and Frequency statistics and Gaussian curve fitting are performed according to a plurality of propagation delay time sample values ​​of the CMOS inverter under the target PMOS width size, so as to obtain propagation delay time distribution information of the CMOS inverter under the target PMOS width size.

8. The CMOS inverter performance evaluation method according to claim 1, characterized in that: The preset number of times is greater than or equal to 5000 times.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the CMOS inverter performance evaluation method according to any one of claims 1 to 8 is implemented.

10. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed by a processor, the CMOS inverter performance evaluation method according to any one of claims 1 to 8 is implemented.

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