Shift register, gate drive circuit, and display panel

Abstract

Embodiments of the present application disclose a shift register, a gate drive circuit and a display panel. The shift register comprises a node voltage control module, a first output module and a second output module. The node voltage control module is configured to control voltages of a first node and a second node. The first output module is configured to output a first gate drive signal according to the voltages of the first node and the second node. The second output module is configured to output a second gate drive signal according to the voltages of the first node and / or the second node. The first gate drive signal is different from the second gate drive signal. In this way, two different gate drive signals can be output by the same shift register, so as to reduce the frame of the display panel and improve user experience.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a shift register, a gate driving circuit and a display panel. BACKGROUND

[0002] In some display panels, pixel circuits include P-type transistors and N-type transistors, and two kinds of gate driving signals are needed to drive the pixel circuits. If two sets of gate driving circuits are set, the frame area will be increased, which affects the user experience. SUMMARY

[0003] The present application provides a shift register, a gate driving circuit and a display panel, which can output two different gate driving signals through the same gate driving circuit, reduce the frame area of the display panel and improve the user experience.

[0004] According to an aspect of the present application, a shift register is provided, which comprises a node voltage control module, a first output module and a second output module, the node voltage control module is connected to a first node and a second node, the first output module is connected to the first node and the second node, and the second output module is connected to the first node and / or the second node.

[0005] The node voltage control module is used to control the potential of the first node and the second node; the first output module is used to output a first gate driving signal through a first output end according to the potential of the first node and the second node; the second output module is used to output a second gate driving signal through a second output end according to the potential of the first node and / or the second node; and the first gate driving signal and the second gate driving signal are different.

[0006] Optionally, one or more of the pulse width, the pulse amplitude and the positive and negative polarity of the pulse amplitude of the first gate driving signal and the second gate driving signal are different.

[0007] Optionally, the second gate driving signal comprises a first level signal and a second level signal.

[0008] Optionally, the first gate driving signal and the second gate driving signal are used to drive transistors of different channel types.

[0009] Optionally, the first gate driving signal is used to drive a P-type transistor, and the second gate driving signal is used to drive an N-type transistor.

[0010] The voltage of the first level signal is lower than the voltage of the second level signal; the second output module comprises a P-type transistor, and the second output module is used to output the first level signal through the P-type transistor.

[0011] Optionally, the P-type transistor comprised by the second output module is a polysilicon transistor.

[0012] Optionally, the first gate drive signal comprises a first level signal and a second level signal.

[0013] Optionally, the pulse of the first gate drive signal overlaps with the pulse of the second gate drive signal.

[0014] Optionally, the duration of the first level signal of the pulse of the first gate drive signal is within the duration of the second level signal of the pulse of the second gate drive signal.

[0015] Optionally, the pulse width of the first gate drive signal is smaller than the pulse width of the second gate drive signal.

[0016] Optionally, the node voltage control module is connected to a clock signal and a start signal, the pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal.

[0017] Optionally, the clock signal connected to the node voltage control module comprises a first clock signal and a second clock signal.

[0018] The pulse of the second clock signal overlaps with the pulse of the start signal, and the pulse of the first clock signal overlaps with the pulse of the first gate drive signal.

[0019] Optionally, the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the first clock signal.

[0020] Optionally, the rising edge of the pulse of the second gate drive signal is aligned with the rising edge of the pulse of the second clock signal.

[0021] Optionally, the falling edge of the pulse of the first gate drive signal is aligned with the falling edge of the pulse of the first clock signal, and the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the first clock signal.

[0022] Optionally, the rising edge and the falling edge of the pulse of the second gate drive signal are respectively aligned with the falling edges of two adjacent pulses of the second clock signal.

[0023] Optionally, the first clock signal and the second clock signal have the same frequency and different phases.

[0024] Optionally, the second output module comprises a first output submodule and a second output submodule, the first output submodule is electrically connected to the second node, and is configured to be turned on or turned off according to the potential of the second node, and transmit the second level signal to the second output end when turned on; or the first output submodule is electrically connected to the first node, and is configured to be turned on or turned off according to the potential of the first node, and transmit the second level signal to the second output end when turned on.

[0025] The second output sub-module is connected with the first node, and is configured to transmit the first level signal to the second output end according to the electric potential of the first node; or the second output sub-module is connected with the second node, and is configured to transmit the first level signal to the second output end according to the electric potential of the second node;

[0026] Optionally, the effective levels of the first gate drive signal and the second gate drive signal overlap.

[0027] Optionally, the effective level of the first gate drive signal is the first level signal, and the effective level of the second gate drive signal is the second level signal.

[0028] Optionally, the effective levels of the first gate drive signal and the second gate drive signal overlap.

[0029] Optionally, the node voltage control module is configured to control the electric potential of the second node to jump from the high level to the low level when the electric potential of the first node jumps from the low level to the high level, and to control the electric potential of the second node to jump from the low level to the high level when the electric potential of the first node jumps from the high level to the low level.

[0030] Optionally, the node voltage control module is configured to control the electric potentials of the first node and the second node to be opposite.

[0031] Optionally, the second output sub-module is connected with the first node.

[0032] Optionally, the first output sub-module comprises a first transistor, a gate of the first transistor is connected with the second node, a first pole of the first transistor is connected with the second power supply line or inputs the second level signal, and a second pole of the first transistor is connected with the second output end.

[0033] The second output sub-module comprises a second transistor, a gate of the second transistor is connected with the first node, a first pole of the second transistor is connected with the first power supply line or inputs the first level signal, and a second pole of the second transistor is connected with the second output end.

[0034] Optionally, the second transistor is a P-type transistor.

[0035] Optionally, the first transistor is a P-type transistor.

[0036] Optionally, the second output sub-module further comprises a first capacitor, a first end of the first capacitor is connected with the gate of the second transistor, and a second end of the first capacitor is connected with the second output end.

[0037] Optionally, the second output sub-module comprises an output control unit and an output unit, the output control unit is connected with the second node, the output control unit is connected with the third node, and the output unit is connected with the third node.

[0038] The output control unit also accesses a preset clock signal, and the output control unit is configured to control the potential of the third node according to the potential of the second node and the preset clock signal, so that the potential of the third node is positively correlated with the potential of the first node;

[0039] Optionally, the node voltage control module accesses a first clock signal and / or a second clock signal, and the preset clock signal comprises the first clock signal or the second clock signal.

[0040] Optionally, the first output sub-module comprises a first transistor, a gate of the first transistor is connected with the second node, a first electrode of the first transistor is connected with the second power supply line or accesses a second level signal, and a second electrode of the first transistor is connected with the second output end; and the output unit comprises a third transistor, a gate of the third transistor is connected with the third node, a first electrode of the third transistor is connected with the first power supply line or accesses a first level signal, and a second electrode of the third transistor is connected with the second output end.

[0041] Optionally, the potential of the third node comprises a third level signal, and a voltage of the third level signal is lower than a voltage of the first power supply line.

[0042] Optionally, an absolute value of a voltage difference between the third level signal and the first level signal is greater than or equal to an absolute value of a threshold voltage of the third transistor.

[0043] Optionally, the third transistor is a P-type transistor.

[0044] Optionally, the first transistor is a P-type transistor.

[0045] Optionally, the second output sub-module further comprises a first capacitor, a first end of the first capacitor is connected with the gate of the third transistor, and a second end of the first capacitor is connected with the second output end.

[0046] Optionally, when the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; and when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential.

[0047] Optionally, the potentials of the second node and the third node are opposite in high and low.

[0048] Optionally, the potentials of the first node and the third node simultaneously jump from a low potential to a high potential, and / or the potentials of the first node and the third node simultaneously jump from a high potential to a low potential.

[0049] Optionally, the potential of the third node further comprises a second level signal, and a voltage of the third level signal is lower than a voltage of the second level signal.

[0050] Optionally, the absolute value of the voltage difference between the third level signal and the voltage of the first power line is greater than or equal to the absolute value of the threshold voltage of the second transistor.

[0051] Optionally, the output control unit comprises a charge-discharge control subunit, a coupling subunit and a unidirectional conduction subunit.

[0052] The charge-discharge control subunit is connected with the second node, the first end of the coupling subunit and the second end of the coupling subunit respectively, the second end of the coupling subunit is connected with the first end of the unidirectional conduction subunit, and the second end of the unidirectional conduction subunit is connected with the third node.

[0053] The charge-discharge control subunit is configured to charge and / or discharge the coupling subunit according to the potential of the second node and a preset clock signal; the coupling subunit is configured to couple the potential change of the first end thereof to the second end; and the unidirectional conduction subunit is configured to be turned on when the potential of the first end thereof is lower than the potential of the third node.

[0054] Optionally, the charge-discharge control subunit comprises a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the second power line or inputs the second level signal, and the second pole of the fourth transistor is connected with the first end of the coupling subunit; the gate of the fifth transistor is connected with the second end of the coupling subunit, the first pole of the fifth transistor inputs the preset clock signal, and the second pole of the fifth transistor is connected with the first end of the coupling subunit.

[0055] Optionally, the coupling subunit comprises a second capacitor, the first pole plate of the second capacitor serves as the first end of the coupling subunit, and the second pole plate of the second capacitor serves as the second end of the coupling subunit.

[0056] Optionally, the second capacitor is greater than the first capacitor.

[0057] Optionally, the unidirectional conduction subunit comprises a sixth transistor, the gate of the sixth transistor is connected with the first pole of the sixth transistor, the gate of the sixth transistor is connected with the second end of the coupling subunit, and the second pole of the sixth transistor is connected with the third node.

[0058] Optionally, the sixth transistor is a P-type transistor.

[0059] Optionally, the first output module comprises a third output sub-module and a fourth output sub-module, the third output sub-module is connected with the first node and is configured to be turned on or turned off according to the potential of the first node and output the second level signal to the first output end when turned on, and the fourth output sub-module is connected with the second node and is configured to be turned on or turned off according to the potential of the second node and output the first clock signal to the first output end when turned on.

[0060] Optionally, the third output sub-module comprises a seventh transistor, a gate of the seventh transistor is connected with the first node, a first electrode of the seventh transistor is connected with the second power supply line or inputs the second level signal, and a second electrode of the seventh transistor is connected with the first output end;

[0061] Optionally, the fourth output sub-module comprises an eighth transistor, a gate of the eighth transistor is connected with the second node, a first electrode of the eighth transistor inputs the first clock signal, and a second electrode of the eighth transistor is connected with the first output end;

[0062] Optionally, the seventh transistor is a P-type transistor, and the eighth transistor is a P-type transistor;

[0063] Optionally, the fourth output sub-module further comprises a third capacitor, a first end of the third capacitor is connected with the second node, and a second end of the third capacitor is connected with the first output end.

[0064] Optionally, the node voltage control module comprises an input unit and a first control unit, the input unit is configured to be turned on or turned off according to the second clock signal, and transmit a start signal to the second node when turned on;

[0065] The first control unit is configured to transmit the first level signal or the second level signal to the first node according to the potential of the second node;

[0066] Optionally, the node voltage control module further comprises a second control unit, the second control unit is configured to transmit the second level signal to the second node according to the potential of the first node and the first clock signal;

[0067] Optionally, the first clock signal, the second clock signal and the start signal each comprise first level pulses and second level pulses arranged alternately, the first level pulse of the start signal overlaps with the first level pulse of the second clock signal, and does not overlap with the first level pulse of the first clock signal;

[0068] Optionally, the first level pulse of the start signal is one or more, and the first level pulses of the first clock signal and the second clock signal are multiple respectively;

[0069] Optionally, the input unit comprises a ninth transistor, a gate of the ninth transistor inputs the second clock signal, a first electrode of the ninth transistor inputs the start signal, and a second electrode of the ninth transistor is connected with the second node;

[0070] Optionally, the shift register further comprises a tenth transistor, the second electrode of the ninth transistor is connected with the second node through the tenth transistor, and a gate of the tenth transistor is connected with the first power supply line or inputs the first level signal;

[0071] Optionally, the first control unit comprises an inverter;

[0072] Optionally, the first control unit comprises an eleventh transistor and a twelfth transistor, a gate of the eleventh transistor is connected with the second electrode of the ninth transistor or the second node, a first electrode of the eleventh transistor is connected with the second power supply line or inputs the second level signal, and a second electrode of the eleventh transistor is connected with the first node; a gate of the twelfth transistor is connected with the second electrode of the ninth transistor or the second node, a first electrode of the twelfth transistor is connected with the first power supply line or inputs the first level signal, and a second electrode of the twelfth transistor is connected with the first node.

[0073] The second control unit comprises a thirteenth transistor and a fourteenth transistor, a first electrode of the thirteenth transistor inputs the second power supply line or the second level signal, a second electrode of the thirteenth transistor is connected with a first electrode of the fourteenth transistor, a second electrode of the fourteenth transistor is connected with the second electrode of the ninth transistor or the second node, one of a gate of the thirteenth transistor and a gate of the fourteenth transistor is connected with the first node, and the other inputs the first clock signal.

[0074] Optionally, the gate of the thirteenth transistor is connected with the first node; and the gate of the fourteenth transistor inputs the first clock signal.

[0075] Optionally, the eleventh transistor is a P-type transistor, and the twelfth transistor is an N-type transistor.

[0076] In a second aspect, the embodiments of the present application further provide a gate drive circuit, which comprises a plurality of shift registers of any of the embodiments of the present application, and the plurality of shift registers are cascaded; a start signal input end of an (n+1)th shift register is connected with a first output end of an nth shift register, wherein n is a positive integer greater than or equal to 1.

[0077] In a third aspect, the embodiments of the present application further provide a display panel, which comprises a pixel circuit and the gate drive circuit of any of the embodiments of the present application,

[0078] The pixel circuit comprises a plurality of transistors, and the first output end and the second output end of the shift register are connected with transistors of different channel types in the pixel circuit.

[0079] Optionally, the pixel circuit comprises a driving transistor, a data writing transistor and a compensation transistor, the data writing transistor is connected between a data line and a first electrode of the driving transistor, and the compensation transistor is connected between a second electrode and a gate of the driving transistor; a gate of the data writing transistor is connected with the first output end, and a gate of the compensation transistor is connected with the second output end.

[0080] Optionally, the data writing transistor is of a P channel type, and the compensation transistor is of an N channel type.

[0081] Optionally, the pixel circuit further comprises a first light-emitting control transistor and a second light-emitting control transistor, the first light-emitting control transistor is connected between the fourth power supply line and the first electrode of the driving transistor, the second light-emitting control transistor is connected between the second electrode of the driving transistor and the first electrode of the light-emitting device, the second electrode of the light-emitting device is connected to the fifth power supply line, the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are connected to the light-emitting control signal line;

[0082] Optionally, the pixel circuit further comprises a first initialization transistor, the gate of the first initialization transistor is connected to the first scan line, the first electrode of the first initialization transistor is connected to the first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate or the second electrode of the driving transistor.

[0083] Optionally, the pixel circuit further comprises a second initialization transistor, the gate of the second initialization transistor is connected to the second scan line, the first electrode of the second initialization transistor is connected to the second initialization signal line, and the second electrode of the second initialization transistor is connected to the first electrode of the light-emitting device.

[0084] The shift register, the gate driving circuit and the display panel provided by the embodiments of the present application can output two different gate driving signals through the same shift register, for example, can meet the driving requirements of the pixel circuit comprising P-type transistors and N-type transistors at the same time, and can reduce the frame of the display panel and improve the user experience.

[0085] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0086] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0087] Figure 1 is a structural schematic diagram of a shift register provided by the embodiments of the present application;

[0088] Figure 2is another structure diagram of a shift register provided by an embodiment of the present application;

[0089] Figure 3 is a structure diagram of a pixel circuit in the related art;

[0090] Figure 4 is another structure diagram of a shift register provided by an embodiment of the present application;

[0091] Figure 5 is another structure diagram of a shift register provided by an embodiment of the present application;

[0092] Figure 6 is an equivalent circuit diagram of the output control unit when the potential of the second node is the second level signal Figure 5

[0093] Figure 7 is another structure diagram of a shift register provided by an embodiment of the present application;

[0094] Figure 8 is another structure diagram of a shift register provided by an embodiment of the present application;

[0095] Figure 9 is another structure diagram of a shift register provided by an embodiment of the present application;

[0096] Figure 10 is another structure diagram of a shift register provided by an embodiment of the present application;

[0097] Figure 11 is another structure diagram of a shift register provided by an embodiment of the present application;

[0098] Figure 12 is a working timing diagram of a shift register provided by an embodiment of the present application;

[0099] Figure 13 is a working timing diagram of another shift register provided by an embodiment of the present application;

[0100] Figure 14 is a structure diagram of a gate driving circuit provided by an embodiment of the present application;

[0101] Figure 15 is a structure diagram of a display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0102] ​In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application, so that those skilled in the art can better understand the technical solutions of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the protection scope of the present application.

[0103] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to include only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device. The connection can include direct connection or indirect connection. The connection can include electrical connection.

[0104] The embodiment of the present application provides a shift register, Figure 1 is a structural schematic diagram of a shift register provided by the embodiment of the present application, referring to Figure 1 The shift register comprises a node voltage control module 110, a first output module 120 and a second output module 130, the node voltage control module 110 is connected to a first node N1 and a second node N2, the first output module 120 is connected to the first node N1 and the second node N2, and the second output module 130 is connected to the first node N1 and / or the second node N2; the node voltage control module 110 is used for controlling the potential of the first node N1 and the second node N2; the first output module 120 is used for outputting a first gate driving signal through a first output end OUT1 according to the potential of the first node N1 and the second node N2; the second output module 130 is used for outputting a second gate driving signal through a second output end OUT2 according to the potential of the first node N1 and / or the second node N2; the first gate driving signal and the second gate driving signal are different.

[0105] The node voltage control module 110 can be connected to input signals, and the number of input signals can be multiple. For example, the input signals include, but are not limited to, a start signal and one or at least two clock signals. The node voltage control module 110 transmits corresponding voltages to the first node N1 and the second node N2 according to the input signals during different operating periods of the shift register. The first node N1 and the second node N2 have different potentials at least for some periods, for example, opposite potentials, opposite high / low values, or opposite polarities.

[0106] The first output module 120 is connected to the first node N1 and the second node N2 respectively. The first output module 120 can output a first gate drive signal to the first output terminal OUT1 of the shift register according to the potentials of the first node N1 and the second node N2. The first gate drive signal includes a first-level signal and a second-level signal. Specifically, during a certain period of operation, the first gate drive signal is a first-level signal; during another period of operation, the first gate drive signal is a second-level signal. The first gate drive signal is used to drive a first-channel type transistor.

[0107] The second output module 130 is connected to the first node N1 and / or the second node N2. The second output module 130 can output a second gate drive signal to the second output terminal OUT2 of the shift register according to the potential of the first node N1 and / or the second node N2. The second gate drive signal includes a first level signal and a second level signal. In some embodiments, the second output module 130 is connected to the first node N1, and the second output module 130 outputs the second gate drive signal to the second output terminal OUT2 of the shift register according to the potential of the first node N1. In other embodiments, the second output module 130 is connected to the second node N2 (…). Figure 1 (As shown in the illustration), the second output module 130 outputs a second gate drive signal to the second output terminal OUT2 of the shift register according to the potential of the second node N2. In other embodiments, the second output module 130 is connected to the first node N1 and the second node N2 respectively, and the second output module 130 outputs the second gate drive signal to the second output terminal OUT2 of the shift register according to the potentials of the first node N1 and the second node N2. Specifically, during a certain period of operation, the second gate drive signal is a first-level signal; during another period of operation, the second gate drive signal is a second-level signal. The second gate drive signal is used to drive a transistor of a second channel type. The first channel type is P-channel, and the second channel type is N-channel, or the first channel type is N-channel, and the second channel type is P-channel. By outputting gate drive signals that can simultaneously drive transistors of two channel types through the same shift register, it is not necessary to set up different gate drive circuits for each type of transistor, which can reduce the bezel of the display panel.

[0108] The shift register of the embodiment can output two different gate driving signals through the same shift register, for example, can meet the driving requirement of the pixel circuit including P-type transistor and N-type transistor, and can reduce the frame of the display panel and improve the user experience.

[0109] Optionally, one or more of the pulse width, pulse amplitude, and positive and negative polarity of the pulse amplitude of the first gate driving signal and the second gate driving signal are different; and / or, the first gate driving signal and the second gate driving signal are used to drive transistors of different channel types. In this way, the first gate driving signal and the second gate driving signal can drive different transistors, for example, drive transistors turned on in different working stages of the pixel circuit of the display panel, and / or drive transistors of different channel types, meet the driving requirement of the pixel circuit, and at the same time reduce the frame of the display panel.

[0110] As described in the above embodiment, the first gate driving signal includes a first level signal and a second level signal; the second gate driving signal includes a first level signal and a second level signal, in some optional embodiments of the present application, the first gate driving signal is used to drive a P-type transistor, and the second gate driving signal is used to drive an N-type transistor; the voltage of the first level signal is lower than the voltage of the second level signal; the second output module 130 includes a P-type transistor, and the second output module 130 is used to output the first level signal through the P-type transistor.

[0111] Specifically, in the related art, the first level signal in the second gate driving signal is output through an N-type oxide transistor, and because the mobility of the oxide transistor is low, when the transistor characteristics fluctuate due to stress, the output waveform stability of the second gate driving signal is poor, and the reliability of the gate driving circuit is reduced. In the embodiment, the second output module 130 includes a P-type transistor, and the first level signal is output through the P-type transistor, wherein the P-type transistor included in the second output module 130 can be a polysilicon transistor, for example, a low-temperature polysilicon transistor, and compared with the N-type oxide transistor, the P-type transistor has higher mobility, which can improve the output stability of the second gate driving signal and improve the reliability of the gate driving circuit.

[0112] Figure 2 is another structure diagram of a shift register provided by the embodiment of the present application, referring to Figure 2Optionally, the second output module 130 comprises a first output submodule 131 and a second output submodule 132. The first output submodule 131 is electrically connected to the second node N2, and is configured to control the potential of the second output end OUT2 according to the potential of the second node N2. For example, the first output submodule 131 is configured to turn on or turn off according to the potential of the second node N2, and transmit the second level signal VGH to the second output end OUT2 when turned on. Alternatively, the first output submodule 131 is electrically connected to the first node N1, and is configured to turn on or turn off according to the potential of the first node N1, and transmit the second level signal VGL to the second output end OUT2 when turned on. The second output submodule 132 is connected to the first node N1, and is configured to control the potential of the second output end OUT2 according to the potential of the first node N1. For example, the second output submodule 132 is configured to transmit the first level signal VGL to the second output end OUT2 according to the potential of the first node N1. The second output submodule 132 is connected to the second node N2, and is configured to control the potential of the second output end OUT2 according to the potential of the second node N2. For example, the second output submodule 132 is configured to transmit the first level signal VGL to the second output end OUT2 according to the potential of the second node N2.

[0113] Specifically, in the second output module 130, the first output submodule 131 can control whether the voltage of the second power line and / or the second level signal VGH is output to the second output terminal OUT2, and the second output submodule 132 can control whether the voltage of the first power line and / or the first level signal VGL is output to the second output terminal OUT2. For example, the on period of the first output submodule 131 and the on period of the second output submodule 132 are different at least in part. For example, the first output submodule 131 and the second output submodule 132 are turned on in time division. Optionally, at least in part of the period (for example, after the t1 stage in the stable working state of the shift register), the node voltage control module 110 is configured to control the potentials of the first node N1 and the second node N2 to be opposite, that is, when the first node N1 is at a high potential, the second node N2 is at a low potential; when the first node N1 is at a low potential, the second node N2 is at a high potential. Specifically, at least in part of the period (for example, after the t1 stage in the stable working state of the shift register), the node voltage control module 110 is configured to control the potential of the first node N1 to jump from a low potential to a high potential, and the potential of the second node N2 to jump from a high potential to a low potential, and the potential of the first node N1 to jump from a high potential to a low potential, and the potential of the second node N2 to jump from a low potential to a high potential. The first output submodule 131 and the second output submodule 132 each include at least one switching element, which can be a transistor. The first output submodule 131 is connected to the second node N2, and the potential of the second node N2 controlled by the node voltage control module 110 controls the on state of the first output submodule 131, thereby controlling whether the second level signal VGH is output to the second output terminal OUT2. The first output submodule 131 can be configured to control the potential of the second output terminal OUT2 according to the potential of the second node N2. Optionally, the first output submodule 131 includes a first transistor T1, the gate of the first transistor T1 is connected to the second node N2, the first electrode of the first transistor T1 is connected to the second power line or the second level signal VGH, and the second electrode of the first transistor T1 is connected to the second output terminal OUT2. The low potential jumping to the high potential can be a rising edge, and the high potential jumping to the low potential can be a falling edge.

[0114] In some embodiments, the second output submodule 132 is connected with the first node N1, and controls the transmission of the first voltage level signal VGL to the second output terminal OUT2 according to the potential of the first node N1. The second output submodule 132 can be used to control the potential of the second output terminal OUT2 according to the potential of the first node N1. In other embodiments, the second output submodule 132 is connected with the second node N2, and controls the transmission of the first voltage level signal VGL to the second output terminal OUT2 according to the potential of the second node N2. The second output submodule 132 can be used to control the potential of the second output terminal OUT2 according to the potential of the second node N2. In the case where the second output submodule 132 is connected with the first node N1, the second output submodule 132 includes a second transistor T2, the gate of the second transistor T2 is connected with the first node N1, the first pole of the second transistor T2 is connected with the first power supply line or the first voltage level signal VGL, and the second pole of the second transistor T2 is connected with the second output terminal OUT2.

[0115] Optionally, the second transistor T2 is a P-type transistor, so as to ensure that the second output module 130 outputs the first voltage level signal VGL through the P-type transistor, ensure the stability of the first voltage level signal VGL in the second gate driving signal output by the shift register, and be beneficial to improving the display effect.

[0116] For example, the switching state of the second transistor T2 is opposite to that of the first transistor T1. For example, when the second transistor T2 changes from being turned on to being turned off, the first transistor T1 changes from being turned off to being turned on. For example, when the second transistor T2 changes from being turned off to being turned on, the first transistor T1 changes from being turned on to being turned off.

[0117] In some optional embodiments of the present application, the first transistor T1 is a P-type transistor, so as to make the second output module 130 output the second voltage level signal VGH through the P-type transistor, ensure the stability of the second voltage level signal VGH in the second gate driving signal output by the shift register, and be beneficial to improving the display effect.

[0118] Optionally, the second output submodule 132 further includes a first capacitor C1, the first end of the first capacitor C1 is connected with the gate of the second transistor T2, and the second end of the first capacitor C1 is connected with the second output terminal OUT2.

[0119] In some embodiments, the effective voltage level of the first gate driving signal and the second gate driving signal overlaps.

[0120] In the present application, the effective voltage level of the first gate driving signal is the voltage level that can make the driven transistor turned on, and the ineffective voltage level of the first gate driving signal is the voltage level that can make the driven transistor turned off. The effective voltage level of the second gate driving signal is the voltage level that can make the driven transistor turned on, and the ineffective voltage level of the second gate driving signal is the voltage level that can make the driven transistor turned off.

[0121] Optionally, the active level of the first gate drive signal is a first level signal VGL, and the active level of the second gate drive signal is a second level signal VGH. In some optional embodiments, the inactive levels of the first gate drive signal and the second gate drive signal overlap.

[0122] In the case where the first gate drive signal is used to drive a P-type transistor and the second gate drive signal is used to drive an N-type transistor, the first level signal VGL is a low level signal, and the second level signal VGH is a high level signal; in the case where the first gate drive signal is used to drive an N-type transistor and the second gate drive signal is used to drive a P-type transistor, the first level signal VGL is a high level signal, and the second level signal VGH is a low level signal.

[0123] The first gate drive signal and the second gate drive signal output by the shift register can be used to drive different transistors in the pixel circuit. Figure 3 is a structural schematic diagram of a pixel circuit in the related art, referring to Figure 3 The pixel circuit includes a drive transistor DT, a data writing transistor M1, and a compensation transistor M2. The data writing transistor M1 is connected between a data line Data and a first electrode of the drive transistor DT, and the compensation transistor M2 is connected between a second electrode and a gate electrode of the drive transistor DT. A first output end OUT1 of the shift register can be connected to the data writing transistor M1 in the pixel circuit, a second output end OUT2 can be connected to the compensation transistor M2 in the pixel circuit, an active level of the first gate drive signal Scan1 is a level that turns on the data writing transistor M1, and an active level of the second gate drive signal Scan2 is a level that turns on the compensation transistor M2. By setting the active level of the first gate drive signal and the active level of the second gate drive signal output by the shift register to overlap, the data writing transistor M1 and the compensation transistor M2 can be turned on at the same time during the overlapping period of the active level of the first gate drive signal and the active level of the second gate drive signal, and then the data voltage on the data line can be written to the gate electrode of the drive transistor DT.

[0124] In some embodiments, the data writing transistor M1 is a P-type transistor, and the compensation transistor M2 is an N-type transistor. That is, the channel type of the data writing transistor M1 is a P-channel, and the channel type of the compensation transistor M2 is an N-channel. Optionally, the P-type transistor in the pixel circuit is a polysilicon transistor, for example, a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. Correspondingly, the display panel is a Low Temperature Polycrystalline Oxide (LTPO) process display panel. In some embodiments, the P-type transistor in the shift register is a polysilicon transistor, for example, a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. That is, the shift register of the present embodiment can be used for driving the LTPO process display panel, which is conducive to ensuring a higher smoothness and lower power consumption of the display panel.

[0125] Optionally, the pixel circuit further comprises a first light-emitting control transistor M3 and a second light-emitting control transistor M4, the first light-emitting control transistor M3 is connected between the fourth power supply line VDD and the first electrode of the driving transistor DT; the second light-emitting control transistor M4 is connected between the second electrode of the driving transistor DT and the first electrode of the light-emitting device D1, the second electrode of the light-emitting device D1 is connected to the fifth power supply line VSS; the gate of the first light-emitting control transistor M3 and the gate of the second light-emitting control transistor M4 are connected to the light-emitting control signal line EM.

[0126] Optionally, the pixel circuit further comprises a first initialization transistor M5, the gate of the first initialization transistor M5 is connected to the first scan line Sn1, the first electrode of the first initialization transistor M5 is connected to the first initialization signal line Vref1, and the second electrode of the first initialization transistor M5 is connected to the gate of the driving transistor DT.

[0127] Optionally, the pixel circuit further comprises a second initialization transistor M6, the gate of the second initialization transistor M6 is connected to the second scan line Sn2, the first electrode of the second initialization transistor M6 is connected to the second initialization signal line Vref2, and the second electrode of the second initialization transistor M6 is connected to the first electrode of the light-emitting device D1.

[0128] Optionally, the pixel circuit further comprises a storage capacitor Cst, the first end of the storage capacitor Cst is connected to the gate of the driving transistor DT, and the second end of the storage capacitor Cst is connected to the fourth power supply line VDD.

[0129] Figure 2The shown shift register shows the case that the second output module 130 is connected to the first node N1 and the second node N2 respectively. In other optional embodiments of the present application, the second output module 130 can be connected to the first node N1 without being connected to the second node N2, and in other optional embodiments of the present application, the second output module 130 can be connected to the second node N2 without being connected to the first node N1.

[0130] Figure 4 is another structure diagram of a shift register provided by an embodiment of the present application, referring to Figure 4 , the shift register can correspond to the case that the second output sub-module 132 is connected to the second node N2. Optionally, the second output sub-module 132 comprises an output control unit 1321 and an output unit 1322, the output control unit 1321 is connected to the second node N2, the output control unit 1321 is connected to the third node N3, and the output unit 1322 is connected to the third node N3; the output control unit 1321 is also connected to a preset clock signal, and the output control unit 1321 is used to control the potential of the third node N3 according to the potential of the second node N2 and the preset clock signal, so that at least part of the time period (for example, after the t1 stage in the stable working state of the shift register), the potential of the third node N3 is positively correlated with the potential of the first node N1, and / or the potential of the third node N3 is inversely correlated with the potential of the second node N2.

[0131] For example, the node voltage control module 110 is connected to the first clock signal and / or the second clock signal. The preset clock signal comprises the first clock signal CK1 (as shown in Figure 4 ) or the second clock signal.

[0132] Optionally, the potential of the third node N3 comprises a third level signal, and the voltage of the third level signal is lower than the voltage of the first power supply line.

[0133] At least part of the time period (for example, after the t1 stage in the stable working state of the shift register), the potential of the third node N3 is positively correlated with the potential of the first node N1, that is, the potential of the third node N3 and the potential of the first node N1 are high at the same time, and are low at the same time. The potential of the first node N1 and the potential of the third node N3 jump from low to high at the same time, and / or the potential of the first node N1 and the potential of the third node N3 jump from high to low at the same time.

[0134] Optionally, at least in part of the period (for example, in the stable state of the shift register, for example, after the stage t1), the potential of the third node N3 is inversely related to the potential of the second node N2, that is, when the potential of the second node N2 jumps from low to high, the potential of the third node N3 jumps from high to low; when the potential of the second node N2 jumps from high to low, the potential of the second node N2 jumps from low to high. Optionally, the potentials of the second node N2 and the third node N3 are opposite.

[0135] Specifically, the output control unit 1321 controls the potential of the third node N3 to be positively related to the potential of the first node N1 according to the potential of the second node N2 and the preset clock signal CK1. Since the node voltage control module 110 can control the potential of the first node N1 to be opposite to the potential of the second node N2, correspondingly, through the control of the output control module, the potential of the third node N3 can be opposite to the potential of the second node N2, so that the first output sub-module 131 and the output unit 1322 are conveniently controlled to be turned on at different times, and then the first output sub-module 131 is turned on and the output unit 1322 is turned off when the second level signal VGH is transmitted to the second output end OUT2; the first output sub-module 131 is turned off and the output unit 1322 is turned on when the first level signal VGL is transmitted to the second output end OUT2.

[0136] Optionally, the first output sub-module 131 includes a first transistor T1, the gate of the first transistor T1 is connected with the second node N2, and / or the potential of the gate of the first transistor T1 is positively related to the potential of the second node N2, and / or the potential of the gate of the first transistor T1 is inversely related to the potential of the first node N1, the first pole of the first transistor T1 is connected with the second power supply line or inputs the second level signal VGH, and the second pole of the first transistor T1 is connected with the second output end OUT2; the output unit 1322 includes a third transistor T3, the gate of the third transistor T3 is connected with the third node N3, and / or the potential of the gate of the third transistor T3 is inversely related to the potential of the second node N2, and / or the potential of the gate of the third transistor T3 is positively related to the potential of the first node N1, the first pole of the third transistor T3 is connected with the first power supply line or inputs the first level signal VGL, and the second pole of the third transistor T3 is connected with the second output end OUT2.

[0137] Optionally, the output control unit 1321 is configured to control the potential of the third node N3 to be a third level signal when the potential of the first node N1 is the first level signal VGL according to the potential of the second node N2 and the preset clock signal, and the voltage of the third level signal is lower than the voltage of the first level signal VGL.

[0138] Specifically, under the control of the node voltage control module 110, the potential of the first node N1 is opposite to the potential of the second node N2. When the potential of the first node N1 is the first level signal VGL, the potential of the second node N2 is the second level signal VGH. When the potential of the second node N2 is the second level signal VGH, the output control unit 1321 controls the potential of the third node N3 to be a third level signal lower than the first level signal VGL according to the first clock signal CK1, so that the gate of the third transistor T3 is the third level signal, the first pole of the third transistor T3 is the first level signal VGL, and the voltage difference between the gate and the first pole of the third transistor T3 is large in absolute value, so that the on state of the third transistor T3 is better, and the first level signal VGL input to the first pole of the third transistor T3 can be transmitted to the second output end OUT2 with equal amplitude, improving the stability of the output of the third transistor T3, ensuring that the on or off state of the transistor driven by the second gate drive signal is better, and helping to improve the display effect. For example, when the transistor driven by the second gate drive signal is an N-type transistor, the first level signal VGL is a low-level signal, and the second level signal VGH is a high-level signal, the N-type transistor driven by the second gate drive signal can be completely turned off under the action of the first level signal VGL in the second gate drive signal.

[0139] Optionally, the potential of the third node N3 further includes a second level signal, and the voltage of the third level signal is lower than the voltage of the second level signal. And / or, the voltage of the third level signal is lower than the voltage of the first power supply line.

[0140] In some optional embodiments of the present application, the absolute value of the voltage difference between the third level signal and the voltage of the first power supply line is greater than or equal to the absolute value of the threshold voltage of the third transistor T3. In this way, when the potential of the third node N3 is the third level signal, the third transistor T3 can be completely turned on, further ensuring that when the third transistor T3 is turned on, the first level signal VGL can be transmitted to the second output end OUT2 with equal amplitude, thereby improving the display effect.

[0141] Optionally, the third transistor T3 is a P-type transistor, so that the second output module 130 outputs the first level signal VGL through the P-type transistor, ensuring the stability of the first level signal VGL in the second gate drive signal output by the shift register, and helping to improve the display effect.

[0142] Optionally, the first transistor T1 is a P-type transistor, so that the second output module 130 outputs the second level signal VGH through the P-type transistor, ensuring the stability of the second level signal VGH in the second gate drive signal output by the shift register, and helping to improve the display effect.

[0143] Optionally, the second output sub-module 132 further comprises a first capacitor C1, a first end of the first capacitor C1 is connected with the gate of the third transistor T3, and a second end of the first capacitor C1 is connected with the second output end OUT2.

[0144] Figure 5 is another structure diagram of a shift register provided by an embodiment of the present application, referring to Figure 5 Optionally, the output control unit 1321 comprises a charge-discharge control sub-unit 13212, a coupling sub-unit 1323 and a unidirectional conduction sub-unit 1324; the charge-discharge control sub-unit 13212 is connected with the second node N2, a first end of the coupling sub-unit 1323 and a second end of the coupling sub-unit 1323 respectively; the second end of the coupling sub-unit 1323 is connected with a first end of the unidirectional conduction sub-unit 1324; a second end of the unidirectional conduction sub-unit 1324 is connected with the third node N3; the charge-discharge control sub-unit 13212 is configured to charge and / or discharge the coupling sub-unit 1323 according to the potential of the second node N2 and a preset clock signal; the coupling sub-unit 1323 is configured to couple the potential change of the first end to the second end; and the unidirectional conduction sub-unit 1324 is configured to be turned on when the potential of the first end of the unidirectional conduction sub-unit 1324 is lower than the potential of the third node N3.

[0145] The preset clock signal is a periodic signal, and the preset clock signal includes first voltage level signal VGL pulses and second voltage level signal VGH pulses arranged alternately. Specifically, when the potential of the second node N2 is the first voltage level signal VGL, the charge-discharge control subunit 13212 transmits the second voltage level signal VGH to the first end of the coupling subunit 1323, so that the potential of the first end of the coupling subunit 1323 rises. Due to the coupling effect of the coupling subunit 1323 itself, the potential of the second end of the coupling subunit 1323 is pulled high, and the unidirectional conduction subunit 1324 is turned off. When the potential of the second node N2 is the second voltage level signal VGH, the charge-discharge control subunit 13212 alternately charges and discharges the coupling subunit 1323 according to the high-low potential transition of the preset clock signal. Specifically, when the potential of the second node N2 is the second voltage level signal VGH and the preset clock signal transitions from high to low, the coupling subunit 1323 discharges, the potential of the first end of the coupling subunit 1323 decreases, due to the coupling effect of the coupling subunit 1323 itself, the potential of the second end of the coupling subunit 1323 is pulled low, the unidirectional conduction subunit 1324 is turned on, the potential of the third node N3 is pulled low, so that the potential of the third node N3 is lower than the first voltage level signal VGL, and the output unit 1322 is turned on to transmit the first voltage level signal VGL to the second output end OUT2 with the same amplitude. When the potential of the second node N2 is the second voltage level signal VGH and the preset clock signal transitions from low to high, the coupling subunit 1323 is charged, the potential of the first end of the coupling subunit 1323 rises, due to the coupling effect of the coupling subunit 1323 itself, the potential of the second end of the coupling subunit 1323 rises, the unidirectional conduction subunit 1324 is turned off, and the potential of the third node N3 remains low, so that the potential of the third node N3 is lower than the first voltage level signal VGL, and the output unit 1322 is turned on to transmit the first voltage level signal VGL to the second output end OUT2 with the same amplitude.

[0146] With reference to Figure 5 Optionally, the charge-discharge control subunit 13212 includes a fourth transistor T4 and a fifth transistor T5. The gate of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second power supply line or inputs the second voltage level signal VGH, and the second electrode of the fourth transistor T4 is connected to the first end of the coupling subunit 1323. The gate of the fifth transistor T5 is connected to the second end of the coupling subunit 1323, the first electrode of the fifth transistor T5 inputs the preset clock signal, and the second electrode of the fifth transistor T5 is connected to the first end of the coupling subunit 1323.

[0147] The channel types of the fourth transistor T4 and the fifth transistor T5 can be the same. The fourth transistor T4 can include a P-type transistor. The fifth transistor T5 can include a P-type transistor.

[0148] Optionally, the coupling subunit 1323 comprises a second capacitor C2, a first plate of the second capacitor C2 serving as a first end of the coupling subunit 1323, and a second plate of the second capacitor C2 serving as a second end of the coupling subunit 1323.

[0149] Optionally, the second capacitor C2 is greater than the first capacitor C1, so that the coupling effect of the first capacitor C1 is smaller, avoiding the inclination of the jump edge of the waveform of the gate drive signal output by the second output end OUT2 due to the too long jump time of the jump edge, and improving the reliability of the output signal.

[0150] Optionally, the unidirectional conduction subunit 1324 comprises a sixth transistor T6, a gate of the sixth transistor T6 being connected with a first electrode of the sixth transistor T6, the gate of the sixth transistor T6 being connected with the second end of the coupling subunit 1323, and a second electrode of the sixth transistor T6 being connected with the third node N3.

[0151] The sixth transistor T6 can comprise a P-type transistor. The channel type of the sixth transistor T6 and the fifth transistor T5 can be the same. The channel type of the sixth transistor T6 and the fourth transistor T4 can be the same.

[0152] Figure 6 is when the potential of the second node is the second-level signal Figure 5 is an equivalent circuit diagram of the output control unit, refer to Figure 5 and Figure 6When the potential of the second node N2 is the first level signal VGL, the fourth transistor T4 is turned on, and the second level signal VGH is transmitted to the second electrode of the fourth transistor T4 and the first end of the coupling subunit 1323, wherein the connection point of the second electrode of the fourth transistor T4 and the first end of the coupling subunit 1323 is recorded as the fourth node N4, and thus when the second node N2 is the first level signal VGL, the fourth node N4 is the second level signal VGH. The potential of the first end of the second capacitor C2 is pulled up, and due to the coupling effect of the second capacitor C2, the potential of the second end (recorded as the fifth node N5) of the second capacitor C2 is also pulled up, so that the sixth transistor T6 is turned off. When the potential of the second node N2 is the second level signal VGH, the fourth transistor T4 is turned off. In the case that the preset clock signal is the first clock signal CK1, when the first clock signal CK1 jumps from high level to low level, the fifth transistor T5 is turned on, and the low-level first clock signal CK1 is transmitted to the fourth node N4 to discharge the second capacitor C2. Due to the coupling effect of the second capacitor C2, the potential of the second end (the fifth node N5) of the first capacitor C1 is pulled down, so that when the potential of the second end of the first capacitor C1 is lower than the potential of the third node N3, the sixth transistor T6 is turned on, and then the potential of the third node N3 is lower than the first level signal VGL, the output unit 1322 is turned on, and the first level signal VGL is transmitted to the second output end OUT2 with the same amplitude. When the first clock signal CK1 jumps from low level to high level, the fifth transistor T5 is turned on, and the high-level first clock signal CK1 is transmitted to the fourth node N4 to charge the second capacitor C2. Due to the coupling effect of the second capacitor C2, the potential of the second end (the fifth node N5) of the second capacitor C2 is raised, the unidirectional conduction subunit 1324 is turned off, the third node N3 still maintains a low potential, so that the potential of the third node N3 is still lower than the first level signal VGL, and the output unit 1322 is turned on to transmit the first level signal VGL to the second output end OUT2 with the same amplitude.

[0153] Optionally, the unidirectional conduction subunit 1324 includes a diode, the cathode of the diode is connected with the second end of the coupling subunit 1323, and the anode of the diode is connected with the third node N3.

[0154] Figure 7 is another structure diagram of a shift register provided by the embodiment of the present application, referring to Figure 7Optionally, the first output module 120 comprises a third output submodule 121 and a fourth output submodule 122, the third output submodule 121 is connected with the first node N1, and the third output submodule 121 is configured to control the potential of the first output end OUT1 according to the potential of the first node N1, for example, the third output submodule 121 is configured to turn on or turn off according to the potential of the first node N1, and output the second level signal VGH to the first output end OUT1 when turned on; the fourth output submodule 122 is connected with the second node N2, and the fourth output submodule 122 is configured to control the potential of the first output end OUT1 according to the potential of the second node N2, for example, the fourth output submodule 122 is configured to turn on or turn off according to the potential of the second node N2, and output the first clock signal CK1 to the first output end OUT1 when turned on.

[0155] Optionally, the third output submodule 121 and the fourth output submodule 122 each comprise at least one switching device, which can be a transistor. By providing that the first output module 120 comprises the third output submodule 121 and the fourth output submodule 122, the third output submodule 121 and the fourth output submodule 122 can be turned on at different times, the third output submodule 121 outputs the second level signal VGH to the first output end OUT1 when the third output submodule 121 is turned on, and the fourth output submodule 122 outputs the first clock signal CK1 to the first output end OUT1 when the fourth output submodule 122 is turned on.

[0156] Optionally, the third output submodule 121 comprises a seventh transistor T7, the gate of the seventh transistor T7 is connected with the first node N1, the first pole of the seventh transistor T7 is connected with the second power supply line or inputs the second level signal VGH, and the second pole of the seventh transistor T7 is connected with the first output end OUT1; optionally, the seventh transistor is a P-type transistor. In this way, the first output module 120 outputs the second level signal VGH through the P-type transistor, which is beneficial to improve the output stability.

[0157] Optionally, the fourth output submodule 122 comprises an eighth transistor T8, the gate of the eighth transistor T8 is connected with the second node N2, the first pole of the eighth transistor T8 inputs the first clock signal CK1, and the second pole of the eighth transistor T8 is connected with the first output end OUT1. Optionally, the eighth transistor T8 is a P-type transistor. In this way, the first output module 120 outputs the first level signal VGL through the P-type transistor, which is beneficial to improve the output stability.

[0158] Optionally, the fourth output submodule 122 further comprises a third capacitor C3, the first end of the third capacitor C3 is connected with the second node N2, and the second end of the third capacitor C3 is connected with the first output end OUT1.

[0159] Figure 8is a structural schematic diagram of another shift register provided by an embodiment of the present application, referring to Figure 8 Optionally, the node voltage control module 110 comprises an input unit 111 and a first control unit 112. The input unit 111 is configured to control transmission of the start signal SIN to the second node N2 according to the second clock signal CK2, for example, to turn on or turn off according to the second clock signal CK2 and transmit the start signal SIN to the second node N2 when turned on. Optionally, the first control unit 112 comprises an inverter, and the first control unit 112 is configured to output the potential of the second node N2 to the first node in an inverted manner, for example, to transmit the first voltage level signal VGL or the second voltage level signal VGH to the first node N1 according to the potential of the second node N2. Optionally, the node voltage control module 110 further comprises a second control unit 113, and the second control unit 113 is configured to transmit the second voltage level signal VGH to the second node N2 according to the potential of the first node N1 and the first clock signal CK1.

[0160] In the display panel, the first clock signal CK1 and the second clock signal CK2 are both periodic signals, the periods of the first clock signal CK1 and the second clock signal CK2 are equal, and the first clock signal CK1 and the second clock signal CK2 each comprise a plurality of first voltage level pulses and a plurality of second voltage level pulses. The first voltage level pulse of the first clock signal CK1 overlaps the second voltage level pulse of the second clock signal CK2, and the second voltage level pulse of the first clock signal CK1 overlaps the first voltage level pulse of the second clock signal CK2. The gate drive circuit in the display panel comprises a plurality of shift registers, and the plurality of shift registers are cascaded. For the first stage shift register, the start signal SIN is provided by an external circuit structure. For the second stage to the last stage shift register, the start signal SIN can be the first gate drive signal output by the previous stage shift register, that is, in the adjacent two stages of registers, the first output end OUT1 of the previous stage shift register is connected to the first output end OUT1 of the next stage shift register. Optionally, the first voltage level pulse of the start signal SIN is one or more, the first voltage level pulse of the start signal SIN overlaps the first voltage level pulse of the second clock signal CK2, and does not overlap the first voltage level pulse of the first clock signal CK1.

[0161] Specifically, the input unit 111 is turned on when the second clock signal CK2 is the first level signal VGL. The first control unit 112 transmits the second level signal VGH to the first node N1 when the second node N2 is the first level signal VGL, and transmits the first level signal VGL to the first node N1 when the second node N2 is the second level signal VGH. The second control unit 113 transmits the second level signal VGH to the second node N2 when the first node N1 is the first level signal VGL and the first clock signal CK1 is the first level signal VGL.

[0162] Figure 9 is a structural diagram of another shift register provided by an embodiment of the present application, referring to Figure 9 Optionally, the input unit 111 includes a ninth transistor T9, the gate of the ninth transistor T9 is connected to the second clock signal CK2, the first electrode of the ninth transistor T9 is connected to the start signal SIN, and the second electrode of the ninth transistor T9 is connected to the second node N2.

[0163] Optionally, the shift register further includes a tenth transistor T10, the second electrode of the ninth transistor T9 is connected to the second node N2 through the tenth transistor T10, or the second electrode of the ninth transistor T9 is connected to the gate of the eighth transistor T8 through the tenth transistor T10; the gate of the tenth transistor T10 is connected to the first power supply line or the first level signal VGL. Taking the tenth transistor T10 as a P-type transistor as an example, the tenth transistor T10 is arranged to prevent the second node N2 from being coupled to an extremely low level, so that the extremely low level is blocked by the tenth transistor T10 and cannot be transmitted to the common end (i.e., the sixth node N6) of the tenth transistor T10 and the ninth transistor T9, thereby protecting the transistor in the second control unit 113 and the ninth transistor T9 connected to the tenth transistor T10 from being damaged due to excessive voltage difference, and improving the reliability of the shift register.

[0164] Figure 10 is a structural diagram of another shift register provided by an embodiment of the present application, referring to Figure 10Optionally, the first control unit 112 includes an eleventh transistor T11 and a twelfth transistor T12. The gate of the eleventh transistor T11 is connected with the second electrode or the second node N2 of the ninth transistor T9. The first electrode of the eleventh transistor T11 is connected with the second power supply line or inputs the second level signal VGH. The second electrode of the eleventh transistor T11 is connected with the first node N1. The gate of the twelfth transistor T12 is connected with the second electrode or the second node N2 of the ninth transistor T9. The first electrode of the twelfth transistor T12 is connected with the first power supply line or inputs the first level signal VGL. The second electrode of the twelfth transistor T12 is connected with the first node N1. Optionally, the eleventh transistor T11 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor. By setting the shift register to include both P-type transistors and N-type transistors, the number of transistor devices included in the shift register can be reduced, which is conducive to reducing the frame and improving the user experience. Optionally, the P-type transistor is a polysilicon transistor, for example, a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. The inverter in the first control unit 112 includes the eleventh transistor T11 and the twelfth transistor T12.

[0165] Specifically, in the case where the ninth transistor T9 is directly connected with the fourth output sub-module (including the eighth transistor T8) at the second node N2, the gate of the eleventh transistor T11 is directly connected with the second node N2. In the case where the ninth transistor T9 is connected with the fourth output sub-module 122 through the tenth transistor T10, the gate of the eleventh transistor T11 is connected with the second electrode (the sixth node N6) of the ninth transistor T9. The same applies to the twelfth transistor T12, which will not be described here. The eleventh transistor T11 is turned on when the second node N2 is the first level signal VGL or the second electrode (the sixth node N6) of the ninth transistor T9 is the first level signal VGL, and transmits the second level signal VGH to the first node N1. The twelfth transistor T12 is turned on when the second node N2 is the second level signal VGH or the second electrode (the sixth node N6) of the ninth transistor T9 is the second level signal VGH, and transmits the first level signal VGL to the first node N1.

[0166] Optionally, the second control unit 113 includes a thirteenth transistor T13 and a fourteenth transistor T14. The first electrode of the thirteenth transistor T13 is connected with the second power supply line and / or inputs the second level signal VGH. The second electrode of the thirteenth transistor T13 is connected with the first electrode of the fourteenth transistor T14. One of the gate of the thirteenth transistor T13 and the gate of the fourteenth transistor T14 is connected with the first node N1, and the other inputs the first clock signal CK1. The second electrode of the fourteenth transistor T14 is connected with the second electrode or the second node N2 of the ninth transistor T9. The gate of the fourteenth transistor T14 inputs the first clock signal CK1.

[0167] Optionally, the gate of the thirteenth transistor T13 is connected with the first node N1; and the gate of the fourteenth transistor T14 is connected with the first clock signal CK1.

[0168] Optionally, the gate of the thirteenth transistor T13 is connected with the first clock signal CK1; and the gate of the fourteenth transistor T14 is connected with the first node N1.

[0169] Specifically, when the first node N1 is the first level signal VGL, the thirteenth transistor T13 is turned on to transmit the second level signal VGH from the first electrode of the thirteenth transistor T13 to the first electrode of the fourteenth transistor T14. When the first clock signal CK1 is the first level signal VGL, the fourteenth transistor T14 is turned on to transmit the signal of the first electrode of the fourteenth transistor T14 to the second electrode (the fifth node N5) of the ninth transistor T9 or the second node N2. When the first node N1 is the first level signal VGL and the first clock signal CK1 of the gate of the fourteenth transistor T14 is the first level signal VGL, the second level signal VGH is transmitted to the second electrode (the sixth node N6) of the ninth transistor T9 or the second node N2 through the thirteenth transistor T13 and the fourteenth transistor T14.

[0170] In other optional embodiments of the present application, the connecting node (i.e. the sixth node N6) of the tenth transistor T10 and the ninth transistor T9 can be used as the second node N2, and the fourth output sub-module comprises the tenth transistor T10.

[0171] Figures 4-10 The preset clock signal is the first clock signal CK1, Figure 11 is another structure diagram of a shift register provided by the embodiments of the present application, referring to Figure 11 In the shift register, the preset clock signal is the second clock signal CK2. Figures 4-11In this embodiment, the second output module 130 is connected to the second node N2, but not to the first node N1. In other embodiments of the invention, the second output module 130 is connected to the first node N1, but not to the second node N2. In this case, an inverter can be used, with its input connected to the first node N1 and its output connected to the first output submodule 131 and the second output submodule 132, respectively. For example, the output of the inverter can be connected to the gate of the first transistor T1 and the gate of the fourth transistor T4 in the output control unit 1321. For example, the output control unit 1321 may also include a second inverter, with the first node N1 connected to the input of the second inverter and its output connected to the charge / discharge control subunit 13212. The charge / discharge control subunit 13212 is connected to the first end and the second end of the coupling subunit 1323, respectively. The charge / discharge control subunit 13212 is used to charge and / or discharge the coupling subunit 1323 according to the potential of the output of the second inverter and a preset clock signal. The second inverter and the inverter in the first control unit 112 have the same or similar structures, which will not be described in detail here.

[0172] Figure 12 This is a timing diagram of a shift register provided in an embodiment of the present invention. The timing diagram corresponds to... Figure 10 The shift register shown is referenced. Figure 10 and Figure 12 Taking transistors T1, T3, T4, T5, T6, T7, T8, T9, T10, T11, T13, and T14 as P-type transistors and T12 as an N-type transistor, and using the first level signal VGL as a low level signal and the second level signal VGH as a high level signal as an example, the working timing of the shift register includes the following stages.

[0173] In the first stage t1, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned on in response to the second clock signal CK2, and the high level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, and the eighth transistor T8 is turned off. The twelfth transistor T12 is turned on according to the high level signal of the sixth node N6, and the first level signal VGL (low level signal) is transmitted to the first node N1, and the seventh transistor T7 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is output to the first output terminal OUT1 through the seventh transistor T7. The fourth transistor T4 is turned off according to the high level signal of the second node N2, and the fifth transistor T5 is turned on according to the initial potential of the fifth node N5, wherein the initial potential of the fifth node N5 is a low level signal (for example, equal to the ground level) in the initial state, and therefore the fifth transistor T5 is turned on to transmit the high level first clock signal CK1 to the fourth node N4, so that the potential of the fourth node N4 is raised, and due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 is also raised. In the initial state, no signal is input to the third node N3, and therefore the initial potential of the third node N3 can be considered as a low level signal, and therefore the potential of the fifth node N5 is higher than that of the third node N3, the sixth transistor T6 is turned off, and the third transistor T3 is turned on to transmit the first level signal VGL (low level signal) to the second output terminal OUT2.

[0174] In the first intermediate state stage t12, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned off according to the second clock signal CK2 in the shift register, the sixth node N6 and the second node N2 maintain the high level of the first stage t1, so that the twelfth transistor T12 remains turned on, and the first node N1 is still low. Because the potential state of the second node N2 is the same as that of the first stage t1, and the first clock signal CK1 is the same as that of the first stage t1, the potential state of the third node N3 is the same as that of the first stage t1, the third transistor T3 is turned on to transmit the first level signal VGL (low level signal) to the second output terminal OUT2.

[0175] In the second stage t2, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 jumps to a high level signal. The ninth transistor T9 is turned off in response to the second clock signal CK2, and no signal is transmitted to the sixth node N6. The sixth node N6 remains at the high level of the previous stage, and the second node N2 remains at the high level of the previous stage. The eighth transistor T8 is turned off. The twelfth transistor T12 remains turned on, and the seventh transistor T7 remains turned on. The second level signal VGH is transmitted to the first output terminal OUT1 through the seventh transistor T7. Due to the jump of the first clock signal CK1 from the high level to the low level, the potential of the fourth node N4 is reduced. Due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 is reduced. When the potential of the fifth node N5 is reduced to be lower than the potential of the third node N3, the sixth transistor T6 is turned on, the lower potential is transmitted to the third node N3, and the third transistor T3 is in a good turned-on state, transmitting the first level signal VGL (low level signal) to the second output terminal OUT2.

[0176] In the second intermediate state stage t23, the start signal SIN is a high level signal for a period of time and is a low level signal for a period of time, the first clock signal CK1 jumps to a high level signal, the second clock signal CK2 remains at a high level signal, the ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the sixth node N6 and the second node N2 maintain the high level of the second stage t2, the twelfth transistor T12 remains turned on, the first node N1 remains at a low level, the seventh transistor T7 remains turned on, and the second level signal VGH is transmitted to the first output terminal OUT1 through the seventh transistor T7. Due to the jump of the first clock signal CK1 from the low level to the high level, the potential of the fourth node N4 is increased. Due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 is increased. The sixth transistor T6 is turned off, the third node N3 can maintain the potential of the second stage t2, the third transistor T3 remains in a good turned-on state, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0177] In the third stage t3, the start signal SIN is a low signal, the first clock signal CK1 is a high signal, and the second clock signal CK2 is a low signal. The ninth transistor T9 is turned on in response to the second clock signal CK1, and the low signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10. The eighth transistor T8 is turned on in response to the low signal of the second node N2, and the high first clock signal CK1 is transmitted to the first output terminal OUT1. The eleventh transistor T11 is turned on in response to the low signal of the sixth node N6, and the second level signal VGH (high signal) is transmitted to the first node N1, and the seventh transistor T7 is turned off in response to the high signal of the first node N1. The first transistor T1 is turned on in response to the low signal of the second node N2, and the second level signal VGH (high signal) is transmitted to the second output terminal OUT2. The fourth transistor T4 is turned on in response to the low signal of the second node N2, and the second level signal VGH (high signal) is transmitted to the fourth node N4. That is, the potential state of the fourth node N4 is the same as that in the second intermediate state stage t23, the potential of the fifth node N5 remains high, the fifth transistor T5 is turned off, the potential of the fifth node N5 is higher than that of the third node N3, and the sixth transistor T6 is turned off.

[0178] In the third intermediate state stage t34, the start signal SIN is a low signal for a period of time and a high signal for another period of time, the first clock signal CK1 is a high signal, and the second clock signal CK2 is a high signal. The ninth transistor T9 in the shift register is turned off in response to the second clock signal CK2, and the sixth node N6 and the second node N2 maintain the low level in the third stage t3. The eighth transistor T8 is turned on in response to the low level of the second node N2, and the high second clock signal CK2 is transmitted to the first output terminal OUT1. The eleventh transistor T11 is turned on in response to the low level of the sixth node N6, and the second level signal VGH (high signal) is transmitted to the first node N1, so that the seventh transistor T7 is turned off. Because the potential state of the second node N2 is the same as that in the third stage t3, and the first clock signal CK1 is the same as that in the third stage t3, the potential states of the fourth node N4, the fifth node N4, and the third node N3 are the same as those in the third stage t3, and the third transistor T3 is turned off. The first transistor T1 is turned on, and the second level signal VGH (high signal) is transmitted to the second output terminal OUT2.

[0179] In the fourth stage t4, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, the second clock signal CK2 is a high level signal, the ninth transistor T9 is turned off in response to the second clock signal CK2, and no signal is transmitted to the sixth node N6. The sixth node N6 keeps the low level of the last stage, and accordingly, the second node N2 keeps the low level of the last stage. The eighth transistor T8 is turned on to transmit the low level first clock signal CK1 to the first output terminal OUT1. The eleventh transistor T11 keeps being turned on, the first node N1 is a high level signal, and accordingly, the seventh transistor T7 keeps being turned off. Because the potential state of the second node N2 is the same as that in the third stage t3, the first transistor T1 is turned on to transmit the second level signal VGH (a high level signal) to the second output terminal OUT2. The states of the third node N3, the fourth node N4 and the fifth node N5 are the same as those in the third intermediate stage t34.

[0180] In the fourth intermediate stage t45, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 in the shift register is turned off according to the second clock signal CK2, the sixth node N6 and the second node N2 maintain the low level of the fourth stage t4, so that the eleventh transistor T11 keeps being turned on, and the first node N1 is still a high level. The eighth transistor T8 still maintains being turned on to transmit the high level second clock signal CK2 to the first output terminal OUT1. Because the potential state of the second node N2 is the same as that in the fourth stage t4, the first transistor T1 is turned on to transmit the second level signal VGH (a high level signal) to the second output terminal OUT2. The states of the third node N3, the fourth node N4 and the fifth node N5 are the same as those in the fourth stage t4.

[0181] In the fifth stage t5, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned on in response to the second clock signal CK2, and the high level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, and the eighth transistor T8 is turned off. The twelfth transistor T12 is turned on according to the high level signal of the sixth node N6, and the first level signal VGL (low level signal) is transmitted to the first node N1, and the seventh transistor T7 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is output to the first output terminal OUT1 through the seventh transistor T7. The fourth transistor T4 is turned off according to the high level signal of the second node N2, the first transistor T1 is turned off according to the high level of the second node N2, the second level signal VGH is no longer output to the second output terminal OUT2, and the potential of the second output terminal OUT2 is gradually lowered. Due to the coupling effect of the first capacitor C1, the potential of the third node N3 is gradually lowered, the fourth node N4 and the fifth node N5 remain high level, so that the sixth transistor T6 is turned off, and the third transistor T3 is turned on to output the first level signal VGL to the second output terminal OUT2.

[0182] In the fifth intermediate state stage t56, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 in the shift register is turned off according to the second clock signal CK2, the sixth node N6 and the second node N2 maintain the high level of the first stage t1, so that the twelfth transistor T12 remains turned on, and the first node N1 is still low. Because the potential state of the second node N2 is the same as that of the first stage t1, and the first clock signal CK1 is the same as that of the first stage t1, the potential state of the third node N3 is the same as that of the first stage t1, and the third transistor T3 is turned on to transmit the first level signal VGL (low level signal) to the second output terminal OUT2.

[0183] In the sixth stage t6, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 jumps to a high level signal. The ninth transistor T9 is turned off in response to the second clock signal CK2, and no signal is transmitted to the sixth node N6, which remains at a high level of the previous stage. Accordingly, the second node N2 remains at a high level of the previous stage, and the eighth transistor T8 is turned off. The twelfth transistor T12 remains turned on, and accordingly, the seventh transistor T7 remains turned on. The second level signal VGH is transmitted to the first output end OUT1 through the seventh transistor T7. The fourth transistor T4 is turned off according to the high level signal of the second node N2. The fifth transistor T5 is turned on. Because the first clock signal CK1 jumps from a high level to a low level, the potential of the fourth node N4 is lowered, and the potential of the fifth node N5 is lowered due to the coupling effect of the second capacitor C2. When the potential of the fifth node N5 is lowered to be lower than the potential of the third node N3, the sixth transistor T6 is turned on, and a lower potential is transmitted to the third node N3, so that the third transistor T3 is in a good turned-on state and transmits the first level signal VGL (a low level signal) to the second output end OUT2.

[0184] In subsequent processes, the fifth stage t5 and the sixth stage t6 are alternately repeated in the same timing. Until the start signal SIN becomes a pulse again, the stage t3 is entered again.

[0185] Figure 13 is another working timing diagram of a shift register provided by an embodiment of the present application. The working timing corresponds to the shift register shown in Figure 11 , and reference is made to Figure 11 and Figure 13 . Still taking the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, and the fourteenth transistor T14 as P-type transistors, and the twelfth transistor T12 as an N-type transistor as examples, and taking the first level signal VGL as a low level signal and the second level signal VGH as a high level signal as examples, the working timing of the shift register includes the following stages.

[0186] In the first stage t1, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. As described in Figure 10The shift register shown in the first stage t1 is different in that the fifth transistor T5 is turned on according to the initial potential of the fifth node N5, and then the low-level second clock signal CK2 is transmitted to the fourth node N4, so that the potential of the fourth node N4 is lowered, and due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 is also lowered, and since the fifth node N5 can be considered as a ground potential in the initial state, the potential of the fifth node N5 is lowered after being coupled, and the potential becomes lower. In the initial state, no signal is input to the third node N3, so the initial potential of the third node N3 can be considered as a low-level signal (for example, a ground level), so the potential of the fifth node N5 is lower than that of the third node N3, the sixth transistor T6 is turned on, and the third transistor T3 is turned on to transmit the first-level signal VGL (low-level signal) to the second output terminal OUT2.

[0187] In the first intermediate state stage t12, the start signal SIN is a high-level signal, the first clock signal CK1 is a high-level signal, and the second clock signal CK2 jumps to a high-level signal. Compared with Figure 10 The shift register shown in the first intermediate state stage t12 is different in that the fifth node N5 is low in the first stage t1, so that at the initial moment of the first intermediate state stage t12, the fifth transistor T5 is turned on to transmit the high-level second clock signal CK2 to the fourth node N4, so that the potential of the fourth node N4 is raised, and due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 is also raised, so that the potential of the fifth node N5 is higher than that of the third node N3, the sixth transistor T6 is turned off, and the third node N3 can still be kept low, so that the third transistor T3 is turned on to transmit the first-level signal VGL (low-level signal) to the second output terminal OUT2.

[0188] In the second stage t2, the start signal SIN is a high-level signal, the first clock signal CK1 jumps to a low-level signal, and the second clock signal CK2 is a high-level signal. Compared with Figure 10 The shift register shown in the second stage t2 is different in that the potential state of the second node N2 is the same as that in the first intermediate stage t12, and the potential state of the second clock signal CK2 is the same as that in the first intermediate stage t12, so that the fourth transistor T4 and the fifth transistor T5 are both turned off, the potential state of the fourth node N4 and the fifth node N5 is the same as that in the first intermediate stage t12, the sixth transistor T6 is turned off, and the third node N3 can still be kept low, so that the third transistor T3 is turned on to transmit the first-level signal VGL (low-level signal) to the second output terminal OUT2.

[0189] In the second intermediate state stage t23, the initial signal SIN is high for a period of time and low for a period of time. The first clock signal CK1 transitions to a high level, while the second clock signal CK2 remains high. Figure 10 The shift register shown differs in the second intermediate state stage from the following: since the potential state of the second node N2 is the same as that of the second stage t2, and the potential state of the second clock signal CK2 is the same as that of the second stage t2, the fourth transistor T4 and the fifth transistor T5 are both turned off. The potential states of the fourth node N4 and the fifth node N5 are the same as those of the first intermediate stage t12. The sixth transistor T6 is turned off, and the third node N3 can still maintain a low level, so that the third transistor T3 is turned on, transmitting the first level signal VGL (low level signal) to the second output terminal OUT2.

[0190] In the third stage t3, the start signal SIN is a low-level signal, the first clock signal CK1 is a high-level signal, and the second clock signal CK2 jumps to a low-level signal. Figure 11 The operation of the shift register shown in the third stage t3 is as follows: Figure 10 The operation of the shift register shown in the third stage t3 is basically the same. It should be noted that, due to... Figure 11 The first terminal of the fifth transistor T5 is connected to the second clock signal CK2. Therefore, at the beginning of the third stage t3, the high-to-low transition of the second clock signal CK2 will have a certain impact on the fourth node N4 and the fifth node N5, causing the potential state of the fourth node N4 and the fifth node N5 to be pulled low at the beginning of the third stage t3, resulting in a spike. Subsequently, it quickly returns to the high level due to the conduction of the fourth transistor T4.

[0191] In the third intermediate state stage t34, the start signal SIN is a low-level signal for a period of time and a high-level signal for a period of time. The first clock signal CK1 is a high-level signal and the second clock signal CK2 is a high-level signal. Figure 11 The operation of the shift register in the third intermediate state t34 shown is similar to... Figure 10 The operation of the shift register shown is basically the same in the third intermediate stage t34.

[0192] In the fourth stage t4, the start signal SIN is a high-level signal, the first clock signal CK1 jumps to a low-level signal, and the second clock signal CK2 is a high-level signal. Figure 11 The operation of the shift register in the fourth stage t4 is shown. Figure 10 The shift register shown operates in essentially the same way during the fourth stage t4.

[0193] In the fourth intermediate state stage t45, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 is a high level signal. Figure 11 The operation of the shift register in the fourth intermediate state stage t45 is basically the same as that of the shift register shown in the fourth stage t4. Figure 10 The operation of the shift register in the fourth intermediate state stage t45 is basically the same as that of the shift register shown in the fourth stage t4.

[0194] In the fifth stage t5, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. Compared with the shift register shown in the fourth stage t4, Figure 10 The difference between the shift register in the fifth stage t5 and the shift register shown in the fourth stage t4 is that the potential of the second output terminal OUT2 is gradually lowered, and due to the coupling effect of the first capacitor C1, the potential of the third node N3 is gradually lowered, and the third transistor T3 is turned on to output the first level signal VGL to the second output terminal OUT2. Since the second clock signal CK1 jumps from a high level to a low level, the potential of the fifth node N5 is lowered, so that the fifth transistor T5 is turned on, and the low level second clock signal CK2 is transmitted to the fourth node N4, the potential of the fourth node N4 is lowered, and when the sixth transistor T6 meets the turn-on condition, the sixth transistor T6 is turned on, the third node N3 is at a low potential, and the third transistor T3 is turned on to output the first level signal VGL to the second output terminal OUT2.

[0195] In the fifth intermediate state stage t56, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 jumps to a high level signal. Compared with the shift register shown in the fourth stage t4, Figure 10 The difference between the shift register in the fifth intermediate state stage t56 and the shift register shown in the fourth stage t4 is that, due to the low level of the fifth node N5 in the fifth stage t5, the fifth transistor T5 is turned on at the initial moment of the fifth intermediate state stage t56 to transmit the high level second clock signal CK2 to the fourth node N4, so that the potential of the fourth node N4 is raised. Due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 is also raised, so that the potential of the fifth node N5 is higher than that of the third node N3, the sixth transistor T6 is turned off, and the third node N3 can still maintain a low level, so that the third transistor T3 is turned on to transmit the first level signal VGL (low level signal) to the second output terminal OUT2.

[0196] In the sixth stage t6, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 jumps to a high level signal. Compared with the shift register shown in the fourth stage t4, Figure 10The shift register shown is different in the sixth stage t6, because the potential state of the second node N2 is the same as that in the fifth intermediate stage t56, and the potential state of the second clock signal CK2 is the same as that in the fifth intermediate stage t56, therefore, the fourth transistor T4 and the fifth transistor T5 are both turned off, the potential state of the fourth node N4 and the fifth node N5 is the same as that in the fifth intermediate stage t56, the sixth transistor T6 is turned off, and the third node N3 can still keep low, so that the third transistor T3 is turned on to transmit the first level signal VGL (low level signal) to the second output end OUT2.

[0197] In the subsequent process, the fifth stage t5 and the sixth stage t6 are alternately repeated in the same timing. Until the start signal SIN becomes a pulse again, the t3 stage is entered again.

[0198] With reference to the foregoing description, the first gate drive signal and the second gate drive signal are alternately repeated in the same timing. Figure 12 and Figure 13 Optionally, the first gate drive signal includes a first level signal and a second level signal.

[0199] Optionally, the pulse of the first gate drive signal overlaps the pulse of the second gate drive signal.

[0200] Optionally, the duration of the first level signal of the pulse of the first gate drive signal is located in the duration of the second level signal of the pulse of the second gate drive signal.

[0201] Optionally, the pulse width of the first gate drive signal is smaller than the pulse width of the second gate drive signal.

[0202] Optionally, the node voltage control module is connected to a clock signal and a start signal, the pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal.

[0203] Optionally, the clock signal connected to the node voltage control module includes a first clock signal CK1 and a second clock signal CK2.

[0204] The pulse of the second clock signal CK2 overlaps the pulse of the start signal, and the pulse of the first clock signal CK1 overlaps the pulse of the first gate drive signal.

[0205] Optionally, the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the first clock signal CK1.

[0206] Optionally, the rising edge of the pulse of the second gate drive signal is aligned with the rising edge of the pulse of the second clock signal CK2.

[0207] Optionally, the falling edge of the pulse of the first gate drive signal is aligned with the falling edge of the pulse of the first clock signal CK1; and the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the first clock signal CK1.

[0208] Optionally, the rising edge and the falling edge of the pulse of the second gate drive signal are aligned with the falling edges of two adjacent pulses of the second clock signal CK2, respectively.

[0209] Optionally, the first clock signal CK1 and the second clock signal CK2 have the same frequency and different phases, for example, opposite phases. The effective potential pulse of the first clock signal CK1 and the effective potential pulse of the second clock signal CK2 do not overlap, for example, there is a time interval. The effective potential of the effective potential pulse of the first clock signal CK1 and the effective potential pulse of the second clock signal CK2 is a first level signal, for example, a low potential.

[0210] In at least part of the period, the rising edges of the plurality of positively correlated signals are synchronized, and the falling edges are synchronized, that is, the directions of the voltage synchronous jumps of the plurality of positively correlated signals are the same. In at least part of the period, the rising edges and the falling edges of the two anti-correlated signals are synchronized, that is, the directions of the voltage synchronous jumps of the two anti-correlated signals are opposite.

[0211] The embodiment of the present application also provides a gate drive circuit, Figure 14 is a structural schematic diagram of a gate drive circuit provided by the embodiment of the present application, referring to Figure 14 The gate drive circuit comprises a plurality of shift registers 10, wherein the shift register 10 is the shift register 10 of any of the above-mentioned embodiments of the present application, the plurality of shift registers 10 are cascaded, and the starting signal input end (which can be connected to the starting signal SIN) of the n+1th shift register is connected with the first output end OUT1 of the nth shift register, wherein n is a positive integer greater than or equal to 1, that is, the first gate drive signal output by the first output end OUT1 of the nth shift register is used as the starting signal of the n+1th register. The starting signal of the first shift register is input from outside.

[0212] The gate drive circuit of the embodiment comprises the shift register of any of the above-mentioned embodiments of the present application, has the beneficial effects of the shift register of any of the above-mentioned embodiments of the present application, and details are not repeated here.

[0213] The gate drive circuit can be connected with a first clock line and a second clock line. The first clock line can be used to provide the first clock signal to the odd-numbered shift registers, and the second clock line can be used to provide the second clock signal to the odd-numbered shift registers. The first clock line can be used to provide the second clock signal to the even-numbered shift registers, and the second clock line can be used to provide the first clock signal to the even-numbered shift registers.

[0214] The embodiment of the present application further provides a display panel, Figure 15 is a structural schematic diagram of a display panel provided by the embodiment of the present application, referring to Figure 3 and Figure 15 The display panel comprises a pixel circuit 2 and the gate drive circuit 1 of any embodiment of the present application, the pixel circuit 2 comprises a plurality of transistors, and the first output end and the second output end of the shift register 10 are connected with different transistors in the pixel circuit 2. For example, the first output end and the second output end of the shift register 10 are connected with different channel type transistors in the pixel circuit 2.

[0215] Optionally, the pixel circuit 2 comprises a drive transistor DT, a data writing transistor M1 and a compensation transistor M2, the data writing transistor M1 is connected between a data line Data and a first electrode of the drive transistor DT, and the compensation transistor M2 is connected between a second electrode and a gate electrode of the drive transistor DT; a gate electrode of the data writing transistor M1 is connected with the first output end OUT1, and the gate electrode of the data writing transistor M1 is connected with a first gate drive signal Scan1; a gate electrode of the compensation transistor M2 is connected with the second output end OUT2, and the gate electrode of the compensation transistor M2 is connected with a second gate drive signal Scan2.

[0216] Optionally, the channel type of the data writing transistor M1 is P channel, and the channel type of the compensation transistor M2 is N channel.

[0217] Optionally, the pixel circuit 2 further comprises a first light emitting control transistor M3 and a second light emitting control transistor M4, the first light emitting control transistor M3 is connected between a fourth power supply line VDD and the first electrode of the drive transistor DT; the second light emitting control transistor M4 is connected between the second electrode of the drive transistor DT and a first electrode of a light emitting device D1, a second electrode of the light emitting device D1 is connected with a fifth power supply line VSS; a gate electrode of the first light emitting control transistor M3 and a gate electrode of the second light emitting control transistor M4 are connected with a light emitting control signal line EM.

[0218] Optionally, the pixel circuit further comprises a first initialization transistor M5, a gate electrode of the first initialization transistor M5 is connected with a first scanning line Sn1, a first electrode of the first initialization transistor M5 is connected with a first initialization signal line Vref1, and a second electrode of the first initialization transistor M5 is connected with a gate electrode or a second electrode of the drive transistor DT.

[0219] Optionally, the pixel circuit further comprises a second initialization transistor M6, a gate electrode of the second initialization transistor M6 is connected with a second scanning line Sn2, a first electrode of the second initialization transistor M6 is connected with a second initialization signal line Vref2, and a second electrode of the second initialization transistor M6 is connected with a first electrode of the light emitting device D1.

[0220] Optionally, the pixel circuit further comprises a storage capacitor Cst, a first end of the storage capacitor Cst is connected to the gate of the driving transistor DT, and a second end of the storage capacitor Cst is connected to the fourth power supply line VDD.

[0221] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, the steps described in the present application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0222] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A shift register, characterized in that, It includes a node voltage control module, a first output module, and a second output module. The node voltage control module is connected to the first node and the second node, the first output module is connected to the first node and the second node, and the second output module is connected to the second node, or the second output module is connected to the first node and the second node. The node voltage control module is used to control the potential of the first node and the second node; The first output module is used to output a first gate drive signal through a first output terminal according to the potentials of the first node and the second node; The second output module is used to output a second gate drive signal through a second output terminal based on the potential of the second node, or based on the potentials of the first node and the second node; the first gate drive signal and the second gate drive signal are different. The second output module includes a first output submodule and a second output submodule. The first output submodule is electrically connected to the second node and is used to turn on or off according to the potential of the second node, and to transmit a second level signal to the second output terminal when it is on. Alternatively, the first output submodule is electrically connected to the first node and is used to turn on or off according to the potential of the first node, and to transmit the second level signal to the second output terminal when it is on. The second output submodule is connected to the second node and is used to transmit a first level signal to the second output terminal according to the potential of the second node; The second output submodule includes an output control unit and an output unit. The output control unit is connected to the second node, the output control unit is connected to the third node, and the output unit is connected to the third node. The output control unit is also connected to a preset clock signal. The output control unit is used to control the potential of the third node according to the potential of the second node and the preset clock signal, so that the potential of the third node is positively correlated with the potential of the first node.

2. The shift register according to claim 1, characterized in that, The pulse width, pulse amplitude, and positive / negative polarity of the first gate drive signal and the second gate drive signal are different in one or more ways.

3. The shift register according to claim 2, characterized in that, The second gate drive signal includes a first level signal and a second level signal.

4. The shift register according to claim 3, characterized in that, The first gate drive signal and the second gate drive signal are used to drive transistors of different channel types; The first gate drive signal is used to drive the P-type transistor, and the second gate drive signal is used to drive the N-type transistor. The voltage of the first level signal is lower than the voltage of the second level signal; the second output module includes a P-type transistor, and the second output module is used to output the first level signal through the P-type transistor.

5. The shift register according to claim 4, characterized in that, The P-type transistor included in the second output module is a polysilicon transistor.

6. The shift register according to claim 3, characterized in that, The first gate drive signal includes the first level signal and the second level signal.

7. The shift register according to claim 2, characterized in that, The pulses of the first gate drive signal overlap with the pulses of the second gate drive signal.

8. The shift register according to claim 6, characterized in that, The duration of the first level signal of the pulse of the first gate drive signal is within the duration of the second level signal of the pulse of the second gate drive signal.

9. The shift register according to claim 2, characterized in that, The pulse width of the first gate drive signal is less than the pulse width of the second gate drive signal.

10. The shift register according to claim 2, characterized in that, The node voltage control module receives a clock signal and a start signal. The pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal.

11. The shift register according to claim 10, characterized in that, The clock signals received by the node voltage control module include a first clock signal and a second clock signal. The pulse of the second clock signal overlaps with the pulse of the start signal, and the pulse of the first clock signal overlaps with the pulse of the first gate drive signal.

12. The shift register according to claim 11, characterized in that, The transition edge of the pulse of the first gate drive signal is aligned with the transition edge of the pulse of the first clock signal.

13. The shift register according to claim 11, characterized in that, The transition edge of the pulse of the second gate drive signal is aligned with the transition edge of the pulse of the second clock signal.

14. The shift register according to claim 11, characterized in that, The falling edge of the pulse of the first gate drive signal is aligned with the falling edge of the pulse of the first clock signal; the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the first clock signal.

15. The shift register according to claim 11, characterized in that, The rising and falling edges of the pulse of the second gate drive signal are aligned with the falling edges of two adjacent pulses of the second clock signal, respectively.

16. The shift register according to claim 11, characterized in that, The first clock signal and the second clock signal have the same frequency but different phases.

17. The shift register according to any one of claims 1-16, characterized in that, The effective levels of the first gate drive signal and the second gate drive signal overlap.

18. The shift register according to any one of claims 1-16, characterized in that, The effective level of the first gate drive signal is a first level signal, and the effective level of the second gate drive signal is a second level signal.

19. The shift register according to any one of claims 1-16, characterized in that, The invalid levels of the first gate drive signal and the second gate drive signal overlap.

20. The shift register according to any one of claims 1-16, characterized in that, The node voltage control module is used to control the second node's potential to change from high to low when the first node's potential changes from low to high, and vice versa.

21. The shift register according to any one of claims 1-16, characterized in that, The node voltage control module is used to control the potentials of the first node and the second node to remain opposite.

22. The shift register according to claim 1, characterized in that, The node voltage control module is connected to a first clock signal and / or a second clock signal, and the preset clock signal includes either the first clock signal or the second clock signal.

23. The shift register according to claim 1, characterized in that, The first output submodule includes a first transistor, the gate of the first transistor is connected to the second node, the first terminal of the first transistor is connected to the second power line or connected to the second level signal, and the second terminal of the first transistor is connected to the second output terminal; the output unit includes a third transistor, the gate of the third transistor is connected to the third node, the first terminal of the third transistor is connected to the first power line or connected to the first level signal, and the second terminal of the third transistor is connected to the second output terminal.

24. The shift register according to claim 23, characterized in that, The potential of the third node includes a third-level signal, the voltage of which is lower than the voltage of the first power line.

25. The shift register according to claim 24, characterized in that, The absolute value of the voltage difference between the third level signal and the first level signal is greater than or equal to the absolute value of the threshold voltage of the third transistor.

26. The shift register according to claim 23, characterized in that, The third transistor is a P-type transistor.

27. The shift register according to claim 23, characterized in that, The first transistor is a P-type transistor.

28. The shift register according to claim 23, characterized in that, The second output submodule further includes a first capacitor, the first end of which is connected to the gate of the third transistor, and the second end of which is connected to the second output terminal.

29. The shift register according to claim 1, characterized in that, When the potential of the second node changes from low to high, the potential of the third node changes from high to low; when the potential of the second node changes from high to low, the potential of the third node changes from low to high.

30. The shift register according to claim 1, characterized in that, The potentials of the second node and the third node remain opposite, high and low.

31. The shift register according to claim 1, characterized in that, The potentials of the first node and the third node simultaneously change from low potential to high potential, and / or the potentials of the first node and the third node simultaneously change from high potential to low potential.

32. The shift register according to claim 24, characterized in that, The potential of the third node also includes a second level signal, the voltage of which is lower than the voltage of the second level signal.

33. The shift register according to claim 24, characterized in that, The absolute value of the voltage difference between the third level signal and the voltage of the first power line is greater than or equal to the absolute value of the threshold voltage of the third transistor.

34. The shift register according to claim 1, characterized in that, The output control unit includes a charge / discharge control subunit, a coupling subunit, and a unidirectional conduction subunit; The charge / discharge control subunit is connected to the second node, the first end of the coupling subunit, and the second end of the coupling subunit, respectively. The second end of the coupling subunit is connected to the first end of the unidirectional conduction subunit, and the second end of the unidirectional conduction subunit is connected to the third node. The charge / discharge control subunit is used to charge and / or discharge the coupling subunit according to the potential of the second node and the preset clock signal; The coupling subunit is used to couple the potential change at its first end to its second end; The unidirectional conduction subunit is used to conduct when the potential at the first end of the unidirectional conduction subunit is lower than the potential of the third node.

35. The shift register according to claim 34, characterized in that, The charge / discharge control subunit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is connected to the second node, the first terminal of the fourth transistor is connected to the second power line or connected to the second level signal, and the second terminal of the fourth transistor is connected to the first end of the coupling subunit. The gate of the fifth transistor is connected to the second end of the coupling subunit, the first terminal of the fifth transistor is connected to the preset clock signal, and the second terminal of the fifth transistor is connected to the first end of the coupling subunit.

36. The shift register according to claim 34, characterized in that, The coupling subunit includes a second capacitor, the first plate of the second capacitor serving as the first end of the coupling subunit, and the second plate of the second capacitor serving as the second end of the coupling subunit.

37. The shift register according to claim 36, characterized in that, The output unit includes a third transistor, the gate of which is connected to the third node, the first terminal of which is connected to a first power line or to the first level signal, and the second terminal of which is connected to the second output terminal. The second output submodule also includes a first capacitor, the first terminal of which is connected to the gate of the third transistor, and the second terminal of which is connected to the second output terminal. The second capacitor is larger than the first capacitor.

38. The shift register according to claim 34, characterized in that, The unidirectional conduction subunit includes a sixth transistor, the gate of which is connected to the first terminal of the sixth transistor, the gate of which is connected to the second terminal of the coupling subunit, and the second terminal of which is connected to the third node.

39. The shift register according to claim 38, characterized in that, The sixth transistor is a P-type transistor.

40. The shift register according to claim 22, characterized in that, The first output module includes a third output submodule and a fourth output submodule. The third output submodule is connected to the first node and is used to turn on or off according to the potential of the first node, and output the second level signal to the first output terminal when it is on. The fourth output submodule is connected to the second node and is used to turn on or off according to the potential of the second node, and to output the first clock signal to the first output terminal when it is turned on.

41. The shift register according to claim 40, characterized in that, The third output submodule includes a seventh transistor, the gate of which is connected to the first node, the first terminal of which is connected to a second power line or a second level signal, and the second terminal of which is connected to the first output terminal.

42. The shift register according to claim 41, characterized in that, The fourth output submodule includes an eighth transistor, the gate of which is connected to the second node, the first terminal of which is connected to the first clock signal, and the second terminal of which is connected to the first output terminal.

43. The shift register according to claim 42, characterized in that, The seventh transistor is a P-type transistor, and the eighth transistor is a P-type transistor.

44. The shift register according to claim 40, characterized in that, The fourth output submodule also includes a third capacitor, the first end of which is connected to the second node, and the second end of which is connected to the first output terminal.

45. The shift register according to claim 40, characterized in that, The node voltage control module includes an input unit and a first control unit. The input unit is used to turn on or off according to a second clock signal, and transmits a start signal to the second node when it is turned on. The first control unit is used to transmit a first level signal or a second level signal to the first node according to the potential of the second node.

46. ​​The shift register according to claim 45, characterized in that, The node voltage control module further includes a second control unit, which is used to transmit the second level signal to the second node according to the potential of the first node and the first clock signal.

47. The shift register according to claim 46, characterized in that, The first clock signal, the second clock signal, and the start signal each include an alternately set first level pulse and a second level pulse. The first level pulse of the start signal overlaps with the first level pulse of the second clock signal, but does not overlap with the first level pulse of the first clock signal.

48. The shift register according to claim 45, characterized in that, The first level pulse of the start signal is one or more, and the first level pulses of the first clock signal and the second clock signal are multiple.

49. The shift register according to claim 46, characterized in that, The input unit includes a ninth transistor, the gate of which is connected to a second clock signal, the first terminal of which is connected to the start signal, and the second terminal of which is connected to a second node.

50. The shift register according to claim 49, characterized in that, The shift register further includes a tenth transistor, the second terminal of which is connected to the second node via the tenth transistor; the gate of the tenth transistor is connected to a first power supply line or to a first level signal.

51. The shift register according to claim 45, characterized in that, The first control unit includes an inverter.

52. The shift register according to claim 49, characterized in that, The first control unit includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is connected to the second terminal or the second node of the ninth transistor. The first terminal of the eleventh transistor is connected to a second power supply line or a second level signal. The second terminal of the eleventh transistor is connected to the first node. The gate of the twelfth transistor is connected to the second terminal or the second node of the ninth transistor. The first terminal of the twelfth transistor is connected to a first power supply line or a first level signal. The second terminal of the twelfth transistor is connected to the first node. The second control unit includes a thirteenth transistor and a fourteenth transistor. The first terminal of the thirteenth transistor is connected to a second power line or a second level signal. The second terminal of the thirteenth transistor is connected to the first terminal of the fourteenth transistor. The second terminal of the fourteenth transistor is connected to the second terminal or a second node of the ninth transistor. One of the gates of the thirteenth transistor and the fourteenth transistor is connected to the first node, and the other is connected to a first clock signal.

53. The shift register according to claim 52, characterized in that, The gate of the thirteenth transistor is connected to the first node; the gate of the fourteenth transistor is connected to the first clock signal.

54. The shift register according to claim 52, characterized in that, The eleventh transistor is a P-type transistor, and the twelfth transistor is an N-type transistor.

55. A gate driving circuit, characterized in that, It includes multiple shift registers as described in any one of claims 1-54, wherein the multiple shift registers are cascaded; the start signal input terminal of the (n+1)th stage shift register is connected to the first output terminal of the nth stage shift register, wherein n is a positive integer greater than or equal to 1.

56. A display panel, characterized in that, Includes pixel circuitry and the gate driving circuitry as described in claim 55. The pixel circuit includes multiple transistors, and the first and second output terminals of the shift register are connected to transistors of different channel types in the pixel circuit.

57. The display panel according to claim 56, characterized in that, The pixel circuit includes a driving transistor, a data writing transistor, and a compensation transistor. The data writing transistor is connected between a data line and the first terminal of the driving transistor, and the compensation transistor is connected between the second terminal and the gate of the driving transistor. The gate of the data writing transistor is connected to the first output terminal, and the gate of the compensation transistor is connected to the second output terminal.

58. The display panel according to claim 57, characterized in that, The data writing transistor has a P-channel type, and the compensation transistor has an N-channel type.

59. The display panel according to claim 58, characterized in that, The pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The first light-emitting control transistor is connected between the fourth power line and the first terminal of the driving transistor. The second light-emitting control transistor is connected between the second terminal of the driving transistor and the first terminal of the light-emitting device. The second terminal of the light-emitting device is connected to the fifth power line. The gates of the first and second light-emitting control transistors are connected to the light-emitting control signal line.

60. The display panel according to claim 57, characterized in that, The pixel circuit further includes a first initialization transistor, the gate of which is connected to a first scan line, the first electrode of which is connected to a first initialization signal line, and the second electrode of which is connected to the gate or the second electrode of the driving transistor.

61. The display panel according to claim 59, characterized in that, The pixel circuit further includes a second initialization transistor, the gate of which is connected to a second scan line, the first electrode of which is connected to a second initialization signal line, and the second electrode of which is connected to the first electrode of the light-emitting device.

Images