Display panel and display device

Abstract

The display panel and the display device provided by the embodiment of the present application comprise a plurality of shift registers which are sequentially cascaded along a first direction; a pixel circuit group comprises at least two pixel circuit units arranged along the first direction; wherein, along the first direction, at least part of the pixel circuit units are not separated by the shift registers. According to the embodiment of the present application, a plurality of pixel circuit units are continuously prepared along the first direction and are not separated by the shift registers, which is beneficial to improve the compactness of the circuit structure prepared in the display panel, to provide the condition of spatial nesting during the circuit preparation, and to improve the space utilization rate during the preparation of the wiring. The feasibility of reducing the area occupied by the circuit structure for preparing the pixel circuit unit and the shift register circuit is improved, sufficient space is reserved at the edge position of the display panel for preparing other kinds of leads, available space is provided, and the application of the display panel in the narrow-frame or frameless display device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] At present, the application demand of narrow frame screen or even frameless screen is more and more wide in the market, such as in the preparation of some special-shaped display screen or large display screen, a plurality of narrow frame or frameless screens can be used to splice. When preparing a narrow frame or frameless screen, in order to enable the display panel to be spliced and connected with other panels, the space near the edge of the display panel can be provided with pixel circuit, electrostatic discharge end and other circuit structures such as lead-out line and multiplexer. At this time, when preparing the pixel circuit and other circuits in the display panel, the wiring around the display panel needs to be avoided, such as cascade line, electrostatic discharge line, pin, and wiring in multiplexer circuit. The above wiring provides sufficient space for preparation, and ensures the normal work of the display panel. Therefore, in the application of some narrow frame and frameless display panel, it is of great significance to improve the compactness and space utilization of the line structure in the process of preparing pixel circuit and shift register in the display panel, which promotes the progress of display technology. SUMMARY

[0003] Therefore, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, the present application provides a display panel, comprising a display area, the display area comprising:

[0005] a driving circuit comprising a plurality of shift registers cascaded in a first direction;

[0006] a pixel circuit group comprising at least two pixel circuit units arranged in the first direction;

[0007] wherein in the first direction, at least part of the pixel circuit units do not include shift registers.

[0008] In a second aspect, the present application provides a display device comprising the display panel provided in the first aspect.

[0009] In the present application, at least part of the pixel circuit units in the first direction do not include shift registers, that is, the pixel circuit units prepared in the pixel circuit group in the display area are arranged continuously and adjacently in the first direction, and the plurality of pixel circuit units arranged adjacently do not include shift registers. For example, as shown in FIG. 1, the pixel circuit units 101, 102, 103 and 104 are arranged adjacently in the first direction, and the pixel circuit units 105, 106, 107 and 108 are arranged adjacently in the first direction. The pixel circuit units 101-104 do not include shift registers, and the pixel circuit units 105-108 do not include shift registers. Figure 1 , Figure 2As shown, two pixel circuit units are prepared adjacent in the first direction, and the two pixel circuit units prepared adjacent can be located between two shift registers of adjacent stages. In combination with the related art, in the first direction, multiple pixel circuit units are prepared continuously without being separated by shift registers, which is conducive to improving the compactness of the circuit structure prepared in the display panel, because the structures of multiple pixel circuit units are similar, and the conditions for spatial nesting are met when the circuit is prepared, and the signal frequencies transmitted on multiple pixel circuit units are also similar, which is conducive to reducing the risk of crosstalk. Therefore, after at least part of the pixel circuit units in the display panel are arranged without including shift registers, it is beneficial to better utilize the space adjacent in the second direction of the wiring, and it is not necessary to arrange multiple wirings along the first direction one by one, thereby improving the space utilization rate when the wiring is prepared. The area occupied by the circuit structure of the prepared pixel circuit unit and shift register circuit is reduced, which provides available space for reserving sufficient avoidance space at the edge position of the display panel for preparing other kinds of lead lines, and is conducive to improving the applicability of the display panel in narrow-frame or frameless display devices. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0011] Figure 1 A plan view of a display panel provided by an embodiment of the present application;

[0012] Figure 2 Another plan view of a display panel provided by an embodiment of the present application;

[0013] Figure 3 A plan view of a display panel provided by an embodiment of the present application; Figure 1 A plan view of a middle region E1;

[0014] Figure 4 A plan view of a display panel provided by an embodiment of the present application; Figure 1 A plan view of a middle region E2;

[0015] Figure 5 A plan view of a display panel provided by an embodiment of the present application; Figure 1 A plan view of a middle region E3;

[0016] Figure 6 A plan view of a display panel provided by an embodiment of the present application; Figure 1 A plan view of a middle region E1 and a region E2;

[0017] Figure 7 A schematic diagram of a pixel circuit provided for an embodiment of the present application;

[0018] Figure 8 A schematic diagram of a pixel circuit provided for an embodiment of the present application; Figure 6 A partial schematic diagram of region E4;

[0019] Figure 9 A planar schematic diagram of a display panel provided for an embodiment of the present application;

[0020] Figure 10 A planar schematic diagram of a display panel provided for an embodiment of the present application;

[0021] Figure 11 A planar schematic diagram of a display panel provided for an embodiment of the present application;

[0022] Figure 12 A planar schematic diagram of a display panel provided for an embodiment of the present application;

[0023] Figure 13 A planar schematic diagram of a display panel provided for an embodiment of the present application;

[0024] Figure 14 A schematic diagram of a pixel circuit provided for an embodiment of the present application; Figure 13 A partial schematic diagram of region E5;

[0025] Figure 15 A planar schematic diagram of a display panel provided for an embodiment of the present application;

[0026] Figure 16 A planar schematic diagram of a display panel provided for an embodiment of the present application;

[0027] Figure 17 A planar schematic diagram of a display panel provided for an embodiment of the present application;

[0028] Figure 18 A planar schematic diagram of a display panel provided for an embodiment of the present application;

[0029] Figure 19 A planar schematic diagram of a display device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0032] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0033] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0034] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0035] It should be understood that although terms such as "first," "second," etc., may be used to describe directions, traces, sub-areas, etc., in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish directions, traces, sub-areas, etc., from one another. For example, without departing from the scope of the embodiments of this application, a first direction may also be referred to as a second direction, and similarly, a second direction may also be referred to as a first direction. Through meticulous and in-depth research, the applicant of this case has provided a solution to the problems existing in the prior art.

[0036] Figure 1 This is a plan view of a display panel provided in an embodiment of this application. Figure 2 This is a plan view of another display panel provided in an embodiment of this application.

[0037] This application provides a display panel 100, such as... Figure 1 , Figure 2As shown, the display panel 100 includes a display area AA, which includes a driving circuit 10. The driving circuit 10 includes a plurality of shift registers 101 cascaded sequentially along a first direction X1. The display area AA also includes a pixel circuit group 20, which includes at least two pixel circuit units 201 arranged along the first direction X1. In the display area AA, at least some of the shift registers 101 are electrically connected to the pixel circuit units 201 to drive the pixel circuit units 201 to operate, thereby realizing the display operation of the display panel 100.

[0038] Optionally, such as Figure 1 As shown, during the fabrication of some narrow-bezel display panels 100, some shift registers 101 in the driving circuit 10 can be located in the bezel area, while some shift registers 102 can be located in the display area AA. Alternatively, as shown... Figure 2 As shown, in the fabrication process of some borderless display panels 100, the shift register 101 in the driving circuit 10 can be located in the display area AA. Of course, during the fabrication process of the display panel 100, the fabrication position of the shift register 101 in the driving circuit 10 can be determined according to the actual usage. When the shift register 101 is fabricated in the display area AA, it is beneficial to improve the space utilization of the display area AA in the display panel 100, reduce the circuit structure fabricated in the bezel of the display panel 100, thereby reducing the bezel area, increasing the effective screen ratio of the display panel 100, and improving the visual experience of the display panel 100.

[0039] Within the display area AA, multiple shift registers 101 are cascaded in the first direction X1. Pixel circuit units 20 are also arranged in the first direction X1 within the display area AA. In related technologies, multiple shift registers and pixel circuit units arranged in the first direction are typically arranged alternately, forming an arrangement of shift register, pixel circuit unit, shift register, pixel circuit unit… In this arrangement, a shift register and a pixel circuit unit are adjacent in the first direction. Typically, the wiring structures belonging to the pixel circuit unit and the shift register are also arranged adjacently in the first direction. This results in high circuit regularity. However, when multiple wirings are arranged adjacently in the first direction, the adjacent spaces in the second direction are often not utilized, increasing the area occupied by the pixel circuit units and shift registers. This is detrimental to improving the compactness of the circuit structure and to reserving sufficient clearance space at the edge of the display panel. The second direction is the direction that intersects with the first direction.

[0040] In this embodiment, at least some of the pixel circuit units 201 are not connected by a shift register 101 along the first direction X1. That is, the pixel circuit units 201 fabricated in the pixel circuit group 20 within the display area AA are arranged consecutively adjacent to each other along the first direction X1, and the aforementioned adjacent pixel circuit units 201 are not connected by a shift register 101. For example, as... Figure 1 , Figure 2 As shown, two pixel circuit units 201 are fabricated adjacently in the first direction X1, and the two adjacent pixel circuit units 201 can be located between two shift registers 101 in adjacent stages. According to related technologies, fabricating multiple pixel circuit units 201 consecutively in the first direction X1 without being separated by shift registers 101 is beneficial for improving the compactness of the circuit structure fabrication in the display panel 100. This is because the structures of multiple pixel circuit units 201 are similar, allowing for spatial nesting during circuit fabrication, and the signal frequencies transmitted on multiple pixel circuit units 201 are also similar, which helps reduce the risk of crosstalk. Therefore, by setting at least some pixel ground units 201 in the display panel 100 to exclude shift registers 101, it is beneficial to better utilize the adjacent space of the traces in the second direction X2, eliminating the need for multiple traces to be arranged sequentially along the first direction X1, thus improving the space utilization rate during trace fabrication. This improves the feasibility of reducing the area occupied by the circuit structure of the pixel circuit unit 201 and the shift register circuit 101, provides sufficient clearance space at the edge of the display panel 100 for the fabrication of other types of leads, and helps to improve the applicability of the display panel 100 in narrow-bezel or borderless display devices.

[0041] Figure 3 An embodiment provided in this application Figure 1 A schematic diagram of the central region E1.

[0042] In one embodiment of this application, combined with Figure 1 , Figure 3 As shown, in the display area AA, the pixel circuit unit 201 includes at least two pixel circuits 30. The multiple pixel circuits 30 included in the pixel circuit unit 201 can each drive one of the light-emitting devices in the same pixel to emit light. The pixel circuit 30 includes a pulse width modulation module 301 and a pulse amplitude modulation module 302. The pulse width modulation module 301 is electrically connected to a first signal line SL1, and the pulse amplitude modulation module 302 is electrically connected to a second signal line SL2. Both the first signal line SL1 and the second signal line SL2 extend along a first direction X1.

[0043] The pixel circuit 30 proposed in the embodiments of the present application is in the form of jointly driving the light emitting device to emit light by the pulse width modulation module 301 and the pulse amplitude modulation module 302. The pulse width modulation module 301 prepared in the pixel circuit 30 can be used to control the light emitting time of the light emitting device driven by the pixel circuit 30. In the pixel circuit 30, the pulse width modulation module 301 is arranged to facilitate better brightness control of the light emitting device. The light emitting time of the light emitting device is adjusted by changing the width of the pulse. Generally, a longer pulse width corresponds to a longer light emitting time, so that the light emitting device generates higher light emitting brightness. The pulse width modulation module 301 can achieve relatively fine brightness control and can be suitable for display applications requiring high resolution and high frequency. The pulse width modulation module 301 can receive a pulse width data signal Pwm-data. The first signal line SL1 can be used to transmit the pulse width data signal Pwm-data. The first signal line SL1 extends in the first direction X1 and can be electrically connected to a plurality of pixel circuits 30 arranged in the first direction X1. The same first signal line SL1 can be time-shared to transmit corresponding pulse width data signals Pwm-data to different pixel circuits 30.

[0044] The pulse amplitude modulation module 302 can receive a pulse amplitude data signal Pam-data. Therefore, the second signal line SL2 can be used to transmit the pulse amplitude data signal Pam-data. Similarly, the second signal line SL2 extends in the first direction X1 and can be electrically connected to a plurality of pixel circuits 30 arranged in the first direction X1. The second signal line SL2 can be time-shared to transmit different pulse amplitude data signals Pam-data to different pixel circuits 30. The pulse amplitude modulation module 302 prepared in the pixel circuit 30 can achieve more accurate light emitting brightness control by adjusting the pulse amplitude of the pulse amplitude data signal Pam-data. Compared with the conventional method of using voltage to control light emitting brightness, the use of the pulse width modulation module 301 and the pulse amplitude modulation module 302 to jointly control the light emitting process of the light emitting device is advantageous to improve the working stability and accuracy of the light emitting device, can effectively reduce the influence of noise in the circuit on the working of the light emitting device, and further improve the image clarity and stability during display of the display panel 100, and improve the visual effect. Moreover, the use of the pixel circuit 30 including the pulse width modulation module 301 and the pulse amplitude modulation module 302 is advantageous to improve the technical standard applicable to the embodiments of the present application, improve the compatibility with existing display technologies, and improve the usability of the embodiments of the present application.

[0045] Further, along the second direction X2, the first signal line SL1 and the second signal line SL2 are respectively located on opposite sides of the pixel circuit unit 201, which is beneficial to improve the structural symmetry of the display panel 100, thereby improving the uniformity of the display panel 100 when working. In addition, if the first signal line SL1 and the plurality of second signal lines SL2 are located on the same side of the pixel circuit unit 201, it is easy to cause the pixel circuit 30 to need to cross a plurality of signal lines when electrically connected with the signal line, which is easy to increase the coupling degree between the wires, and is not conducive to ensuring the accuracy of the signal transmission of the first signal line SL1 and the second signal line SL2. Therefore, in the embodiment of the present application, the first signal line SL1 and the second signal line SL2 are respectively located on opposite sides of the pixel circuit unit 201, which is beneficial to improve the accuracy of the pulse width data signal Pwm-data and the pulse amplitude data signal Pam-data received by the pixel circuit 30, and is beneficial to ensure the working stability of the pixel circuit 30 in combination with the arrangement manner of the pixel circuit unit 201 and the shift register 201 proposed in the embodiment of the present application, thereby improving the feasibility of the embodiment of the present application.

[0046] In an embodiment of the present application, continuing to refer to the display panel 100 shown in FIG. 1, the pixel circuit 30 in the same pixel circuit group 20 is electrically connected with the shift register 101 in the same pixel circuit group 20 along the first direction X1. Figure 1 、 Figure 3 In the embodiment of the present application, the pulse width modulation module 301 and the pulse amplitude modulation module 302 in the same pixel circuit 30 are electrically connected and prepared adjacent along the first direction X1. It can be known from the above that, in the display panel 100 including at least part of the pixel circuit units 201 without the shift register 101, the pulse width modulation module 301 of the pixel circuit 30 in one of the pixel circuit units 201 in the same pixel circuit group 20 is adjacent to the pulse amplitude modulation module 302 of the pixel circuit 30 in the pixel circuit unit 201 adjacent along the first direction X1.

[0047] Since the pulse width modulation module 301 is electrically connected with the first signal line SL1, the pulse amplitude adjustment module 302 is electrically connected with the second signal line SL2, and the first signal line SL1 and the second signal line SL2 are respectively located on opposite sides of the pixel circuit unit 201 in the second direction X2. Then, the winding direction when the pulse width modulation module 301 is electrically connected with the first signal line SL1 and the winding direction when the pulse amplitude adjustment module 302 is electrically connected with the second signal line SL2 can be opposite. Thus, when the pulse width modulation module 301 of one of the two pixel circuits 30 adjacent in the first direction X1 is adjacent to the pulse amplitude adjustment module 302 of the other pixel circuit, the first signal line SL1 and the second signal line SL2 electrically connected by the two pixel circuits 30 in the first direction X1 have the possibility of being prepared by mutually using the space adjacent in the second direction X2; it is beneficial to make the circuit structure of the pulse width modulation module 301 of one of the two pixel circuits 30 adjacent in the first direction X1 and the circuit structure of the pulse amplitude adjustment module 302 of the other pixel circuit 30 at least partially nested in space, and the plurality of pixel circuit units 20 prepared in the first direction X1 have the ability to shrink inward, providing a space for the preparation of other wires at the edge position of the display panel 100.

[0048] In an embodiment of the present application, continuing to refer to the pulse width modulation module 301 and the pulse amplitude adjustment module 302 shown in the Figure 1 、 Figure 3 , the pulse width modulation module 301 and the first signal line SL1 are electrically connected through the first wire L1, and the pulse amplitude adjustment module 302 and the second signal line SL2 are electrically connected through the second wire L2. It should be noted that the first signal line SL1 and the second signal line SL2 are wires extending in the first direction X1. When the pixel circuit 30 is electrically connected with the first signal line SL1, the first wire L1 can be wound from the pixel circuit 30 towards the side where the first signal line SL1 is located. At least part of the first wire L1 extends in the second direction X2 and electrically connects a plurality of first signal lines SL1 of a plurality of pixel circuits 30 in the same pixel circuit unit 201. When the first wire L1 is electrically connected with the corresponding first signal line SL1, it needs to cross other first signal lines SL1. Therefore, the first wire L1 and the first signal line SL1 can be located in different film layers, and the first wire L1 and the first signal line SL1 are electrically connected through punching. Similarly, the second wire L2 and the second signal line SL2 can be located in different film layers, and the second wire and the second signal line SL2 are electrically connected through punching.

[0049] It is conceived that in the same pixel circuit unit 201, the plurality of first wires L1 are all routed towards the side where the first signal line SL1 is located, and the plurality of pixel circuits 20 can be arranged along the second direction X2, at this time, the portions parallel in the first direction X1 between the plurality of first wires L1 also exist in the portions parallel in the second direction X2. Similarly, in the same pixel circuit unit 201, the portions parallel in the first direction X1 between the plurality of second wires L2 also exist in the portions parallel in the second direction X2.

[0050] In the embodiment of the present application, in the same pixel circuit group 20, at least part of the first wires L1 electrically connected with the pulse width modulation module 301 in one of the pixel circuit units 201 overlap with at least part of the second wires L2 electrically connected with the pulse amplitude modulation module 302 in another of the pixel circuit units 201 in the second direction X2, which is beneficial to fully utilize the space between the two adjacent pixel circuit units 201, so that the wires prepared in the first direction X1 can utilize the space mutually, reduce the space occupied when the first wires L1 and the second wires L2 are prepared, and improve the space utilization rate when the wire structure is prepared in the display area AA. In addition, the overlap here refers to the positions corresponding in the second direction X2, not the contact of the two wires.

[0051] Figure 4 A pixel circuit provided in an embodiment of the present application Figure 1 a plan view of the region E2, Figure 5 A pixel circuit provided in an embodiment of the present application Figure 1 a plan view of the region E3, Figure 6 A pixel circuit provided in an embodiment of the present application Figure 1 a plan view of the region E1 and the region E2.

[0052] In an embodiment of the present application, as shown in Figure 4 The pulse amplitude modulation module 302 in the pixel circuit 30 includes a light-emitting driving current output end OUT1, and the light-emitting driving current output end OUT1 is electrically connected with the light-emitting device 200. In the structure of the display panel 100, the light-emitting device 200 is generally located on the side of the pixel circuit 30 facing the light-emitting surface of the display panel 100, and the light-emitting driving current end OUT1 of the pixel circuit 30 is electrically connected with one pole of the light-emitting device 200. The pixel circuit 30 includes a relatively complex circuit structure, and along the direction perpendicular to the plane where the display panel 100 is located, the area occupied by the pixel circuit 30 is generally larger than the area occupied by the light-emitting device 200 electrically connected therewith. Therefore, when the light-emitting device 200 and the pixel circuit 30 are prepared one by one in the display panel 100, there is a case that the light-emitting device 200 and the pixel circuit 30 are not completely aligned, and there is also a case that the light-emitting driving current end OUT of the pixel circuit 30 needs to be routed to a certain extent to realize electrical connection with the light-emitting device 200.

[0053] In the same pixel circuit 30, the distance between the pulse amplitude modulation module 302 and the light emitting device 200 driven thereby in the first direction X1 is different from the distance between the pulse width modulation module 301 and the light emitting device 200 driven thereby in the first direction X1.

[0054] In the related art, the pulse width modulation module in the pixel circuit is usually arranged to be close to the upper frame, and the pulse amplitude modulation module is arranged to be close to the lower frame. In the first direction, the distance between the light emitting device 200 close to the upper frame and the pulse width modulation module 301 in the pixel circuit 30 electrically connected to the light emitting device 200 is greater than the distance between the light emitting device 200 and the pulse amplitude modulation module 302 in the pixel circuit 30 electrically connected to the light emitting device 200. The distance between the light emitting device 200 close to the lower frame and the pulse amplitude modulation module 302 in the pixel circuit 30 electrically connected to the light emitting device 200 is greater than the distance between the light emitting device 200 and the pulse width modulation module 301 in the pixel circuit 30 electrically connected to the light emitting device 200.

[0055] In the embodiments of the present application, the arrangement order of the pulse width modulation module 301 and the pulse amplitude modulation module 302 in the first direction X1 in the first type of pixel circuit 30A is opposite to the arrangement order of the pulse width modulation module 301 and the pulse amplitude modulation module 302 in the first direction X1 in the second type of pixel circuit 30B. Alternatively, as shown in FIG. 1B, the display panel 100 is arranged to include the first type of pixel circuit 30A; or alternatively, as shown in FIG. 1C, the display panel 100 is arranged to include the second type of pixel circuit 30B. Alternatively, as shown in FIG. 1D, the display panel 100 is arranged to include the first type of pixel circuit 30A and the second type of pixel circuit 30B. The first type of pixel circuit 30A is the pixel circuit 30 in which the pulse amplitude modulation module 302 is closer to the upper frame of the display panel 100 than the pulse width modulation module 301, and the second type of pixel circuit 30B is the pixel circuit 30 in which the pulse width modulation module 301 is closer to the upper frame of the display panel 100 than the pulse amplitude modulation module 302. The first type of pixel circuit 30A and the second type of pixel circuit 30B are described by taking the first type of pixel circuit 30A as an example. Figure 4 Figure 5 Figure 6 Figure 4 ​​​As shown, the pixel circuit 30 in the display panel 100 is set as the first type of pixel circuit 30A, which is conducive to making the distance between the pulse amplitude modulation module 302 in the part of the pixel circuit 30 at least close to the upper frame area and the light emitting device 200 to which the pulse amplitude modulation module 302 is electrically connected closer than the distance between the pulse width modulation module 301 and the light emitting device 200, which is conducive to reducing the degree of wire winding when the light emitting driving current end OUT1 in the pulse amplitude modulation module 302 is electrically connected to the light emitting device 200, thereby reducing the amount of wire in the display panel 100 and providing more space for preparing other leads in the display panel 100. Alternatively, as shown, Figure 5 As shown, the pixel circuit 30 in the display panel 100 is set as the second type of pixel circuit 30B, which is conducive to making the distance between the pulse amplitude modulation module 302 in the part of the pixel circuit 30 at least close to the lower frame area and the light emitting device 200 to which the pulse amplitude modulation module 302 is electrically connected closer than the distance between the pulse width modulation module 301 and the light emitting device 200, which is conducive to reducing the degree of wire winding when the light emitting driving current end OUT1 in the pulse amplitude modulation module 302 is electrically connected to the light emitting device 200, thereby reducing the amount of wire in the display panel 100 and providing more space for preparing other leads in the display panel 100. It should be noted that the wire connecting the pixel circuit 30 and the light emitting device 200 can be located in different film layers from the transistors and other structures of the pixel circuit 30, and the wire connecting the pixel circuit 30 and the light emitting device 200 in the schematic diagram will use a cross-line process in the actual structure and will not cross other wires in the pixel circuit 30 and the shift register 101.

[0056] Alternatively, as shown, Figure 6 As shown, the pixel circuit 30 in the display panel 100 is set as the second type of pixel circuit 30B, which is conducive to making the distance between the pulse amplitude modulation module 302 in the part of the pixel circuit 30 at least close to the lower frame area and the light emitting device 200 to which the pulse amplitude modulation module 302 is electrically connected closer than the distance between the pulse width modulation module 301 and the light emitting device 200, which is conducive to reducing the degree of wire winding when the light emitting driving current end OUT1 in the pulse amplitude modulation module 302 is electrically connected to the light emitting device 200, thereby reducing the amount of wire in the display panel 100 and providing more space for preparing other leads in the display panel 100. It should be noted that the wire connecting the pixel circuit 30 and the light emitting device 200 can be located in different film layers from the transistors and other structures of the pixel circuit 30, and the wire connecting the pixel circuit 30 and the light emitting device 200 in the schematic diagram will use a cross-line process in the actual structure and will not cross other wires in the pixel circuit 30 and the shift register 101.

[0057] Figure 7A schematic diagram of a pixel circuit is provided for an embodiment of the present application, Figure 8 A schematic diagram of a pixel circuit is provided for an embodiment of the present application, Figure 6 A partial schematic diagram of a middle region E4.

[0058] In one embodiment of the present application, in combination with Figure 7 , Figure 8As shown, the pixel circuit 30 in the form of 17T3C is exemplarily provided to generate a light-emitting driving current to drive the light-emitting device 200 to emit light. Optionally, the light-emitting device 200 is any one of a micro light-emitting diode (Micro-LED), a mini light-emitting diode (Mini-LED), and an organic light-emitting diode (OLED). The pixel circuit 30 includes a pulse width modulation module 301 and a pulse amplitude modulation module 302. The pulse width modulation module 301 includes transistors T1-T7. The transistor T1 is configured to receive a first power supply driving signal Pwm-VDD of the pulse width modulation module 301. The transistor T2 is configured to receive a pulse width data signal Pwm-data and transmit the pulse width data signal Pwm-data to the transistor T3. The transistor T4 is configured to compensate a threshold voltage of the transistor T3. The transistor T5 is configured to receive a pulse width reset signal Pwm-ref. The transistor T6 is connected in series between a sweep constant voltage signal line SWEEP_GND and a first capacitor C1 (e.g., a plate of the first capacitor C1 connected to the sweep signal line SWEEP). When the transistor T6 is turned on, the sweep constant voltage provided by the sweep constant voltage signal line SWEEP_GND is transmitted to the first capacitor C3. The sweep constant voltage can be the same as a high level of the sweep signal or the same as a low level of the sweep signal. At this time, the sweep constant voltage signal line SWEEP_GND and the sweep signal line SWEEP both provide signals to one plate of the first capacitor C1 (e.g., a plate of the first capacitor C3 connected to the sweep signal line SWEEP), which can further ensure the stability of the potential of the plate of the first capacitor C1 and reduce signal disturbance caused by the surrounding signals. The transistor T7 is configured to electrically connect the pulse width modulation module 301 and the pulse amplitude modulation module 302.The pulse amplitude modulation module 302 includes transistors T8-T14, wherein the transistor T8 is configured to receive the second power supply driving signal Pam-VDD of the pulse amplitude modulation module 302; the transistor T9 is configured to control the light emitting driving current to flow to the light emitting device 200; the transistor T10 is configured to receive the pulse amplitude data signal Pam-data and transmit the pulse amplitude data signal Pam-data to the transistor T11; the transistor T12 is configured to compensate the threshold voltage of the transistor T11 to the gate of the transistor T11; the transistor T13 is configured to receive the pulse amplitude reset signal Pam-REF and transmit the pulse amplitude reset signal Pam-REF to the gate of the transistor T11; the transistor T14 is configured to receive the reset signal transmitted by the reset signal line Pam-INIT and transmit the reset signal to the first electrode of the light emitting device 200; the transistor T15 is turned on to transmit the voltage provided by the second power supply driving signal Pam-VDD to the second capacitor C2, so that the voltage on the second power supply driving signal Pam-VDD is applied to the pulse amplitude modulation module 302 in the light emitting stage, and the light emitting driving current is provided to the light emitting device 200; the transistor T16 is connected in series between the first power supply driving signal Pwm-VDD and the second capacitor C2, and the transistor T16 is turned on to transmit the voltage provided by the first power supply driving signal Pwm-VDD to the second capacitor C2; the transistor T17 is also connected in series between the first power supply driving signal Pwm-VDD and the second capacitor C2, and the transistor T15 is turned on to transmit the voltage provided by the first power supply driving signal Pwm-VDD to the second capacitor C2. Further, the pulse amplitude modulation module 302 further includes a third capacitor C3 connected in series between the reset signal line Pam-INIT and the second capacitor C2, which can be used to stabilize the plate potential of the second capacitor C2.

[0059] In the embodiment of the present application, the circuit structure of the first type of pixel circuit 30A is symmetrical to the circuit structure of the second type of pixel circuit 30B, which is beneficial to improve the convenience when the first type of pixel circuit 30A and the second type of pixel circuit 30B are prepared in the display panel 100, improve the structural regularity of the display panel 100, and is beneficial to prepare the display panel 100 by using the symmetrical preparation method, and improve the preparation efficiency of the display panel 100. Moreover, it is beneficial to ensure the uniformity of the first type of pixel circuit 30A and the second type of pixel circuit 30B when the first type of pixel circuit 30A and the second type of pixel circuit 30B are used, reduce the difference between the two when driving the light emitting device 200, and improve the uniformity display effect of the display panel 100.

[0060] Figure 9 A plan view of another display panel is provided in the embodiment of the present application.

[0061] In one embodiment of the present application, as Figure 9As shown, the display region AA includes a first sub-region AA1, a second sub-region AA2, and a third sub-region AA3 distributed in the first direction X1, and the first sub-region AA1 and the third sub-region AA3 are respectively located on opposite sides of the second sub-region AA2 in the first direction X1. Alternatively, in the first direction X1, the first sub-region AA1 is located in a region closer to the upper frame in the display region AA, the third sub-region AA3 is located in a region closer to the lower frame in the display region AA, and the second sub-region AA2 is located in a region closer to the middle in the display region AA.

[0062] In the embodiments of the present application, in combination with Figure 6 As shown, one of the first sub-region AA1 and the third sub-region AA3 includes the first type of pixel circuit 30A, and the other includes the second type of pixel circuit 30B. Alternatively, the first sub-region AA1 includes the first type of pixel circuit 30A, and the second type of pixel circuit 30B includes the second type of pixel circuit 30B, which is conducive to reducing the wiring distance between the light-emitting driving current output end OUT1 and the light-emitting device 200 in the first sub-region AA1 and the third sub-region AA3 at the same time. In combination with Figure 9 As shown, the second sub-region AA2 includes the first type of pixel circuit 30A and / or the second type of pixel circuit 30B, which is conducive to adaptively preparing the first type of pixel circuit 30A and / or the second type of pixel circuit 30B in the second sub-region AA2 according to actual use, and further improves the wiring preparation compactness in the display region AA.

[0063] Figure 10 Another planar schematic diagram of a display panel provided by an embodiment of the present application is provided, Figure 11 Another planar schematic diagram of a display panel provided by an embodiment of the present application is provided.

[0064] In an embodiment of the present application, as Figures 9-11 As shown, the first sub-region AA1 and / or the third sub-region AA3 include the pixel circuit group 20, and the second sub-region AA2 does not include the pixel circuit group 20. As known from the above, the pixel circuit group 20 includes a plurality of adjacent pixel circuit units 201, and no shift register 101 is included between adjacent pixel circuit units 201, which is conducive to realizing the structure shrinkage when preparing the pixel circuit 30, and providing more space for the display panel 100 near the edge region. In the embodiments of the present application, alternatively, as Figure 9 As shown, the first sub-region AA1 includes the pixel circuit group 20, and the second sub-region AA2 does not include the pixel circuit group 20, which is conducive to realizing the space shrinkage of the pixel circuit 30 and the wiring structure prepared in the first sub-region AA1, increasing the space for preparing other leads between the first sub-region AA1 and the upper edge of the display panel 100, and improving the splicing performance of the display panel 100. Alternatively, as Figure 10As shown, the third sub-area AA2 is provided with the pixel circuit group 20, and the second sub-area AA2 is not provided with the pixel circuit group 20, which is beneficial to realize the space shrink of the pixel circuit 30 and the wiring structure prepared in the third sub-area AA3, increase the space for preparing other leads between the third sub-area AA3 and the lower edge of the display panel 100, and improve the splicing performance of the display panel 100. Alternatively, as shown in FIG. 2, the first sub-area AA1 and the third sub-area AA3 are provided with the pixel circuit group 20, and the second sub-area AA2 is not provided with the pixel circuit group 20, which is beneficial to realize the space shrink of the pixel circuit 30 and the wiring structure prepared in the first sub-area AA1 and the third sub-area AA3, and increase the space for preparing other leads in the upper edge region and the lower edge region of the display panel 100. In addition, the second sub-area AA2 of the display panel 100 is not provided with the pixel circuit group 20, which is beneficial to reduce the number of pixel circuit groups 20 prepared in the display panel 100, balance the wiring impedance in the display panel 100, reduce the wiring collection degree in the display panel 100, and improve the working stability of the display panel 100. Figure 11

[0065] Figure 12 Another planar schematic diagram of a display panel is provided in an embodiment of the present application.

[0066] In an embodiment of the present application, as shown in FIG. 1, the display panel 100 further includes a shift register group 40, and the shift register group 40 includes at least two shift registers 101 arranged along the first direction X1. Figure 12

[0067] The above description mentions that in the prior art, the shift register and the pixel circuit unit are usually arranged alternately along the first direction X1, the circuit structures of the shift register and the pixel circuit unit are quite different, and the part of the wiring between the shift register and the pixel circuit unit needs to be prepared in the form of being arranged along the first direction in sequence, which is easy to waste the wiring structure preparation space in the display panel.

[0068] ​​In the embodiments of the present application, and similar to the pixel circuit group 20, the shift register group 40 is arranged between two adjacent pixel circuit units 20 in the first direction X1, and at least part of the shift registers 101 does not include the pixel circuit unit 20, which is beneficial to utilize the structural similarity of the shift registers 101, arrange multiple cascaded shift registers 101 in the same shift register group 40, and the shift registers 101 do not include the pixel circuit unit 20 therebetween, which is beneficial to realize the spatial nesting of the circuit structures of the adjacent regions of the two shift registers 101 in the shift register group 40, and reduce the area occupied by the shift registers 101 when prepared. Moreover, the shift register group 40 is arranged between two adjacent pixel circuit units 20, which is beneficial to apply the scheme of arranging the pixel circuit group 20 of the present application, optimize the electrical connection mode between the shift registers 101 and the pixel circuit 30, and reduce the degree of wire winding of the electrical connection of the shift registers 101.

[0069] Figure 13 A plan view of another display panel is provided in the embodiments of the present application.

[0070] In one embodiment of the present application, as shown in Figure 13 , the shift register 101 includes an output terminal OUT2, and the output terminal OUT2 of the shift register 101 is electrically connected to the pixel circuit 30 adjacent to the shift register 101 in the first direction X1. The shift register 101 can be used to generate a control signal such as a scanning signal, a light-emitting driving signal, and the like for controlling the pixel circuit 30 to perform different operations, and the control signal is output from the output terminal OUT2 of the shift register 101 to the pixel circuit 30.

[0071] In the embodiments of the present application, the output terminal OUT2 of the shift register 101 is electrically connected to the pixel circuit 30 adjacent to the shift register 101 in the first direction X1, which is beneficial to reduce the electrical connection distance between the output terminal OUT2 and the pixel circuit 30, thereby reducing the wire winding when electrically connecting the output terminal OUT2 to the pixel circuit 30, and further reducing the space occupied by the wire structure.

[0072] Figure 14 A partial view of a region E5 in a display panel is provided in the embodiments of the present application. Figure 13

[0073] In one embodiment of the present application, as shown in Figure 13 , Figure 14 , the output terminal OUT2 of the shift register 101 is also electrically connected to the input terminal IN1 of the next stage shift register 101, and the control signal output from the output terminal OUT2 of the shift register 101 is also transmitted to the input terminal IN1 of the next stage shift register 101 as a driving signal of the next stage shift register 101, thereby realizing the cascading of multiple shift registers 101 arranged in the first direction X1.​Figure 14 A circuit layout schematic diagram of a shift register 101 provided in an embodiment of the present application is mainly used to show the structural relationship between the first type of shift register 101A and the second type of shift register 101B.

[0074] Among the at least two shift registers 101 included in the shift register group 40, the first type of shift register 101A and the second type of shift register 101B are cascaded, and the output end OUT2 of the first type of shift register 101A is electrically connected to the input end IN1 of the second type of shift register 101B. Figure 13 、 Figure 14 As shown in the figure, the shift register 101 in which the input end IN1 and the output end OUT2 are arranged in the first direction X1 in sequence is the first type of shift register 101A, and the direction of the cascade of the plurality of shift registers 101 is the same as the direction in which the input end IN1 and the output end OUT2 of the shift register 101 are arranged in the first direction X1 in sequence; the shift register 101 in which the input end IN1 and the output end OUT2 are arranged in the first direction X1 in sequence is the second type of shift register 101B, and the direction of the cascade of the plurality of shift registers 101 is opposite to the direction in which the input end IN1 and the output end OUT2 of the shift register 101 are arranged in the first direction X1 in sequence.

[0075] In an embodiment of the present application, the output end OUT2 of the first type of shift register 101A and the output end OUT2 of the second type of shift register 101B are arranged on opposite sides in the first direction X1 in the same shift register group 40, the output end OUT2 of the first type of shift register 101A is arranged on the pixel circuit 30 adjacent to it in the first direction X1, and the output end OUT2 of the second type of shift register 101B is arranged on the pixel circuit 30 adjacent to it in the first direction X1, which is conducive to adapting the scheme of the pixel circuit group 20 proposed in the present application to the arrangement of the shift register group 40, and by arranging the output end OUT2 of the first type of shift register 101A and the output end OUT2 of the second type of shift register 101B on opposite sides in the first direction X1, the distance between the plurality of shift registers 101 in the same shift register group 40 and the pixel circuit 30 electrically connected to them is shorter, further reducing the wiring between the shift register 101 and the pixel circuit 30.

[0076] In an embodiment of the present application, continuing to refer to Figure 13 As shown in the figure, no pixel circuit unit 20 is included between the first type of shift register 101A and the second type of shift register 101B adjacent to each other in the first direction X1, which is conducive to further improving the compactness of the circuit structure during preparation of the display panel 100, maintaining the structural uniformity of the display panel 100, and thus improving the uniformity of the display panel 100 during display.

[0077] In an embodiment of the present application, continuing to refer to Figure 14As shown, the circuit structure of the first type of shift register 101A is symmetrical to the circuit structure of the second type of shift register 101B, which is conducive to realizing that the output terminals OUT2 of the first type of shift register 101A and the second type of shift register 101B are both oriented towards the pixel circuit 30 adjacent thereto, and shortens the distance required for winding when the output terminal OUT2 is electrically connected to the adjacent pixel circuit 30.

[0078] Figure 15 A plane schematic diagram of yet another display panel provided by an embodiment of the present application is shown in FIG. 6. Figure 16 A plane schematic diagram of yet another display panel provided by an embodiment of the present application is shown in FIG. 6.

[0079] In an embodiment of the present application, as shown in FIG. 1, Figures 15-16 In the first direction X1, the distance between at least part of two adjacent first type of shift registers 101A is equal to the distance between at least part of two adjacent second type of shift registers 101B.

[0080] Optionally, as shown in FIG. 1, Figure 15As shown, the pixel circuit units 201 and the shift register units 101 are alternately arranged in the first sub-area AA1 and the third sub-area AA3 of the display area AA, and each of the pixel circuit units 201 includes two pixel circuit units 201, and each of the shift register units 101 includes one first type shift register 101A and one second type shift register 101B. In the first sub-area AA1 and / or the third sub-area AA3, between two first type shift registers 101A belonging to two adjacent shift register units 101, there are one first type shift register 101A and two pixel circuit units 201; similarly, between two second type shift registers 101B belonging to two adjacent shift register units 101, there are one second type shift register 101B and two pixel circuit units 201. In terms of the width occupied by the first type shift register 101A and the second type shift register 101B in the first direction X1, the distance between the two first type shift registers 101A in the first sub-area AA1 and / or the third sub-area AA3 is equal to the distance between the two second type shift registers 101B. In addition, the display area AA further includes a second sub-area AA2 between the first sub-area AA1 and the third sub-area AA3 in the first direction X1, and the pixel circuit units 201 and the shift register units 101 in the second sub-area AA2 are alternately arranged in the first direction X1. Taking the shift register units 101 in the second sub-area AA2 as the first type shift register 101A, in the display area AA in the first direction X1, between the two first type shift registers 101A in the second sub-area AA2, there is only one pixel circuit unit 201, which is not equal to the distance between the two second type shift registers 101B in the first sub-area AA1 and / or the third sub-area AA3.

[0081] Optionally, as Figure 16As shown, the display area AA is provided with the shift register group 40 and the pixel circuit group 20, the shift register group 40 and the pixel circuit group 20 are arranged alternately in the first direction X1, and two pixel circuit units 201 are included in one pixel circuit group 20, one first type shift register 101 and one second type shift register 102 are included in one shift register group 40. Then, between two first type shift registers 101A adjacent in the first direction X1, one second type shift register 101B and two pixel circuit units 201 are included, and between two second type shift registers 101B adjacent in the first direction X1, one first type shift register 101B and two pixel circuit units 201 are included, which is beneficial to realize that the distance between two first type shift registers 101A adjacent in the first direction X1 is equal to the distance between two second type shift registers 101B adjacent in the first direction X1, and is beneficial to further improve the uniformity of the circuit structure preparation of the display panel 100, so that the impedance of the wires distributed in each area of the display panel 100 is more uniform, and the uniformity of the display panel 100 is improved.

[0082] In an embodiment of the present application, with continuous reference to Figure 15 As shown, the distance between at least part of the shift registers 101 and the upper level shift registers 101 is not equal to the distance between the lower level shift registers 101. With reference to Figure 14 As shown, in the first sub-area AA1 and / or the third sub-area AA3, the first type shift register 101A and the second type shift register 101B in the same shift register group 40 are adjacent and cascaded, and no other circuit is included between the first type shift register 101A and the second type shift register 101B in the same shift register group 40. In the same shift register group 40, for example, the output end OUT2 of the first type shift register 101A is cascaded with the input end IN1 of the second type shift register 101B, then the first type shift register 101A and the upper level cascaded shift register 101 are the second type shift register 101B located in different shift register groups 40, and the pixel circuit unit 201 is included between the two cascaded shift registers 101 in different shift register groups 40, so that the distance between at least part of the shift registers 101 and the upper level shift registers 101 is not equal to the distance between the lower level shift registers 101 in the display panel, which is beneficial to improve the diversity of the circuit structure preparation of the embodiment of the present application, improve the applicability of the embodiment of the present application, and provide a reference for related technical personnel.

[0083] Figure 17 A plane schematic diagram of another display panel provided by an embodiment of the present application is shown in FIG. 6. Figure 18 A plane schematic diagram of another display panel provided by an embodiment of the present application is shown in FIG. 6.

[0084] In an embodiment of the present application, as shown in Figures 17-18 The display area AA includes a first sub-area AA1, a second sub-area AA2, and a third sub-area AA3 distributed in the first direction X1. The first sub-area AA1 and the third sub-area AA3 are respectively located on opposite sides of the second sub-area AA2 in the first direction X1.

[0085] Optionally, as shown in Figure 17 In the first sub-area AA1, the pixel circuit groups 20 and the shift register groups 40 are arranged alternately in the first direction X1. According to the content of the preparation of the pixel circuit groups 20 and the shift register groups 40 in the display panel 100, the arrangement of the pixel circuit groups 20 and the shift register groups 40 is conducive to the space shrinkage of the pixel circuit 30 structure and the shift register 101 circuit structure, thereby being conducive to reducing the area occupied when the pixel circuit 30 and the shift register 101 are prepared, and at least being conducive to improving the avoidable space between the first sub-area AA1 and the upper edge of the display panel 100, thereby providing a preparation space for other drive circuits and electrical connection leads.

[0086] Optionally, as shown in Figure 18 In the third sub-area AA3, the pixel circuit groups 20 and the shift register groups 40 are arranged alternately in the first direction X1. Similarly, the arrangement of the pixel circuit groups 20 and the shift register groups 40 is conducive to the space shrinkage of the pixel circuit 30 structure and the shift register 101 circuit structure, thereby being conducive to reducing the area occupied when the pixel circuit 30 and the shift register 101 are prepared, and at least being conducive to improving the avoidable space between the third sub-area AA3 and the lower edge of the display panel 100, thereby providing a preparation space for other drive circuits and electrical connection leads.

[0087] Optionally, as shown in Figure 15 In the first sub-area AA1 and the third sub-area AA3, the pixel circuit groups 20 and the shift register groups 40 are arranged alternately in the first direction X1. Similarly, the arrangement of the pixel circuit groups 20 and the shift register groups 40 is conducive to the space shrinkage of the pixel circuit 30 structure and the shift register 101 circuit structure, thereby being conducive to reducing the area occupied when the pixel circuit 30 and the shift register 101 are prepared, being conducive to improving the avoidable space between the first sub-area AA1 and the upper edge of the display panel 100, and being conducive to improving the avoidable space between the third sub-area AA3 and the lower edge of the display panel 100, thereby providing sufficient preparation space for other drive circuits and electrical connection leads, being conducive to the splicing of the display panel 100, and improving the screen-to-body ratio of the display panel 100.

[0088] In an embodiment of the present application, continuing to refer to Figures 15-18As shown, the number of pixel circuits 30 included in the pixel circuit group 20 is the same as the number of shift registers 101 included in the shift register group 40, which is advantageous for adapting the circuit of the pixel circuit group 20 and the shift register 101 in the electrical connection structure, so that the compactness when each shift register 101 in the shift register group 40 is electrically connected with each pixel circuit 30 in the pixel circuit group 20.

[0089] In an embodiment of the present application, with continued reference to Figures 15-18 As shown, the pixel circuit group 20 includes two pixel circuit units 201 adjacent in the first direction X1, and the shift register group 40 includes two shift registers 101 adjacent in the first direction X1, which is advantageous for realizing that both of the two shift registers 101 in the shift register group 40 are electrically connected with the pixel circuit 30 adjacent thereto, reduces the risk that the shift register 101 in the shift register group 40 needs to cross other shift registers 101 to be electrically connected with the pixel circuit 30, and is advantageous for reducing the electrical connection distance between the pixel circuit and the shift register 101, further realizing the structure of the pixel circuit 30 and the shift register 101 to be inwardly contracted, and providing more available space for the display panel 100.

[0090] Figure 19 A planar schematic diagram of a display device provided in an embodiment of the present application.

[0091] An embodiment of the present application provides a display device 300, as shown in the figure. Figure 19 As shown, the display device 300 includes the display panel 100 provided in any one of the above embodiments. Optionally, the display device 300 can be a large-scale spliced screen, a conference room screen, a mobile phone, a special-shaped display screen, or the like display device.

[0092] In the display device 300, the shift register 101 is not included between at least part of the pixel circuit units 201 arranged in the first direction X1, that is, the pixel circuit units 201 prepared in the pixel circuit group 20 in the display area AA are arranged in the first direction X1 in a continuous and adjacent manner, and the shift register 101 is not included between the above adjacent multiple pixel circuit units 201. For example, as shown in the figure, Figure 1 、 Figure 2As shown, two pixel circuit units 201 are prepared adjacently in the first direction X1, and the two pixel circuit units 201 prepared adjacently can be located between two shift registers 101 of adjacent stages. In combination with the related art, in the first direction X1, multiple pixel circuit units 201 are prepared continuously without being separated by a shift register 101, which is beneficial to improve the compactness of the circuit structure prepared in the display panel 100, because the structures of the multiple pixel circuit units 201 are similar, the conditions for spatial nesting are met when the circuit is prepared, and the signal frequencies transmitted on the multiple pixel circuit units 201 are also similar, which is beneficial to reduce the risk of crosstalk. Therefore, after at least part of the pixel circuit units 201 in the display panel 100 are arranged without including a shift register 101 therebetween, it is beneficial to better utilize the space adjacent in the second direction X2. It is not necessary to arrange multiple wires along the first direction X1 one by one, thereby improving the space utilization rate when the wires are prepared. The feasibility of reducing the area occupied by the circuit structures of the pixel circuit units 201 and the shift register circuit 101 is improved, sufficient avoiding space is reserved at the edge position of the display panel 100, which provides available space for preparing other kinds of leads, and is beneficial to improve the applicability of the display panel 100 in narrow-frame or frameless display devices.

[0093] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that, Includes a display area, the display area including: The driving circuit includes multiple shift registers cascaded sequentially along a first direction; A pixel circuit group, comprising at least two pixel circuit units arranged along the first direction; Type 1 pixel circuit; The second type of pixel circuit has the pulse width modulation module and pulse amplitude modulation module arranged in the first direction in the opposite order to the pulse width modulation module and pulse amplitude modulation module arranged in the first direction in the second type of pixel circuit. In the first direction, at least some of the pixel circuit units do not include shift registers.

2. The display panel according to claim 1, characterized in that, The pixel circuit unit includes at least two pixel circuits, each pixel circuit including a pulse width modulation module and a pulse amplitude modulation module. The pulse width modulation module is electrically connected to a first signal line, and the pulse amplitude modulation module is electrically connected to a second signal line. Both the first signal line and the second signal line extend along the first direction; along the second direction, the first signal line and the second signal line are located on opposite sides of the pixel circuit unit.

3. The display panel according to claim 2, characterized in that, In the same pixel circuit group, among two adjacent pixel circuits in the first direction, the pulse width modulation module of one pixel circuit is adjacent to the pulse amplitude modulation module of the other pixel circuit.

4. The display panel according to claim 3, characterized in that, The pulse width modulation module is electrically connected to the first signal line through a first trace, and the pulse amplitude modulation module is electrically connected to the second signal line through a second trace; In the same pixel circuit group, at least a portion of the first trace electrically connected to the pulse width modulation module in one pixel circuit unit overlaps with at least a portion of the second trace electrically connected to the pulse amplitude modulation module in the other pixel circuit unit in the second direction.

5. The display panel according to claim 2, characterized in that, The pulse amplitude modulation module in the pixel circuit includes a light-emitting driving current output terminal, which is electrically connected to the light-emitting device; in the same pixel circuit, the distance between the pulse amplitude modulation module and the light-emitting device it drives in the first direction is different from the distance between the pulse width modulation module and the light-emitting device it drives in the first direction.

6. The display panel according to claim 5, characterized in that, The circuit structure of the first type of pixel circuit is symmetrical to that of the second type of pixel circuit.

7. The display panel according to claim 6, characterized in that, The display area includes a first sub-area, a second sub-area, and a third sub-area distributed in the first direction. The first sub-area and the third sub-area are respectively located on opposite sides of the second sub-area in the first direction. One of the first sub-area and the third sub-area includes the first type of pixel circuit and the other includes the second type of pixel circuit. The second sub-area includes the first type of pixel circuit and / or the second type of pixel circuit.

8. The display panel according to claim 7, characterized in that, The first sub-region and / or the third sub-region includes the pixel circuit group, while the second sub-region does not include the pixel circuit group.

9. The display panel according to claim 1, characterized in that, The display panel further includes a shift register group, which includes at least two shift registers arranged along a first direction; In the first direction, the shift register group is located between two adjacent pixel circuit units, and at least some of the shift registers do not include the pixel circuit units.

10. The display panel according to claim 9, characterized in that, The shift register includes an output terminal, which is electrically connected to the pixel circuit adjacent to it in the first direction.

11. The display panel according to claim 10, characterized in that, The output of the shift register is also electrically connected to the input of the next-level shift register; the shift register group includes at least two shift registers, including a cascaded first-type shift register and a second-type shift register; the output of the first-type shift register is electrically connected to the input of the cascaded second-type shift register. In the same shift register group, the output terminals of the first type of shift register and the second type of shift register face opposite sides in the first direction. The output terminal of the first type of shift register faces the pixel circuit adjacent to it in the first direction, and the output terminal of the second type of shift register faces the pixel circuit adjacent to it in the first direction.

12. The display panel according to claim 11, characterized in that, The pixel circuit unit is not included between the first type shift register and the second type shift register that are adjacent in the first direction.

13. The display panel according to claim 11, characterized in that, The circuit structure of the first type of shift register is symmetrical to that of the second type of shift register.

14. The display panel according to claim 11, characterized in that, In the first direction, the distance between at least two partially adjacent first-type shift registers is equal to the distance between at least two partially adjacent second-type shift registers.

15. The display panel according to claim 11, characterized in that, At least some of the shift registers are not at a distance equal to the distance between them and the shift registers at their next higher level.

16. The display panel according to claim 9, characterized in that, The display area includes a first sub-area, a second sub-area, and a third sub-area distributed in the first direction, wherein the first sub-area and the third sub-area are respectively located on opposite sides of the second sub-area in the first direction; At least the first sub-region and / or the third sub-region includes the shift register group and the pixel circuit group arranged alternately in the first direction.

17. The display panel according to claim 16, characterized in that, The number of pixel circuits included in the pixel circuit group is the same as the number of shift registers included in the shift register group.

18. The display panel according to claim 17, characterized in that, The pixel circuit group includes two adjacent pixel circuit units in the first direction, and the shift register group includes two adjacent shift registers in the first direction.

19. A display device, characterized in that, Includes the display panel as described in any one of claims 1-18.

Images