Power semiconductor device and plastic packaging method thereof

Abstract

The invention relates to the technical field of power semiconductors, and discloses a power semiconductor device and a plastic packaging method. The power semiconductor device comprises a chip, a conducting strip and a plastic package body. The front surface of the chip is provided with a source and a grid; the conducting strip is fixed on the front face of the chip through a welding layer and comprises a source electrode conducting strip connected with the source electrode and a grid electrode conducting strip connected with the grid electrode, and the source electrode conducting strip comprises a source electrode conducting strip chip end located on the chip and a source electrode conducting strip pin end extending out of the chip. The sum of the thickness of the source electrode conducting strip chip end, the thickness of the welding layer and the thickness of the chip is equal to the thickness of the source electrode conducting strip pin end, and the grid electrode conducting strip comprises a grid electrode conducting strip chip end and a grid electrode conducting strip pin end far away from the chip. According to the power semiconductor device and the plastic packaging method provided by the invention, the plastic packaging process can be simplified, the plastic packaging efficiency is improved, the limitation of plastic packaging conditions is reduced, and the competitive advantage of products is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a power semiconductor device and a plastic packaging method thereof. Background Art

[0002] Power semiconductor devices are core components in power electronics technology. They are mainly used for the conversion, distribution, control and energy saving of electric energy. These devices are capable of handling high voltage and high current and are commonly used in power electronic devices such as power converters, inverters, motor drives, etc. The classification of power semiconductor devices can be carried out from multiple dimensions. For example, according to the control characteristics, they can be divided into uncontrolled devices (such as diodes), semi-controlled devices (such as thyristors) and fully controlled devices.

[0003] In existing power semiconductor devices, bonding wires are used to connect the chip and the pins. Power semiconductor devices connected by this bonding wire method have poor thermal performance, large plastic packaging volume, poor signal transmission quality, and low reliability, which in turn causes great mechanical damage to the power semiconductor devices and limited lifespan, and cannot meet the requirements of high reliability. As a new type of plastic packaging process that replaces the traditional wire bonding process, the conductive sheet bonding (ClipBond) process is increasingly used in power semiconductor devices and power semiconductor modules. Compared with the traditional wire bonding method, the plastic packaging using the conductive sheet bonding process improves the current carrying capacity and heat dissipation performance of the device, reduces the on-resistance and parasitic inductance of the device, and is an inevitable trend in the development of power semiconductor plastic packaging.

[0004] However, the power semiconductor devices currently produced using the conductive sheet bonding process have problems such as complex plastic packaging process, poor quality controllability, large plastic packaging volume, and serious delamination failure. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a power semiconductor device and a method for encapsulating the same, which can simplify the encapsulation process, improve the quality of the encapsulation, and reduce the volume of the encapsulation.

[0006] In order to solve the above technical problems, the embodiment of the present application provides a power semiconductor device, which includes a chip, a conductive sheet and a plastic package. The front of the chip has a source and a gate; the conductive sheet is fixed to the front of the chip through a welding layer, the conductive sheet includes a source conductive sheet connected to the source and a gate conductive sheet connected to the gate, the source conductive sheet and the gate conductive sheet are arranged one by one, the source conductive sheet includes a source conductive sheet chip end located on the chip and a source conductive sheet pin end extending outside the chip, the sum of the thickness of the source conductive sheet chip end, the thickness of the welding layer, and the thickness of the chip is equal to the thickness of the source conductive sheet pin end, the gate conductive sheet includes a gate conductive sheet chip end and a gate conductive sheet pin end away from the chip, the sum of the thickness of the gate conductive sheet chip end, the thickness of the welding layer, and the thickness of the chip is equal to the thickness of the gate conductive sheet pin end, and a through hole and a groove are arranged in the middle of the source conductive sheet chip end; the plastic package covers the front of the chip and all or part of the conductive sheet.

[0007] The embodiment of the present application also provides a method for plastic packaging of a power semiconductor device, comprising the following steps:

[0008] S11: metallizing the front and back sides of the wafer;

[0009] S12: attaching a carrier film to the back of the wafer, and then cutting the wafer to form a plurality of chips arranged in an array;

[0010] S13: Printing welding material on the front side of the chip;

[0011] S14: manufacturing a plurality of conductive sheets;

[0012] S15: placing a plurality of conductive sheets at corresponding positions of each chip and performing reflow soldering;

[0013] S16: Plastic encapsulate all chips as a whole;

[0014] S17: Cut the entire plastic package to form a power semiconductor device.

[0015] The power semiconductor device and its plastic encapsulation method provided by the embodiment of the present application use a conductive sheet to replace the original bonding wire, and set multiple through holes and multiple irregular grooves on the conductive sheet, so that the conductive sheet and the chip are fixed more firmly, avoiding the occurrence of delamination failure. By attaching an integral carrier film to the back of the wafer, the plastic encapsulation process is always carried out on the integral carrier film, and a lead frame is not required as a substrate, which greatly simplifies the plastic encapsulation process, improves the plastic encapsulation efficiency, reduces the restrictions on plastic encapsulation conditions, improves the product's competitive advantage, and improves the plastic encapsulation quality and product performance.

[0016] In some embodiments, a plurality of notches are disposed on the side of the source conductive sheet chip end, and / or a plurality of grooves are disposed on the front and back sides of the conductive sheet, and the grooves are symmetrically distributed on both sides of the front and back sides of the conductive sheet.

[0017] In some embodiments, the back side of the chip is exposed outside the plastic package.

[0018] In some embodiments, a side of the gate conductive sheet lead end away from the chip and a side of the source conductive sheet lead end away from the chip are both exposed outside the plastic package.

[0019] In some embodiments, the sides of the gate conductive sheet lead end and the source conductive sheet lead end that are away from each other are exposed outside the plastic package.

[0020] In some embodiments, a lead frame is further provided on the back of the chip, and the lead frame is provided with multiple pins. The gate conductive sheet pin end and the source conductive sheet pin end are electrically connected to the corresponding pins respectively. The side of the lead frame facing away from the chip is exposed outside the plastic package, and the side of the multiple pins away from the chip are exposed outside the plastic package and are used to conduct the chip signals, and the conductive sheets are all covered inside the plastic package.

[0021] In some embodiments, before placing the plurality of conductive sheets at corresponding positions of each chip, all gate conductive sheet lead ends are connected to another source conductive sheet lead end adjacent to the left and right of the gate conductive sheet as a whole.

[0022] In some embodiments, after all gate conductive sheet pin ends are connected to another adjacent source conductive sheet pin end on the left and right as a whole, the connection points between the gate conductive sheet pin ends and another adjacent source conductive sheet pin ends on the left and right on the same column of chips are connected in series as a whole through copper bars, and the width of the copper bars is smaller than the diameter of the cutting knife.

[0023] In some embodiments, when metallizing the back side of the wafer, titanium, nickel, and silver metal layers are sequentially plated on the back side of the wafer.

[0024] In some embodiments, when printing the soldering material on the front side of the chip, a metal stencil is used to print the soldering material.

[0025] In some embodiments, when manufacturing a plurality of conductive sheets, a layer of tin is electroplated on the backsides of all gate conductive sheet pin ends and all source conductive sheet pin ends. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0027] Figure 1 is a schematic diagram of the side structure of a power semiconductor device provided by some embodiments of the present application;

[0028] Figure 2 is a schematic structural diagram of a conductive sheet type 1 in a power semiconductor device provided in some embodiments of the present application;

[0029] Figure 3 The power semiconductor device provided by some embodiments of the present application Figure 2 Schematic diagram of the cross-section structure at AA in the middle;

[0030] Figure 4 is a schematic structural diagram of a conductive sheet type 2 in a power semiconductor device provided in some embodiments of the present application;

[0031] Figure 5 It is a schematic diagram of a structure in which a conductive sheet of type 1 is fixed to a chip during the manufacturing process of a power semiconductor device provided by some embodiments of the present application;

[0032] Figure 6 It is a schematic diagram of a structure in which a conductive sheet of type 2 is fixed to a chip during the manufacturing process of a power semiconductor device provided by some embodiments of the present application;

[0033] Figure 7 It is a schematic diagram of the structure in which a conductive sheet is welded to a lead frame during the manufacturing process of a power semiconductor device provided in some embodiments of the present application;

[0034] Figure 8 is a schematic diagram of the side structure of a power semiconductor device provided in some embodiments of the present application when it has a lead frame;

[0035] Fig. 9 is a flow chart of a plastic packaging process of a power semiconductor device provided in some embodiments of the present application;

[0036] Fig.10 It is a schematic diagram of the structure of a power semiconductor device after wafer metallization and cutting during plastic packaging provided by some embodiments of the present application;

[0037] Fig.11 It is a schematic diagram of the structure of a chip after printing welding material during the plastic packaging process of a power semiconductor device provided in some embodiments of the present application;

[0038] Fig.12 It is a schematic diagram of the structure after welding when the conductive sheet is type 1 during the plastic packaging process of the power semiconductor device provided in some embodiments of the present application;

[0039] Fig.13 It is a schematic structural diagram of a power semiconductor device provided in some embodiments of the present application, when the conductive sheet of the chip is type 2, after the chip is integrally plastic-sealed and cut;

[0040] Fig.14 This is a product appearance diagram when the conductive sheet in the power semiconductor device provided by some embodiments of the present application is type 1;

[0041] Fig.15 This is a product appearance diagram when the conductive sheet in the power semiconductor device provided in some embodiments of the present application is type 2.

[0042] Explanation of the reference numerals: 11-chip; 111-source; 112-gate; 12-conductive sheet; 121-source conductive sheet; 1211-source conductive sheet chip end; 1212-through hole; 1213-groove; 1214-notch; 1215-source conductive sheet pin end; 122-gate conductive sheet; 1221-gate conductive sheet chip end; 1222-gate conductive sheet pin end; 13-plastic package; 14-lead frame; 15-pin; 16-wafer; 17-soldering layer; 18-copper bar. DETAILED DESCRIPTION

[0043] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in each embodiment of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not constitute any limitation, and the various embodiments can be combined with each other and referenced to each other without contradiction.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0045] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0046] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0047] Power semiconductor devices are core components in power electronics technology. They are mainly used for the conversion, distribution, control and energy saving of electric energy. These devices are capable of handling high voltage and high current and are commonly used in power electronic devices such as power converters, inverters, motor drives, etc. The classification of power semiconductor devices can be carried out from multiple dimensions. For example, according to the control characteristics, they can be divided into uncontrolled devices (such as diodes), semi-controlled devices (such as thyristors) and fully controlled devices.

[0048] In existing power semiconductor devices, bonding wires are used to connect the chip and the pins. Power semiconductor devices connected by this bonding wire method have poor thermal performance, large plastic packaging volume, poor signal transmission quality, and low reliability, which in turn causes great mechanical damage to the power semiconductor devices and limited lifespan, and cannot meet the requirements of high reliability. As a new type of plastic packaging process that replaces the traditional wire bonding process, the conductive sheet bonding (ClipBond) process is increasingly used in power semiconductor devices and power semiconductor modules. Compared with the traditional wire bonding method, the plastic packaging using the conductive sheet bonding process improves the current carrying capacity and heat dissipation performance of the device, reduces the on-resistance and parasitic inductance of the device, and is an inevitable trend in the development of power semiconductor plastic packaging.

[0049] However, the power semiconductor devices currently produced using the conductive sheet bonding process have problems such as complex plastic packaging process, poor quality controllability, large plastic packaging volume, and serious delamination failure.

[0050] In order to solve the problems of complex plastic encapsulation process, poor quality controllability and serious delamination failure of existing power semiconductor devices. Some embodiments of the present application provide a power semiconductor device, which uses a conductive sheet instead of the original bonding wire, and sets a plurality of through holes and a plurality of irregularly shaped grooves on the conductive sheet, so that the conductive sheet and the chip are fixed more firmly, and the bonding between the conductive sheet and the molding material is strengthened, and the probability of delamination failure is reduced. By attaching an integral carrier film to the back of the wafer, the plastic encapsulation process of the power semiconductor device is always carried out on the integral carrier film, and a lead frame is not required as a substrate, which greatly simplifies the plastic encapsulation process, improves the plastic encapsulation efficiency, reduces the restrictions on plastic encapsulation conditions, improves the competitive advantage of the product, and improves the plastic encapsulation quality and product performance.

[0051] Combine the following Figures 1 to 15 The power semiconductor device and the plastic packaging method thereof provided in some embodiments of the present application are described.

[0052] Some embodiments of the present application provide a power semiconductor device, including a chip 11, a conductive sheet 12, and a plastic package 13. The front of the chip 11 has a source 111 and a gate 112; the conductive sheet 12 is fixed to the front of the chip 11 through a welding layer, and the conductive sheet 12 includes a source conductive sheet 121 connected to the source 111 and a gate conductive sheet 122 connected to the gate 112. The source conductive sheet 121 and the gate conductive sheet 122 are arranged in a one-to-one correspondence. The source conductive sheet 121 includes a source conductive sheet chip end 1211 located on the chip 11 and a source conductive sheet pin end 1215 extending outside the chip 11. The thickness of the source conductive sheet chip end 1211 and the thickness of the welding layer 17 are The sum of the thickness of the chip 11 is equal to the thickness of the source conductive sheet pin end 1215, the gate conductive sheet 122 includes a gate conductive sheet chip end 1221 and a gate conductive sheet pin end 1222 away from the chip 11, the sum of the thickness of the gate conductive sheet chip end 1221, the thickness of the welding layer 17 and the thickness of the chip 11 is equal to the thickness of the gate conductive sheet pin end 1222, and a through hole 1212 and a groove 1213 are provided in the middle position of the source conductive sheet chip end 1211; the plastic package 13 covers the front side of the chip 11 and all or part of the conductive sheet 12.

[0053] Specifically, Figure 1 , Figure 2 and Figure 3As shown, the portion of the front side of the wafer 16 with an aluminum metal layer is the source 111 or gate 112 of the chip 11. The welding layer 17 is formed of welding material, usually solder paste, or other metal materials that meet the welding requirements of power semiconductor devices. The welding material needs to be conductive and can transmit the signal of the chip 11. The welding layer 17 is formed by the reflow operation so that the conductive sheet 12 is fixed and electrically connected to the chip 11. The source 111 plays the role of inputting signals and outputting load currents of the chip 11, and the gate 112 is the control electrode of the chip 11, which controls the conduction and cutoff by controlling the voltage of the gate 112. The conductive sheet 12 includes two separate parts, a source conductive sheet 121 and a gate conductive sheet 122. The source 111 of each chip 11 corresponds to a source conductive sheet 121, and the gate 112 of each chip 11 corresponds to a gate conductive sheet 122. The conductive sheet 12 is divided into a pin end and a chip end. The end of the conductive sheet 12 fixed to the chip 11 is the chip end, and the end away from the chip 11 is the pin end. In a power semiconductor device with a lead frame 14, the pin end of the conductive sheet 12 is connected to the pin 15 of the lead frame 14, and the conductive sheet 12 is completely covered in the plastic package 13. In a power semiconductor device without a lead frame 14, the pin end of the conductive sheet 12 is completely exposed outside the plastic package 13 on the side away from the chip 11. Whether it is the source conductive sheet 121 or the gate conductive sheet 122, the sum of the thickness of the chip end, the thickness of the welding layer 17, and the thickness of the chip 11 is equal to the thickness of the pin end of the conductive sheet 12, that is, the back of the pin end of the conductive sheet 12 and the back of the chip 11 are in the same horizontal plane during the plastic package, ensuring the quality and beauty of the plastic package. A through hole 1212 is provided in the middle position of the chip end 1211 of the source conductive sheet, and there can be multiple through holes 1212, which is conducive to the discharge of air between the conductive sheet 12 and the chip 11 during reflow soldering, and prevents the solder layer 17 from being too large to cause poor heat dissipation and increase in on-resistance. The groove 1213 can be a plurality of irregular shapes. The groove 1213 is provided for filling with welding materials or epoxy resin during plastic encapsulation, so that the welding and plastic encapsulation are more solid, the displacement of the conductive sheet 12 during the reflow soldering process and the stratification between the plastic encapsulation material and the conductive sheet 12 are reduced, the plastic encapsulation quality is improved, and the performance and competitive advantage of the power device products are enhanced.

[0054] In addition, when the power device is encapsulated, the front and side surfaces of the chip 11 are completely covered in the encapsulation body 13, including all or part of the conductive sheet 12. Figure 8 As shown, when the power device has a lead frame structure 14, the front and side surfaces of the chip 11 are covered in the plastic package 13, and the back surface of the chip 11 is mounted on the lead frame 14 and is also covered in the plastic package 13. At this time, the conductive sheet 12 is completely covered in the plastic package 13. Figure 1As shown, when the power device does not have a lead frame 14 structure, the front and side surfaces of the chip 11 are covered in the plastic package 13, and the back surface of the chip 11 is exposed outside the plastic package 13. At this time, the front surface of the conductive sheet 12 is covered in the plastic package 13, and the side and back surfaces of the conductive sheet 12 are exposed outside the plastic package 13.

[0055] Some embodiments of the present application also provide a plastic package for a semiconductor device, such as Fig. 9 As shown, the plastic packaging method includes the following steps:

[0056] S11: Metallizing the front and back sides of the wafer 16.

[0057] Specifically, the portion of the front side of the wafer 16 with the aluminum metal layer is the source 111 and the gate 112 of the chip 11. Metallizing the front side of the wafer 16 means coating the source 111 and the gate 112 with titanium / nickel / silver (Ti / Ni / Ag) by sputtering, or coating the source 111 and the gate 112 with nickel / palladium / gold (Ni / Pd / Au) by chemical plating, in order to enhance the surface solderability and facilitate the subsequent mounting of the conductive sheet 12 on the chip 11 with solder paste. Fig.10 As shown, the white parts in the source 111111 and the gate 112112 are the metal parts of the wafer 16 after metallization. After the front side is metallized, the back side of the wafer 16 is ground and thinned to make the thickness of the wafer 16 reach the thickness required by the design, and then three layers of metal are evaporated on the back side of the wafer 16, which are titanium, nickel, and silver in sequence. The purpose of thinning and metallizing the back side of the wafer 16 is to reduce the contact resistance of the back drain. When the power device has a lead frame 14 structure, the front and back sides of the wafer 16 also need to be metallized, and the steps and functions are similar to those described above.

[0058] S12: A carrier film (not shown in the figure because it is a transparent film) is attached to the back of the wafer 16, and then the wafer 16 is cut to form a plurality of chips 11 arranged in an array.

[0059] Specifically, after step S11, an integral carrier film is attached to the back of the wafer 16, and the carrier film may be a UV (Ultraviolet) film. The UV film is generally transparent, which is convenient for checking the back of the wafer 16 during processing. The UV film is a thin film material that has been treated with ultraviolet light curing. This film can be irradiated with ultraviolet rays to rapidly cure the coating on its surface, thereby increasing the hardness and wear resistance of the film. The viscosity of the UV film can be adjusted as needed to meet different process requirements. The high-viscosity UV film has a higher viscosity before UV irradiation, while the low-viscosity UV film has a significantly reduced peeling degree after UV irradiation, making it easy to take and place the chip 11 without residual glue. Ultraviolet light irradiation can be set to increase or decrease its viscosity by changing the irradiation time and irradiation intensity. During the cutting process, it is necessary to prevent water vapor and pollutants from entering and reduce the vibration effect on the chip 11, so it is necessary to maintain a strong adhesion between the film and the back of the chip 11. The wafer 16 is then cut according to the grain size and layout using a high-speed rotating blade. After cutting, the wafer 16 is as follows Fig.10 As shown, each crystal grain forms an array-arranged chip 11. When cutting, the cutting blade preferably only cuts through the wafer 16, without cutting through the carrier film, so as to always ensure the array arrangement of the chips 11, which is convenient for subsequent overall operation. When the power device has a lead frame 14 structure, the carrier film is completely cut through, and then the carrier film is removed to form a single chip 11.

[0060] S13: Printing soldering material on the front side of the chip 11 .

[0061] Specifically, according to the size of the source 111 and gate 112 pads of the wafer 16 and the single chip 11, a metal mesh (referred to as steel mesh) and reserved holes for printing welding materials are designed. Align the reserved holes of the mesh with the source 111 and gate 112 pads of the chip 11, and print a certain thickness of welding material. Or directly use the dispensing method to apply the welding material on the surface of the wafer 16 pad. When the power device has a lead frame 14 structure, after the chip 11 is separated from the wafer 16, it is mounted one by one on the base island of the lead frame 14, and then the welding material is printed or applied on the corresponding welding area on the surface of the chip 11. Because the embodiment of the present application does not require a lead frame 14, the steps of separating the chip 11 from the wafer 16 and then mounting it on the base island are omitted, and the carrying film is directly used as a carrier to print the welding material on the entire wafer 16, which simplifies the plastic encapsulation process and improves the plastic encapsulation efficiency.

[0062] S14: manufacturing a plurality of conductive sheets 12.

[0063] Specifically, the conductive sheet 12 is manufactured according to the structural requirements of the conductive sheet 12 design, and the number of the conductive sheets 12 needs to meet the number of chips 11 after cutting in step S12. The substrate of the conductive sheet 12 is made of high-purity alloy material (C19120), which has high electrical and thermal conductivity. There are two types of conductive sheets 12 in the specific manufacturing process. Type 1 of the conductive sheet 12 is: Figure 2 As shown, U-shaped notches 1214 are designed around the conductive sheet 12, and a through hole 1212 is designed in the middle to facilitate air discharge during reflow soldering, and prevent the soldering layer 17 from having too large voids, resulting in poor heat dissipation and increased on-resistance; grooves 1213 (not hollowed out) are designed on the lower and upper surfaces of the conductive sheet 12, which are used to fill and lock soldering materials and epoxy resin molding compounds, respectively, to reduce the offset of the conductive sheet 12 during reflow soldering and the delamination between the molding compound and the conductive sheet 12. The back of the pin end of the conductive sheet 12 is pre-plated with 99.5% tin. Conductive sheet 12 type 2 is: Figure 4 and Figure 6 As shown, on the basis of type 1 of the conductive sheet 12, the gate conductive sheet pin end 1222 is connected to another source conductive sheet pin end 1215 adjacent to the left and right, so that the conductive sheet 12 becomes an integrated structure design, and further, copper bars 18 can be added to connect the conductive sheets 12 in the same column to form an integral structure. The design of type 2 can greatly improve the efficiency of the bonding operation, and the copper bars 18 connected in the middle can be cut and separated later. The diameter of the copper bar 18 is smaller than the diameter of the cutting knife, and the copper bar 18 can be completely broken by the cutting knife to eliminate the influence of the copper bar 18 on the signal transmission of the chip 11.

[0064] S15: placing a plurality of conductive sheets 12 at corresponding positions of each chip 11 and performing reflow soldering.

[0065] Specifically, when the conductive sheet 12 is welded in a structure of type 1, the source conductive sheet 121 and the gate conductive sheet 122 are separated and need to be bonded in two steps. They need to be placed in corresponding positions of the chip 11 respectively. After all are placed, they are fixed by reflow soldering. When the conductive sheet 12 is welded in a structure of type 2, such as Figure 6 and Figure 7As shown, the same column of source conductive sheets 121 on the left side are connected in series through copper bars 18; the same column of gate conductive sheets 122 on the right side are connected in series through copper bars 18; the other middle column of gate conductive sheet pin ends 1222 are connected to the other adjacent source conductive sheet pin ends 1215 to form a whole, and the conductive sheets 12 in the same column are connected to each other through copper bars 18 at the middle position between the source conductive sheet pin ends 1215 and the gate conductive sheet pin ends 1222 to form an integral structure, so that only the integral conductive sheet 12 structure connected by copper bars 18 needs to be bonded to the corresponding position of the chip 11, which greatly improves the bonding efficiency and the speed of plastic sealing. The printed welding material is used to mount the conductive sheet 12 on the source 111 pad and the gate 112 pad of the chip 11, and then fixed by reflow soldering. The welding material is usually solder paste, but can also be other metal materials that meet the welding requirements of power semiconductor devices. The welding material needs to be conductive and able to transmit the signal of the chip 11. The welding material is formed into a welding layer 17 through the reflow operation so that the conductive sheet 12 is fixed and electrically connected to the chip 11.

[0066] S16: Plastic-encapsulate all the chips 11 as a whole.

[0067] Specifically, after the conductive sheet 12 is reflow-soldered, all the chips 11 are plastic-sealed on the molding equipment, and epoxy resin molding compound is poured, and the epoxy resin molding compound is solidified to form an overall plastic-sealed structure. Because the back of the wafer 16 is affixed with a carrier film, the plastic-sealing compound will not cover the back of the wafer 16 and the back of the pin end of the conductive sheet 12. The back of the wafer 16 can be used as the drain of the chip 11, and the pin end of the conductive sheet 12 can be used as a contact to conduct the signal of the chip 11. At this time, the back of the chip 11 is exposed outside the plastic-sealed body 13.

[0068] S17: cutting the entire plastic package 13 to form a power semiconductor device.

[0069] Specifically, at the same position as the cutting in step S12, a cutting knife is used to cut the plastic package body 13 after the overall plastic packaging. The UV film viscosity is reduced by ultraviolet light irradiation, so that it is separated from the metal layer on the back of the power semiconductor device, and becomes a single power semiconductor device. If a conductive sheet 12 of type 1 is used, the thickness of the cutting knife at this time is roughly the same as the cutting knife in step S12. If a conductive sheet 12 of type 2 is used, the width of the cutting knife is larger than the diameter of the copper bar 18, and the copper bar 18 can be completely broken by the cutting knife, eliminating the influence of the copper bar 18 on the signal transmission of the chip 11. Fig.13It is a schematic diagram after the cutting knife cuts the wafer 16 again and before the UV film is removed. In the figure, the upper black part is not plastic-encapsulated, the middle black line is the cutting opening left by the cutting knife, and the side is the exposed source conductive sheet pin end 1215 and gate conductive sheet pin end 1222. When the power device has a lead frame 14 structure, the lead frame 14 needs to be cut through together to form a power device product.

[0070] The above-mentioned encapsulation method, by attaching an integral carrier film to the back of the wafer 16, the encapsulation process of the power semiconductor device is always carried out on the integral carrier film, and the lead frame 14 is not required as a substrate, which greatly simplifies the encapsulation process, improves the efficiency of the encapsulation, reduces the restrictions on the encapsulation conditions, improves the competitive advantage of the product, and improves the quality of the encapsulation and product performance. In power devices that require a lead frame 14 as a substrate, conventional encapsulation methods can be used for encapsulation, and the above-mentioned conductive sheet 12 is used to replace the original bonding wire. A plurality of through holes 1212 and a plurality of irregularly shaped grooves 1213 are provided on the conductive sheet 12, so that the conductive sheet 12 and the chip 11 are fixed more firmly, the bonding between the conductive sheet 12 and the molding compound is strengthened, and the occurrence of delamination failure is avoided. When the power device has a lead frame 14 structure, the carrier film of step S12 is completely cut through, and then the carrier film is removed to form a single core 11. The single chip 11 is attached to the lead frame 14 with solder paste, the conductive sheet 12 is placed, reflow soldering is performed, and finally the lead frame 14 is cut through together to form a power device product.

[0071] In some embodiments of the present application, a plurality of notches 1214 are provided on the side of the source conductive sheet chip end 1211, and / or a plurality of grooves 1213 are provided on the front and back sides of the conductive sheet 12, and the grooves 1213 are symmetrically distributed on both sides of the front and back sides of the conductive sheet 12.

[0072] It should be noted that a plurality of U-shaped notches 1214 are provided on the side of the chip end 1211 of the source conductive sheet, which provide a channel for the gas generated during the reflow process to be discharged, increase the contact area between the conductive sheet 12 and the solder paste, and increase the locking strength between the conductive sheet 12 and the epoxy molding compound. On the lower surface and upper surface of the conductive sheet 12 (i.e., symmetrically distributed on both sides of the front and back of the conductive sheet 12), non-hollowed grooves 1213 are designed. The grooves 1213 on the lower surface of the conductive sheet 12 are used for filling and locking the welding material to reduce the displacement of the conductive sheet 12 during the reflow process. The grooves 1213 on the upper surface of the conductive sheet 12 are used for filling and locking the epoxy molding compound to reduce the risk of delamination failure of the epoxy molding compound and between the molding compound and the conductive sheet 12.

[0073] In some embodiments of the present application, the back side of the chip 11 is exposed outside the plastic package 13 .

[0074] It should be noted that if Figure 1 As shown, when the power device does not have a lead frame, the back of the chip 11 is flush with the back of the plastic package 13. During the plastic packaging process, the back of the chip 11 is covered with a carrier film. During the plastic packaging, the carrier film blocks the plastic packaging material from entering the back of the chip 11. In the final power device product, the back of the chip 11 is exposed outside the plastic package 13.

[0075] In some embodiments of the present application, a side of the gate conductive sheet pin end 1222 away from the chip 11 and a side of the source conductive sheet pin end 1215 away from the chip 11 are both exposed outside the plastic package 13 .

[0076] It should be noted that if Fig.14 and Fig.15 As shown, in a semiconductor power device without a lead frame 14 structure, the gate conductive sheet pin end 1222 and the source conductive sheet pin end 1215 are both exposed outside the plastic package 13 on two sides away from the chip 11, and the back sides of the two conductive sheet 12 pin ends are also exposed outside the plastic package 13. This large-area exposed structure is conducive to the stability of the transmitted signal.

[0077] In some embodiments of the present application, the sides of the gate conductive sheet pin end 1222 and the source conductive sheet pin end 1215 that are away from each other are both exposed outside the plastic package 13 .

[0078] It should be noted that if Fig.15 As shown, when the conductive sheet 12 is type 2, since the copper strip 18 is used to connect the conductive sheet 12 into a whole, the conductive sheet 12 is cut into pieces in the power device product. Fig.15 The left and right sides of the circuit will inevitably leak out the sides of the gate conductive sheet pin end 1222 and the source conductive sheet pin end 1215. This structure increases the signal transmission path on the one hand, facilitating the stability of the transmitted signal; on the other hand, it is conducive to heat dissipation.

[0079] In some embodiments of the present application, a lead frame 14 is further provided on the back side of the chip 11, and the lead frame 14 is provided with a plurality of pins 15. The gate conductive sheet pin end 1222 and the source conductive sheet pin end 1215 are electrically connected to the corresponding pins 15 respectively. The side of the lead frame 14 facing away from the chip 11 is exposed outside the plastic package 13, and the side of the plurality of pins 15 away from the chip 11 is exposed outside the plastic package 13 and is used to conduct the signal of the chip 11. The conductive sheet 12 is completely covered inside the plastic package 13.

[0080] It should be noted that the conductive sheet 12 designed in the embodiment of the present application is mainly used in a structure without a lead frame 14. When there is a lead frame 14, the conductive sheet 12 can also be used. At this time, it is necessary to first separate the chip 11 from the wafer 16, and then mount it one by one on the base island of the lead frame 14, and then print or apply welding material on the corresponding welding area on the surface of the chip 11, and then fix the conductive sheet 12 on the chip 11. The lead frame 14 has a plurality of pins 15, and the pin ends of the conductive sheet 12 are electrically connected to the corresponding pins 15. The back of the lead frame 14 is exposed outside the plastic package 13, and the conductive sheet 12 is completely covered inside the plastic package 13. The pins 15 of the lead frame 14 conduct the signals of the chip 11.

[0081] In some embodiments of the present application, before cutting the encapsulated wafer 16 or after cutting the encapsulated wafer 16 and before removing the UV film, the encapsulated wafer 16 is lasered to engrave a seal on the front side of the encapsulated body 13 .

[0082] Specifically, when the power device adopts the traditional plastic packaging that requires the lead frame 14, the entire lead frame 14 must be cut after the laser to separate the products. The step method of the present application is mainly used for advanced plastic packaging, such as WLCSP (Wafer-Level Chip Scale Packaging). The laser step can be placed before or after cutting, and the operation sequence requirements are more flexible. The seal generally has the trademark LOGO of the chip design company, the product name and the production date, or there will be some special numbers or letter codes to distinguish batches and other information.

[0083] In some embodiments of the present application, before placing a plurality of conductive sheets 12 at corresponding positions of each chip 11 , all gate conductive sheet pin ends 1222 are connected to another source conductive sheet pin end 1215 adjacent to the left and right sides as a whole.

[0084] It should be noted that after the gate conductive sheet pin end 1222 is connected to another adjacent source conductive sheet pin end 1215 as a whole, the bonding of the conductive sheet 12 can be completed in one step, and there is no need to bond the source conductive sheet 121 and the gate conductive sheet 122 separately in two steps (such as Figure 5 As shown, two-step bonding is required, which improves the efficiency of the bonding operation. At this time, the connection between the pin ends of the conductive sheet 12 needs to be cut off through a subsequent cutting step.

[0085] In some embodiments of the present application, after all gate conductive sheet pin ends 1222 are connected to another adjacent source conductive sheet pin end 1215 on the left and right as a whole, the connection points between the gate conductive sheet pin end 1222 and another adjacent source conductive sheet pin end 1215 on the same column of chips 11 are connected in series as a whole through copper bars 18, and the diameter of the copper bars 18 is smaller than the diameter of the cutting knife.

[0086] That is to say, the conductive sheet 12 of type 2 is used for bonding, and the whole row is bonded in one step, which greatly improves the efficiency of the bonding operation, and then the copper strips 18 connected in the middle are cut and separated. The width of the copper strips 18 is smaller than the diameter of the cutting knife, and the copper strips 18 can be completely broken by the cutting knife, eliminating the influence of the copper strips 18 on the signal transmission of the chip 11.

[0087] In some embodiments of the present application, when metallizing the back side of the wafer 16 , titanium, nickel, and silver metal layers are sequentially plated on the back side of the wafer 16 .

[0088] It should be noted that the main function of the silver layer on the back of the chip 11 is to make the contact electrode form a good ohmic contact. The chip 11 after back metallization has the characteristics of small saturation voltage drop, reliable welding, small on-state source-drain resistance, good heat dissipation, low working energy consumption, etc., and is commonly used in small and medium power transistors. Titanium (Ti) and silicon (Si) on the chip 11 can be well combined, but the resistance is relatively high. Nickel (Ni) is used as the middle bonding layer, and the outermost silver-plated (Ag) layer can also protect the nickel (Ni) layer.

[0089] In some embodiments of the present application, when printing the soldering material on the front side of the chip 11 , a metal mesh is used to print the soldering material.

[0090] It should be noted that before printing, a metal mesh (referred to as steel mesh) and reserved holes that conform to the overall chip 11 layout can be designed, and the reserved hole position is the position where the welding material is printed. Align the reserved holes of the mesh with the source 111 and gate 112 pads of the chip 11, and print a certain thickness of welding material. The welding material can be printed by metal mesh printing, or by the traditional solder paste method. Both can be achieved. The metal mesh printing method has higher precision and efficiency, and also has high requirements on the equipment process capability.

[0091] In some embodiments of the present application, when manufacturing a plurality of conductive sheets 12 , the back surfaces of all gate conductive sheet pin ends 1222 and all source conductive sheet pin ends 1215 are electroplated with a layer of tin.

[0092] That is, a layer of tin is electroplated on the side where all gate conductive sheet pin ends 1222 are flush with the back side of the chip 11 and the side where all source conductive sheet pin ends 1215 are flush with the back side of the chip 11. Electroplating can form a protective metal layer on the pin ends of the conductive sheet 12 to improve its corrosion resistance and mechanical strength, and can also improve the electrical properties of the conductive sheet 12 and extend its service life. Metallic tin is a preferred metal.

[0093] The existing plastic encapsulation technology requires that the chip 11 be set on the lead frame 14, and the base island of the lead frame 14 needs to be printed with solder paste and other welding materials. The chip 11 is welded to the lead frame 14 through the welding material. The power semiconductor device provided in the embodiment of the present application is pasted with an overall carrier film on the back of the wafer 16. The plastic encapsulation process of the power semiconductor device is always carried out on the overall carrier film, and the lead 15 frame is not required as a substrate, which greatly simplifies the plastic encapsulation process and improves the plastic encapsulation efficiency. At the same time, because there is no need to purchase an expensive lead frame 14, the product processing cost is effectively reduced, and there is no need to consider the influencing factors of the lead frame 14. It is only necessary to consider the matching of the conductive sheet 12 design and the chip 11 design, which greatly reduces the restrictions of the conductive sheet 12 bonding process on the plastic encapsulation. Since there is no need for the lead frame 14 as a carrier, it is only necessary to control the offset of the conductive sheet 12 during the reflow soldering process, thereby avoiding the influence of the offset of the lead frame 14 on the delamination failure of the power semiconductor device. By using the conductive sheet 12 to replace the original bonding wire, a plurality of through holes 1212, notches 1214 and a plurality of irregular grooves 1213 are provided on the conductive sheet 12, so that the conductive sheet 12 and the chip 11 are more firmly fixed, the occurrence of delamination failure is avoided, and the quality of the plastic package is improved. The overall design of the conductive sheet 12 with an integrated structure and multiple columns greatly improves the bonding efficiency and effectively reduces the product processing cycle.

[0094] In addition, the design of directly exposing the metal layer on the back of the chip 11 as a drain outside the plastic package further reduces the influence of the plastic package parasitic parameters and improves the heat dissipation and electrical performance of the product. For the traditional plastic package of the same type, taking the more efficient QFN (Quad Flat No-leads Package) as an example, its plastic package efficiency (the ratio of chip area to plastic package area tends to 1 for the highest efficiency) is 0.3 to 0.4. The size of the chip 11 provided in the embodiment of the present application is 4mm*4mm*0.25mm, and the area of ​​the chip 11 is 16mm 2 ; Plastic sealing size is 4.5mm*5mm*0.85mm, plastic sealing area is 22.5mm 2 , its plastic packaging efficiency reaches 0.71, which is greatly improved. Therefore, when the assembly space is limited and the product performance requirements are high, the power semiconductor device provided by the embodiment of the present application is smaller in size and lower in cost.

[0095] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A power semiconductor device, characterized in that: include: A chip, wherein the front side of the chip has a source and a gate; A conductive sheet fixed to the front of the chip through a welding layer, the conductive sheet comprising a source conductive sheet connected to the source and a gate conductive sheet connected to the gate, the source conductive sheet comprising a source conductive sheet chip end located on the chip and a source conductive sheet pin end extending outside the chip, the sum of the thickness of the source conductive sheet chip end, the thickness of the welding layer, and the thickness of the chip is equal to the thickness of the source conductive sheet pin end, the gate conductive sheet comprising a gate conductive sheet chip end and a gate conductive sheet pin end away from the chip, the sum of the thickness of the gate conductive sheet chip end, the thickness of the welding layer, and the thickness of the chip is equal to the thickness of the gate conductive sheet pin end, and a through hole and a groove are provided in the middle of the source conductive sheet chip end; The plastic package covers the front surface of the chip and all or part of the conductive sheet.

2. The power semiconductor device according to claim 1, characterized in that: The side edge of the source electrode conductive sheet chip end is provided with a plurality of notches; and / or, A plurality of the grooves are disposed on the front and back sides of the conductive sheet, and the grooves are symmetrically distributed on both sides of the front and back sides of the conductive sheet.

3. The power semiconductor device according to claim 1, characterized in that: The back side of the chip is exposed outside the plastic package.

4. The power semiconductor device according to claim 1, characterized in that: The side of the gate conductive sheet lead end away from the chip and the side of the source conductive sheet lead end away from the chip are both exposed outside the plastic package.

5. The power semiconductor device according to claim 4, characterized in that: The sides of the gate conductive sheet pin end and the source conductive sheet pin end that are away from each other are both exposed outside the plastic package.

6. The power semiconductor device according to claim 1, characterized in that: A lead frame is also provided on the back of the chip, and the lead frame is provided with a plurality of pins. The gate conductive sheet pin end and the source conductive sheet pin end are electrically connected to the corresponding pins respectively. The side of the lead frame facing away from the chip is exposed outside the plastic package, and the sides of the plurality of pins away from the chip are all exposed outside the plastic package and are used to conduct the signals of the chip. The conductive sheets are all covered inside the plastic package.

7. A method for plastic packaging of a power semiconductor device, characterized in that: The plastic encapsulation method is used for plastic encapsulating the semiconductor device according to any one of claims 1 to 6, and the plastic encapsulation method comprises the following steps: Metallizing the front and back sides of the wafer; A carrier film is attached to the back of the wafer, and then the wafer is cut to form a plurality of chips arranged in an array; Printing welding material on the front side of the chip; manufacturing a plurality of the conductive sheets; Placing a plurality of the conductive sheets at corresponding positions of each chip and performing reflow soldering; Performing overall plastic sealing on all the chips; The whole plastic package is cut to form the power semiconductor device.

8. The method for plastic packaging of a power semiconductor device according to claim 7, characterized in that: Before placing the plurality of conductive sheets at corresponding positions of each chip, all the gate conductive sheet lead ends are connected to another source conductive sheet lead end adjacent to the left and right sides as a whole.

9. The method for plastic packaging of a power semiconductor device according to claim 8, characterized in that: After all the gate conductive sheet pin ends are connected to the other adjacent source conductive sheet pin ends on the left and right as a whole, the connection points between the gate conductive sheet pin ends and the other adjacent source conductive sheet pin ends on the left and right on the same column of the chips are connected in series into a whole through copper bars, and the width of the copper bars is smaller than the diameter of the cutting knife.

10. The method for plastic packaging of a power semiconductor device according to claim 7, characterized in that: When manufacturing a plurality of the conductive sheets, a layer of tin is electroplated on the backsides of all the gate conductive sheet pin ends and all the source conductive sheet pin ends.

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