Ga2o3 field effect transistor based on heterojunction hole super injection and preparation method thereof

Abstract

The application discloses a gallium oxide field effect transistor based on a heterojunction hole super-injection and a preparation method thereof, and solves the problem of small current density of the gallium oxide field effect transistor. The P-type heterostructure region is additionally arranged, the Ga2O3 epitaxial layer channel is arranged on the Ga2O3 substrate, the source metal and the P-type heterostructure material region are arranged on two ends of the Ga2O3 epitaxial layer channel, and the P-type heterostructure material region and the Ga2O3 epitaxial layer channel form a hetero-PN junction. The method comprises the following steps: pretreatment, mesa etching, source metal growth, ohmic annealing, drain heterojunction and electrode material growth, preparation and opening of the gate dielectric, and growth of the gate metal. The P-type heterostructure material and the channel form a heterojunction, the drain metal and the P-type heterostructure material adopt a self-alignment process, the p-type NiO material is used as the p-type gallium oxide material instead, the p-NiO and n-Ga2O3 hole super-injection effect is utilized, the reverse breakdown voltage is improved, and the forward conduction resistance is reduced. The application can be applied to power electronic devices such as inverters with a working voltage greater than 5V.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and mainly relates to a field effect transistor, in particular to a Ga2O3 field effect transistor based on a heterojunction hole super-injection and a preparation method thereof, which can be used for power electronic devices such as inverters. TECHNICAL BACKGROUND

[0002] As an emerging ultra-wide bandgap semiconductor material, Ga2O3 has a bandgap width of 4.5-4.9 eV and a critical breakdown field strength of about 8 MV / cm, and the theoretical power can be more than twice that of SiC and GaN. Moreover, due to the relatively low crystal acquisition price and excellent thermal stability, Ga2O3 is one of the most popular and important materials in the field of power semiconductor devices.

[0003] For a power device, the power figure of merit (P-FOM) is often used to evaluate the comprehensive level of the device in power applications; and the two most important indicators in the power figure of merit are the specific on-resistance R on,sp and the breakdown voltage BV. Due to the ultra-wide bandgap and high critical breakdown field strength of Ga2O3, as well as the optimized design of the device field plate and terminal structure by researchers, the breakdown voltage of Ga2O3 field effect transistor has reached a very high level. At present, Ga2O3 transistors with a breakdown voltage exceeding 10 kV have been designed and implemented, and thus a very high power figure of merit is achieved. However, the forward on-state performance is worth paying attention to, and the difficulty in improving the current density will distort the actual power performance of the high power figure of merit brought by the ultra-high withstand voltage.

[0004] Unlike the breakdown voltage, which can be easily improved by designing device size and building field plates, the specific on-resistance is often limited by the properties of the material itself. The modulation methods for the on-resistance of the transistor in the prior art are very limited. The resistance of the transistor device generally considers two parts: source-drain ohmic resistance and channel resistance. The general idea is to reduce the ohmic contact resistance of the source and drain of the transistor through various experimental methods, or to reduce the resistance of these two parts respectively by designing the channel width-length ratio to achieve the overall resistance level. Generally speaking, the obstacle to further improve the current density lies in the channel mobility level and channel scattering effect, as well as the channel carrier density. In the case of stable material, it is difficult for the general design method to have an impact on these factors.

[0005] In summary, Ga2O3 field effect transistors are faced with the great obstacle of difficulty in reducing the specific on-resistance. The inherent channel mobility level and channel scattering effect of gallium oxide material hinder the further improvement of the current density, and the comprehensive level of the device is difficult to reach the limit of Ga2O3 transistor. SUMMARY

[0006] The purpose of the present application is to solve the problem of low current density of gallium oxide field effect transistor, and provide a Ga2O3 field effect transistor based on heterojunction hole super injection with improved current density.

[0007] The present application is a Ga2O3 field effect transistor based on heterojunction hole super injection, which comprises a Ga2O3 substrate, a Ga2O3 epitaxial layer channel, a source metal, a drain metal, a gate dielectric, and a gate metal.

[0008] The present application is also a preparation method of a Ga2O3 field effect transistor based on heterojunction hole super injection, which is applicable to any Ga2O3 field effect transistor based on heterojunction hole super injection according to claims 1 to 6.

[0009] Step 1: sample selection and pretreatment: Ga2O3 homoepitaxial wafer is used, and is cleaned with acetone, isopropyl alcohol and deionized water, and is dried with nitrogen;

[0010] Step 2: mesa etching: the above-mentioned epitaxial wafer is etched to form a mesa of the channel and the source and drain metals, and the mesa retains the main part of a MOSFET including the source and the drain;

[0011] Step 3: source metal growth: after the above-mentioned sample is masked and photolithography is performed, the source metal is grown; Step 4: ohmic annealing: the sample with grown source metal is annealed to form ohmic contact;

[0012] Step 5: growth of drain heterojunction and electrode material: after the Ga2O3 epitaxial layer channel is masked by thick glue AZ 4620, a hole is opened on the side of the Ga2O3 epitaxial layer channel where the source metal is not grown, and a heterojunction material is grown by magnetron sputtering; after the growth of the P-type heterojunction material area is completed, the photoresist is not stripped, and a layer of drain metal forming an ohmic contact is continuously grown on the P-type heterojunction material area, and then the sample with the overall structure of the P-type heterojunction material area and the drain metal is stripped to complete the growth of the drain heterojunction and the electrode material;

[0013] Step 6: preparation and opening of gate dielectric: the sample completed in the above steps is grown with a gate dielectric material; then the upper surfaces of the source metal and the drain metal are photoetched, and the grown dielectric material is opened by a semiconductor dielectric etching machine RIE to expose the source and drain metals;

[0014] Step 7: growth of gate metal: finally, the photoresist mask is used to grow the gate metal on the gate dielectric layer, photoetch the side of the channel near the source, and strip to complete the device fabrication.

[0015] The present application provides a new technical means to solve the technical problem of small current density. The existing technology does not have a means to regulate carrier density through a homogeneous p-n junction, and the present application uses p-type NiO material as a substitute for p-type gallium oxide material, utilizes the hole super-injection effect generated in the heterojunction formed by p-NiO and n-Ga2O3, significantly increases the reverse breakdown voltage, and reduces the forward on-resistance.

[0016] Compared with the prior art, the present application has the following beneficial effects:

[0017] Effectively reduce the characteristic on-resistance: the present application utilizes the hole super-injection phenomenon discovered in the Ga2O3 heterojunction diode to effectively increase the current density in the channel and reduce the characteristic on-resistance of the field effect transistor under a certain voltage level.

[0018] Reduce static loss and improve device reliability: the present application introduces a p-n junction gate control structure into the MOSFET, which constitutes an enhancement mode gallium oxide device, so that the device is in an off state when the gate voltage is zero biased, reducing the static loss of the device and improving the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1It is a gallium oxide field effect transistor structure diagram based on the drain heterojunction hole super injection of the application.

[0020] Figure 2 It is a specific embodiment of a vertical device of the application, and the principle is the same as that of a horizontal device.

[0021] Figure 3 It is a process flow chart of the application.

[0022] Figure 4 It is a preparation method flow chart of the application. Specific embodiments

[0023] Example 1:

[0024] The gallium oxide field effect transistor in the prior art does not have a means for regulating carrier density through a p-n junction, and it is difficult to improve the current density of the gallium oxide field effect transistor channel.

[0025] The application is a gallium oxide field effect transistor based on heterojunction hole super injection, and the structure of the application includes a Ga2O3 substrate, a Ga2O3 epitaxial layer channel, a source metal, a drain metal, a gate dielectric, and a gate metal. Figure 1 , Figure 1The application also includes a P-type heterostructure region 4, which uses p-type NiO material as a substitute for p-type gallium oxide material, utilizes the hole super-injection effect generated in the heterojunction formed by p-NiO and n-Ga2O3, significantly improves the reverse breakdown voltage, and reduces the forward conduction resistance.

[0026] The application is an overall technical solution, and the application introduces a P-type heterostructure region 4 arranged above the Ga2O3 epitaxial layer channel 2 and forming a hetero-PN junction with the upper surface of the Ga2O3 epitaxial layer channel 2.

[0027] The application uses p-NiO as a substitute for p-type gallium oxide material, forms a heterojunction with n-Ga2O3, utilizes the conductivity modulation effect in the n-Ga2O3 / p-NiO heterojunction, and when forward bias, the hole barrier is reduced, the holes in the p region jump into the n region through the PN heterojunction, and when the hole concentration is higher than the electron concentration, the electron concentration is induced to rise, and the on-resistance is reduced.

[0028] Embodiment 2

[0029] The overall scheme of the Ga2O3 field effect tube based on the heterojunction hole super-injection is the same as that in embodiment 1, the Ga2O3 epitaxial layer channel 2 of the application is a Ga2O3 homo-epitaxial material based on hydride vapor phase epitaxy (HVPE) high-temperature growth, the thickness of the Ga2O3 epitaxial layer is 200 nm-800 nm, the doping concentration of the Ga2O3 epitaxial layer is 1x10 15 cm -3 -1x10 18 cm -3 .

[0030] The range of the thickness of the Ga2O3 epitaxial layer in the application is 200nm-800nm, and the thickness range can be adjusted according to the actual application in the actual application, and the purpose is to make the etching process penetrate the epitaxial layer to the substrate to obtain a mesa conductive channel, as long as the mesa etching depth is greater than the thickness of the epitaxial layer, and the isolation of the device is ensured. When the etching depth is 200nm, the Ga2O3 epitaxial layer thickness can be 300nm, and when the etching depth is 900nm, the Ga2O3 epitaxial layer thickness can be 800nm;

[0031] The doping concentration of the Ga2O3 epitaxial layer in the application is 1x10 15 cm -3 -1x10 18 cm -3 , and the actual application can be adjusted according to the actual application, and the different current levels and withstand voltage conditions are measured and adjusted, and the conduction under the applied bias is ensured. For example, when the design standard of a device is 1.5kV for blocking voltage BV, the doping concentration of the epitaxial layer can be 1x10 15 cm -3 , and when the design standard of a device is 300V for blocking voltage BV, the doping concentration of the epitaxial layer can be 1x10 18 cm -3

[0032] The production method of the epitaxial layer of the application is given as HVPE high-temperature grown Ga2O3 homoepitaxial material, and the advantage is that the epitaxial layer grown by HVPE high temperature can maintain stable performance in the annealing process during device preparation.

[0033] Example 3:

[0034] The overall scheme of the Ga2O3 field effect tube based on heterojunction hole super injection is the same as that of examples 1-2, and the material of the P-type heterojunction region 4 is one of nickel oxide P-type semiconductor material or chromium oxide P-type semiconductor material, that is, one of nickel oxide or chromium oxide P-type semiconductor material.

[0035] In this embodiment, one of the p-type NiO film and the p-type CrO2 film is introduced to form a heterojunction with the n-type gallium oxide material, and the main advantage is that the heterojunction is formed by the semiconductor heterojunction material and the n-type gallium oxide material, and a significant hole super injection effect is generated, thereby improving the withstand voltage of the current Ga2O3 field effect transistor and greatly reducing the on-resistance.

[0036] Example 4:

[0037] The overall scheme of the Ga2O3 field effect tube based on the heterojunction hole super injection is the same as that in Embodiment 1-3, and the metal material of the drain metal 5 is one or more of titanium, aluminum, nickel, gold, platinum, iridium and molybdenum, and the drain metal 5 forms an ohmic contact with the material of the P-type heterojunction region 4.

[0038] In this example, multiple choices of the drain metal 5 are given, and different metal materials can be selected to form an ohmic contact with the P-type heterojunction region 4 material, so as to ensure the stability of the output characteristics of the Ga2O3 field effect tube.

[0039] Embodiment 5:

[0040] The overall scheme of the Ga2O3 field effect tube based on the heterojunction hole super injection is the same as that in Embodiments 1-4, the metal material of the source metal 3 is one or more of titanium, aluminum, nickel, gold, platinum, iridium and molybdenum, and the source metal 3 forms an ohmic contact with the Ga2O3 epitaxial layer channel 2; and the metal material of the gate metal 7 is one or more of titanium, aluminum, nickel, gold, platinum, iridium and molybdenum.

[0041] In this example, multiple choices of the source metal 3 and the gate metal 7 are given, so as to ensure the stability of the output characteristics of the Ga2O3 field effect tube. The advantage is that the source electrode with good contact can reduce the contact resistance, and further achieve the purpose of reducing the overall resistance level.

[0042] Embodiment 6:

[0043] The overall scheme of the Ga2O3 field effect tube based on the heterojunction hole super injection is the same as that in Embodiment 1, the material of the gate dielectric 6 is one or more of aluminum oxide, silicon oxide and hafnium oxide, and the thickness of the gate dielectric 6 is 15 nm-20 nm.

[0044] The application introduces one or more of aluminum oxide, silicon oxide and hafnium oxide as the gate dielectric material, and one of them can be used in the general scheme, or multiple ones can be used; the application gives that the thickness of the gate dielectric is 15 nm-20 nm, which can be adjusted according to the design standard in the actual implementation process. When the design sub-threshold swing is 120 / dec, the thickness of the gate dielectric can be 20 nm; when the design sub-threshold swing is 100 / dec, the thickness of the gate dielectric can be 15 nm.

[0045] The advantages include that the material has a high dielectric constant, the thickness of the dielectric material can be thinned to improve the gate control ability, and in the process, the opening processing can be performed through RIE dielectric etching, and the process cost is low.

[0046] Embodiment 7:

[0047] The present invention also provides a method for preparing a Ga2O3 field effect transistor based on heterojunction hole superinjection, which is performed for any of the Ga2O3 field effect transistors based on heterojunction hole superinjection according to Examples 1-6. After the same photolithography mask is formed, two layers of material, a P-type heterogeneous material region 4 and a drain metal 5, are grown in sequence to achieve a self-aligned process of the P-type heterogeneous material region 4 and the drain metal 5. The specific preparation process includes the following steps:

[0048] Step 1: Sample selection and pretreatment: Use Ga2O3 homogeneous epitaxial wafers, clean them with acetone, isopropyl alcohol and deionized water respectively, and blow dry them with nitrogen.

[0049] Step 2: Mesa etching: Etch the epitaxial wafer to form a mesa of the channel and source and drain metals, and retain the main part of a MOSFET such as the source and drain on the mesa.

[0050] Step 3: Source metal growth: mask the sample and perform photolithography, then grow the source metal.

[0051] Step 4: Ohmic annealing: Anneal the sample after growing the source metal to form an ohmic contact.

[0052] Step 5: Growth of drain heterojunction and electrode materials: After using a thick AZ 4620 mask above the Ga2O3 epitaxial layer channel, a hole is photolithographically opened on the side of the Ga2O3 epitaxial layer channel where the source metal is not grown, and the heterojunction material is grown by magnetron sputtering. After the growth of the P-type heterogeneous material area is completed, the photoresist is not stripped off, and a layer of drain metal forming an ohmic contact is continued to grow above the P-type heterogeneous material area. The sample with the completed P-type heterogeneous material area and the drain metal overall structure is then stripped off to complete the growth of the drain heterojunction and electrode materials.

[0053] Step 6: Preparation and opening of gate dielectric: Grow gate dielectric material on the entire sample that has completed the above steps; then perform photolithography openings on the upper surfaces of the source metal and drain metal, and use a semiconductor dielectric etcher RIE to open holes in the grown dielectric material to expose the source and drain metal.

[0054] Step 7: Growth of gate metal: Finally, use a photoresist mask to photolithographically grow gate metal on the side of the middle of the channel near the source above the gate dielectric layer. After peeling off, the device is completed.

[0055] The present invention is a general technical solution. On the basis of Ga2O3 field effect transistor, thick photoresist AZ 4620 photolithography is used. After the P-type heterogeneous material region is grown, the photoresist is not stripped off, and a layer of drain metal forming an ohmic contact is grown on the P-type heterogeneous material region. Then, the sample with the completed P-type heterogeneous material region and drain metal structure is stripped off.

[0056] The advantage is that the growth of the P-type hetero-material region and the drain metal share the same self-aligned process of one-time photolithography, ensuring that the edge of the drain metal is perfectly covered on the edge of the P-type hetero-material region, reducing process errors, ensuring that the current of the drain is regulated by the heterojunction, and increasing the current density.

[0057] Example 8:

[0058] The overall scheme of the Ga2O3 field effect tube based on heterojunction hole super injection and the preparation method thereof is the same as that in Example 7, and the ohmic annealing in step 4 is realized by using a rapid thermal annealing device RTA, and the process conditions are as follows:

[0059] Reaction chamber gas: N2;

[0060] Gas flow rate: 1200 sccm;

[0061] Chamber pressure: atmospheric pressure;

[0062] Annealing temperature: 475 DEG C;

[0063] Annealing time: 60 s.

[0064] The process conditions given in the present application can ensure that the source metal and the gallium oxide channel form ohmic contact with the smallest contact resistance, and ensure the carrier concentration of the epitaxial layer channel.

[0065] Example 9:

[0066] The overall scheme of the Ga2O3 field effect tube based on heterojunction hole super injection and the preparation method thereof is the same as that in Examples 7-8, and the heterojunction region material in step 5 is obtained by magnetron sputtering, and the process conditions are as follows:

[0067] Reaction chamber pressure: 10 mTorr;

[0068] Ionization voltage: 1-3 kV;

[0069] Reaction chamber gas: O2, N2, Ar.

[0070] The process conditions given in the present application can prepare a high-quality P-type hetero-material thin film, and generate a smooth NiO thin film with a thickness of 100 nm and good surface roughness.

[0071] Example 10:

[0072] The overall scheme of the Ga2O3 field effect tube based on heterojunction hole super injection is the same as that in Examples 1-9, and the gate medium in step 6 is obtained by using an atomic layer-by-layer deposition system ALD, which has a low interface fixed charge amount, and the process conditions are as follows:

[0073] Reaction chamber pressure: 5 Pa;

[0074] Chamber gas: N2;

[0075] Gas flow rate: 300 sccm;

[0076] Growth rate: 0.15 nm / cycle.

[0077] The process conditions given in the present application, after experiments and verification, the above process conditions can make the present application in the environment of high purity nitrogen can deposit out the impurity concentration of Al2O3 material, under the gas flow rate of 300 sccm, after 40 minutes can deposit out the surface flat, thickness of 20nm Al2O3 isolation layer.

[0078] Example 11:

[0079] The overall scheme of Ga2O3 field effect tube based on heterojunction hole super injection and its preparation method is the same as that of examples 1-10. Ga2O3 homoepitaxial wafer is used, the substrate is n-type β-Ga2O3 of UID, the thickness is 650μm; the epitaxial layer is Si-doped β-Ga2O3 film, the thickness is 500nm, and is cleaned with acetone, isopropyl alcohol and deionized water respectively, and is dried with nitrogen.

[0080] As shown in Figure 3 (b), after the above epitaxial wafer is masked, ICP etching technology is used, the etching gas BCl3 / Ar flow rate is 70:10, the RF power is 300w, the etching time is 5min, and the etching depth is 800nm, the Ga2O3 epitaxial layer is etched through, only the device mesa and the epitaxial layer channel are reserved, and the channel width is 2um.

[0081] As shown in Figure 3 (c), after the device with completed mesa etching is photoetched, electron beam evaporation is used to evaporate metal Ti / Au=60 / 150nm in the source electrode area as the source electrode; after stripping the photoresist, rapid thermal annealing is used, the annealing temperature is 475℃, and the annealing time is 1min, so as to form ohmic contact.

[0082] As shown in Figure 3 (d), thick glue AZ6130 is used for photoetching, then magnetic control sputtering is used to first grow a heterojunction in the drain electrode area, the p-type material in the present application is NiO, and two layers with different doping concentrations are evaporated, the thickness and doping concentration of the two layers are respectively a lower layer of 60nm, 1×10 18 cm -3 and an upper layer of 30nm, 1×10 19 cm -3 oxide nickel to form a specific heterojunction area.

[0083] After completion, as shown in Figure 3(e) As shown, the sample grown with NiO is not peeled off first, and a layer of metal is evaporated on the same area by self-alignment process, the metal type and thickness are Ni / Au = 60 / 120 nm. Then, the sample is peeled off by hot water bath NMP solution to complete the fabrication of the drain region of the sample.

[0084] As shown in Figure 3 (f), first, the gate dielectric layer is grown. The dielectric material and thickness used in this embodiment are Al2O3, 20 nm, obtained by atomic layer deposition ALD, and the process temperature is 200°C. The source and drain regions of the sample after growing the dielectric are etched by wet etching to expose the source and drain metal electrodes; finally, after photolithography, the gate metal is grown, the metal type is Ti / Au, the thickness is 60 / 150 nm, the gate-drain spacing L GD = 5 um, the source-drain spacing L GS = 1.5 um, and the gate width L G = 2 um. After peeling off, the device is completed.

[0085] Example 12:

[0086] This embodiment is a preparation process of a vertical gallium oxide field effect transistor based on heterojunction hole super injection, and its structure diagram is shown in Figure 2 Ga2O3 substrate 1 is used as a base, which is covered with Ga2O3 epitaxial layer channel 2, source metal 3 covers the lower surface of Ga2O3 substrate 1, P-type hetero material region 4 is located directly above Ga2O3 epitaxial layer channel 2, and forms a pn heterojunction with it, and drain metal 5 is located directly above P-type hetero material region 4. The gate dielectric 6 covers both ends of the step sidewall formed by the Ga2O3 epitaxial layer channel 2, the P-type hetero material region 4 and the drain metal 5. The gate metal 7 is arranged above the gate dielectric 6, and the step sidewall formed by the Ga2O3 epitaxial layer channel 2, the P-type hetero material region 4 and the drain metal 5.

[0087] The preparation process includes:

[0088] First, a Ga2O3 homoepitaxial wafer is used, the substrate is n-type β-Ga2O3 with UID, and the thickness is 650 μm; the epitaxial layer is a Si-doped β-Ga2O3 film with a thickness of 500 nm, which is cleaned with acetone, isopropyl alcohol and deionized water, and dried with nitrogen;

[0089] Ti / Au = 60 / 150 nm is evaporated on the source region on the back of the sample by electron beam evaporation, as the source electrode; then rapid thermal annealing is used, the annealing temperature is 475°C, and the annealing time is 1 min, to form the source ohmic contact.

[0090] Ga2O3 epitaxial layer is etched by ICP method to form Ga2O3 vertical channel, BCl3 / Ar flow ratio is set to 70:10, RF power is 300w, and etching time is 50min. The Ga2O3 vertical channel has a height of 800nm and a width of 600nm.

[0091] After etching, a heterojunction is first grown on the etched drain region by magnetron sputtering, the p-type material in the example is NiO, and two layers with different doping concentrations are deposited, the thickness and doping concentration of the two layers are respectively 60nm, 1×10 18 cm -3 of the lower layer and 30nm, 1×10 19 cm -3 of the upper layer of nickel oxide to form a specific heterojunction region.

[0092] After completion, the sample grown with NiO is not peeled off first, a layer of metal is deposited above the same area by self-alignment process, the metal type and thickness are Ni / Au=60 / 120nm. Then, the sample is peeled off by hot water bath NMP solution to complete the preparation of the drain region of the sample.

[0093] The gate dielectric layer is grown. In this embodiment, the dielectric material and thickness are HrO2, 20nm, which are obtained by atomic layer deposition (ALD), and the process temperature is 200℃. The source-drain region of the sample after growing the dielectric is etched by wet etching to expose the source-drain metal electrode; finally, the gate metal is grown after photolithography, the metal type is Ti / Au, and the thickness is 60 / 150nm, and the device is completed after peeling off.

[0094] In summary, the present invention provides a gallium oxide field-effect transistor based on heterojunction hole superinjection and a method for preparing the same. This solves the problem in the prior art that gallium oxide field-effect transistors lack a means to regulate carrier density through a pn junction. The present invention uses p-type NiO material as a substitute for p-type gallium oxide material, utilizing the hole superinjection effect generated in the heterojunction formed by p-NiO and n-Ga2O3 to significantly increase the reverse breakdown voltage and reduce the forward on-resistance. The present invention discloses a Ga2O3 field effect transistor based on heterojunction hole superinjection, which comprises a Ga2O3 substrate, a Ga2O3 epitaxial layer channel, a source metal, a drain metal, a gate dielectric, and a gate metal. The device is characterized in that the device further comprises a P-type heterostructure region. The overall structure is as follows: the Ga2O3 substrate serves as the base of the device, on which a Ga2O3 epitaxial layer channel is provided; the source metal and the P-type heterogeneous material region are respectively arranged at two ends above the Ga2O3 epitaxial layer channel; the drain metal is arranged directly above the P-type heterogeneous material region; the lower surface of the drain metal forms an ohmic contact with the material of the P-type heterojunction region; the gate dielectric is arranged between the P-type heterogeneous material region and the source metal, and the gate metal is arranged above the gate dielectric; the P-type heterogeneous material region forms a heterogeneous PN junction with the upper surface of the Ga2O3 epitaxial layer channel, and the overall structure constitutes a Ga2O3 field effect transistor based on heterojunction hole superinjection with a high current density. The preparation method of the present invention includes: sample selection and pretreatment; mesa etching; source metal growth; ohmic annealing; drain heterojunction and electrode material growth; gate dielectric preparation and opening; gate metal growth. The innovation of the present invention is that a P-type heterogeneous material is provided on one side of the channel to form a heterojunction with the channel, and the growth of the drain metal and the growth of the P-type heterogeneous material adopt a self-aligned process. Its advantage is that it utilizes the hole superinjection effect generated in the heterojunction formed by p-NiO and n-Ga2O3 to significantly improve the reverse breakdown voltage and reduce the forward on-resistance. The self-aligned process ensures that the edge of the drain metal perfectly covers the edge of the P-type heterogeneous material area, reducing process errors, ensuring that the drain current is regulated by the heterojunction, and increasing the current density. It can be used in power electronic equipment such as inverters with a drain operating voltage greater than 5V.

Claims

1. A Ga2O3 field effect transistor based on heterojunction hole super-injection, the structure comprising: Ga2O3 substrate, Ga2O3 epitaxial layer channel, source metal, drain metal, gate dielectric, gate metal, characterized in that, The P-type heterojunction region is also included; the overall structure is as follows: Ga2O3 substrate as the base of the device, with Ga2O3 epitaxial layer channel; source metal, P-type hetero material region are respectively arranged on both ends of the Ga2O3 epitaxial layer channel, drain metal is arranged directly above the P-type hetero material region, the lower surface of the drain metal forms ohmic contact with the material of the P-type heterojunction region, gate dielectric is arranged between the P-type hetero material region and the source metal, and the gate metal is arranged above the gate dielectric; the P-type hetero material region and the upper surface of the Ga2O3 epitaxial layer channel form a heterojunction PN junction, and the whole constitutes a Ga2O3 field effect tube based on heterojunction hole super injection with large current density.

2. The Ga2O3 field effect transistor based on heterojunction hole super injection according to claim 1, characterized in that, The Ga2O3 epitaxial layer channel is based on a Ga2O3 homoepitaxial material grown by hydride vapor phase epitaxy (HVPE) at high temperature, and the thickness of the Ga2O3 epitaxial layer is 200 nm-800 nm; the doping concentration of the Ga2O3 epitaxial layer is 1x10 15 cm -3 -1x10 18 cm -3 .

3. The Ga2O3 field effect transistor based on heterojunction hole super injection as claimed in claim 1, wherein, The material of the P-type heterojunction region is either a nickel oxide P-type semiconductor material or a chromium oxide P-type semiconductor material.

4. The Ga2O3 field effect transistor based on heterojunction hole super injection as claimed in claim 1, wherein, The metal material used for the drain metal is one or more of titanium, aluminum, nickel, gold, platinum, iridium, and molybdenum, and the drain metal forms ohmic contact with the material of the P-type heterojunction region.

5. The Ga2O3 field effect transistor based on heterojunction hole super injection as claimed in claim 1, wherein, The metal material used for the source metal is one or more of titanium, aluminum, nickel, gold, platinum, iridium, and molybdenum, and the source metal forms ohmic contact with the Ga2O3 epitaxial layer channel; the metal material used for the gate metal is one or more of titanium, aluminum, nickel, gold, platinum, iridium, and molybdenum.

6. The Ga2O3 field effect transistor based on heterojunction hole super injection as claimed in claim 1, wherein, The material of the gate dielectric is one or more of aluminum oxide, silicon oxide, and hafnium oxide, and the thickness of the gate dielectric is 15-20 nm.

7. A method of manufacturing a Ga2O3 field effect transistor based on heterojunction hole super-injection, for any of the Ga2O3 field effect transistors based on heterojunction hole super-injection according to any one of claims 1 to 6, characterized in that, After the same step of photolithography mask, the P-type hetero material region and the drain metal are grown in sequence, realizing the self-alignment process of the P-type hetero material region and the drain metal, and the specific preparation process includes the following steps: Step 1: sample selection and pretreatment: Ga2O3 homoepitaxial wafer is used, and acetone, isopropyl alcohol, and deionized water are used for cleaning, and nitrogen is used for drying; Step 2: mesa etching: the above epitaxial wafer is etched to form a channel and a mesa of source and drain metal, and the mesa retains the main part of the MOSFET; Step 3: source metal growth: the above sample is masked after photolithography, and then the source metal is grown; Step 4: ohmic annealing: the sample with grown source metal is annealed to form ohmic contact; Step 5: drain heterojunction and electrode material growth: after masking with thick glue AZ 4620 on the Ga2O3 epitaxial layer channel, a hole is opened on the side of the Ga2O3 epitaxial layer channel where the source metal is not grown, and the heterojunction material is grown by magnetron sputtering method; after the growth of the P-type hetero material region is completed, the photoresist is not stripped, and a layer of ohmic contact drain metal is grown on the P-type hetero material region, and then the sample with the overall structure of the P-type hetero material region and the drain metal is stripped to complete the growth of the drain heterojunction and the electrode material; Step 6: preparation and hole opening of gate dielectric: the sample completed in the above steps is grown with gate dielectric material; then the upper surface of the source and drain metal is photolithographically opened, and the grown dielectric material is opened by semiconductor dielectric etching machine RIE, so that the source and drain metal is exposed; Step 7: Growth of gate metal: Finally, the gate metal is grown on the gate dielectric layer using a photoresist mask, which is patterned on the channel near the source side. After stripping the photoresist, the device is completed.

8. The method for preparing a Ga2O3 field effect transistor based on heterojunction hole superinjection according to claim 7, characterized in that: Step 4: Ohmic annealing is achieved using a rapid thermal annealing (RTA) device, with the following process conditions: Reaction chamber gas: N2; Gas flow rate: 1200 sccm; Cavity pressure: Atmospheric pressure; Annealing temperature: 475°C; Annealing time: 60s.

9. The method of claim 7, wherein the Ga2O3 field effect transistor is a heterojunction hole super-injection based Ga2O3 field effect transistor. In step 5, the heterojunction region material is obtained by magnetron sputtering, with the following process conditions: Reaction chamber pressure: 10 mTorr; Ionization voltage: 1kV-3kV; Reaction chamber gas: O2, N2, Ar.

10. The method of claim 7, wherein the Ga2O3 heterojunction field effect transistor is formed by a process comprising: forming a Ga2O3 layer on a substrate; forming a first electrode on the Ga2O3 layer; forming a second electrode on the Ga2O3 layer; and forming a gate on the Ga2O3 layer. In step 6, the gate dielectric is obtained using an atomic layer deposition (ALD) system, which has a low interface fixed charge quantity, with the following process conditions: Reaction chamber pressure: 5 Pa; Reaction chamber gas: N2; Gas flow rate: 300 sccm; Growth rate: 0.15 nm / cycle.

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