Multi-element computing power fusion control chip and manufacturing method

Abstract

The invention discloses a multivariate computing power fusion control chip and a manufacturing method. The chip comprises a P-type substrate layer, a DMOS unit, a PMOS unit, an NMOS unit, a bipolar unit, a first P well region unit and a second P well region unit. The DMOS unit, the PMOS unit, the NMOS unit, the bipolar unit, the first P well region unit and the second P well region unit are respectively arranged in shallow grooves of the P-type substrate layer; the DMOS unit, the first P well region unit, the NMOS unit, the PMOS unit, the second P well region unit and the bipolar unit are sequentially arranged in the horizontal direction. By integrating a plurality of different units, the chip can keep stable operation in a complex working environment, so that faults caused by unstable voltage or overlarge transient current are reduced, the reliability of the circuit is improved, the influence of power supply fluctuation on sensitive digital and analog circuits is avoided, and meanwhile, the power consumption loss is also reduced.

Description

Background Art

[0002] With the rapid development of science and technology, modern electronic devices are moving towards higher performance, low power consumption and intelligence. Especially in the fields of autonomous driving, industrial control, Internet of Things and communications, the requirements for computing power and energy efficiency are becoming more stringent.

[0003] However, the increase in integration and computing power requirements has brought challenges in power consumption and thermal management. In order to reduce power consumption while meeting computing power requirements, the commonly used technology is to integrate a variety of different types of computing units (including central processing units (CPU), power management chips, power-specific modules, FPGAs, complementary metal oxide semiconductors (CMOS) and other units) to form a single chip that can achieve highly parallel processing and multi-task optimization to meet the computing power requirements of complex systems.

[0004] However, the commonly used methods currently have the following technical problems: Although the above-mentioned computing units have significant advantages in low power consumption and high-density integration, they have significant limitations in high voltage, high current processing and integration of power devices. When the voltage is unstable or the transient current is too large, it is easy to cause failures, causing the circuit to burn out. Summary of the invention

[0005] The present invention proposes a multi-computing power fusion control chip and a manufacturing method, which can solve the technical problem that the existing integrated chips are prone to failure when the voltage is unstable or the transient current is too large.

[0006] A first aspect of an embodiment of the present invention provides a multi-computing power fusion control chip, and the multi-computing power fusion control chip method includes: a P-type substrate layer, a DMOS unit, a PMOS unit, an NMOS unit, a bipolar unit, a first P-well unit and a second P-well unit;

[0007] The DMOS unit, the PMOS unit, the NMOS unit, the bipolar unit, the first P-well unit and the second P-well unit are respectively arranged in shallow grooves in the P-type base layer;

[0008] The DMOS unit, the first P-well unit, the NMOS unit, the PMOS unit, the second P-well unit and the bipolar unit are sequentially arranged in a horizontal direction.

[0009] In combination with the first aspect, in one implementation, the DMOS unit includes: a first deep N well layer, a first Pbody layer, and a first Ndrift layer;

[0010] The first Pbody layer and the first Ndrift layer are respectively disposed on the first deep N well layer, and the first Pbody layer and the first Ndrift layer are connected;

[0011] The first Pbody layer is provided with a gate port and a source port, and the first Ndrift layer is provided with a drain port.

[0012] In combination with the first aspect, in one implementation, the DMOS unit includes: a second deep N well layer, a second Pbody layer and two second Ndrift layers;

[0013] The second Pbody layer and the two first Ndrift layers are respectively disposed on the second deep N well layer, and the second Pbody layer is respectively connected to the two second Ndrift layers;

[0014] The second Pbody layer is provided with a gate port and a source port, and the second Ndrift layer is provided with a drain port.

[0015] In combination with the first aspect, in one implementation, the DMOS unit includes: a third deep N well layer, two third Pbody layers and a third Ndrift layer;

[0016] The two third Pbody layers and the third Ndrift layer are respectively disposed on the third deep N well layer, and the third Ndrift layer is respectively connected to the two third Pbody layers;

[0017] The third Pbody layer is provided with a gate port and a source port, and the third Ndrift layer is provided with a drain port.

[0018] In combination with the first aspect, in one implementation, the bipolar cell includes: a fourth deep N-well layer, an Nwell layer, and a fourth Pbody layer;

[0019] The Nwell layer and the fourth Pbody layer are respectively disposed on the fourth deep N well layer;

[0020] The fourth Pbody layer is provided with a base port and an emitter port, and the Nwell layer is provided with a collector port.

[0021] In combination with the first aspect, in an implementation manner, the PMOS unit includes: a fourth Ndrift layer, and the fourth Ndrift layer is provided with a gate port, a source port, a drain port and a base port.

[0022] In combination with the first aspect, in an implementation manner, the NMOS unit includes: a Pwell layer, and the Pwell layer is provided with a gate port, a source port, a drain port, and a base port.

[0023] A second aspect of an embodiment of the present invention provides a method for manufacturing a multi-computing power fusion control chip, the method comprising:

[0024] After initially doping the starting wafer to form a substrate, a plurality of deep N wells and a plurality of shallow trenches are constructed on the substrate, so that the plurality of deep N wells are spaced apart by the plurality of shallow trenches;

[0025] Constructing a PMOS unit, an NMOS unit and a DMOS unit in the deep N-well respectively;

[0026] Performing metallization processing on the PMOS unit, the NMOS unit and the DMOS unit so that ports of the PMOS unit, the NMOS unit and the DMOS unit are connected;

[0027] After adding a passivation layer to the PMOS unit, the NMOS unit and the DMOS unit, they are packaged to obtain a multi-computing power fusion control chip.

[0028] A third aspect of an embodiment of the present invention provides a method for manufacturing a DMOS unit, the method comprising:

[0029] After constructing a deep N well on a substrate of a wafer, an N drift region is formed in the deep N well;

[0030] Constructing a P-Body region on the source side of the N drift region and an N+ drain region on the top of the N drift region, and constructing an N+ source region and a P+ source region on the top of the P-Body region respectively;

[0031] Constructing shallow trenches on both sides of the N+ source region, the P+ source region and the N+ drain region and injecting insulating materials to form an isolation layer;

[0032] After a gate oxide layer is grown between the P-Body region and the N-drift region and polysilicon is deposited to form a gate, the wafer is annealed to obtain a DMOS unit.

[0033] A fourth aspect of an embodiment of the present invention provides a manufacturing device for a multi-computing power fusion control chip, the device comprising:

[0034] A substrate processing module, used for constructing a plurality of deep N wells and a plurality of shallow trenches on the substrate after initially doping the starting wafer to construct the substrate, so as to separate the plurality of deep N wells by using the plurality of shallow trenches;

[0035] A cell construction module, used to construct a PMOS cell, an NMOS cell and a DMOS cell in the deep N-well respectively;

[0036] A metallization module, used for performing metallization processing on the PMOS unit, the NMOS unit and the DMOS unit, so as to connect the ports of the PMOS unit, the NMOS unit and the DMOS unit;

[0037] The packaging module is used to package the PMOS unit, the NMOS unit and the DMOS unit after adding a passivation layer to obtain a multi-computing power fusion control chip.

[0038] A fifth aspect of an embodiment of the present invention provides a manufacturing device for a DMOS unit, the device comprising:

[0039] A drift region module, used for forming an N drift region in the deep N well after constructing the deep N well on the substrate of the wafer;

[0040] A construction area module, used to construct a P-Body area on the source side of the N drift area and an N+ drain area on the top of the N drift area, and to construct an N+ source area and a P+ source area on the top of the P-Body area respectively;

[0041] An isolation layer construction module is used to construct shallow trenches on both sides of the N+ source region, the P+ source region and the N+ drain region and inject insulating materials to form an isolation layer;

[0042] The annealing module is used to perform annealing on the wafer after growing a gate oxide layer and depositing polysilicon to form a gate between the P-Body region and the N-drift region to obtain a DMOS unit.

[0043] Compared with the prior art, the embodiment of the present invention provides a multi-computing power fusion control chip and a manufacturing method, and its beneficial effect is that: the present invention includes a DMOS unit, a first P-well area unit, an NMOS unit, a PMOS unit, a second P-well area unit and a bipolar unit arranged in sequence in the horizontal direction, and each unit is arranged on a P-type substrate layer. By integrating multiple different units, the chip can maintain stable operation in a complex working environment, reduce failures caused by unstable voltage or excessive transient current, improve circuit reliability, avoid the impact of power supply fluctuations on sensitive digital and analog circuits, and also reduce power consumption losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a schematic diagram of the structure of a multi-computing power fusion control chip provided by an embodiment of the present invention. Figure 1 ;

[0045] Figure 2 This is a schematic diagram of the structure of a multi-computing power fusion control chip provided by an embodiment of the present invention. Figure 2 ;

[0046] Figure 3 The structure of a DMOS unit provided by an embodiment of the present invention is shown in FIG. Figure 1 ;

[0047] Figure 4 The structure of a DMOS unit provided by an embodiment of the present invention is shown in FIG. Figure 2 ;

[0048] Figure 5 The structure of a DMOS unit provided by an embodiment of the present invention is shown in FIG. Figure 3 ;

[0049] Figure 6 It is a flow chart of a method for manufacturing a multi-computing power fusion control chip provided by one embodiment of the present invention;

[0050] Figure 7 It is a schematic flow chart of a method for manufacturing a DMOS unit provided by one embodiment of the present invention;

[0051] Figure 8 It is a structural schematic diagram of a manufacturing device for a multi-computing power fusion control chip provided by an embodiment of the present invention;

[0052] Fig. 9 It is a structural schematic diagram of a DMOS unit manufacturing device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] With the rapid development of science and technology, modern electronic devices are moving towards higher performance, low power consumption and intelligence. Especially in the fields of autonomous driving, industrial control, Internet of Things and communications, the requirements for computing power and energy efficiency are becoming more stringent.

[0055] However, the increase in integration and computing power requirements has brought challenges in power consumption and thermal management. In order to reduce power consumption while meeting computing power requirements, the commonly used technology is to integrate a variety of different types of computing units (including central processing units (CPU), power management chips, power-specific modules, FPGAs, complementary metal oxide semiconductors (CMOS) and other units) to form a single chip that can achieve highly parallel processing and multi-task optimization to meet the computing power requirements of complex systems.

[0056] However, the commonly used methods currently have the following technical problems: Although the above-mentioned computing units have significant advantages in low power consumption and high-density integration, they have significant limitations in high voltage, high current processing and integration of power devices. When the voltage is unstable or the transient current is too large, it is easy to cause failures, causing the circuit to burn out.

[0057] In order to solve the above problems, a multi-computing power fusion control chip and a manufacturing method provided in an embodiment of the present application will be introduced and explained in detail through the following specific embodiments.

[0058] Reference Figure 1 , showing a schematic diagram of the structure of a multi-computing power fusion control chip provided by an embodiment of the present invention.

[0059] Wherein, as an example, the multi-computing power fusion control chip may include: a P-type substrate layer, a DMOS unit, a PMOS unit, an NMOS unit, a bipolar unit, a first P-well region unit, and a second P-well region unit;

[0060] The DMOS unit, the PMOS unit, the NMOS unit, the bipolar unit, the first P-well unit and the second P-well unit are respectively arranged in shallow grooves in the P-type base layer;

[0061] The DMOS unit, the first P-well unit, the NMOS unit, the PMOS unit, the second P-well unit and the bipolar unit are sequentially arranged in a horizontal direction.

[0062] In one embodiment, the present invention can use the BCD (Bipolar-CMOS-DMOS) process to generate the above-mentioned multi-computing power fusion control chip. By integrating bipolar units, CMOS units and DMOS power units through the above-mentioned process, the multiple needs of signal processing, digital control and power transmission can be taken into account.

[0063] Moreover, the BCD process integrates three different types of units, each with unique electrical characteristics. The bipolar unit can be a bipolar transistor (Bipolar Transistor), which performs well in analog signal processing and high-gain amplification, can handle large currents and provide excellent linearity. CMOS units are widely used in digital circuits and logic control due to their low power consumption, high speed and high integration. DMOS (double diffused metal oxide semiconductor) units, especially LDMOS for high-voltage power control, can handle high voltage and high current, and are suitable for power conversion and drive circuits. Therefore, the BCD process integrates these three units on a single chip to achieve a high degree of integration of analog, digital and power circuits, greatly improving the performance, integration and energy efficiency of the system.

[0064] The high transconductance and strong load driving capability of bipolar units and the high integration and low power consumption of CMOS are combined to solve the problem of chip area and energy efficiency caused by the fusion of multiple computing powers; DMOS power unit integration technology is studied to solve the power loss problem in the process of multiple computing power fusion. The BCD process comprehensively studied in this task can greatly reduce power loss, improve system performance, save circuit packaging costs, and have better reliability.

[0065] In one embodiment, the bipolar junction unit (BJT) has high transconductance characteristics and can provide strong load driving capability at high current density. This makes it have irreplaceable advantages in analog signal amplification and processing, and precise current control. By rationally arranging the position and function distribution of the bipolar unit, the demand for external driving circuits can be effectively reduced, the overall area can be reduced, and the power handling capability can be enhanced.

[0066] CMOS unit (can include PMOS unit and NMOS unit): With its high integration and low power consumption, CMOS technology is widely used in the digital circuit part of the chip. The CMOS unit in this solution is mainly responsible for the logic control and data processing part of the multi-computing power unit (such as CPU, GPU, NPU, etc.). The high integration of CMOS process can integrate a large number of complex digital logic units in a smaller chip area, effectively improve the area utilization, and further optimize the overall energy efficiency of the chip.

[0067] Combining bipolar transistors and CMOS for use in digital circuit modules in chips can improve area utilization and increase efficiency.

[0068] DMOS unit (LDMOS): As a power conversion and management module, the LDMOS unit has the characteristics of extremely high switching speed, strong driving capability, high input impedance, good thermal stability, and low on-resistance, and performs well in handling high current tasks. LDMOS is mainly used in the power modules related to the power management module to reduce power loss.

[0069] Reference Figure 2 , showing a schematic diagram of the structure of a multi-computing power fusion control chip provided by an embodiment of the present invention Figure 2 .

[0070] In one embodiment, the bipolar cell comprises: a fourth deep N-well layer, an Nwell layer, and a fourth Pbody layer;

[0071] The Nwell layer and the fourth Pbody layer are respectively disposed on the fourth deep N well layer;

[0072] The fourth Pbody layer is provided with a base port and an emitter port, and the Nwell layer is provided with a collector port.

[0073] Reference Figure 2 In one embodiment, the PMOS unit comprises: a fourth Ndrift layer, wherein the fourth Ndrift layer is provided with a gate port, a source port, a drain port and a base port.

[0074] Reference Figure 2 In one embodiment, the NMOS unit comprises: a Pwell layer, wherein the Pwell layer is provided with a gate port, a source port, a drain port and a base port.

[0075] It should be noted that CMOS technology: CPU cores usually use CMOS to implement their main parts. CMOS has the advantages of low power consumption and high-density integration, and is suitable for processors, logic circuits, and various computing modules.

[0076] CMOS technology: used in most digital IO circuit designs, with the advantages of low power consumption and high density. Transistor: may be used in some analog IO interfaces, such as the input part for signal amplification or protection circuits. The combination of transistor and CMOS can improve the efficiency of level conversion and enhance the stability of IO signals.

[0077] Reference Figure 3 , showing a schematic diagram of the structure of a DMOS unit provided by an embodiment of the present invention Figure 1 In one embodiment, the DMOS cell comprises: a first deep N-well layer, a first Pbody layer, and a first Ndrift layer;

[0078] The first Pbody layer and the first Ndrift layer are respectively disposed on the first deep N well layer, and the first Pbody layer and the first Ndrift layer are connected;

[0079] The first Pbody layer is provided with a gate port and a source port, and the first Ndrift layer is provided with a drain port.

[0080] In one embodiment, the structure of the DMOS cell is as follows: Figure 3 As shown. The DMOS unit can be called the LDMOS unit. LDMOS is a power device with a double diffusion structure. The DMOS unit can be implanted twice in the same source / drain region, once with a higher concentration of arsenic (As) and once with a lower concentration of boron (B). After the implantation, a high-temperature push-in process is performed. Since boron diffuses faster than arsenic, it will diffuse further laterally under the gate boundary (P well in the figure), forming a channel with a concentration gradient. Its channel length is determined by the difference in the distance of the two lateral diffusions.

[0081] In order to increase the breakdown voltage, there is a drift region between the active region and the drain region. The drift region in LDMOS is the key to the design of this type of unit or device, and the breakdown voltage can be changed by controlling the length of the drift region. The impurity concentration in the drift region is relatively low, so when LDMOS is connected to high voltage, the drift region can withstand higher voltage due to its high resistance.

[0082] Reference Figure 4 , showing a schematic diagram of the structure of a DMOS unit provided by an embodiment of the present invention Figure 2 In one embodiment, the DMOS cell comprises: a second deep N well layer, a second Pbody layer and two second Ndrift layers;

[0083] The second Pbody layer and the two first Ndrift layers are respectively disposed on the second deep N well layer, and the second Pbody layer is respectively connected to the two second Ndrift layers;

[0084] The second Pbody layer is provided with a gate port and a source port, and the second Ndrift layer is provided with a drain port.

[0085] Reference Figure 5 , showing a schematic diagram of the structure of a DMOS unit provided by an embodiment of the present invention Figure 3 In one embodiment, the DMOS cell comprises: a third deep N well layer, two third Pbody layers and a third Ndrift layer;

[0086] The two third Pbody layers and the third Ndrift layer are respectively disposed on the third deep N well layer, and the third Ndrift layer is respectively connected to the two third Pbody layers;

[0087] The third Pbody layer is provided with a gate port and a source port, and the third Ndrift layer is provided with a drain port.

[0088] The "lateral diffusion" design of the DMOS unit allows current to flow laterally, which can effectively disperse the current and avoid the problem of heat concentration. This diffusion structure reduces the heat generation of the power device, thereby reducing the heat dissipation requirements and heat loss. This structure enables the DMOS unit to operate stably at higher power without reducing efficiency and increasing power consumption due to heat problems.

[0089] Meanwhile, in order to improve area utilization, a folded structure of the DMOS cell may be used.

[0090] In one embodiment, the folded common source structure of the DMOS cell is as follows: Figure 4 As shown: The source of this structure is shared by multiple adjacent units, and the current flows from the source into each unit and then flows to its respective drain. The gate and drain parts are arranged on both sides of the source along the current path. This folding design is conducive to dense integration and improved power density.

[0091] In one embodiment, the folded common source structure of the DMOS cell is as follows: Figure 5 As shown: In the folded common drain structure, the drain is shared by multiple adjacent cells, and the drain terminal of the entire circuit is kept at the same potential. The current flows in from the source of each cell, converges to the common drain, and finally flows out through the drain. This design makes the current path more uniform and optimizes the thermal management of the cell or device.

[0092] Reference Figure 4 and 5 ,compared to Figure 4 and Figure 5 The common advantages of the DMOS unit compared to the ordinary structure are as follows:

[0093] (1) Compact structural layout: Folded common source / drain allows more power units to be accommodated in the same area by sharing the source / drain area on the chip. This folded design can integrate more source and drain units without significantly increasing the chip area, thereby increasing the power output per unit area. Because the chip area is more efficiently utilized, greater output power can be obtained in the same area, thereby improving power density.

[0094] (2) Reduce parasitic inductance and parasitic resistance: The folded design can effectively reduce parasitic inductance and resistance, thereby improving the high-speed response performance of the entire circuit. This characteristic of reducing parasitic effects is particularly suitable for high-frequency applications and can still maintain stable power output during high-frequency operation. Since the parasitic inductance is reduced, the power loss generated when the current flows is reduced, so the entire structure can carry higher power at high frequencies without affecting performance.

[0095] (3) Thermal management and current distribution: The shared design of the folded common source / drain can make the current more evenly distributed between cells, which helps improve thermal management and make the local temperature rise slower and more evenly distributed.

[0096] compared to Figure 4 and Figure 5 The differences between the DMOS units are as follows:

[0097] (1) Folded Common Drain The common drain reduces the output impedance and makes the voltage following characteristics better, which is particularly suitable for driving large loads. It is suitable as a buffer stage or driver stage at the output end and can maintain high signal integrity.

[0098] (2) The shared source reduces the parasitic resistance between multiple units, reducing the overall on-resistance. It is suitable for high-gain applications and can provide higher current amplification at the input end.

[0099] like Figure 4 and Figure 5 The DMOS unit folding structure shown combines the common gate and common drain structures to realize the folding structure of the DMOS unit. The DMOS unit folding structure can achieve higher power density within a limited chip area.

[0100] The traditional DMOS cell structure needs to occupy a large area when processing high power, especially in high current and high voltage scenarios. The folded structure of the DMOS cell of the present invention "folds" the conduction path through a more efficient layout design, thereby integrating more active devices on the same silicon wafer area and increasing power output capability. The folded structure of the DMOS cell helps to reduce the on-resistance (Ronon). The smaller the on-resistance, the lower the loss generated by the device in the on state, thereby reducing power consumption.

[0101] In actual operation, if the general IO involves high voltage or high current driving requirements, DMOS cells may be used to handle these tasks, such as output driving of high-power signals.

[0102] DMOS cells are commonly used in power switching circuits, drive circuits, and high-voltage control circuits due to their high withstand voltage characteristics and low on-resistance. When processing power and load switching, LDMOS technology can be used to achieve efficient switching operations and energy management.

[0103] By rationally allocating different technologies in each unit, the advantages of each process can be maximized, thereby improving the overall performance of the chip. The high transconductance and strong load driving capability of BJT and the low power consumption and high-density integration of CMOS enable digital circuit parts such as CPU cores, logic circuits, and FPGAs to achieve high-speed computing and maintain low power consumption while controlling the size of the chip area. On the other hand, LDMOS is very suitable for use in power-specific modules and power management modules due to its high voltage resistance and low conduction loss, ensuring that voltage conversion, power transmission and other tasks can be completed efficiently when processing high-power tasks. In this way, different types of computing power can be coordinated while achieving optimal performance in each part.

[0104] By using LDMOS technology to handle high power and high voltage parts, the chip has better robustness when facing high current impact and high voltage environment. This enables the chip to maintain stable operation in complex working environments, reduce failures caused by unstable voltage or excessive transient current, and improve circuit reliability. The high voltage resistance and efficient power switching capability of LDMOS also ensure that the power management module can provide a stable and reliable power supply, avoiding the impact of power supply fluctuations on sensitive digital and analog circuits. At the same time, it also reduces power consumption losses.

[0105] In this embodiment, the embodiment of the present invention provides a multi-computing power fusion control chip, and its beneficial effect is that: the present invention includes a DMOS unit, a first P-well area unit, an NMOS unit, a PMOS unit, a second P-well area unit and a bipolar unit arranged in sequence in the horizontal direction, and each unit is arranged on a P-type substrate layer. By integrating multiple different units, the chip can maintain stable operation in a complex working environment, reduce failures caused by unstable voltage or excessive transient current, improve circuit reliability, avoid power supply fluctuations on sensitive digital and analog circuits, and also reduce power consumption losses.

[0106] Reference Figure 6 , showing a flow chart of a method for manufacturing a multi-computing power fusion control chip provided by an embodiment of the present invention.

[0107] As an example, the manufacturing method of the multi-computing power fusion control chip may include:

[0108] S11, after initially doping the starting wafer to form a substrate, construct a plurality of deep N wells and a plurality of shallow trenches on the substrate, so as to use the plurality of shallow trenches to space the plurality of deep N wells.

[0109] In specific operations, the starting wafer and initial doping can be performed. The choice of substrate usually uses a P-type substrate (such as the P-substrate shown in the picture) as the starting point of the process to ensure that different areas can achieve the required device characteristics through proper doping control in subsequent processes.

[0110] In order to integrate bipolar transistors and DMOS devices, a deep N-well (such as Figure 2 The “Deep N Well” in the figure is used to support the structure of subsequent bipolar cells (NPN) and DMOS power devices.

[0111] Next, shallow trench isolation (STI) is formed between the device regions to prevent interference between different devices. The function of STI is to separate the device regions structurally by filling with insulating materials such as silicon dioxide to improve electrical isolation.

[0112] S12, constructing a PMOS unit, an NMOS unit and a DMOS unit in the deep N-well respectively.

[0113] In one embodiment, P well and N well may be doped, specifically in the NPN region, by forming a P well and a P+ region in the N well to create a base region of the NPN, and doping an N+ region on the top of the P well to form an emitter and a collector.

[0114] P+ is doped in the base region (P well) to form a base electrode connection. Inside the base region, the N+ region acts as an emitter, and the collector is formed in the N well region.

[0115] Electrical connections are made to the base (B), emitter (E) and collector (C) through metal contacts.

[0116] In CMOS (NMOS unit and PMOS unit), P well and N well need to be formed in the CMOS region for the creation of NMOS and PMOS devices, respectively. P well is used for NMOS, and N well is used for PMOS.

[0117] N+ is doped in the P well region of the NMOS, and P+ is doped in the N well region of the PMOS to form a source region and a drain region, respectively.

[0118] Between the source and drain regions, an oxide layer is deposited and gate metal is added to form the gates of NMOS and PMOS. The gate controls the opening and closing of the channel to achieve the logic control of CMOS.

[0119] When constructing a DMOS cell, a P-Body can be formed in the DMOS device area (right side) by doping P-type material in the N-well area to control the opening of the channel. In the P-Body area, P+ and N+ areas are further doped. The P+ area is used for grounding and forming a stable current path, the N+ area forms the source, and the N-drift area forms the drain.

[0120] Then, above the P-Body region, oxide and gate metal are deposited to form a gate structure that controls the flow of current. The change in gate voltage will control the flow of current between the source and drain, thereby achieving power control of DMOS.

[0121] S13, performing metallization processing on the PMOS unit, the NMOS unit, and the DMOS unit, so as to connect the ports of the PMOS unit, the NMOS unit, and the DMOS unit.

[0122] Next, the electrodes can be connected through metallization steps at the source, drain, gate, base and collector regions of each cell, such as Figure 2 The regions marked with B, E, C, S, G, and D are shown.

[0123] The interconnect layout is then designed between the various regions to ensure that the bipolar, CMOS, and DMOS devices can be electrically connected to form complete circuit functions while preventing signal interference.

[0124] S14, after adding a passivation layer to the PMOS unit, the NMOS unit and the DMOS unit, they are packaged to obtain a multi-computing power fusion control chip.

[0125] After all cells, devices, and metal interconnects are completed, a passivation layer is added to protect the device from external environmental influences such as moisture and contamination.

[0126] Packaging: You can choose the appropriate packaging method according to application requirements and package the entire chip to improve reliability.

[0127] Through the above manufacturing process, the overall performance of the multi-computing power fusion control chip can be improved. The high transconductance and strong load driving capability of BJT, the low power consumption and high-density integration of CMOS enable the digital circuit parts such as CPU core, logic circuit, FPGA to achieve high-speed computing, maintain low power consumption, and control the size of the chip area. On the other hand, LDMOS is very suitable for use in power-specific modules and power management modules due to its high voltage resistance and low conduction loss, ensuring that voltage conversion, power transmission and other tasks can be completed efficiently when processing high-power tasks. In this way, different types of computing power can work together while achieving optimal performance in each part.

[0128] By using LDMOS technology to handle high power and high voltage parts, the chip has better robustness when facing high current impact and high voltage environment. This enables the chip to maintain stable operation in complex working environments, reduce failures caused by unstable voltage or excessive transient current, and improve circuit reliability. The high voltage resistance and efficient power switching capability of LDMOS also ensure that the power management module can provide a stable and reliable power supply, avoiding the impact of power supply fluctuations on sensitive digital and analog circuits. At the same time, it also reduces power consumption losses.

[0129] Reference Figure 7 , showing a schematic flow chart of a method for manufacturing a DMOS unit provided by an embodiment of the present invention.

[0130] As an example, the manufacturing method of the DMOS unit may include:

[0131] S21 . After constructing a deep N well on a wafer substrate, an N drift region is formed in the deep N well.

[0132] Specifically, a deep N-well can be first formed on the P-type substrate to provide the main drift region of the LDMOS. Implanted material: Phosphorus (P) or Arsenic (As). Dose range: 10^12-10^13atoms / cm^2. Implantation energy: higher energy (such as hundreds of keV) to ensure that the doped atoms penetrate deep into the P-substrate to form a deep N-well.

[0133] Next, a shallow N drift region can be formed above the Deep n well region to share the electric field, increase resistance, and increase breakdown voltage. Implanted material: Phosphorus (P). Dose range: 10^12atoms / cm^2. Implantation energy: Medium energy (tens to hundreds of keV), ensuring that the depth of the doped layer is moderate.

[0134] S22, constructing a P-Body region on the source side of the N drift region and an N+ drain region on the top of the N drift region, and constructing an N+ source region and a P+ source region on the top of the P-Body region respectively.

[0135] In one embodiment, a P-Body region may be formed near the source of the N drift region to achieve the switching characteristics of the LDMOS. Implantation material: Boron (B). Dose range: 10^13-10^14atoms / cm^2. Implantation energy: relatively low energy (10-50keV) to form a shallow P region.

[0136] Next, N+ and P+ source regions are formed on top of the P-Body region to provide ohmic contact between the source and the P-Body. Implant material: Phosphorus (P) for N+ source, Boron (B) for P+ source. Dose range: N+: 10^15-10^16atoms / cm^2P+: 10^15-10^16atoms / cm^2Implant energy: Low energy (several keV) to ensure the formation of shallow, high-concentration doped regions.

[0137] At the end of the N drift region, an N+ region is formed as the drain region. Implanted material: phosphorus (P) or arsenic (As). Dose range: 10^15-10^16atoms / cm^2 Implantation energy: low energy (several keV), ensuring the formation of a shallow N+ highly doped region.

[0138] S23, constructing shallow trenches on both sides of the N+ source region, the P+ source region and the N+ drain region and injecting insulating material to form an isolation layer.

[0139] In one embodiment, a shallow trench isolation (STI) structure may be formed on both sides of the source and drain regions to enhance the isolation effect of the device. Material: silicon dioxide (SiO2) or other insulating materials. Process: realized by etching and filling, without involving ion implantation.

[0140] S24, after growing a gate oxide layer between the P-Body region and the N-drift region and depositing polysilicon to form a gate, annealing the wafer to obtain a DMOS unit.

[0141] A gate oxide is grown between the P-Body and N-drift regions, and polysilicon is deposited to form the gate. Materials: Silicon dioxide (SiO2) is used as the gate oxide, and polysilicon is used for the gate.

[0142] After ion implantation, the wafer is annealed to activate the doped atoms and repair the lattice damage caused by the implantation process. Temperature range: 800-1000°C. Time: tens of seconds to several minutes, depending on the annealing process (such as rapid thermal annealing RTA).

[0143] The "lateral diffusion" design of LDMOS allows current to flow laterally, which can effectively disperse the current and avoid the problem of heat concentration. This diffusion structure reduces the heat generation of power devices, thereby reducing heat dissipation requirements and heat loss. This structure enables LDMOS to operate stably at higher power without reducing efficiency and increasing power consumption due to heat problems.

[0144] At the same time, in order to improve area utilization, the folded structure of LDMOS can be used. Figure 4 and Figure 5 .

[0145] The embodiment of the present invention also provides a manufacturing device for a multi-computing power fusion control chip, see Figure 8 , showing a structural schematic diagram of a manufacturing device for a multi-computing power fusion control chip provided by an embodiment of the present invention.

[0146] Wherein, as an example, the manufacturing device of the multi-computing power fusion control chip may include:

[0147] The substrate processing module 801 is used to construct a plurality of deep N wells and a plurality of shallow trenches on the substrate after initially doping the starting wafer to construct the substrate, so as to separate the plurality of deep N wells by using the plurality of shallow trenches;

[0148] A cell construction module 802 is used to construct a PMOS cell, an NMOS cell and a DMOS cell in the deep N well respectively;

[0149] A metallization module 803, used for performing metallization processing on the PMOS unit, the NMOS unit and the DMOS unit, so as to connect the ports of the PMOS unit, the NMOS unit and the DMOS unit;

[0150] The packaging module 804 is used to package the PMOS unit, the NMOS unit and the DMOS unit after adding a passivation layer to obtain a multi-computing power fusion control chip.

[0151] The present invention also provides a manufacturing device for a DMOS unit. Fig. 9 , showing a schematic structural diagram of a DMOS unit manufacturing device provided by an embodiment of the present invention.

[0152] Wherein, as an example, the manufacturing device of the DMOS unit may include:

[0153] The drift region module 901 is used to form an N drift region in the deep N well after constructing the deep N well on the substrate of the wafer;

[0154] A construction area module 902 is used to construct a P-Body area on the source side of the N drift area and an N+ drain area on the top of the N drift area, and to construct an N+ source area and a P+ source area on the top of the P-Body area respectively;

[0155] An isolation layer construction module 903 is used to construct shallow trenches on both sides of the N+ source region, the P+ source region and the N+ drain region and inject insulating materials to form an isolation layer;

[0156] The annealing module 904 is used to anneal the wafer after growing a gate oxide layer and depositing polysilicon to form a gate between the P-Body region and the N-drift region to obtain a DMOS unit.

[0157] Those skilled in the art can clearly understand that, for the sake of convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0158] Furthermore, an embodiment of the present application also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method for manufacturing a multi-computing power fusion control chip as described in the above embodiment or the method for manufacturing a DMOS unit as described in the above embodiment.

[0159] Furthermore, an embodiment of the present application also provides a computer-readable storage medium, which stores a computer-executable program, and the computer-executable program is used to enable a computer to execute the manufacturing method of the multi-computing power fusion control chip as described in the above embodiment or the manufacturing method of the DMOS unit as described in the above embodiment.

[0160] It should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. When an element such as a layer, region or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on" or "above" another element, there is no intermediate element. It should also be understood that when an element is referred to as being "under" or "below" another element, it can be directly under or below the other element, or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly under" or "below" another element, there is no intermediate element. Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0161] Those skilled in the art will appreciate that the embodiments of the present application may also provide computer program products. Therefore, the present application may adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application may adopt the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program codes.

[0162] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), apparatuses, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0163] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0164] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0165] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A multi-computing power fusion control chip, characterized in that: The chip comprises: a P-type substrate layer, a DMOS unit, a PMOS unit, an NMOS unit, a bipolar unit, a first P-well region unit and a second P-well region unit; The DMOS unit, the PMOS unit, the NMOS unit, the bipolar unit, the first P-well unit and the second P-well unit are respectively arranged in shallow grooves in the P-type base layer; The DMOS unit, the first P-well unit, the NMOS unit, the PMOS unit, the second P-well unit and the bipolar unit are sequentially arranged in a horizontal direction.

2. The multi-computing power fusion control chip according to claim 1, characterized in that: The DMOS unit comprises: a first deep N well layer, a first Pbody layer, and a first Ndrift layer; The first Pbody layer and the first Ndrift layer are respectively disposed on the first deep N well layer, and the first Pbody layer and the first Ndrift layer are connected; The first Pbody layer is provided with a gate port and a source port, and the first Ndrift layer is provided with a drain port.

3. The multi-computing power fusion control chip according to claim 1, characterized in that: The DMOS unit comprises: a second deep N well layer, a second Pbody layer and two second Ndrift layers; The second Pbody layer and the two first Ndrift layers are respectively disposed on the second deep N well layer, and the second Pbody layer is respectively connected to the two second Ndrift layers; The second Pbody layer is provided with a gate port and a source port, and the second Ndrift layer is provided with a drain port.

4. The multi-computing power fusion control chip according to claim 1, characterized in that: The DMOS unit comprises: a third deep N well layer, two third Pbody layers and a third Ndrift layer; The two third Pbody layers and the third Ndrift layer are respectively disposed on the third deep N well layer, and the third Ndrift layer is respectively connected to the two third Pbody layers; The third Pbody layer is provided with a gate port and a source port, and the third Ndrift layer is provided with a drain port.

5. The multi-computing power fusion control chip according to any one of claims 1 to 4, characterized in that: The bipolar cell comprises: a fourth deep N-well layer, an Nwell layer, and a fourth Pbody layer; The Nwell layer and the fourth Pbody layer are respectively disposed on the fourth deep N well layer; The fourth Pbody layer is provided with a base port and an emitter port, and the Nwell layer is provided with a collector port.

6. The multi-computing power fusion control chip according to any one of claims 1 to 4, characterized in that: The PMOS unit comprises: a fourth Ndrift layer, wherein the fourth Ndrift layer is provided with a gate port, a source port, a drain port and a base port.

7. The multi-computing power fusion control chip according to any one of claims 1 to 4, characterized in that: The NMOS unit comprises a Pwell layer, wherein the Pwell layer is provided with a gate port, a source port, a drain port and a base port.

8. A method for manufacturing a multi-computing power fusion control chip, characterized in that: The method comprises: After initially doping the starting wafer to form a substrate, a plurality of deep N wells and a plurality of shallow trenches are constructed on the substrate, so that the plurality of deep N wells are spaced apart by the plurality of shallow trenches; Constructing a PMOS unit, an NMOS unit and a DMOS unit in the deep N-well respectively; Performing metallization processing on the PMOS unit, the NMOS unit and the DMOS unit so that ports of the PMOS unit, the NMOS unit and the DMOS unit are connected; After adding a passivation layer to the PMOS unit, the NMOS unit and the DMOS unit, they are packaged to obtain a multi-computing power fusion control chip.

9. A method for manufacturing a DMOS unit, characterized in that: The method comprises: After constructing a deep N well on a substrate of a wafer, an N drift region is formed in the deep N well; Constructing a P-Body region on the source side of the N drift region and an N+ drain region on the top of the N drift region, and constructing an N+ source region and a P+ source region on the top of the P-Body region respectively; Constructing shallow trenches on both sides of the N+ source region, the P+ source region and the N+ drain region and injecting insulating materials to form an isolation layer; After a gate oxide layer is grown between the P-Body region and the N-drift region and polysilicon is deposited to form a gate, the wafer is annealed to obtain a DMOS unit.

10. A manufacturing device for a multi-computing power fusion control chip, characterized in that: The method comprises: A substrate processing module, used for constructing a plurality of deep N wells and a plurality of shallow trenches on the substrate after initially doping the starting wafer to construct the substrate, so as to separate the plurality of deep N wells by using the plurality of shallow trenches; A cell construction module, used to construct a PMOS cell, an NMOS cell and a DMOS cell in the deep N-well respectively; A metallization module, used for performing metallization processing on the PMOS unit, the NMOS unit and the DMOS unit, so as to connect the ports of the PMOS unit, the NMOS unit and the DMOS unit; The packaging module is used to package the PMOS unit, the NMOS unit and the DMOS unit after adding a passivation layer to obtain a multi-computing power fusion control chip.

Images