Preparation method of nanometer transistor sensing platform and nanometer transistor sensing platform

Abstract

The invention provides a preparation method of a nanometer transistor sensing platform and the nanometer transistor sensing platform, and the method comprises the steps: attaching a first photoresist layer and depositing a sacrificial layer on a completed back gate device, enabling the first photoresist layer to cover a metal electrode, and enabling the sacrificial layer to cover the first photoresist layer and a channel region; removing the first photoresist layer and stripping the sacrificial layer covering the first photoresist layer so as to retain the sacrificial layer in the channel; depositing a passivation layer on the sacrificial layer in the metal electrode and the channel; attaching a second photoresist layer on the passivation layer to expose an area needing to be etched and removed; etching the passivation layer corresponding to the channel region and a part of the metal electrode; and removing the second photoresist layer, and removing the sacrificial layer in the channel. The sacrificial layer reserved in the channel region can greatly protect the channel material layer in the subsequent steps, so that the problem of photoresist residue in the traditional process is perfectly solved, and a more stable basis is provided for application of a biosensor and the like.

Description

Technical Field

[0001] The present invention relates to the field of field effect transistor biosensors, and in particular to a preparation method of a nano transistor sensing platform and a nano transistor sensing platform. Background Art

[0002] Semiconductor carbon nanotubes (CNTs) are ideal channel materials for ultra-sensitive field effect transistor (FET) biosensors due to their unique physical and chemical properties. Their atomic layer thickness enables them to maintain good electrical properties at the micro-nano scale, while also having excellent biocompatibility and size compatibility, which gives CNTs significant advantages in biosensor applications.

[0003] However, the passivation process in the current nano-transistor process still uses a photoresist process, and through characterization, it was found that the photoresist removal was not very clean and remained in the passivation channel. In terms of the impact on device performance, such residues will not only lead to a decline in device performance, but may also increase the hysteresis of the device, affecting its stability and sensitivity; from the perspective of the impact on later functionalization, residual photoresist may interfere with subsequent functionalization processes. Specifically, the binding of the probe to the channel surface site will be affected, reducing the success rate of modification. This problem is particularly important in biosensors because the binding efficiency of biomolecules is directly related to the sensitivity and accuracy of the sensor.

[0004] In order to improve the problem caused by the residual passivation glue, the inventor team of the applicant tried pure oxygen etching and ozone cleaning to improve the cleanliness of the channel surface, but these traditional plasma etching processes may cause serious damage to carbon nanotubes. The damage may manifest as structural changes in CNTs, decreased electron mobility, etc., which greatly affects the electrical performance of the device. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a method for preparing a nano-transistor sensing platform and a nano-transistor sensing platform to eliminate or improve one or more defects existing in the prior art.

[0006] In a first aspect, the present invention provides a method for preparing a nano-transistor sensing platform, the method comprising the following steps:

[0007] The step of depositing a sacrificial layer is as follows: attaching a first photoresist layer and depositing a sacrificial layer on the completed back-gate device, wherein the back-gate device comprises a substrate, a channel material layer and a metal electrode, the channel material layer is attached to a surface of the substrate, the metal electrode is attached to the channel material layer, the metal electrode does not completely cover the channel material layer and forms a channel region of the back-gate device; the first photoresist layer covers the metal electrode, and the sacrificial layer covers the first photoresist layer and the channel region; then removing the first photoresist layer and stripping off the sacrificial layer covering the first photoresist layer to retain the sacrificial layer in the channel region;

[0008] Depositing a passivation layer step: depositing a passivation layer on the metal electrode and the sacrificial layer in the channel region;

[0009] Etching step: attaching a second photoresist layer on the passivation layer to expose the area to be etched and removed; etching the passivation layer corresponding to the channel area and part of the metal electrode;

[0010] Cleaning step: removing the second photoresist layer and removing the sacrificial layer in the channel area.

[0011] In some embodiments, a double-layer resist process is used to attach the first photoresist layer in the step of depositing the sacrificial layer and / or to attach the second photoresist layer in the etching step.

[0012] In some embodiments, the sacrificial layer is a thin film structure of aluminum, yttrium or aluminum+yttrium, and its thickness does not exceed 100 nm.

[0013] In some embodiments, the material of the channel material layer is any one of carbon nanotubes, silicon, silicon carbide, silicon nitride, gallium nitride, IGZO, gallium arsenide and TMDs.

[0014] In some embodiments, the passivation layer is made of any one of Parylene film, silicon nitride, aluminum nitride, silicon dioxide, fluorinated polymer, polyimide and PMMA; when the passivation layer is made of Parylene film, its thickness does not exceed 20 μm.

[0015] In some embodiments, in the etching step, the etching time of the Parylene film used as the passivation layer is 400-500s, and the etching power is 50-100W.

[0016] In some embodiments, in the etching step, the layer is patterned by dry etching.

[0017] In some embodiments, after the step of depositing the passivation layer and before the step of etching, the Parylene film is subjected to heat treatment, mechanical treatment, plasma treatment, chemical treatment or surface modification to improve its physical or chemical properties.

[0018] In some embodiments, in the step of depositing a sacrificial layer, the first photoresist layer is removed and the sacrificial layer covering the first photoresist layer is stripped by placing the device in a stripping solution;

[0019] In the cleaning step, a cleaning solution is used to remove the second photoresist layer, and a sacrificial layer cleaning solution is used to remove the sacrificial layer.

[0020] In a second aspect, the present invention also provides a nano-transistor sensing platform manufactured by the above-mentioned preparation method.

[0021] In some embodiments, the nano-transistor sensing platform includes a silicon oxide substrate, a carbon nanotube, a metal electrode and a passivation layer arranged layer by layer, the passivation layer covers the silicon oxide substrate and a portion of the metal electrode, and the carbon nanotube has an exposed channel region.

[0022] The preparation method of the present invention uses precise layered deposition and etching technology. The sacrificial layer retained in the channel greatly reduces the contact between the channel area and the passivation photoresist, and can protect the channel material layer in subsequent steps (especially during the etching of the passivation layer). It perfectly solves the problem of photoresist residue in traditional processes, improves the performance and reliability of the nano-transistor sensing platform, and provides a more stable foundation for applications such as biosensors.

[0023] Additional advantages, purposes, and features of the present invention will be described in part in the following description, and will become apparent to those skilled in the art after studying the following, or may be learned from the practice of the present invention. The purposes and other advantages of the present invention may be achieved and obtained by the structures specifically indicated in the specification and the accompanying drawings.

[0024] Those skilled in the art will appreciate that the objectives and advantages that can be achieved with the present invention are not limited to the above specific description, and the above and other objectives that can be achieved by the present invention will be more clearly understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention. The components in the drawings are not drawn to scale, but are only for illustrating the principles of the present invention. In order to facilitate the illustration and description of some parts of the present invention, the corresponding parts in the drawings may be enlarged, that is, they may become larger relative to other components in the exemplary device actually manufactured according to the present invention. In the drawings:

[0026] Figure 1 It is a block diagram of a method for preparing a nano-transistor sensing platform in one embodiment of the present invention.

[0027] Figure 2-Figure 9 Schematic diagram of the preparation steps of a nano-transistor sensing platform in one embodiment of the present invention.

[0028] Fig.10 The figure is a comparison of electron microscope images of the device channel surface obtained by the prior art and the preparation method of the present invention.

[0029] Fig.11 It is a comparison chart of the lds-Vgs table of the device made by the prior art and the preparation method of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments and the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0031] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0032] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, elements, steps or components, but does not exclude the presence or addition of one or more other features, elements, steps or components.

[0033] It should also be noted that, unless otherwise specified, the term “connection” herein may refer not only to a direct connection but also to an indirect connection involving an intermediate.

[0034] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0035] During the preparation process of the ultra-sensitive field effect transistor sensor in the prior art, organic polymers are easily left on the carbon nanotubes (channels). The organic polymer generally refers to a material that is not completely removed during the preparation or processing process. The organic polymer may include photoresist, polymer insulating layer, functionalized polymer and auxiliary agents or additives. Photoresist is used to form patterns during the photolithography process. If it is not completely removed, it may remain in the channel. Polymer insulating layers such as polytetrafluoroethylene (PTFE) or polyimide (PI) are used for electrical insulation and protection, but may leave residues in some cases. Auxiliary agents or additives such as plasticizers or stabilizers, substances added during the polymer preparation process, may leave residues in the channel.

[0036] If conventional gas etching and ozone cleaning techniques are used, the carbon nanotubes in the sensing channel may be damaged, affecting their electrical properties and stability.

[0037] The growth temperature of the commonly used passivation layers such as silicon nitride and silicon oxide is too high, which may cause thermal damage to the carbon nanotubes and their substrates, affecting the performance of the device. The thermal expansion coefficients and chemical properties of these materials do not match those of carbon-based materials, which may lead to interface stress and delamination, reducing the reliability of the device. Silicon nitride and silicon oxide deposited by magnetron sputtering may have insufficient insulation under certain conditions, affecting the electrical performance of the device. The positive photoresist passivation process is not durable enough in the face of acids, alkalis and organic solvents, which may cause the passivation layer to fail and affect the long-term stability of the device. Although the negative photoresist process can provide better resolution, the common residue problem may affect subsequent processes and cause device performance to deteriorate.

[0038] In order to solve or alleviate the problem of residual photoresist or passivation glue in the channel in the prior art, the present invention provides a nano transistor preparation process containing a protective layer + Parylene passivation layer etching window, which reduces the influence of photoresist residue in the process, keeps the channel in a relatively clean state, and ensures that the channel material layer in the channel is protected when the passivation window is etched.

[0039] In a first aspect, the present invention provides a method for preparing a nano-transistor sensing platform, such as Figure 1 As shown, the method comprises the following steps:

[0040] S10, a step of depositing a sacrificial layer: attaching a first photoresist layer and depositing a sacrificial layer on the completed back-gate device, wherein: Figure 2As shown, the back-gate device includes a substrate, a channel material layer and a metal electrode; the channel material layer is attached to a surface of the substrate, the metal electrode is attached to the channel material layer, the metal electrode does not completely cover the channel material layer and forms a channel region of the back-gate device; the first photoresist layer covers the metal electrode, and the sacrificial layer covers the first photoresist layer and the channel region; then the first photoresist layer is removed and the sacrificial layer covering the first photoresist layer is stripped off to retain the sacrificial layer in the channel region.

[0041] In the above steps, the completed back-gate device includes a substrate ( Figure 2 Silicon oxide substrate in), channel material layer ( Figure 2 carbon nanotubes in the Figure 2 The substrate is used as the foundation of the entire device; the channel material layer can be made of carbon nanotubes (CNTs); the channel region is the exposed region of the carbon nanotubes not covered by the metal electrode, which can ensure the passage of current; the metal electrode is an electrode used to connect to the carbon nanotubes. A first photoresist layer is attached to the metal electrode, which is used to protect the metal electrode. A sacrificial layer is deposited on the first photoresist layer, covering the entire channel region and the photoresist layer. The first photoresist layer is removed, and the sacrificial layer covering it is peeled off, in order to retain the sacrificial layer in the channel. The sacrificial layer retained in the channel can protect the carbon nanotubes in subsequent steps.

[0042] S20, depositing a passivation layer: depositing a passivation layer on the metal electrode and the sacrificial layer in the channel region. The purpose of depositing a passivation layer is to prevent the external environment from affecting the carbon nanotubes and improve the stability and durability of the device.

[0043] S30, etching step: attaching a second photoresist layer on the passivation layer to expose the area to be etched and removed; etching the passivation layer corresponding to the channel and part of the metal electrode. In this step, attaching a second photoresist layer on the passivation layer to protect the area that does not need to be etched. The specific area in the passivation layer is removed by the etching process, mainly targeting the channel and part of the metal electrode, to achieve the required electrical contact.

[0044] S40, cleaning step: removing the second photoresist layer and the sacrificial layer in the channel region. In this step, finally, the second photoresist layer and the sacrificial layer in the channel are removed to ensure the cleanliness of the channel region, laying a foundation for subsequent functionalization steps and practical applications.

[0045] In the above embodiments, the preparation method of the present invention uses precise layered deposition and etching technology, and the sacrificial layer retained in the channel greatly reduces the contact between the carbon nanotube channel and the passivation photoresist, which can protect the carbon nanotubes in subsequent steps (especially in the process of etching the Parylene film), perfectly solves the problem of photoresist residue in traditional processes, improves the performance and reliability of the nano-transistor sensing platform, and provides a more stable foundation for applications such as biosensors.

[0046] In some embodiments, the first photoresist layer attached in the step of depositing the sacrificial layer and / or the second photoresist layer attached in the etching step adopts a double-layer glue process. The double-layer glue process can achieve higher resolution in the exposure process by using photoresists of different thicknesses and types, making the details of the pattern more accurate and suitable for the production of complex structures. The double-layer glue process can obtain better control in the stripping process, ensuring that the lower material (such as the sacrificial layer, the metal electrode or the Parylene film) will not be damaged during stripping, reducing the stripping residue. The upper layer glue can protect the lower pattern in etching or other processing steps to avoid damage to the lower pattern due to chemical corrosion or physical damage. The thickness and material properties of the double-layer glue can be adjusted according to different process requirements to adapt to different exposure and etching conditions, thereby optimizing the overall manufacturing process. Through a suitable double-layer glue structure, the subsequent cleaning and processing steps can be simplified, and the repeatability and stability of the process can be improved. Due to the enhanced protection of the lower structure and the improved accuracy of the pattern, the use of the double-layer glue process can effectively improve the yield of the manufacturing process.

[0047] In some embodiments, the sacrificial layer is a thin film structure of aluminum, yttrium or aluminum + yttrium, and its thickness does not exceed 100nm. Aluminum and yttrium have good selectivity in certain chemical etching processes, so that the sacrificial layer can be effectively removed in subsequent processes without damaging the carbon nanotubes below. Controlling the thickness of the sacrificial layer within 100nm helps to improve the overall performance of the device, reduce the impact on the upper material, and also helps to maintain the miniaturization of the device. Aluminum, yttrium and their alloys have good thermal stability, can maintain structural integrity during high-temperature treatment, and reduce the risk of thermal damage. Aluminum, yttrium and their alloys as conductors can provide good electrical conductivity in certain scenarios. In practical applications, the compatibility of the selective etching solution of the sacrificial layer, the interface characteristics with the underlying material, and the impact of subsequent processes on the overall device performance can also be considered.

[0048] In some embodiments, the material of the channel material layer is any one of carbon nanotubes, silicon, silicon carbide, silicon nitride, gallium nitride, IGZO, gallium arsenide and TMDs. Among them, the selection of the channel material layer may depend on the performance requirements, manufacturing process and application scenarios of the device. For example, carbon nanotubes have excellent electronic conductivity, mechanical strength and thermal conductivity. The two-dimensional characteristics of carbon nanotubes also make them exhibit good electrical conductivity at the nanoscale, and can be widely used in low-power, high-frequency, high-performance field effect transistors (FETs), especially carbon nanotube FETs (CNT-FETs). Silicon is the most common semiconductor material, and the mature process and good processability of silicon materials make it the mainstream material for electronic devices. Silicon carbide (SiC) is a wide bandgap semiconductor material with excellent high temperature, high pressure and high frequency performance, suitable for electronic devices in high power, high temperature and harsh environments. Silicon nitride (Si3N4) is a wide bandgap semiconductor with good chemical stability, mechanical strength and thermal stability, and can be used as an isolation layer, protective layer and material for high temperature and high power devices. Gallium nitride (GaN) is a wide bandgap semiconductor material with high breakdown electric field, high electron mobility and high frequency performance, and can be used in high-power and high-frequency electronic devices. IGZO (Indium Gallium Zinc Oxide) is an oxide semiconductor material composed of indium (Indium), gallium (Gallium) and zinc (Zinc). It is a transparent metal oxide semiconductor with high electron mobility and good optical transparency. It can be used in display technology, touch screens, OLED displays and other electronic devices. Gallium arsenide (GaAs) is a III-V semiconductor material with high electron mobility, high operating frequency and low power consumption. It can be used in high-speed, radio frequency and optoelectronic devices. TMDs (Transition Metal Dichalcogenides) are a class of two-dimensional materials with strong interlayer interactions and excellent electronic properties. They are suitable for manufacturing low-power and high-performance electronic devices. Common TMDs include molybdenum disulfide (MoS2), tungsten disulfide (WS2), etc. By selecting the appropriate channel material according to the process, device requirements and material properties, the performance of the device can be optimized. The channel material in the embodiment of the present invention is preferably carbon nanotubes.

[0049] In some embodiments, the passivation layer uses any one of Parylene film, silicon nitride, aluminum nitride, silicon dioxide, fluorinated polymer, polyimide and PMMA. The choice of passivation layer material may depend on the working environment of the device, the required chemical stability, physical properties and application requirements. Parylene is a polymer film with a very uniform thickness and high chemical stability. Its high corrosion resistance and excellent electrical insulation properties make it very suitable for protecting electronic devices in high humidity and corrosive environments. Silicon nitride (Si3N4) is an inorganic material with good mechanical strength, thermal stability and chemical stability; when used as a passivation layer, silicon nitride can effectively isolate the impact of the external environment on the device. Aluminum nitride (AlN) is a high thermal conductivity material that can maintain good stability in a high temperature environment and can be used as a high-temperature passivation material, especially when electronic devices need to dissipate heat. Silicon dioxide (SiO2) is a common insulating material with good electrical insulation, chemical stability and thermal stability. Fluorinated polymers (such as PTFE, polytetrafluoroethylene) have very low surface energy, excellent chemical stability and electrical insulation, and are particularly suitable for environments that require waterproofing, anti-fouling and chemical corrosion resistance. Polyimide (PI) is a high-performance plastic with good thermal stability, mechanical strength and electrical insulation properties, and can be used in environments that require high temperature resistance and chemical corrosion resistance. PMMA (polymethyl methacrylate) is a transparent plastic with good optical and mechanical properties. When selecting a passivation layer material, it is necessary to comprehensively consider the device's operating environment, temperature range, chemical stability, electrical insulation, and protection requirements from the external environment. Each material has its specific advantages and application areas. Selecting the right passivation layer material can help improve the performance and reliability of the device.

[0050] Optionally, when the passivation layer is made of Parylene film, its thickness does not exceed 20μm. Parylene is a polymer with good insulating properties that can effectively isolate current and prevent short circuits and leakage. Parylene has good tolerance to a variety of chemicals and is suitable for use in humid or corrosive environments. The deposition process of Parylene is usually vapor deposition, which can form a uniform and seamless film, suitable for devices with complex geometries. Controlling the thickness within 20μm can protect the device while avoiding negative impacts on device performance and adapting to miniaturized design requirements. Parylene can still maintain good mechanical and electrical properties at higher temperatures and is suitable for special temperature treatment processes. In practical applications, when selecting Parylene as a passivation layer, its compatibility with other materials, the optimization of the deposition process, and the influence of subsequent treatment on the performance of the film layer can also be considered, or other materials can be selected as the passivation layer, such as other polymer materials (polyimide, etc.), fluoropolymers, metal oxides, carbon-based materials or self-assembled monolayers.

[0051] In some embodiments, in the etching step, the etching time of the Parylene film used as the passivation layer is 400-500s, and the etching power is 50-100W. The etching time of 400-500 seconds can ensure that the Parylene film is fully removed, especially in the case of thicker film layers. Too long etching time may cause damage to the underlying material, so it is necessary to optimize according to the specific film thickness and the characteristics of the etching gas used. The etching power of 50-100W can provide enough energy to ensure that Parylene is effectively removed in the reaction chamber. Higher power can increase the etching rate, but it may also cause greater plasma damage or thermal damage to the underlying material, so it is necessary to balance the use of specific power. In addition, it is also necessary to consider etching gas and substrate temperature. Selecting a suitable etching gas (such as oxygen, fluoride, etc.) has an important influence on the etching rate and selectivity. Maintaining an appropriate substrate temperature can reduce thermal damage to the film layer and improve etching uniformity.

[0052] In some embodiments, in the etching step, the layer is patterned by dry etching (such as plasma etching or reactive ion etching, RIE). Dry etching can achieve high-resolution patterning and is suitable for micron and submicron structure production. By selecting appropriate etching gases and parameters, high-selective etching of different materials can be achieved, reducing damage to underlying materials. The dry etching process can be carried out in a vacuum environment, avoiding potential corrosion of the material by liquid etchants and reducing the impact on other sensitive layers. Dry etching can perform good plasma control, and can accurately control the etching rate and shape to meet the requirements of complex geometric structures.

[0053] The process of dry etching: photoresist is applied to the surface to be etched, and then exposed and developed to form the desired pattern. The sample is placed in the etching equipment, and the chemical reaction generated by plasma is used to remove the material. According to the set power and time, the desired structure is accurately etched. After the etching is completed, the photoresist is removed and the integrity and accuracy of the pattern are checked.

[0054] In some embodiments, after the step of depositing the passivation layer and before the step of etching, the Parylene film is subjected to heat treatment, mechanical treatment, plasma treatment, chemical treatment or surface modification to improve its physical or chemical properties. Heat treatment can improve the degree of cross-linking and stability of the film layer by heating, improve the mechanical strength and thermal stability of the Parylene film, remove the residual stress in the film, and improve the density of the film. Mechanical treatment is to improve the surface flatness and smoothness of the film layer by physical grinding or polishing, enhance the adhesion of the film and reduce the surface roughness, which is conducive to the smooth progress of subsequent processes (such as coating or etching). Plasma treatment can modify the surface properties of the film by using the chemical activity of plasma, which can improve the hydrophilicity or hydrophobicity of the film, improve the interfacial adhesion with other materials, and remove surface contaminants. Chemical treatment can use chemical solutions or gases to clean or modify the surface, and can change the chemical composition of the surface through chemical reactions to improve the corrosion resistance and other physical properties of the film. Surface modification can enhance the functionality of the membrane through self-assembled monolayers (SAMs) or other surface modification techniques, which can give the membrane specific functions such as anti-fouling, antibacterial or improved wettability to meet specific application requirements.

[0055] In some embodiments, in the step of depositing a sacrificial layer, the first photoresist layer is removed and the sacrificial layer covering the first photoresist layer is stripped by placing the device in a stripping solution. For example, the device can be specifically placed in a stripping solution, which can effectively remove the first photoresist layer. The stripping solution can contain an organic solvent (such as acetone or isopropanol) that can dissolve the photoresist to ensure its complete removal. During the stripping process, the sacrificial layer will also be affected, thereby facilitating removal. Further, a suitable sacrificial material is selected so that it can be effectively dissolved in the stripping solution, for example, a polymer soluble in a specific solvent can be used.

[0056] In some embodiments, in the cleaning step, a cleaning solution is used to remove the second photoresist layer, and a sacrificial layer cleaning solution is used to remove the sacrificial layer. The selection of the cleaning solution should be based on the type of photoresist to ensure its effectiveness and compatibility with the underlying material. The sacrificial layer cleaning solution is used to remove the deposited sacrificial layer, ensuring that the layer is completely removed to avoid interference with subsequent steps. The chemical composition of the cleaning solution should match the characteristics of the sacrificial layer material to achieve a fast and thorough cleaning effect.

[0057] To further explain the method for preparing the nano-transistor sensing platform in the embodiment of the present invention, Figure 2-Figure 9 A possible implementation method is described in detail.

[0058] refer to Figure 2 , Figure 2The nano transistor back-gate device is manufactured, and the back-gate device includes a silicon oxide substrate, a carbon nanotube and a deposited metal (ie, a metal electrode). Figure 3 In the step of depositing the sacrificial layer, the process of combining ultraviolet exposure and depositing the sacrificial layer metal (aluminum, yttrium or aluminum + yttrium) can effectively realize the formation of the desired structure. In more detail, a double-layer glue process is used to expose the layer to be stripped. The bottom glue can use a photoresist with moderate thickness to provide a good substrate to ensure the stability of the subsequent photolithography layer. The top glue can use a thinner photoresist as a protective layer to enhance the resolution and image quality. The photoresist is coated on the surface of the device and exposed by ultraviolet light. During the exposure, a specific mask is used to define the layer to be stripped. After exposure, development is performed to remove the unexposed or exposed glue layer to form the desired pattern.

[0059] The metal of the deposited sacrificial layer in the embodiment of the present invention can be aluminum, yttrium or aluminum + yttrium, which has good depositability and subsequent removability. The deposition process can use physical vapor deposition (PVD), chemical vapor deposition (CVD) and other technologies to uniformly deposit the metal layer on the developed photoresist pattern. Ensure that the thickness of the metal during the deposition process meets the requirements of subsequent processes. Reference Figure 4 ,After the metal deposition is completed, the photoresist is removed by stripping or chemical cleaning to expose the deposited metal layer and leave only the sacrificial layer in the trench.

[0060] refer to Figure 5 , the device with the sacrificial layer stripped off is placed in the Parylene coating equipment to deposit the Parylene film, which needs to be controlled within 20um. It is understood that the Parylene film can cover the entire upper surface of the device. The film deposition step may include cleaning the device, equipment calibration, etc. to improve the adhesion and uniformity of the Parylene film and ensure the stability and consistency of the deposition process. Parylene film can be deposited by chemical vapor deposition (CVD) process. The process involves heating the Parylene precursor (such as Parylene N, C or D) to vaporization and then depositing it on the device surface in a vacuum environment. During the deposition process, the deposition rate and time need to be monitored to ensure that the final film thickness is controlled within 20μm. The desired thickness can be achieved by adjusting the gas flow, temperature and deposition time. Parylene film has excellent mechanical strength, chemical corrosion resistance and good electrical insulation properties, and evenly covers the entire upper surface of the device, including complex structures and fine features, ensuring good protection and insulation properties.

[0061] refer to Figure 6After the growth of Parylene is completed, a double-layer glue process is used to expose the layer to be etched, exposing the metal electrode of the device (exposing the area to be etched and removed). Before photolithography, ensure that the Parylene surface is clean and free of pollution to enhance the adhesion of the photoresist. Select a suitable photoresist (such as a primer and a top glue) and apply it evenly on the Parylene surface. Use spin coating to evenly apply the bottom layer of photoresist. A thicker photoresist can be selected to provide support. Spin-coat a thinner photoresist to increase resolution and detail retention. Use a mask to align the exposure device to define the area to be etched (part of the metal electrode). Ensure that the exposure time and light intensity are appropriate to obtain a clear pattern. Immerse the exposed device in a developer to remove the unexposed or exposed photoresist (depending on the type of glue used) to form the desired pattern. According to the characteristics of Parylene, choose dry etching (such as plasma etching) or wet etching to ensure that the Parylene layer can be accurately removed without damaging the underlying structure.

[0062] refer to Figure 7 After the photolithography and development of the Parylene film are completed, it is then placed in an ICP (inductively coupled plasma) etching device, and the Parylene film is etched using a fluorine-based gas combination. The etching time is controlled within 400s-500s, and the etching power can be controlled between 50W-100W. Specifically, ensure that the ICP etching equipment operates normally, and perform necessary preheating and cleaning to avoid any contamination. Select a suitable fluorine-based gas combination, commonly used are SF6, CF4 or CHF3, etc., and determine the specific proportion according to the etching requirements. Set the etching time between 400 seconds and 500 seconds, and adjust it according to the thickness of the Parylene film and the required etching depth. Set the etching power between 50W and 100W. Higher power can increase the etching rate, but it needs to be monitored to prevent over-etching or damage to the underlying material. During the etching process, ensure that a vacuum is formed in the chamber to maintain the stability of the plasma. Start the ICP etching program and monitor the gas flow and etching power to ensure that they are within the set range. During the etching process, monitor the etching rate and plasma status in real time, and adjust the gas flow or power if necessary. When the set time is up, turn off the gas and power to end the etching process. Wait for the chamber pressure to return to normal pressure before removing the sample safely.

[0063] refer to Figure 8 and Fig. 9After the etching of the Parylene device is completed, the subsequent cleaning step is crucial. After that, the etching mask glue is removed with a cleaning solution, and the sacrificial layer is removed with a sacrificial layer cleaning solution, and the Parylene device is ready. Select a suitable cleaning solution according to the type of photoresist used, commonly used ones include degumming agents or acetone, etc. Soak the device in the cleaning solution, or wipe it gently with a dust-free cloth to remove the residual mask glue. Adjust the immersion time according to the type of glue and the residual situation, usually a few minutes to more than ten minutes. According to the sacrificial layer material used, select a suitable removal liquid, such as hydrofluoric acid (HF) for removing the aluminum layer, and use chemical solvents to remove the yttrium layer. Place the device in the sacrificial layer cleaning solution to ensure complete immersion. Control the cleaning time to avoid excessive corrosion. During the cleaning process, check the removal effect regularly to ensure that the sacrificial layer is completely removed.

[0064] In a second aspect, the present invention also provides a nano-transistor sensing platform manufactured by the above-mentioned preparation method.

[0065] In some embodiments, the nano-transistor sensing platform includes a silicon oxide substrate, a carbon nanotube, a metal electrode and a passivation layer arranged layer by layer, the passivation layer covers the silicon oxide substrate and a portion of the metal electrode, and the carbon nanotube has an exposed channel region.

[0066] In this embodiment, carbon nanotubes are used as active sensing materials with excellent conductivity and sensitivity. The channel region of the carbon nanotubes is designed to be exposed, which is convenient for interaction with the substance to be measured and improves the response capability of the sensor. Metal electrodes are arranged at both ends of the carbon nanotubes for applying voltage and reading signals. The metal electrodes can ensure good contact performance to reduce contact resistance. The passivation layer covers the silicon oxide substrate and part of the metal electrode to play a protective and stabilizing role. The passivation layer can reduce the influence of environmental factors on the sensing performance, such as interference from humidity and impurities.

[0067] The exposed carbon nanotube channel region enhances the contact with the analyte, thereby improving the sensing sensitivity. The setting of the passivation layer can effectively reduce the impact of the external environment on the performance of the device, and increase its stability and reliability. This nano-transistor sensing platform has broad application potential in environmental monitoring, biosensing and gas detection.

[0068] like Fig.10 As shown, Fig.10 (a) is an electron microscope image of the channel surface of the Parylene device in the prior art without etching the aluminum sacrificial layer, and it can be seen that there are many residues on the surface; Fig.10 (b) is an electron microscope image of the channel surface of the Parylene device after etching with an aluminum sacrificial layer. It can be seen that the surface is very clean and the residues are all etched away by the aluminum sacrificial layer.

[0069] like Fig.11 As shown, Fig.11 (a) is the lds-Vgs table of the Parylene device etched without using the aluminum sacrificial layer (using the photoresist process as the passivation layer) in the prior art. Wherein, lds is the drain-source current (Drain-Source Current), in amperes (A). Vgs is the gate-source voltage (Gate-Source Voltage), in volts (V). Gatel is the gate voltage, which is usually used to describe the external voltage of the control gate. It can be seen that the hysteresis of the Parylene device etched using the photoresist process as the passivation layer in the prior art is very large.

[0070] Fig.11 (b) and Fig.11 (c) is the lds-Vgs table of the Parylene device after etching the aluminum sacrificial layer. It can be seen that the overall performance of the device has been greatly improved, and its hysteresis can basically reach 0mV.

[0071] According to the method for preparing the nano-transistor sensing platform and the nano-transistor sensing platform in the embodiments of the present invention, the technical effects that can be obtained include at least:

[0072] (1) The preparation method of the present invention uses precise layered deposition and etching technology. The sacrificial layer retained in the channel greatly reduces the contact between the carbon nanotube channel and the passivation photoresist, which can protect the carbon nanotubes in subsequent steps (especially in the process of etching the Parylene film), perfectly solving the problem of photoresist residue in traditional processes, improving the performance and reliability of the nano-transistor sensing platform, and providing a more stable foundation for applications such as biosensors.

[0073] (2) The present invention achieves the passivation effect while avoiding adding additional process steps through the mutual compatibility of the sacrificial layer process, the passivation process and the etching process; this process integration improves manufacturing efficiency and simplifies the overall process.

[0074] (3) The performance of the nano-transistor sensing platform prepared by the present invention is significantly improved, and the hysteresis phenomenon is greatly reduced, ensuring the stability and response speed of the device. At the same time, the process effectively prevents the damage and shedding of carbon nanotubes, reduces the organic residues on the channel surface, thereby improving the reliability and service life of the sensor.

[0075] (4) The present invention optimizes the production and application process of Parylene, reducing material and processing costs; this makes the nanotransistor sensing platform more economically feasible and suitable for large-scale application and commercial promotion.

[0076] It should be clear that the present invention is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present invention.

[0077] In the present invention, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with features of other embodiments or replace features of other embodiments.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a nano-transistor sensing platform, characterized in that: The method comprises the following steps: The step of depositing a sacrificial layer is as follows: attaching a first photoresist layer and depositing a sacrificial layer on the completed back-gate device, wherein the back-gate device comprises a substrate, a channel material layer and a metal electrode, the channel material layer is attached to a surface of the substrate, the metal electrode is attached to the channel material layer, the metal electrode does not completely cover the channel material layer and forms a channel region of the back-gate device; the first photoresist layer covers the metal electrode, and the sacrificial layer covers the first photoresist layer and the channel region; then removing the first photoresist layer and stripping off the sacrificial layer covering the first photoresist layer to retain the sacrificial layer in the channel region; Depositing a passivation layer step: depositing a passivation layer on the metal electrode and the sacrificial layer in the channel region; Etching step: attaching a second photoresist layer on the passivation layer to expose the area to be etched and removed; etching the passivation layer corresponding to the channel area and part of the metal electrode; Cleaning step: removing the second photoresist layer and removing the sacrificial layer in the channel area.

2. The method for preparing the nano-transistor sensing platform according to claim 1, characterized in that: The first photoresist layer is attached in the step of depositing the sacrificial layer and / or the second photoresist layer is attached in the etching step by using a double-layer resist process.

3. The method for preparing the nano-transistor sensing platform according to claim 1, characterized in that: The sacrificial layer is a thin film structure of aluminum, yttrium or aluminum + yttrium, and its thickness does not exceed 100nm; or, The material of the channel material layer is any one of carbon nanotubes, silicon, silicon carbide, silicon nitride, gallium nitride, IGZO, gallium arsenide and TMDs.

4. The method for preparing the nano-transistor sensing platform according to claim 1, characterized in that: The passivation layer is any one of Parylene film, silicon nitride, aluminum nitride, silicon dioxide, fluorinated polymer, polyimide and PMMA; When the passivation layer is made of Parylene film, its thickness does not exceed 20 μm.

5. The method for preparing the nano-transistor sensing platform according to claim 4, characterized in that: In the etching step, the etching time of the Parylene film used as the passivation layer is 400-500s, and the etching power is 50-100W.

6. The method for preparing the nano-transistor sensing platform according to claim 4, characterized in that: After the step of depositing the passivation layer and before the step of etching, the Parylene film is subjected to heat treatment, mechanical treatment, plasma treatment, chemical treatment or surface modification to improve its physical or chemical properties.

7. The method for preparing the nano-transistor sensing platform according to claim 1, characterized in that: In the etching step, a dry etching method is used to graphically manufacture the layer.

8. The method for preparing the nano-transistor sensing platform according to claim 1, characterized in that: In the step of depositing a sacrificial layer, the first photoresist layer is removed and the sacrificial layer covering the first photoresist layer is stripped by placing the device in a stripping solution; In the cleaning step, a cleaning solution is used to remove the second photoresist layer, and a sacrificial layer cleaning solution is used to remove the sacrificial layer.

9. A nano-transistor sensing platform prepared by the preparation method according to any one of claims 1 to 8.

10. The nano-transistor sensing platform according to claim 9, characterized in that: The nano-transistor sensing platform comprises a silicon oxide substrate, a carbon nanotube, a metal electrode and a passivation layer which are arranged layer by layer. The passivation layer covers the silicon oxide substrate and a part of the metal electrode, and the carbon nanotube has an exposed channel region.

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