Read / write acceleration methods, devices, storage controller chips, and storage media

Abstract

This application discloses a read / write acceleration method, apparatus, storage control chip, and storage medium. The method includes: processing multiple operation instructions according to preset configuration rules to obtain a multi-transfer operation instruction table; storing the multi-transfer operation instruction table in a static random access memory (SRAM); reading the multi-transfer operation instruction table and loading the operation instructions one by one to complete the Flash read / write operation. This application achieves Flash read / write by using the MT mode. Compared to the ST mode, the generated multi-transfer operation instruction table is stored in the SRAM. The NFCMU module managing the Flash inside the main controller can directly access the SRAM to read and load the multi-transfer operation instruction table, eliminating the need for additional CPU time to execute corresponding firmware code for reading and loading, thereby accelerating the processing of each Flash read / write operation by the main controller.

Description

Technical Field

[0001] This invention relates to the field of flash memory technology, and in particular to a read / write acceleration method, apparatus, storage control chip, and storage medium. Background Technology

[0002] NAND Flash (hereinafter referred to as Flash) is the most mainstream storage medium today and is widely used in the manufacture of various types of storage products, such as USB flash drives, SD cards, and SSDs (solid-state drives). Storage products include storage controller chips (hereinafter referred to as controllers), Flash, and PCBs. The controller runs firmware that manages the Flash to store data, while the PCB is the substrate that provides electrical connection between the controller and the Flash.

[0003] The read / write performance of storage products is positively correlated with their price; higher performance generally means a higher price. The read / write performance of storage products is affected by the controller, Flash memory, and firmware. In related technologies, each time the Flash memory performs a read / write task, the controller needs to configure a single transfer instruction (ST) to execute the task. In ST mode, because the controller's CPU access registers are used to configure the instruction, and the CPU execution of the code takes time, this directly impacts the Flash memory's read / write performance. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a read / write acceleration method, apparatus, storage control chip, and storage medium that can improve the read / write performance of Flash memory. A first aspect of this application provides a read / write acceleration method, comprising:

[0005] Multiple operation instructions are processed according to preset configuration rules to obtain a multi-transmission operation instruction table;

[0006] Store the multitransmission operation instruction table in the static random access memory area;

[0007] The multi-transmission operation instruction table is read, and the operation instructions in the multi-transmission operation instruction table are loaded one by one to complete the read and write operation on the Flash.

[0008] In one preferred embodiment, the step of processing multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table includes:

[0009] When the DMA processes the current batch of data, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transfer operation instruction table, which is used for the next batch of data processing.

[0010] In one preferred embodiment, the step of processing multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table includes:

[0011] Read the operation information from the host and determine the required operation instructions based on the operation information;

[0012] The multiple operation instructions are sorted according to the operation order of the operation information;

[0013] Based on the sorting results, multiple operation instructions are combined, and an operation end flag is added at the end to obtain a multi-transmission operation instruction table.

[0014] In one preferred embodiment, the operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor and the higher 4 bits represent the instruction information.

[0015] A second aspect of this application provides a read / write acceleration device, comprising:

[0016] The configuration module is used to process multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table;

[0017] The storage module is used to store the multi-transmission operation instruction table in the static random access memory area;

[0018] The operation module is used to read the multi-transmission operation instruction table and load the operation instructions in the multi-transmission operation instruction table one by one to complete the read and write operations on the Flash.

[0019] In one preferred embodiment, the configuration module is used to process multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table, including:

[0020] When the DMA processes the current batch of data, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transfer operation instruction table, which is used for the next batch of data processing.

[0021] In one preferred embodiment, the configuration module includes:

[0022] The reading unit is used to read operation information from the Host and determine the required operation instructions based on the operation information.

[0023] The sorting unit is used to sort multiple operation instructions according to the operation order of the operation information;

[0024] The identification unit is used to combine multiple operation instructions based on the sorting result and add an operation end flag bit at the end to obtain a multi-transmission operation instruction table.

[0025] In one preferred embodiment, the operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor and the higher 4 bits represent the instruction information.

[0026] A third aspect of this application provides a storage control chip, including the read / write acceleration device as described above.

[0027] A fourth aspect of this application provides a computer-readable storage medium storing executable code that, when executed by a processor of an electronic device, causes the processor to perform the read / write acceleration method as described above.

[0028] The technical solution of this application includes: processing multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table; storing the multi-transmission operation instruction table in a static random access memory area; reading the multi-transmission operation instruction table and loading the operation instructions in the multi-transmission operation instruction table one by one to complete the Flash read and write operation. This application realizes Flash read and write by adopting MT mode. Compared with ST mode, the generated multi-transmission operation instruction table is stored in the static random access memory area. The NFCMU module inside the main controller that manages the Flash can directly access the static random access memory area to read and load the multi-transmission operation instruction table, without the need to execute corresponding firmware code involving additional CPU time to achieve reading and loading, thereby speeding up the processing of each Flash read and write operation by the main controller. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic flowchart illustrating a read / write acceleration method according to an embodiment of this application;

[0031] Figure 2 The diagram shown is a flowchart of a read / write acceleration method according to another embodiment of this application.

[0032] Figure 3 The diagram shown is a schematic representation of a read / write acceleration device according to an embodiment of this application.

[0033] Figure 4 The diagram shown is a structural schematic of a read / write acceleration device according to another embodiment of this application;

[0034] Figure 5 The diagram shown is a schematic diagram of the structure of a storage control chip in one embodiment of this application;

[0035] Figure 6 The diagram shows the architecture of a storage control chip in a related technology.

[0036] Figure 7 The diagram shown is a schematic of the architecture of the storage control chip of this application;

[0037] Figure 8 The diagram shown is a waveform comparison diagram between related technologies and this application. Detailed Implementation

[0038] To facilitate understanding of the present invention, a more complete description of the invention is provided below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0039] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] In related technologies, each time Flash performs a read / write task, the controller needs to configure a single operation instruction (SingleTransfer, ST) to execute the read / write task. In ST mode, since the controller's CPU operation register completes the operation instruction configuration, and the CPU needs to spend a certain amount of time executing the code, this will directly affect the read / write performance of Flash.

[0042] Therefore, in order to solve the above-mentioned technical problems, this application provides a read / write acceleration method that can improve the read / write performance of Flash.

[0043] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0044] Figure 1 The diagram shown is a flowchart of a read / write acceleration method according to an embodiment of this application.

[0045] Please see Figure 1 A method for accelerating read and write operations includes the following steps:

[0046] Step S110: Process multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table.

[0047] It's important to note that operation instructions are commands that enable Flash to perform read and write tasks. In simpler terms, they are like "instructors," telling Flash how to operate on the data each time it performs a read or write task.

[0048] In this embodiment, the structure of the operation instructions is shown in Table 1. Each operation instruction occupies at least 1 byte, where the "index factor" represents the specific type of the operation instruction, usually represented by the lower 4 bits. The "instruction information" represents the specific data included in the operation instruction; the "instruction information" included in different types of operation instructions may be the same or different.

[0049] Location (unit: Bit) ≥4 0～3 type Command Information (Info) Index factor

[0050] Table 1

[0051] The type and structure of operation instructions can be designed by the main controller manufacturer, and are not specifically limited in this embodiment. Common types of operation instructions for various storage protocols include: no-operation, delayed operation, send command, send address, send small amount of data, send batch data, receive small amount of data, receive batch data, jump operation, and end operation. Among these, sending address, sending data, sending small amount of data, receiving small amount of data, sending batch data, and receiving batch data are the most commonly used operations by the main controller on the Flash memory.

[0052] For example, if the operation instruction is to send an address, its corresponding index factor can be "0x05"; the instruction information includes address length + address information, where the length of a single address is configurable, generally 4 bytes; the address information may be one or multiple.

[0053] For example, if the operation instruction is to send a small amount of data, its corresponding index factor can be "0x06"; the instruction information includes the data length + data, where the total data length is configurable and is generally 4 bytes; the data may be one or more.

[0054] For example, if the operation instruction is to send a batch of data, its corresponding index factor can be "0x08"; the instruction information is the BufferID address + checksum, where the BufferID address is the address where the data is retrieved, and the BufferID address equals 2. N The checksum is the verification code for this data, used to verify and check the data to ensure its accuracy.

[0055] In this embodiment, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transmission operation instruction table, which can be implemented as follows: read operation information from the Host, determine the required operation instructions based on the operation information; sort the multiple operation instructions according to the operation order of the operation information; combine the multiple operation instructions based on the sorting result, and add an operation end flag bit at the end to obtain the multi-transmission operation instruction table.

[0056] Step S120: Store the multitransfer operation instruction table in the static random access memory area.

[0057] It should be noted that the obtained multitransfer operation instruction table is stored in the static random access memory area, i.e., SRAM, which can be easily accessed at any time, thereby improving the reading and loading of the multitransfer operation instruction table.

[0058] Step S130: Read the multi-transmission operation instruction table and load the operation instructions in the multi-transmission operation instruction table one by one to complete the Flash read and write operation.

[0059] The technical solution of this embodiment uses MT mode to read and write to Flash. Compared with ST mode, the generated multitransfer operation instruction table is stored in the static random access memory area. The NFCMU module inside the main controller that manages Flash can directly access the static random access memory area to read and load the multitransfer operation instruction table. There is no need to execute the corresponding firmware code to read and load, which involves additional CPU time, thereby speeding up the processing of each read and write operation of Flash by the main controller.

[0060] In addition, the technical solution of this embodiment does not require the CPU to operate the register to configure a single operation instruction before executing the read / write task each time the Flash performs a read / write task. The multi-transfer operation instruction table of this embodiment includes multiple operation instructions, so it is not necessary to wait for the CPU to configure the next operation instruction before the next data read / write can be executed after each data read / write is completed.

[0061] Figure 2 The diagram shown is a flowchart of a read / write acceleration method according to another embodiment of this application.

[0062] Please see Figure 2 A method for accelerating read and write operations includes the following steps:

[0063] Step S210: When the DMA processes the current batch of data, it processes multiple operation instructions according to the preset configuration rules to obtain a multi-transfer operation instruction table, which is used for the next batch of data processing.

[0064] It's important to note that operation instructions are commands that enable Flash to perform read and write tasks. In simpler terms, they are like "instructors," telling Flash how to operate on the data each time it performs a read or write task.

[0065] In this embodiment, the structure of the operation instructions is shown in Table 1 of step S110, and will not be repeated here. Each operation instruction occupies at least 1 byte, where the "index factor" represents the specific type of the operation instruction, usually represented by the lower 4 bits. The "instruction information" represents the specific data included in the operation instruction. The "instruction information" included in different types of operation instructions may be the same or different.

[0066] The type and structure of the operation instructions can be designed by the main controller manufacturer, and are not specifically limited in this embodiment. For various storage protocols, common types of operation instructions may include: no-operation, delayed operation, send command, send address, send small amount of data, send batch data, receive small amount of data, receive batch data, jump operation, and end operation. Among these, sending address, sending data, sending small amount of data, receiving small amount of data, sending batch data, and receiving batch data are the most commonly used operations by the main controller on the Flash memory. Please refer to step S110 for an illustration of the operation types; further details are omitted here.

[0067] In this embodiment, the current state of the DMA is read. When the DMA processes the current batch of data, the generation process of the multi-transfer operation instruction table is initiated. Multiple operation instructions are processed using preset configuration rules to obtain the multi-transfer operation instruction table, which is then used for the next batch of data processing. The timing of processing is optimized when multiple operation instructions are processed to obtain the multi-transfer operation instruction table using preset configuration rules. As the main controller plays a data processing role, DMA (Direct Memory Access) can pre-process multiple operation instructions using preset configuration rules to obtain the multi-transfer operation instruction table while processing data, thus preparing for the next DMA data processing and shortening the interval between processing two data items, thereby improving Flash read / write performance.

[0068] Step S220: Store the multitransfer operation instruction table in the static random access memory area.

[0069] It should be noted that the obtained multitransfer operation instruction table is stored in the static random access memory area, i.e., SRAM, which can be easily accessed at any time, thereby improving the reading and loading of the multitransfer operation instruction table.

[0070] Step S230: Read the multi-transmission operation instruction table and load the operation instructions in the multi-transmission operation instruction table one by one to complete the Flash read and write operation.

[0071] The technical solution of this embodiment uses MT mode to read and write to Flash. Compared with ST mode, the generated multitransfer operation instruction table is stored in the static random access memory area. The NFCMU module inside the main controller that manages Flash can directly access the static random access memory area to read and load the multitransfer operation instruction table. There is no need to execute the corresponding firmware code to read and load, which involves additional CPU time, thereby speeding up the processing of each read and write operation of Flash by the main controller.

[0072] In addition, the technical solution of this embodiment does not require the CPU to operate the register to configure a single operation instruction before executing the read / write task each time the Flash performs a read / write task. The multi-transfer operation instruction table of this embodiment includes multiple operation instructions, so it is not necessary to wait for the CPU to configure the next operation instruction before the next data read / write can be executed after each data read / write is completed.

[0073] To better understand the technical solution of this application, the following specific examples will be used to explain in detail the technical effects that this application can achieve (the writing process is used as an example; the reading process is similar to the writing process, and you can refer to the writing process for understanding).

[0074] like Figure 6 The diagram shows the architecture of the main controller in related technologies. The main controller 800 includes a CPU module 810, a register SFR 820, an NFCMU module 830, and a DMA module 840. These functional modules interact via an AHB bus (not shown). The CPU module 810 receives signals and data from the host and manages other functional modules. The NFCMU module manages the Flash1000 and is the core functional module for interaction between the main controller 800 and the Flash1000.

[0075] According to the processing flow of the main controller 800 in the relevant technology, when several data entries arrive (including data A, B, C, D, E, F, G, H, and I), to write these data entries to Flash, firstly, the CPU module 810 needs to operate the SFR820 register to configure a single operation instruction (ST). That is, each data entry requires a corresponding operation instruction before the operation. The main controller 800 performs 8 write operations, and correspondingly, the CPU module 810 also needs to operate the SFR820 register 8 times; otherwise, it cannot generate 8 operation instructions. Furthermore, before processing each data entry, the DMA module 840 needs to retrieve and load the operation instruction corresponding to the data, such as... Figure 8 The diagram shows the writing process. From Figure 8 As can be seen, before writing data A, operation instruction ST1 must be configured; before writing data B, operation instruction ST2 must also be configured; and so on. That is, after each data write, the DMA module 850 needs to wait for the CPU module 810 to configure the next operation instruction before it can execute the next data read / write operation. This affects the data processing efficiency of the DMA module 850. Therefore, the above-described main control 800 processing architecture has a flaw.

[0076] For the main control architecture of this application, please refer to [link / reference]. Figure 7 The main controller 900 includes: CPU module 910, register SFR920, NFCMU module 930, DMA module 940 and static storage SRAM950. The above functional modules interact through the AHB bus (not shown in the figure).

[0077] Please refer to the processing flow of the main controller 900 according to this application. Figure 8 Similarly, data A through I is written. First, the current status of the DMA module 940 is read to determine if it is processing data. If so, the processing flow of the multiple transfer operation instruction table is initiated. Next, the operation information from the host is read, and the required operation instructions are determined based on the operation information, confirming that all operation instructions are write operations. The multiple operation instructions are sorted according to the operation order from the host, combined based on the sorting result, and an operation end flag is added at the end to obtain the multiple transfer operation instruction table, as shown in Table 2.

[0078]

[0079] Table 2

[0080] The obtained multi-transfer operation instruction table is stored in the static storage SRAM 950 (the configuration of the operation instructions is still handled by the CPU module 910 operation register SFR920, the specific process of which is described above and will not be repeated here). When data A to I need to be written, the NFCMU module 930 directly accesses the static storage SRAM 950, reads and loads the multi-transfer operation instruction table, and writes data A to I sequentially into the Flash according to the operation instructions in the multi-transfer operation instruction table. Since the multi-transfer operation instruction table is pre-configured when the DMA module 940 processes the previous data, the DMA module 940 does not need to wait too long to start processing data A to I, greatly improving the Flash write performance. Furthermore, in the processing flow of related technologies, after each data write, the DMA module 850 needs to wait for the CPU module 810 to complete the configuration of the next operation instruction before it can execute the read / write of the next data. That is, the CPU module 910 has to execute firmware code to configure each data write, which consumes time. In contrast, although the multi-transfer operation instruction table of the present application is also configured through the operation register SFR920 of the CPU module 910, it is processed centrally. Only one execution of firmware code is needed to configure all the operation instructions required for the data to be written, which can greatly save the resource overhead of the CPU module 910 and greatly improve the write performance of Flash.

[0081] Figure 8 This is a waveform comparison diagram between related technologies and the present application. The upper part is the waveform generated according to the method of the related technologies, and the lower part is the waveform generated according to the method of the present application. By comparison, the dotted line part is the time that can be saved. According to the comparison of the waveform diagrams, it can be seen that the technical solution of the present application has a significant improvement on the read and write performance of Flash.

[0082] Corresponding to the foregoing method embodiments, this application also provides a read / write acceleration device and its corresponding embodiments.

[0083] Figure 3 A schematic diagram of the read / write acceleration device in one embodiment of this application is shown.

[0084] Please see Figure 3 A read / write acceleration device 300 includes: a configuration module 310, a storage module 320, and an operation module 330.

[0085] The configuration module 310 is used to process multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table.

[0086] In this embodiment, the operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor and the higher 4 bits represent the instruction information.

[0087] In this embodiment, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transmission operation instruction table, which can be implemented as follows: read operation information from the Host, determine the required operation instructions based on the operation information; sort the multiple operation instructions according to the operation order of the operation information; combine the multiple operation instructions based on the sorting result, and add an operation end flag bit at the end to obtain the multi-transmission operation instruction table.

[0088] Storage module 320 is used to store the multitransfer operation instruction table into the static random access memory area.

[0089] The operation module 330 is used to read the multi-transmission operation instruction table and load the operation instructions in the multi-transmission operation instruction table one by one to complete the Flash read and write operation.

[0090] This application implements Flash reading and writing by adopting MT mode. Compared with ST mode, the generated multitransfer operation instruction table is stored in the static random access memory area. The NFCMU module inside the main controller that manages Flash can directly access the static random access memory area to read and load the multitransfer operation instruction table. There is no need to execute the corresponding firmware code to achieve reading and loading by consuming additional CPU time, thereby speeding up the processing of each Flash reading and writing operation by the main controller.

[0091] It should be noted that the read / write acceleration method implemented by the read / write acceleration device disclosed in this embodiment is the same as that in the above embodiments, and therefore will not be described in detail here. Optionally, each module and the other operations or functions described above are respectively for implementing the methods in the foregoing embodiments.

[0092] Figure 4 A schematic diagram of the read / write acceleration device according to another embodiment of this application is shown.

[0093] Please see Figure 4 A read / write acceleration device 300 includes a configuration module 310, a storage module 320, and an operation module 330. For functional descriptions of the storage module 320 and the operation module 330, please refer to [link to relevant documentation]. Figure 3 This will not be elaborated upon here.

[0094] The configuration module 310 is used to process multiple operation instructions according to preset configuration rules when the DMA processes the current batch of data, and obtain a multi-transfer operation instruction table, which is used for the next batch of data processing.

[0095] In this embodiment, the current state of the DMA is read. When the DMA processes the current batch of data, the generation process of the multi-transfer operation instruction table is initiated. Multiple operation instructions are processed using preset configuration rules to obtain the multi-transfer operation instruction table, which is then used for the next batch of data processing. The timing of processing is optimized when multiple operation instructions are processed to obtain the multi-transfer operation instruction table using preset configuration rules. As the main controller plays a data processing role, DMA (Direct Memory Access) can pre-process multiple operation instructions using preset configuration rules to obtain the multi-transfer operation instruction table while processing data, thus preparing for the next DMA data processing and shortening the interval between processing two data items, thereby improving Flash read / write performance.

[0096] Configuration module 310 includes: a reading unit 311, and sorting units 312 and 313. Wherein:

[0097] The reading unit 311 is used to read operation information from the host and determine the required operation instructions based on the operation information.

[0098] The sorting unit 312 is used to sort multiple operation instructions according to the operation order of the operation information.

[0099] The identifier unit 313 is used to combine multiple operation instructions based on the sorting result and add an operation end identifier bit at the end to obtain a multi-transmission operation instruction table.

[0100] The technical solution of this embodiment uses MT mode to read and write to Flash. Compared with ST mode, the generated multitransfer operation instruction table is stored in the static random access memory area. The NFCMU module inside the main controller that manages Flash can directly access the static random access memory area to read and load the multitransfer operation instruction table. There is no need to execute the corresponding firmware code to read and load, which involves additional CPU time, thereby speeding up the processing of each read and write operation of Flash by the main controller.

[0101] In addition, the technical solution of this embodiment does not require the CPU to operate the register to configure a single operation instruction before executing the read / write task each time the Flash performs a read / write task. The multi-transfer operation instruction table of this embodiment includes multiple operation instructions, so it is not necessary to wait for the CPU to configure the next operation instruction before the next data read / write can be executed after each data read / write is completed.

[0102] like Figure 5 The diagram shown is a structural schematic of a storage control chip according to an embodiment of this application.

[0103] Please refer to 5, a storage control chip 500, which includes the read / write acceleration device 300 described above.

[0104] The storage control chip 500 of this application implements read and write operations on Flash using MT mode. Compared with ST mode, the generated multitransfer operation instruction table is stored in the static random access memory area. The NFCMU module inside the main controller that manages Flash can directly access the static random access memory area to read and load the multitransfer operation instruction table. There is no need to execute the corresponding firmware code to achieve reading and loading, which involves additional CPU time, thereby speeding up the processing of each read and write operation of Flash by the main controller.

[0105] In this embodiment, the storage control chip 500 reads the current state of the DMA. When the DMA processes the current batch of data, it initiates the generation process of a multi-transfer operation instruction table. Multiple operation instructions are processed using preset configuration rules to obtain the multi-transfer operation instruction table, which is then used for the next batch of data processing. The timing of processing is optimized when multiple operation instructions are processed to obtain the multi-transfer operation instruction table using preset configuration rules. As the main controller plays a data processing role, DMA (Direct Memory Access) can pre-process multiple operation instructions using preset configuration rules to obtain the multi-transfer operation instruction table while processing data, preparing for the next DMA data processing and shortening the interval between processing two data items, thereby improving Flash read / write performance.

[0106] In addition, the storage control chip 500 in this embodiment does not require the CPU to operate the register to configure a single operation instruction before executing the read / write task each time the Flash performs a read / write task. The multi-transfer operation instruction table in this embodiment includes multiple operation instructions, so it is not necessary to wait for the CPU to configure the next operation instruction before executing the read / write of the next piece of data after each data read / write is completed.

[0107] Furthermore, the method according to this application can also be implemented as a computer program or computer program product, which includes computer program code instructions for performing some or all of the steps in the method described above.

[0108] Alternatively, this application may be implemented as a computer-readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium) storing executable code (or computer program or computer instruction code) thereon, which, when executed by a processor of an electronic device (or server, etc.), causes the processor to perform part or all of the steps of the methods described above according to this application.

[0109] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for accelerating read and write operations, characterized in that, include: When DMA processes the current batch of data, operation information from the host is read in advance, the required operation instructions are determined according to the operation information, the multiple operation instructions are sorted according to the operation order of the operation information, the multiple operation instructions are combined and processed based on the sorting result, and an operation end flag is added at the end to obtain a multi-transmission operation instruction table, which is used for the next batch of data processing. Store the multitransmission operation instruction table in the static random access memory area; The multi-transmission operation instruction table is read, and the operation instructions in the multi-transmission operation instruction table are loaded one by one to complete the read and write operation on the Flash.

2. The read / write acceleration method according to claim 1, characterized in that, The operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor and the higher 4 bits represent the instruction information.

3. A read / write acceleration device, characterized in that, include: The configuration module is used to read operation information from the host when DMA processes the current batch of data, determine the required operation instructions according to the operation information, sort multiple operation instructions according to the operation order of the operation information, perform centralized combination processing on the sorting result of multiple operation instructions, and add an operation end flag bit at the end to obtain a multi-transmission operation instruction table, which is used for the next batch of data processing. The storage module is used to store the multi-transmission operation instruction table in the static random access memory area; The operation module is used to read the multi-transmission operation instruction table and load the operation instructions in the multi-transmission operation instruction table one by one to complete the read and write operations on the Flash.

4. The read / write acceleration device according to claim 3, characterized in that, The operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor and the higher 4 bits represent the instruction information.

5. A storage control chip, characterized in that, Includes the read / write acceleration device as described in claim 3 or 4.

6. A computer-readable storage medium, characterized in that, The device stores executable code that, when executed by a processor of an electronic device, causes the processor to perform the read / write acceleration method as described in claim 1 or 2.

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