Instruction processing method and system based on many-core system and electronic equipment

Abstract

The invention provides an instruction processing method and system based on a many-core system and electronic equipment. The method comprises the steps that a second processing core sends stored shared instruction data to a first processing core; the first processing core combines the shared instruction data with multiple pieces of private instruction data stored in the first processing core to obtain multiple composite program instructions, and the multiple composite program instructions are operated through the first processing core; wherein the plurality of composite program instructions multiplex the shared instruction data. According to the mode, the reusable shared instruction data among the plurality of cores is only stored in the second processing core (namely the instruction supply core) and is transmitted to the first processing core (namely the instruction use core) during use, so that the storage space of the first processing core can be prevented from being occupied, the data storage efficiency is improved, and the user experience is improved. The many-core system can process more and more complex instruction data by using limited storage space, so that the performance of the many-core system is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to an instruction processing method, system and electronic device based on a many-core system. Background Art

[0002] Many-core system refers to a system composed of one or more many-core processors, which has high performance and parallel processing capabilities. Many-core processors can integrate multiple processor cores (also called processing cores) and are widely used in the field of high-performance computing, such as scientific computing, machine learning, image processing, etc.

[0003] In the process of executing program instructions based on a many-core system, it is necessary to uniformly schedule and process program instructions in multiple processor cores. However, in the related art, there may be a lot of redundancy in the instruction content of program instructions between multiple processor cores, which results in a huge waste of storage space. Therefore, how to improve the storage efficiency of program instructions in a many-core system has become a problem that needs to be solved urgently. Summary of the invention

[0004] The present disclosure provides an instruction processing method, system and electronic device based on a many-core system.

[0005] In a first aspect, the present disclosure provides an instruction processing method based on a many-core system, wherein the many-core system includes a plurality of processing cores, and the method includes:

[0006] The second processing core sends the stored shared instruction data to the first processing core;

[0007] The first processing core combines the shared instruction data with multiple private instruction data stored in the first processing core to obtain multiple composite program instructions, and runs the multiple composite program instructions through the first processing core; wherein the multiple composite program instructions reuse the shared instruction data.

[0008] In a second aspect, the present disclosure provides a many-core system, the many-core system comprising a plurality of processing cores, the plurality of processing cores comprising: a second processing core used as an instruction supply core, and a first processing core used as an instruction use core, wherein:

[0009] The second processing core is used to send the stored shared instruction data to the first processing core;

[0010] The first processing core is used to combine the shared instruction data with multiple private instruction data stored in the first processing core to obtain multiple composite program instructions, and run the multiple composite program instructions; wherein the multiple composite program instructions reuse the shared instruction data.

[0011] In a third aspect, the present disclosure provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, and one or more of the computer programs are executed by the at least one processor to enable the at least one processor to perform the above-mentioned method.

[0012] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above method when executed by a processor / processing core.

[0013] In the embodiment provided by the present disclosure, first, the second processing core sends the stored shared instruction data to the first processing core, and then, the first processing core combines the shared instruction data with the multiple private instruction data stored in the first processing core, respectively, to obtain multiple compound program instructions (one compound program instruction is a complete executable instruction), and runs the multiple compound program instructions through the first processing core. In this way, multiple compound program instructions can reuse the shared instruction data. It can be seen that by storing the shared instruction data that can be reused between multiple cores only in the second processing core (i.e., the instruction supply core), and transmitting it to the first processing core (i.e., the instruction use core) when in use, it is possible to avoid occupying the storage space of the first processing core, improve the efficiency of data storage, and enable the multi-core system to process more and more complex instruction data using limited storage space, thereby improving the performance of the multi-core system.

[0014] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 A schematic diagram of a flow chart of an instruction processing method based on a many-core system provided by an embodiment of the present disclosure is shown;

[0017] Figure 2 A distribution diagram of a many-core system is shown;

[0018] Figure 3 A distribution diagram of another many-core system is shown;

[0019] Figure 4 A block diagram of a many-core system provided in an embodiment of the present disclosure;

[0020] Figure 5 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0022] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0023] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0026] In the related art, there may be a lot of redundancy in the instruction content of program instructions between multiple processor cores, which results in a huge waste of storage space. In order to solve the above problem, the present application stores the shared instruction data that can be reused between multiple cores only in the second processing core (i.e., the instruction supply core), and transmits it to the first processing core (i.e., the instruction use core) when in use, thereby avoiding occupying the storage space of the first processing core, improving the efficiency of data storage, and enabling the many-core system to process more and more complex instruction data using limited storage space, thereby improving the performance of the many-core system.

[0027] Figure 1 FIG. 1 is a flow chart of an instruction processing method based on a multi-core system provided by an embodiment of the present disclosure. The multi-core system includes multiple processing cores. Figure 1 As shown, the instruction processing method includes:

[0028] Step S110: the second processing core sends the stored shared instruction data to the first processing core.

[0029] The second processing core may be referred to as an instruction supply core corresponding to the shared instruction data, and the first processing core may be referred to as an instruction use core corresponding to the shared instruction data. Specifically, the second processing core sends the stored shared instruction data to the first processing core for use by the first processing core. The number of the first processing cores may be one or more.

[0030] Furthermore, when there is a direct connection relationship between the first processing core and the second processing core (i.e., the first processing core is directly connected to the second processing core), the second processing core directly sends the shared instruction data to the first processing core. When there is an indirect connection relationship between the first processing core and the second processing core (i.e., the first processing core is not directly connected to the second processing core, but is indirectly connected through other processing cores), the second processing core transmits the shared instruction data to the first processing core through forwarding by other processing cores. This application does not limit the connection relationship between the first processing core and the second processing core and the data transmission method.

[0031] Step S120: the first processing core combines the shared instruction data with the multiple private instruction data stored in the first processing core to obtain multiple composite program instructions, and runs the multiple composite program instructions through the first processing core; wherein the multiple composite program instructions reuse the shared instruction data.

[0032] The first processing core has a plurality of private instruction data stored therein, and these private instruction data can be combined with the shared instruction data from the second processing core to obtain a plurality of composite program instructions, so that the plurality of composite program instructions can be run by the first processing core. Each composite program instruction is a complete executable instruction, and therefore, a composite program instruction can also be referred to as an executable instruction.

[0033] Wherein, each compound program instruction includes at least two parts: shared instruction data and private instruction data. Accordingly, a compound program instruction refers to an instruction or instruction sequence composed of multiple simple instructions for implementing more complex functions. Wherein, a simple instruction can be in various forms such as instruction fragments and instruction local data. In the present application, a compound program instruction includes at least shared instruction data and private instruction data.

[0034] Among them, shared instruction data is usually instruction content that appears repeatedly in the target program, and the instruction content that appears repeatedly can be reused by multiple processing cores. Therefore, in order to avoid the waste of storage resources caused by repeated storage of the same content by multiple processing cores, in the present application, the instruction content reused between multiple processing cores is uniformly stored in the second processing core as shared instruction data to reduce the number of repeated storage times and improve the utilization rate of storage resources.

[0035] In addition, private instruction data refers to data used only by this processing core and does not need to be shared with other processing cores. Generally, the shared instruction part reused between multiple processing cores can be determined first, and the content other than the shared instruction part is the private instruction data of each processing core. Private instruction data does not need to be reused by other processing cores, so it only needs to be stored in the private storage space inside the processing core. Specifically, during the program compilation stage, the compiler can analyze the sharing relationship between the program instructions corresponding to multiple processing cores in the multi-core system, and determine the instruction fragments shared by multiple associated processing cores based on the sharing relationship. Among them, multiple associated processing cores refer to: multiple processing cores that have an associated relationship because they need to share a part of the same instruction content. Accordingly, according to the instruction fragments shared by multiple associated processing cores, the program instructions are segmented and processed to obtain the shared instruction data in the program instructions. And, the part other than the shared instruction fragments is segmented into private instruction data. In addition, the transmission path of the shared instruction data in the multi-core system can also be determined based on the positional relationship between the multiple associated processing cores corresponding to the shared instruction data.

[0036] Among them, the shared instruction data in the multi-core system can be multiple copies, and the multiple associated processing cores corresponding to each shared instruction data can be the same or different. For any shared instruction data, the position distribution between the multiple associated processing cores corresponding to the shared instruction data is determined, so that the transmission path of the shared instruction data can be determined based on the position distribution. For example, the multiple associated processing cores corresponding to the shared instruction data are processing core a, processing core b and processing core c, respectively, and processing core a is connected to processing core b, and processing core b is connected to processing core c. Correspondingly, the transmission path can be set to be transmitted from the instruction supply core to processing core a, then from processing core a to processing core b, and finally from processing core b to processing core c. It can be seen that the above-mentioned first processing core and / or second processing core can be any processing core in the associated processing core. In general, multiple associated processing cores can be used as the first processing core, and the second processing core can be any processing core in the multiple associated processing cores, or it can be the remaining processing cores except for the multiple associated processing cores, and this application does not limit this.

[0037] In the embodiment provided by the present disclosure, first, the second processing core sends the stored shared instruction data to the first processing core, and then, the first processing core combines the shared instruction data with the multiple private instruction data stored in the first processing core respectively to obtain multiple compound program instructions, and runs the multiple compound program instructions through the first processing core. In this way, multiple compound program instructions can reuse the shared instruction data. It can be seen that by storing the shared instruction data that can be reused between multiple cores only in the second processing core (i.e., the instruction supply core) and transmitting it to the first processing core (i.e., the instruction use core) when in use, it is possible to avoid occupying the storage space of the first processing core, improve the efficiency of data storage, and enable the many-core system to process more and more complex instruction data using limited storage space, thereby improving the performance of the many-core system.

[0038] Among them, the shared instruction data can be stored in only one copy, for example, only in the in-core storage of a certain computing core (i.e., processing core), and all instruction-using cores that need to use the shared instruction data can obtain it. The method of storing only one copy helps to save storage space and improve storage efficiency. Alternatively, the shared instruction data can also be stored in multiple copies at the same time, for example, redundantly stored in the in-core storage of several computing cores, and all instruction-using cores that need to use the shared instruction data can obtain it. The method of storing multiple copies helps each instruction-using core to flexibly select the appropriate instruction supply core according to the transmission cost corresponding to the transmission path, so as to shorten the instruction transmission delay. It can be seen that the specific number of stored copies of the shared instruction mainly depends on the balance between the transmission cost and the storage cost. For example, if only one copy is stored, the transmission path is too far, then one more copy can be stored in the path to reduce the transmission path.

[0039] It should be noted that the first processing core and the second processing core mentioned above may be any processing core in the multi-core system. In other words, for any processing core, when processing a shared instruction data, it may serve as an instruction supply core (i.e., the second processing core); when processing another shared instruction data, it may serve as an instruction use core (i.e., the first processing core).

[0040] In addition, the second processing core can also combine the shared instruction data stored in the processing core with the private instruction data stored in the processing core to obtain a composite program instruction. For example, the second processing core can combine the shared instruction data stored in the processing core with multiple private instruction data stored in the processing core to obtain multiple composite program instructions. It can be seen that the second processing core can use the shared instructions and private instructions stored in itself to obtain the composite program instructions (i.e. executable instructions) required by the processing core. Similarly, there can be multiple private instructions in the second processing core, so as to realize the reuse within the core; and the shared instructions in the second processing core are also used to send to other processing cores for reuse. In short, the second processing core itself can be used as an instruction supply core or as an instruction use core. Similarly, the first processing core can also be used as an instruction supply core and / or instruction use core for other shared instructions.

[0041] In addition, those skilled in the art may also make various modifications and variations to the embodiments of the present disclosure:

[0042] In an optional implementation, if there are multiple first processing cores, the second processing core sends the stored shared instruction data to the first processing core in the following manner: First, the second processing core determines multiple first processing cores corresponding to the shared instruction data, and determines the processing core transmission order between the multiple first processing cores according to the position distribution of the multiple first processing cores. For example, the transmission route can be determined according to the position distribution of the multiple first processing cores, and then the processing core transmission order can be determined according to the transmission route. Then, according to the above-mentioned processing core transmission order, the shared instruction data is sent to the i-th first processing core, so that the i-th first processing core forwards the shared instruction data to the i+1-th first processing core; wherein i is a natural number.

[0043] The number of transmission routes determined according to the distribution positions of the plurality of first processing cores may be one or more. For example, when the plurality of first processing cores are sequentially connected, the transmission route may be one. For another example, when the plurality of first processing cores are respectively connected to the second processing cores, the transmission routes may be multiple. Accordingly, the number of the i-th first processing core may be one or more.

[0044] Figure 2 A distribution diagram of a many-core system is shown, Figure 2As shown, core 1 is the second processing core that serves as an instruction supply core, and cores 2, 3, and 6 are all first processing cores that serve as instruction use cores. Figure 2 According to the distribution shown, the transmission route is determined to be core 1-core 2-core 3-core 6. Accordingly, core 1 first sends the stored shared instruction data to the first first processing core (i.e., core 2) so that the first first processing core forwards the shared instruction data to the second first processing core (i.e., core 3), and then the second first processing core (i.e., core 3) forwards the shared instruction data to the third first processing core (i.e., core 6).

[0045] Figure 3 A distribution diagram of another multi-core system is shown, such as Figure 3 As shown, the instruction supply core in the middle is used as the second processing core, and cores 1, 2, 3, and 4 respectively connected to the second processing core are all first processing cores used as instruction use cores. Figure 3 According to the distribution shown in the figure, four transmission routes are determined. Accordingly, the instruction supply core transmits the shared instruction data to core 1, core 2, core 3, and core 4 respectively. Figure 3 There may be other first processing cores connected to core 1, core 2, core 3 or core 4, so core 1, core 2, core 3 or core 4 is further used to transmit the received shared instruction data to other first processing cores connected thereto. In addition, the number of shared instruction data stored in the second processing core may be multiple, such as Figure 3 In the instruction 1, instruction 2 and instruction 3, different shared instruction data may correspond to different first processing cores, and the sending timing of different shared instruction data may also be different. Therefore, the second processing core needs to perform scheduling processing.

[0046] Among them, the routing transmission path (i.e., transmission route) for shared instruction data can be set in the following manner: a shared instruction is first issued from an instruction supply core, and is sent to one or more instruction-using cores in sequence, wherein the multiple instruction-using cores of the path can use the received shared instruction (combined with their own private instructions) to assemble instructions, thereby forming a complete instruction to execute the complete instruction. Among them, after the multiple instruction cores of the path receive and use the shared instruction, they are sent to the next instruction-using core without storing the shared instruction; until all the cores that need to use the shared instruction have used up the shared instruction. This method can greatly save storage space. The above method can reduce the storage length of the program and enable a stronger instruction reuse relationship between processing cores. Specifically, a reused instruction stream can be established between processing cores, or a dedicated instruction supply core (such as Figure 3 The instruction supply core located in the center).

[0047] Optionally, for the same shared instruction, there may be one or more instruction supply cores. Also, there may be one or more instruction use cores that directly send the shared instruction through the instruction supply core. Figure 3 In the example, the number of instruction-using cores that directly send the shared instruction through the instruction supply core may be 4. In addition, the number of the instruction-using cores (ie, the first processing core used to forward the shared instruction after using it) that are passed through may be one or more.

[0048] In an optional implementation, when there are multiple shared instruction data stored in the second processing core, and different shared instruction data depend on different input data, the second processing core sends the stored shared instruction data to the first processing core in the following manner: First, according to the data transmission order between the multiple input data corresponding to the first processing core, determine the instruction transmission order between the multiple shared instruction data. For example, the correspondence between each shared instruction data and the input data it depends on is determined in advance, and based on the correspondence and the data transmission order between the multiple input data, the instruction transmission order between the multiple shared instruction data can be determined. Then, the second processing core sends multiple shared instruction data to the first processing core in sequence according to the above-mentioned instruction transmission order. In this way, the flow order of the shared instruction data can be reasonably determined according to the data flow between the cores or the order of data calculation, so that the timing of sending the shared instruction data is more reasonable.

[0049] For example, during data calculation, based on the order of data calculation between different cores, shared instructions are used to flow between multiple cores to complete the instruction calculation of data; for example, for Figure 2 For core 9 in the example, the data transmission order between the corresponding multiple input data is: data 1-data 2-data 3, where instructions 1 and 2 both depend on data 1, instruction 3 depends on data 2, and instruction 4 depends on data 3. Therefore, based on the above data transmission order, the instruction transmission order must be subject to the following order constraints: (instruction 1, instruction 2)-instruction 3-instruction 4, where the transmission order between instruction 1 and instruction 2 can be set arbitrarily. In this way, the flow order of shared instructions depends on the data flow or data calculation order between different cores.

[0050] In an optional implementation, the shared instruction data stored in the second processing core includes: shared instruction data corresponding to multiple different reuse levels; wherein the number of instruction-using cores corresponding to the shared instruction data at different reuse levels is different. It can be seen that the reuse level is used to characterize the reuse range of the shared instruction data. Therefore, the second processing core needs to store the corresponding reuse level of each shared instruction data and the identifiers of each instruction-using core contained in the reuse level. Accordingly, the second processing core sends the stored shared instruction data to the first processing core in the following manner: First, the second processing core determines the instruction-using core corresponding to the m-th reuse level, and sends the shared instruction data corresponding to the m-th reuse level to the instruction-using core corresponding to the m-th reuse level. Then, the second processing core determines the instruction usage core corresponding to the m+1th multiplexing level, and sends the shared instruction data corresponding to the m+1th multiplexing level to the instruction usage core corresponding to the m+1th multiplexing level; wherein m is a natural number, and the number of instruction usage cores corresponding to the m+1th multiplexing level is greater than the number of instruction usage cores corresponding to the m+1th multiplexing level.

[0051] Specifically, the shared part may include multiple levels, corresponding to different reuse levels. Among them, whether the shared instructions are hierarchical depends mainly on whether the shared part is layered. For example, assuming that the instructions used by different cores are as follows:

[0052] Core 1: mother instruction, child instruction 1, child instruction 2; Core 2: mother instruction, child instruction 1, child instruction 3;

[0053] Core 3: parent instruction, child instruction 1, child instruction 4; Core 4: parent instruction, child instruction 1, child instruction 5;

[0054] Core 5: mother instruction, child instruction 6, child instruction 7; Core 6: mother instruction, child instruction 6, child instruction 8;

[0055] Core 7: parent instruction, child instruction 6, child instruction 9; Core 8: parent instruction, child instruction 6, child instruction 10.

[0056] Among them, the parent instruction is an implementation method of the shared instruction data mentioned above. It can be seen that the shared instructions in the above example are divided into two levels: the first level is the parent instruction, and the second level is the sub-instruction 1 and / or sub-instruction 6. Among them, the number of cores used by the instructions corresponding to the first level is 8, that is, all 8 cores need to use the parent instruction. The number of cores used by the instructions corresponding to the second-level sub-instruction 1 is 4, which are cores 1 to core 4 respectively; the number of cores used by the instructions corresponding to the second-level sub-instruction 6 is also 4, which are cores 5 to core 8 respectively.

[0057] During the transmission process, the slave instruction supply core first transmits the first-level shared instruction, i.e., the parent instruction, and then transmits the second-level shared instruction, such as sub-instruction 1, which is sequentially transmitted to core 1, core 2, core 3, and core 4. Similarly, the slave instruction supply core first transmits the first-level shared instruction, i.e., the parent instruction, and then transmits the second-level shared instruction, such as sub-instruction 6, which is sequentially transmitted to core 5, core 6, core 7, and core 8. In this case, assuming that each sub-instruction is combined with the parent instruction to form a composite program instruction, each core executes more than two instructions in succession. For example, the instructions actually executed by core 1 include: parent instruction + sub-instruction 1, parent instruction + sub-instruction 2.

[0058] In an optional implementation, when the first processing core combines shared instruction data with multiple private instruction data stored in the first processing core, it can be achieved in the following way: the first processing core stores the shared instruction data corresponding to the mth multiplexing level from the second processing core through the mth data queue, and stores the shared instruction data corresponding to the m+1th multiplexing level from the second processing core through the m+1th data queue; the shared instruction data corresponding to the mth multiplexing level and the shared instruction data corresponding to the m+1th multiplexing level are respectively combined with the multiple private instruction data stored in the first processing core.

[0059] For example, still taking the above example, core 1 stores the shared instruction data (i.e., the parent instruction) corresponding to the first multiplexing level from the second processing core through the first data queue, and stores the shared instruction data (i.e., the sub-instruction 1) corresponding to the second multiplexing level from the second processing core through the second data queue. Accordingly, the parent instruction is combined with the sub-instruction 1 and the sub-instruction 2 respectively to obtain two composite program instructions.

[0060] In addition, it should be noted that a data type identifier can also be set for shared instruction data corresponding to multiple different reuse levels, and the data type identifier is used to characterize the data type of the shared instruction data as a parent instruction or a child instruction. Among them, the parent instruction refers to: the instruction part reused by multiple composite program instructions within the same processing core, and the child instruction refers to: the instruction part that needs to be combined with the corresponding parent instruction to obtain the corresponding composite program instruction. It can be seen that the parent instruction mainly refers to the instruction part that can be reused by multiple composite program instructions within the same processing core, while the child instruction refers to the instruction part that cannot be reused by multiple composite program instructions within the same processing core. Correspondingly, in the above example, since the data type identifier of the shared instruction data corresponding to the first reuse level is the parent instruction identifier, and the data type identifier of the shared instruction data corresponding to the second reuse level is the child instruction identifier, therefore, in the subsequent instruction combination stage, the parent instruction needs to be combined with the received child instruction 1 and the child instruction 2 stored in the processing core itself, so as to obtain a composite program instruction 1 containing a parent instruction and a child instruction 1, and a composite program instruction 2 containing a parent instruction and a child instruction 2. It can be seen that in the above manner, the compound program instruction includes two parts: a parent instruction and a child instruction. Moreover, the parent instructions among multiple compound program instructions can be the same, and only the child instructions are different.

[0061] It can be seen that, when the instruction fragments in the target program to which the compound program instruction belongs meet the preset arrangement conditions, the compound program instruction may include: first instruction data whose data type is a parent instruction type, and second instruction data whose data type is a child instruction type; wherein the second instruction data of the child instruction type contained in multiple compound program instructions can reuse the first instruction data of the same parent instruction type. Accordingly, when the shared instruction data corresponding to the mth reuse level and the shared instruction data corresponding to the m+1th reuse level are respectively combined with the multiple private instruction data stored in the first processing core, it can be achieved in the following manner: respectively determine that the data type of the shared instruction data corresponding to each reuse level is a parent instruction type or a child instruction type; for the shared instruction data of the parent instruction type, respectively combine it with the shared instruction data of the child instruction type and the multiple private instruction data stored in the first processing core.

[0062] Among them, when the instruction fragments in the target program to which the composite program instruction belongs meet the preset arrangement conditions, the target program can be considered to be a target program of the first type. For example, part of the area or all of the area in the target program of the first type meets the preset arrangement conditions (such as the reusable instruction part in the program is arranged in a tree form). It can be seen that the target program of the first type can be a complete program or a local area in the program. Among them, the preset arrangement conditions may include: multiple recurring instruction fragments contained in the target program are arranged in a tree structure, a linear structure, a loop nested structure, etc., and appear multiple times in a certain pattern.

[0063] It is precisely because the target program contains multiple repetitive instruction fragments that appear multiple times in a certain regular pattern, therefore, the repetitive instruction fragments can be used as parent instructions, and the non-repetitive instruction fragments can be used as sub-instructions, so that multiple sub-instructions can reuse the same parent instruction. For example, when a parent instruction corresponds to sub-instruction 1, sub-instruction 2, and sub-instruction 3, a composite program instruction 1 containing a parent instruction and sub-instruction 1, a composite program instruction 2 containing a parent instruction and sub-instruction 2, and a composite program instruction 3 containing a parent instruction and sub-instruction 3 can be combined to obtain a composite program instruction 1 containing a parent instruction and sub-instruction 1, a composite program instruction 2 containing a parent instruction and sub-instruction 2, and a composite program instruction 3 containing a parent instruction and sub-instruction 3, thereby saving storage space without repeatedly storing the parent instruction. Accordingly, the shared instruction data in the present application is preferably parent instruction data.

[0064] For example, in the existing neural network instruction set architecture, an operator or fusion operator is usually mapped to a hardware instruction. For example, a convolution instruction may include: instruction type, instruction ID, size of each dimension of the convolution, padding / stride / dilation parameters, calculation accuracy, parallel expansion strategy, data read and write address, and address stepping during the calculation process. When a neural network contains multiple convolution operations, the program executed by the hardware contains multiple such convolution instructions. However, there are often repeated operations of several operators in neural networks, especially in large models, where not only the operators contained in each layer are the same, but also the shapes of the operators are the same. In addition, there is a lot of repetitive information in the instruction content of the hardware instructions, and the existing memory access is redundant for the storage of repetitive information in the instruction content. Therefore, the above-mentioned hierarchical structured composite program instructions are particularly suitable for the above-mentioned scenarios.

[0065] It can be seen that when the composite program instructions are hierarchical structures, they can be implemented based on the instruction set format of the parent-child instruction format. Accordingly, the relationship between instructions used by different processing cores can include the following multiple ways:

[0066] (1) Different processing cores can share a complete instruction. For example, the complete instructions used by different processing cores are exactly the same, that is, the parent instruction and the child instruction are the same.

[0067] (2) Different processing cores can share some instruction data:

[0068] For example, all parent instructions may be shared between different processing cores. For example, the multi-level parent instructions used by different processing cores may be the same, but the sub-instructions may be different. This approach may be applicable to the case where the composite program instruction includes one or more levels of sub-parent instructions.

[0069] For another example, different processing cores can share some parent instruction data. For example, taking the case of three-level parent-child instructions nesting as an example, the first-level parent instructions and second-level parent instructions used by different processing cores are the same, and the third-level parent instructions can be different, and the child instructions are also different.

[0070] Among them, no matter how many layers of loop nesting the parent-child instruction contains, as long as the instructions between the processing cores are the same, they can be called shared instructions, and the instructions between the processing cores are different can be called private instructions of each core.

[0071] In addition, private instruction data can be stored in the following storage methods: each processing core has its own private instructions stored in its on-core storage. For example, sub-instructions other than shared instructions are stored; for another example, private parent instructions and private child instructions other than shared instructions are stored (in the case of multi-level parent-child instructions being nested). As a special case, some processing cores store both shared instructions and their own private instructions.

[0072] The so-called nesting of parent-child instructions means that the interior of the current child instruction further includes: a next-level parent instruction shared by multiple next-level child instructions, and multiple next-level child instructions. Accordingly, when processing the current child instruction, it needs to be further split into next-level compound program instructions corresponding to multiple next-level child instructions, wherein each next-level compound program instruction contains a next-level parent instruction and a corresponding next-level child instruction.

[0073] In addition, it should be noted that, when a processing core stores both shared instructions and its own private instructions, that is, when the second processing core combines the shared instruction data stored by the processing core with the private instruction data stored in the processing core to obtain a composite program instruction, in order to facilitate addressing operations within the processing core, the second processing core can perform instruction processing in the following manner:

[0074] First, according to the first address information stored in the first register, the shared instruction data as the parent instruction is obtained. Among them, the first register can also be called an address register, a program counter, etc. The first register is used to store the storage address of the parent instruction in a storage space (such as a memory space). Accordingly, according to the first address information stored in the first register, the storage address of the parent instruction can be determined, and then the shared instruction data as the parent instruction is obtained according to the storage address.

[0075] Then, according to the second address information stored in the second register, multiple sub-instruction data (i.e., private instructions) corresponding to the current parent instruction are obtained in sequence; wherein, the second address information stored in the second register can be dynamically updated to represent the storage address of the sub-instruction data to be obtained. Among them, the sub-instruction is usually an instruction content that does not appear repeatedly or appears less frequently, and multiple sub-instruction data can reuse the same parent instruction. Among them, the second register can also be called an address register, a program counter, etc. The second register is used to store the storage address of the sub-instruction data corresponding to the parent instruction in a storage space (such as a memory space). Accordingly, according to the second address information stored in the second register, the storage address of each sub-instruction data corresponding to a parent instruction can be determined. Since one parent instruction corresponds to multiple sub-instructions, the second address information in the second register will be updated multiple times during the processing of the same parent instruction so that the second register can accurately represent the storage address of the sub-instruction data to be obtained.

[0076] Finally, for each acquired sub-instruction data, the sub-instruction data is combined with the shared instruction data as the parent instruction into a compound program instruction, thereby obtaining a plurality of compound program instructions corresponding to the plurality of sub-instruction data.

[0077] The above-mentioned addressing method is particularly suitable for the case where the compound program instruction is a hierarchical structure (that is, the instruction fragments in the target program to which the compound program instruction belongs meet the preset arrangement conditions) and are implemented in an instruction set format based on the parent-child instruction format. The above-mentioned method can obtain the shared instruction data as the parent instruction through the first register; and, through the second register, can sequentially obtain multiple sub-instruction data corresponding to the parent instruction; wherein the second address information stored in the second register can be dynamically updated to represent the storage address of the sub-instruction data to be obtained. Accordingly, for each sub-instruction data obtained, the sub-instruction data is combined with the parent instruction into a compound program instruction. It can be seen that this method can enable multiple sub-instruction data to reuse the same parent instruction (that is, shared instruction data), so that the shared instruction data only needs to be stored in one copy, without the need for repeated storage multiple times, thereby reducing storage space and saving storage overhead.

[0078] In addition, the above-mentioned implementation of the instruction set format based on the parent-child instruction format is particularly suitable for a large model including multiple network layers. The large model generally has the following characteristics: the operator characteristics of the preset operators contained in at least two network layers are the same, that is, the preset operators contained in at least two network layers are repeated. Among them, the operator characteristics of the preset operator may include: operator type (such as characterized by operation types such as convolution type, multiplication type, etc.) and / or operator shape. Among them, the operator shape is a shape or structural characteristic related to an operator (such as a matrix or tensor). The operator shape may refer to the dimension of the matrix or tensor corresponding to the operator, that is, the number of rows and columns (for matrices) or more dimensions (for tensors). For example, a 3x4 matrix has a shape of 3 rows and 4 columns. Accordingly, multiple repeated instruction fragments (i.e., sub-instructions) are used to implement all or part of the functions of the preset operator.

[0079] In an optional implementation, before the first processing core combines the shared instruction data with the multiple private instruction data stored in the first processing core, the following operations are further performed: the first processing core stores the shared instruction data received from the second processing core in the cache space; when the first processing core determines that the private instruction data to be executed contains an empty instruction, the shared instruction data corresponding to the empty instruction is obtained from the cache space. Among them, multiple cache queues can be set in the cache space to cache shared instruction data of different multiplexing levels. Usually, in the instruction-using core, there are multiple instructions (i.e., private instruction data), and under normal circumstances, the instructions are read and executed one by one, and a preset mark (such as a NOP empty instruction) for characterizing the empty instruction is inserted in advance at the position where the shared instruction needs to be obtained. After reading the empty instruction, the shared instruction required here is queried from the cache. If the shared instruction passed in by other cores has not yet been stored in the cache, continue to wait.

[0080] The above-mentioned method of inserting empty instructions is particularly suitable for the case where the instruction fragments in the target program to which the composite program instruction belongs do not meet the preset arrangement conditions. Accordingly, the composite program instruction may include: a plurality of instruction fragments arranged in sequence. Among them, some instruction fragments are private instruction data stored in the processing core, and some instruction fragments are shared instruction data that need to be obtained from the instruction supply core, wherein the empty instructions are pre-inserted at the instruction fragment position corresponding to the shared instruction data. It can be seen that the above-mentioned instruction fragments include the shared instruction data from the second processing core and the private instruction data stored in the first processing core; and the empty instructions correspond to the shared instruction data from the second processing core.

[0081] Among them, when the instruction fragments in the target program to which the compound program instruction belongs do not meet the preset arrangement conditions, the target program can be considered to be a target program of the second type. For example, part of the area or all of the area in the target program of the second type does not meet the preset arrangement conditions. It can be seen that the target program of the second type can be a complete program or a local area in the program. In order to improve the adaptability of the compound program instruction and enable it to be widely used in various types of target programs, the compound program instruction can be designed as a compound program instruction of a non-hierarchical structure. In this type of compound program instruction, a plurality of instruction fragments arranged in order are fixedly included. By storing the instruction fragments reused by multiple processing cores as shared instruction data, the problem of repeated storage of the same data by multiple processing cores can be avoided, thereby improving storage efficiency.

[0082] It can be seen that, when the compound program instruction is a non-hierarchical structure (that is, the instruction fragments in the target program to which the compound program instruction belongs do not meet the preset arrangement conditions), the compound program instruction can be set to be fixed to contain multiple instruction fragments arranged in sequence. Among the multiple instruction fragments arranged in sequence, the fragments shared by multiple processing cores are used as shared instruction data, and the fragments used only by this processing core are used as private instruction data. Considering that a processing core can store both shared instructions and its own private instructions, that is: the second processing core can combine the shared instruction data stored by the processing core with the private instruction data stored in the processing core to obtain the compound program instruction. Accordingly, in order to facilitate addressing operations within the processing core, in the case where the compound program instruction is a non-hierarchical structure, the second processing core can perform instruction processing in the following manner:

[0083] First, according to the multiple address information stored in the multiple address registers, multiple instruction fragments of the composite program instruction to be processed are obtained; wherein the multiple address information stored in the multiple address registers is dynamically updated according to the pre-configured instruction update program. Among them, the multiple instruction fragments of the composite program instruction to be processed may include the shared instruction data stored by the processing core mentioned above and the private instruction data stored in the processing core. For example, some instruction fragments of the composite program instruction to be processed belong to the shared instruction data, while other instruction fragments belong to the private instruction data. In the present application, multiple address registers are pre-set to store the storage addresses of multiple instruction fragments contained in the same composite program instruction. Among them, the number of multiple address registers can be determined according to the instruction complexity of the composite program instruction. If the instruction complexity of the composite program instruction is higher, the number of address registers is more; if the instruction complexity of the composite program instruction is lower, the number of address registers is less. Among them, the multiple address registers in the present application are used to record the storage addresses of the instruction fragments, which can be program counters or other various forms of registers. The present application does not limit the specific type and implementation method of the address register. In addition, since different compound program instructions correspond to different instruction fragments, during the process of processing different compound program instructions, the value of the address register is also dynamically updated to point to multiple instruction fragments in the compound program instruction currently being processed.

[0084] Then, the multiple instruction fragments are combined and processed to obtain the composite program instruction to be processed currently; wherein the composite program instruction to be processed currently is any instruction in the target program, and multiple composite program instructions in the target program reuse the same instruction fragment.

[0085] In the above method, the address register is dynamically updated by the instruction update program, so that the storage locations of multiple instruction fragments in the composite program instruction to be processed can be dynamically adapted. In addition, the same instruction fragment does not need to be stored repeatedly, but only needs to be stored as shared data in multiple processing cores. The instruction update program can flexibly point to multiple instruction fragments in the composite program instruction to be processed by dynamically adjusting the value of the address register. In short, by designing the instruction update program, the problem of redundant storage of the same instruction fragment can be avoided, thereby saving storage space and storage overhead.

[0086] Optionally, in the above method, the target program may include multiple compound program instructions, and the instruction update program may include multiple groups of update instructions corresponding one-to-one to the multiple compound program instructions; wherein, multiple address registers correspond one-to-one to multiple instruction fragments of each compound program instruction, and each group of update instructions further includes: multiple address update instructions corresponding one-to-one to the multiple address registers, each address update instruction is used to update the corresponding address register so that the address information in the address register points to the storage address of the instruction fragment corresponding to the address register in the compound program instruction currently to be processed. For example, if the number of multiple address registers is M, the instruction update program can be generated in the following manner: split the target program into multiple non-repeating instruction fragments, and store the multiple non-repeating instruction fragments in a preset address space; for the i-th compound program instruction in the target program, determine the storage address of the M instruction fragments of the i-th compound program instruction in the preset address space; based on the positional relationship between the storage address of the M instruction fragments of the i-1-th compound program instruction in the preset address space and the storage address of the M instruction fragments of the i-th compound program instruction in the preset address space, generate the i-th group of update instructions corresponding to the i-th compound program instruction in the instruction update program; wherein the i-th group of update instructions is used to update the M address information stored in the M address registers from the storage address of the M instruction fragments of the i-1-th compound program instruction in the preset address space to the storage address of the M instruction fragments of the i-th compound program instruction in the preset address space; wherein i is a natural number. Preferably, the instruction units contained in the target program that appear multiple times can be stored as a reusable instruction fragment in the first type of storage area in the preset address space; the instruction units contained in the target program that do not appear multiple times can be stored as a non-reusable instruction fragment in the second type of storage area in the preset address space; and the M address registers can further include: a first group of registers for pointing to the instruction fragments in the first type of storage area, and a second group of registers for pointing to the instruction fragments in the second type of storage area; and the i-th group of update instructions further includes: a first group of address update instructions for updating the first group of registers, and a second group of address update instructions for updating the second group of registers; wherein the update logic of the first group of address update instructions is different from that of the second group of address update instructions. Among them, the first type of storage area is mainly used to store instruction fragments corresponding to shared instruction data, and the second type of storage area is mainly used for instruction fragments corresponding to private instruction data. Through the above-mentioned separate storage and update methods, it is convenient to flexibly set different types of update instructions according to the characteristics of different types of instruction fragments, thereby improving the update efficiency.In addition, the instructions in the target program mentioned above may be coarse-grained instructions, and the instruction features of the coarse-grained instructions may include at least one of the following: the amount of information contained in the instruction is greater than a preset information amount threshold; the instruction processing time is greater than a preset time threshold; the instruction storage space is greater than a preset space threshold; the number of operators contained in the instruction is greater than a preset number threshold (for example, the more types and numbers of operators, the more complex the instruction). Correspondingly, neural network acceleration chips often require a larger storage space to store these instructions. However, due to the limited storage space inside the chip, the number of instructions that can be processed by the neural network acceleration chip is also limited due to the upper limit of the chip storage space, which seriously affects the processing power of the neural network acceleration chip. The multiplexing method in the present application can better solve the problem of insufficient space.

[0087] In an optional implementation, the shared instruction data includes: instruction data for characterizing the operator operation type; the private instruction data includes: instruction data for characterizing the operation parameters corresponding to the operator operation type; wherein the operator operation type includes: convolution type; the operation parameters corresponding to the operator operation type include: parameters for characterizing the convolution size, and / or parameters for characterizing the convolution input data. For example, a composite program instruction can be applied to a neural network; and the parent instruction contained in the composite program instruction may include: instruction data for characterizing the operator operation type; the child instruction contained in the composite program instruction may include: instruction data for characterizing the operation parameters corresponding to the operator operation type. wherein the operator operation type may include: convolution type; the operation parameters corresponding to the operator operation type may include: parameters for characterizing the convolution size, and / or parameters for characterizing the convolution input data. It can be seen from this that the instruction code corresponding to the operator operation type of the convolution type can be used as the parent instruction, and the data information for characterizing the specific parameters of the convolution can be used as the child instruction. Accordingly, multiple sub-instruction data in multiple compound program instructions are used to rely on different convolution parameters and implement multiple convolution processes based on the same convolution operation mode (ie, the same parent instruction).

[0088] In an optional implementation, the number of second processing cores is multiple, and the second processing core is determined based on the load data of multiple processing cores in the many-core system, and / or the second processing core is determined based on the routing data between the second processing core and the first processing core in the many-core system. Optionally, in order to achieve the purpose of load balancing, the idleness of each processing core can be dynamically determined, and based on the current idleness of each processing core, the processing core with an idleness higher than a preset idleness threshold is switched to a new second processing core, and in the subsequent processing process, the shared instruction data is sent to the new second processing core to maximize the performance of the entire many-core system.

[0089] In summary, the above-mentioned shared instruction data can be either a parent instruction or a child instruction in a hierarchical composite program instruction, or a reusable instruction fragment in a non-hierarchical composite program instruction. In addition, the shared instruction data can be either a complete instruction, or a partial content or all parent instructions in an instruction, and the present application does not limit the specific implementation form of the shared instruction data.

[0090] In addition, from the instruction level, the method in this application can be applied when multiple instructions are the same. For example, if the two executed networks both include convolution operations, the instructions corresponding to the two convolution operations can be shared.

[0091] In a related manner, although the multi-core chip integrates multiple processor cores on one chip, and each core can independently perform computing tasks, the overall performance and energy efficiency are improved through parallel processing. However, each core needs to store the complete instruction data that it needs to execute in the in-core storage. Even if there is a large amount of duplication of instruction data between multiple cores, it still needs to repeatedly occupy a large amount of on-core storage space. Through the method in this application, only one or several shared instructions need to be stored, and they are sent to the instruction-using core that uses the shared instructions in a relay manner, saving a lot of on-core storage.

[0092] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0093] In addition, the present disclosure also provides an instruction processing device, an electronic device, and a computer-readable storage medium, all of which can be used to implement any model training method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0094] Figure 4 A block diagram of a many-core system provided in an embodiment of the present disclosure.

[0095] Reference Figure 4 The embodiment of the present disclosure provides a many-core system, the many-core system includes a plurality of processing cores, the plurality of processing cores include: a second processing core 52 used as an instruction supply core, and a first processing core 51 used as an instruction use core, wherein:

[0096] The second processing core is used to send the stored shared instruction data to the first processing core;

[0097] The first processing core combines the shared instruction data with multiple private instruction data stored in the first processing core to obtain multiple composite program instructions, and runs the multiple composite program instructions through the first processing core; wherein the multiple composite program instructions reuse the shared instruction data.

[0098] In an optional implementation, if there are multiple first processing cores, the second processing core is used to send the stored shared instruction data to the first processing core in the following manner:

[0099] The second processing core determines a plurality of first processing cores corresponding to the shared instruction data, and determines a processing core transmission order among the plurality of first processing cores according to the position distribution of the plurality of first processing cores;

[0100] The shared instruction data is sent to the i-th first processing core according to the processing core transmission order, so that the i-th first processing core forwards the shared instruction data to the i+1-th first processing core; wherein i is a natural number.

[0101] In an optional implementation, when the number of shared instruction data stored in the second processing core is multiple and different shared instruction data depend on different input data, the second processing core is specifically configured to:

[0102] determining an instruction transmission order among the plurality of shared instruction data according to a data transmission order among the plurality of input data corresponding to the first processing core;

[0103] The second processing core sends the plurality of shared instruction data to the first processing core in sequence according to the instruction transmission order.

[0104] In an optional implementation, the shared instruction data stored in the second processing core includes: shared instruction data corresponding to a plurality of different multiplexing levels; wherein the number of instruction usage cores of the shared instruction data corresponding to different multiplexing levels is different;

[0105] Then the second processing core is specifically used to send the stored shared instruction data to the first processing core in the following manner:

[0106] The second processing core determines the instruction use core corresponding to the m-th multiplexing level, and sends the shared instruction data corresponding to the m-th multiplexing level to the instruction use core corresponding to the m-th multiplexing level;

[0107] The second processing core determines the instruction use core corresponding to the m+1th multiplexing level, and sends the shared instruction data corresponding to the m+1th multiplexing level to the instruction use core corresponding to the m+1th multiplexing level;

[0108] Here, m is a natural number, and the number of instruction usage cores corresponding to the m-th multiplexing level is greater than the number of instruction usage cores corresponding to the m+1-th multiplexing level.

[0109] In an optional implementation, the first processing core is specifically configured to:

[0110] storing the shared instruction data corresponding to the mth multiplexing level from the second processing core through the mth data queue, and storing the shared instruction data corresponding to the m+1th multiplexing level from the second processing core through the m+1th data queue;

[0111] The shared instruction data corresponding to the m-th multiplexing level and the shared instruction data corresponding to the (m+1)-th multiplexing level are respectively combined with the plurality of private instruction data stored in the first processing core.

[0112] In an optional implementation, the instruction fragments in the target program to which the compound program instruction belongs meet a preset arrangement condition, and the compound program instruction includes: first instruction data whose data type is a parent instruction type, and second instruction data whose data type is a child instruction type; wherein the second instruction data of the child instruction type contained in the plurality of compound program instructions can reuse the first instruction data of the same parent instruction type;

[0113] Then the first processing core is specifically used for:

[0114] Determine respectively whether the data type of the shared instruction data corresponding to each multiplexing level is a parent instruction type or a child instruction type;

[0115] The shared instruction data of the parent instruction type are combined with the shared instruction data of the child instruction type and the multiple private instruction data stored in the first processing core.

[0116] In an optional implementation, the first processing core is further used to: store the shared instruction data received from the second processing core into a cache space; and when it is determined that the private instruction data to be executed is associated with an empty instruction, obtain the shared instruction data corresponding to the empty instruction from the cache space.

[0117] In an optional implementation, the instruction fragment in the target program to which the composite program instruction belongs does not meet the preset arrangement condition, and the composite program instruction includes: a plurality of instruction fragments arranged in sequence; wherein the instruction fragments include: shared instruction data from the second processing core, and private instruction data stored in the first processing core; and the empty instruction corresponds to the shared instruction data from the second processing core.

[0118] In an optional implementation, the shared instruction data includes: instruction data for characterizing an operator operation type; the private instruction data includes: instruction data for characterizing an operation parameter corresponding to the operator operation type;

[0119] Among them, the operator operation type includes: a convolution type; the operation parameters corresponding to the operator operation type include: a parameter used to characterize a convolution size, and / or a parameter used to characterize convolution input data.

[0120] In an optional implementation, the number of the second processing cores is multiple, and the second processing core is determined based on load data of multiple processing cores in the many-core system, and / or the second processing core is determined based on routing data between the second processing core and the first processing core in the many-core system.

[0121] In an optional implementation, the many-core system further includes:

[0122] A routing processing device, configured to analyze the sharing relationship between program instructions corresponding to multiple processing cores in the many-core system through a compiler, determine the instruction fragments shared by multiple associated processing cores according to the sharing relationship; segment the program instructions according to the instruction fragments shared by the multiple associated processing cores to obtain shared instruction data in the program instructions; and determine a transmission path of the shared instruction data in the many-core system according to the positional relationship between the multiple associated processing cores corresponding to the shared instruction data;

[0123] The first processing core and / or the second processing core is any one of the associated processing cores.

[0124] In an optional implementation, the second processing core is further used to: combine the shared instruction data stored in the processing core with the private instruction data stored in the processing core to obtain a composite program instruction.

[0125] In an optional implementation manner, the instruction of the target program to which the composite program instruction belongs is a coarse-grained instruction, and the instruction features of the coarse-grained instruction include at least one of the following:

[0126] The amount of information contained in the instruction is greater than the preset information amount threshold;

[0127] The instruction processing time is longer than the preset time threshold;

[0128] The instruction storage space is greater than the preset space threshold;

[0129] The number of operators contained in the instruction is greater than the preset number threshold.

[0130] Figure 5A block diagram of an electronic device provided in an embodiment of the present disclosure.

[0131] Reference Figure 5 An embodiment of the present disclosure provides an electronic device, which includes: at least one processor 901; at least one memory 902, and one or more I / O interfaces 903, connected between the processor 901 and the memory 902; wherein the memory 902 stores one or more computer programs that can be executed by the at least one processor 901, and the one or more computer programs are executed by the at least one processor 901 so that the at least one processor 901 can execute the above-mentioned instruction processing method.

[0132] In some embodiments, the processing device may be a brain-like chip, which can use vectorized computing and needs to load the weight information and other parameters of the neural network model through an external memory such as a double data rate (DDR) synchronous dynamic random access memory. Therefore, the batch processing used in the embodiments of the present disclosure has a higher computing efficiency.

[0133] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above instruction processing method when executed by a processor / processing core. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0134] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned instruction processing method.

[0135] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0136] As is known to those of ordinary skill in the art, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0137] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0138] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0139] The computer program product described herein may be implemented in hardware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), etc.

[0140] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0141] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0142] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0143] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0144] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for processing instructions based on a many-core system, wherein the many-core system includes a plurality of processing cores, the method comprising: The second processing core sends the stored shared instruction data to the first processing core; The first processing core combines the shared instruction data with multiple private instruction data stored in the first processing core to obtain multiple composite program instructions, and runs the multiple composite program instructions through the first processing core; wherein the multiple composite program instructions reuse the shared instruction data.

2. The method according to claim 1, wherein: If there are multiple first processing cores, the second processing core sending the stored shared instruction data to the first processing core includes: The second processing core determines a plurality of first processing cores corresponding to the shared instruction data, and determines a processing core transmission order among the plurality of first processing cores according to the position distribution of the plurality of first processing cores; The shared instruction data is sent to the i-th first processing core according to the processing core transmission order, so that the i-th first processing core forwards the shared instruction data to the i+1-th first processing core; wherein i is a natural number.

3. The method according to claim 1 or 2, wherein: In a case where the number of shared instruction data stored in the second processing core is multiple and different shared instruction data depend on different input data, the second processing core sending the stored shared instruction data to the first processing core includes: determining an instruction transmission order among the plurality of shared instruction data according to a data transmission order among the plurality of input data corresponding to the first processing core; The second processing core sends the plurality of shared instruction data to the first processing core in sequence according to the instruction transmission order.

4. The method according to claim 1, wherein: The shared instruction data stored in the second processing core includes: shared instruction data corresponding to a plurality of different multiplexing levels; wherein the number of instruction usage cores of the shared instruction data corresponding to different multiplexing levels is different; Then the second processing core sending the stored shared instruction data to the first processing core includes: The second processing core determines the instruction use core corresponding to the m-th multiplexing level, and sends the shared instruction data corresponding to the m-th multiplexing level to the instruction use core corresponding to the m-th multiplexing level; The second processing core determines the instruction use core corresponding to the m+1th multiplexing level, and sends the shared instruction data corresponding to the m+1th multiplexing level to the instruction use core corresponding to the m+1th multiplexing level; Here, m is a natural number, and the number of instruction usage cores corresponding to the m-th multiplexing level is greater than the number of instruction usage cores corresponding to the m+1-th multiplexing level.

5. The method according to claim 4, wherein: The first processing core combining the shared instruction data with the plurality of private instruction data stored in the first processing core respectively comprises: The first processing core stores the shared instruction data corresponding to the mth multiplexing level from the second processing core through the mth data queue, and stores the shared instruction data corresponding to the m+1th multiplexing level from the second processing core through the m+1th data queue; The shared instruction data corresponding to the m-th multiplexing level and the shared instruction data corresponding to the (m+1)-th multiplexing level are respectively combined with the plurality of private instruction data stored in the first processing core.

6. The method according to claim 5, wherein: The instruction fragments in the target program to which the compound program instruction belongs meet the preset arrangement condition, and the compound program instruction includes: first instruction data whose data type is a parent instruction type, and second instruction data whose data type is a child instruction type; wherein the second instruction data of the child instruction type contained in the plurality of compound program instructions can reuse the first instruction data of the same parent instruction type; Then, combining the shared instruction data corresponding to the mth multiplexing level and the shared instruction data corresponding to the m+1th multiplexing level with the plurality of private instruction data stored in the first processing core respectively includes: Determine respectively whether the data type of the shared instruction data corresponding to each multiplexing level is a parent instruction type or a child instruction type; The shared instruction data of the parent instruction type are combined with the shared instruction data of the child instruction type and the multiple private instruction data stored in the first processing core.

7. The method according to claim 1, wherein: Before the first processing core combines the shared instruction data with the plurality of private instruction data stored in the first processing core respectively, the method further includes: The first processing core stores the shared instruction data received from the second processing core into a cache space; When the first processing core determines that the private instruction data to be executed is associated with an empty instruction, the shared instruction data corresponding to the empty instruction is acquired from the cache space.

8. The method according to claim 7, wherein: The instruction fragment in the target program to which the composite program instruction belongs does not meet the preset arrangement condition, and the composite program instruction includes: a plurality of instruction fragments arranged in sequence; wherein the instruction fragment includes: shared instruction data from the second processing core, and private instruction data stored in the first processing core; and the empty instruction corresponds to the shared instruction data from the second processing core.

9. The method according to claim 1 or 2, wherein: The shared instruction data includes: instruction data for characterizing an operator operation type; the private instruction data includes: instruction data for characterizing an operation parameter corresponding to the operator operation type; Among them, the operator operation type includes: a convolution type; the operation parameters corresponding to the operator operation type include: a parameter used to characterize a convolution size, and / or a parameter used to characterize convolution input data.

10. The method according to claim 1 or 2, wherein: There are multiple second processing cores, and the second processing cores are determined according to load data of multiple processing cores in the many-core system, and / or the second processing cores are determined according to routing data between the second processing core and the first processing core in the many-core system.

11. The method according to claim 1 or 2, wherein: The method further comprises: Analyzing, by a compiler, a sharing relationship between program instructions corresponding to a plurality of processing cores in the many-core system, and determining instruction fragments shared by a plurality of associated processing cores according to the sharing relationship; According to the instruction fragments shared by the multiple associated processing cores, the program instructions are segmented to obtain shared instruction data in the program instructions; Determining a transmission path of the shared instruction data in the many-core system according to a positional relationship between a plurality of associated processing cores corresponding to the shared instruction data; The first processing core and / or the second processing core is any one of the associated processing cores.

12. The method according to claim 1, wherein: The method further comprises: The second processing core combines the shared instruction data stored in the processing core with the private instruction data stored in the processing core to obtain a composite program instruction.

13. The method according to claim 1, wherein: The instruction of the target program to which the composite program instruction belongs is a coarse-grained instruction, and the instruction features of the coarse-grained instruction include at least one of the following: The amount of information contained in the instruction is greater than the preset information amount threshold; The instruction processing time is longer than the preset time threshold; The instruction storage space is greater than the preset space threshold; The number of operators contained in the instruction is greater than the preset number threshold.

14. A many-core system, the many-core system comprising a plurality of processing cores, the plurality of processing cores comprising: A second processing core for serving as an instruction supply core, and a first processing core for serving as an instruction use core, wherein: The second processing core is used to send the stored shared instruction data to the first processing core; The first processing core is used to combine the shared instruction data with multiple private instruction data stored in the first processing core to obtain multiple composite program instructions, and run the multiple composite program instructions; wherein the multiple composite program instructions reuse the shared instruction data.

15. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 13.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the method according to any one of claims 1 to 13.

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