Driving backplane and display panel

Abstract

The present application discloses a driving backplane and a display panel, which belong to the field of display technology. The driving backplane includes: a substrate, and a plurality of pixel driving circuits, a plurality of first data lines and a plurality of second data lines located on one side of the substrate. A plurality of first pixel driving circuits in a column of pixel driving circuits are electrically connected to a first data line, and a plurality of second pixel driving circuits in a column of pixel driving circuits are electrically connected to a second data line. In a first direction, the signal output points in the first pixel driving circuit and / or the second pixel driving circuit are distributed between the first data line and the second data line, and the minimum distance between the signal output point and the first data line, and the minimum distance between the signal output point and the second data line are both greater than 0. In this way, the two data lines can provide data signals to different pixel driving circuits respectively, ensuring that each pixel driving circuit has sufficient charging time and improving the display effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving backplane and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) is a current-type organic light-emitting device. OLED display panels are widely used in the display field due to their advantages such as thin thickness, self-luminescence, high resolution, and fast response speed.

[0003] An OLED display panel typically includes a driver backplane and multiple light-emitting devices, which are electrically connected to the driver backplane. The driver backplane includes a substrate, as well as multiple pixel driver circuits and multiple data lines located on one side of the substrate. The multiple pixel driver circuits are arranged in multiple rows and columns, and the multiple columns of pixel driver circuits are electrically connected to the multiple data lines in a one-to-one correspondence. Each data line provides a data signal to a corresponding column of pixel driver circuits. When a data signal is input to a pixel driver circuit, the row corresponding to this pixel driver circuit can be turned on for charging.

[0004] Since one data line provides a data signal to each pixel driving circuit in a corresponding column of pixel driving circuits, to prevent mischarging, the pixel driving circuits are turned on row by row for charging, which results in a shorter charging time for each pixel driving circuit and affects the display effect of the display panel. Summary of the Invention

[0005] This application provides a driving backplane and a display panel that can solve the problem of short charging time of pixel driving circuits. The technical solution is as follows:

[0006] In one aspect, a driving backplane is provided, comprising: a substrate, and a plurality of pixel driving circuits, a plurality of first data lines, and a plurality of second data lines located on one side of the substrate;

[0007] The plurality of pixel driving circuits are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction; the first data lines and the second data lines extend in directions parallel to the second direction; a column of the pixel driving circuits includes a plurality of first pixel driving circuits and a plurality of second pixel driving circuits, the plurality of first pixel driving circuits are electrically connected to one first data line, the plurality of second pixel driving circuits are electrically connected to one second data line, and the first data line and the second data line are located on both sides of the column of the pixel driving circuits;

[0008] The first pixel driving circuit and the second pixel driving circuit both have a signal output point, and the signal output point is used to be electrically connected to the light emitting device;

[0009] The signal output points in the first pixel driving circuit and / or the second pixel driving circuit are distributed between the first data line and the second data line in the first direction, and in the first direction, the minimum distance between the signal output point and the first data line, and the minimum distance between the signal output point and the second data line are both greater than 0.

[0010] Optionally, in the first direction, a minimum distance between a signal output point in the first pixel driving circuit and the first data line is greater than or equal to a minimum distance between a signal output point in the first pixel driving circuit and the second data line;

[0011] And / or, in the first direction, the minimum distance between the signal output point in the second pixel driving circuit and the second data line is greater than or equal to the minimum distance between the signal output point in the second pixel driving circuit and the first data line.

[0012] Optionally, the first pixel driving circuit and / or the second pixel driving circuit includes:

[0013] a first transistor, wherein a gate of the first transistor is electrically connected to a first reset signal line, a first electrode of the first transistor is electrically connected to a first initial power line, and a second electrode of the first transistor is electrically connected to a first node;

[0014] a second transistor, wherein a gate of the second transistor is electrically connected to the gate signal line, a first electrode of the second transistor is electrically connected to the third node, and a second electrode of the second transistor is electrically connected to the first node;

[0015] a third transistor, wherein a gate of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the second node;

[0016] a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the gate signal line, a first electrode of the fourth transistor is electrically connected to the first data line or the second data line, and a second electrode of the fourth transistor is electrically connected to the second node;

[0017] a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the light emission control signal line, a first electrode of the fifth transistor is electrically connected to the first power line, and a second electrode of the fifth transistor is electrically connected to the second node;

[0018] a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the light emission control signal line, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the signal output point;

[0019] a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the second reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial power line, and a second electrode of the seventh transistor is electrically connected to the signal output point;

[0020] A storage capacitor, wherein a first capacitor electrode of the storage capacitor is connected to the first power line, and a second capacitor electrode of the storage capacitor is electrically connected to the first node.

[0021] Optionally, the third node includes a first body portion and a second body portion, the first body portion extends along the first direction, and the second body portion extends along the second direction; one end of the first body portion is electrically connected to the second body portion, the other end of the first body portion is electrically connected to the first electrode of the third transistor, one end of the second body portion is electrically connected to the first electrode of the second transistor, and the other end of the second body portion is electrically connected to the first electrode of the sixth transistor;

[0022] The orthographic projection of the second body portion in the first pixel driving circuit on the substrate does not overlap with the orthographic projection of the second data line on the substrate.

[0023] Optionally, an orthographic projection of the first body portion of the first pixel driving circuit on the substrate and an orthographic projection of the second data line on the substrate have a first overlapping area;

[0024] The first power line has a first shielding portion, which is located between the first body portion and the second data line in a direction perpendicular to the substrate, and the first overlapping area is located within an orthographic projection of the first shielding portion on the substrate.

[0025] Optionally, in the first direction, a minimum distance between a signal output point in the first pixel driving circuit and the second data line is greater than or equal to a minimum distance between a second body portion in the first pixel driving circuit and the second data line.

[0026] Optionally, the driving backplane further includes: a light shielding layer, the light shielding layer being electrically connected to the first power line; orthographic projections of the channel regions of the first transistor, the second transistor, the third transistor, and the fourth transistor on the substrate are all located within the orthographic projection of the light shielding layer on the substrate;

[0027] The light-shielding layer has a first light-shielding trace, the overall extension direction of the first light-shielding trace is parallel to the first direction, and the orthographic projection of the first light-shielding trace on the substrate does not overlap with the orthographic projection of the first strip portion on the substrate.

[0028] Optionally, the driving backplane further includes: an auxiliary power line, the overall extension direction of the auxiliary power line being parallel to the second direction, and the auxiliary power line having: auxiliary line segments distributed in the first direction between the first data line and a signal output point in the first pixel driving circuit;

[0029] In the first direction, the minimum distance between the signal output point of the first pixel driving circuit and the auxiliary line segment is less than or equal to the minimum distance between the signal output point of the first pixel driving circuit and the second data line.

[0030] Optionally, the driving backplane further includes: a light shielding layer, the light shielding layer being electrically connected to the first power line;

[0031] The light-shielding layer has a second light-shielding trace, the overall extension direction of the second light-shielding trace is parallel to the second direction, and the orthographic projection of the second light-shielding trace on the substrate overlaps with the orthographic projection of the power auxiliary line on the substrate.

[0032] Optionally, the first node includes a first part, a second part, and a third part, the first end of the first part, the first end of the second part, and the first end of the third part are electrically connected to each other, the second end of the first part is electrically connected to the second electrode of the first transistor, the second end of the second part is electrically connected to the second electrode of the second transistor, and the second end of the third part is electrically connected to the gate of the third transistor;

[0033] The orthographic projection of the second light-shielding trace on the substrate overlaps with the orthographic projection of the first portion on the substrate.

[0034] Optionally, an orthographic projection of the first portion on the substrate and an orthographic projection of the power auxiliary line on the substrate have a second overlapping area;

[0035] The first power line further has a second shielding portion, which is located between the first portion and the auxiliary power line in a direction perpendicular to the substrate, and the second overlapping area is located within an orthographic projection of the second shielding portion on the substrate.

[0036] Optionally, there is a transition zone connected to the second overlapping area in the orthographic projection of the power auxiliary line on the substrate. The transition zone is located outside the orthographic projection of the second light-shielding line on the substrate and overlaps with the orthographic projection of the second shielding part on the substrate.

[0037] Optionally, the second node includes a third body and a fourth body, the third body extends along the first direction, and the fourth body extends along the second direction; one end of the third body is electrically connected to the fourth body, the other end of the third body is electrically connected to the second electrode of the third transistor, one end of the fourth body is electrically connected to the second electrode of the fourth transistor, and the other end of the fourth body is electrically connected to the second electrode of the fifth transistor;

[0038] The orthographic projection of the third body portion of the first pixel driving circuit on the substrate and the orthographic projection of the first data line on the substrate have a third overlapping area;

[0039] The first power line further has a third shielding portion, which is located between the third body portion and the first data line in a direction perpendicular to the substrate, and the third overlapping area is located within an orthographic projection of the third shielding portion on the substrate.

[0040] Optionally, in the first direction, the fourth transistor in the first pixel driving circuit is located on a side of the first data line away from a signal output point in the first pixel driving circuit, and the fourth transistor in the second pixel driving circuit is located on a side of the second data line away from the signal output point in the second pixel driving circuit;

[0041] In the first direction, a minimum distance between the fourth transistor in the first pixel driving circuit and the first data line is equal to a minimum distance between the fourth transistor in the second pixel driving circuit and the second data line.

[0042] Optionally, the driving backplane has a plurality of periodic partitions, eight pixel driving circuits are distributed in one periodic partition, and the eight pixel driving circuits are arranged in two rows and four columns;

[0043] Among them, within the same periodic partition, the two pixel driving circuits arranged in the second direction are respectively: one first pixel driving circuit and one second pixel driving circuit; the four pixel driving circuits arranged in the first direction are respectively: two first pixel driving circuits distributed continuously and two second pixel driving circuits distributed continuously.

[0044] Optionally, the driving backplane further includes: a first power line; the first power line has a plurality of second shielding portions, the plurality of second shielding portions corresponding to the plurality of pixel driving circuits, and the second shielding portions and the corresponding pixel driving circuits are distributed in the same sub-pixel area;

[0045] Among them, for the two second shielding parts arranged adjacent to each other in the second direction within the same periodic partition, the orthographic projection of one second shielding part on the substrate overlaps with the orthographic projection of the first data line on the substrate, and does not coincide with the orthographic projection of the second data line on the substrate; the orthographic projection of the other second shielding part on the substrate overlaps with the orthographic projection of the second data line on the substrate, and does not coincide with the orthographic projection of the first data line on the substrate.

[0046] Optionally, the driving backplane has a display area and a non-display area distributed around the display area; the plurality of pixel driving circuits, the plurality of first data lines, and the plurality of second data lines are all located at least within the display area;

[0047] The driving backplane further includes: a multiplexer and a plurality of binding pads, wherein the multiplexer and the plurality of binding pads are both located in the non-display area, and the multiplexer is closer to the display area than the plurality of binding pads;

[0048] The multiplexer has a plurality of first ports on a side facing the display area, and a plurality of second ports on a side facing away from the display area; the plurality of first ports are electrically connected to the plurality of first data lines and the plurality of second data lines, and the plurality of second ports are electrically connected to the plurality of binding pads.

[0049] On the other hand, a display panel is provided, comprising: any one of the above-mentioned driving backplanes, and a plurality of light-emitting devices electrically connected to the driving backplane.

[0050] Optionally, the display panel further comprises: a plurality of first electrode blocks disposed separately; the plurality of first electrode blocks correspond to the plurality of light-emitting devices, and the anodes of the light-emitting devices are at least part of the corresponding first electrode blocks;

[0051] The driving backplane further includes: a first power line; the first power line includes: a plurality of first sub-power lines extending along the second direction, and a plurality of second sub-power lines extending along the first direction; the first sub-power lines are electrically connected to the second sub-power lines at an intersection; in the first direction, the width of the first sub-power line is greater than the width of the first data line, and greater than the width of the second data line;

[0052] In which, the orthographic projection of the first electrode block on the substrate overlaps with the orthographic projections of the adjacently arranged first data line and the second data line on the substrate, and overlaps with the orthographic projections of two adjacently arranged first sub-power lines on the substrate; in the first direction, the adjacently arranged first data line and the second data line are distributed between two adjacent first sub-power lines.

[0053] The beneficial effects of the technical solution provided by this application include at least:

[0054] Multiple first pixel driving circuits in a column of pixel driving circuits can be electrically connected to a corresponding first data line, and multiple second pixel driving circuits in a column of pixel driving circuits can be electrically connected to a corresponding second data line. In this way, the two data lines can respectively provide data signals to different pixel driving circuits, thereby ensuring that each pixel driving circuit has sufficient charging time, thereby improving the display effect of the display panel. At the same time, the signal output points in the first pixel driving circuit and / or the second pixel driving circuit can be distributed between the corresponding first data line and the corresponding second data line in the first direction, and the minimum distance between the signal output point and the corresponding first data line, as well as the minimum distance between the signal output point and the corresponding second data line in the first direction, can both be greater than zero. In this way, the distance between the first data line and the second data line can be large, thereby preventing the first data line and the second data line from interfering with each other. It can also ensure that the signal output point has a certain distance from each of the first data line and the second data line, thereby reducing the impact of the data signals loaded on the first data line and the second data line on the signal output point, making the potential of the signal output point more stable, and further improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] Figure 1 This is a top view of a driving backplane provided in an embodiment of the present application;

[0057] Figure 2 This is a structural diagram of a driving backplane provided in an embodiment of the present application;

[0058] Figure 3 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0059] Figure 4This is a schematic diagram of the film structure of a driving backplane provided in an embodiment of the present application;

[0060] Figure 5 This is a structural layout of a light shielding layer in a driving backplane provided in an embodiment of the present application;

[0061] Figure 6 This is a structural layout of an active layer in a driver backplane provided in an embodiment of the present application;

[0062] Figure 7 This is a structural layout of a first gate layer in a driving backplane provided in an embodiment of the present application;

[0063] Figure 8 This is a structural layout of a second gate layer in a driving backplane provided in an embodiment of the present application;

[0064] Figure 9 This is a structural layout of a first conductive layer in a driving backplane provided in an embodiment of the present application;

[0065] Figure 10 This is a structural layout of a second conductive layer in a driving backplane provided in an embodiment of the present application;

[0066] Figure 11 This is a structural layout of a light shielding layer, an active layer, and a first gate layer stacked in a driving backplane provided by an embodiment of the present application;

[0067] Figure 12 The present invention provides a structural layout of a driving backplane provided by an embodiment of the present invention, in which an active layer, a first gate layer, a second gate layer, a first conductive layer and a second conductive layer are superimposed.

[0068] Figure 13 This is a structural layout of a light shielding layer, an active layer, a first gate layer, and a first conductive layer stacked in a driving backplane provided by an embodiment of the present application;

[0069] Figure 14 This is a structural layout of a superimposed light shielding layer and an active layer in a driving backplane provided by an embodiment of the present application;

[0070] Figure 15 This is a structural layout of a light shielding layer, an active layer, a first gate layer, and a second gate layer stacked in a driving backplane provided by an embodiment of the present application;

[0071] Figure 16 This is a structural layout of a light shielding layer, an active layer, a first gate layer, a second gate layer, and a first conductive layer in a driving backplane provided by an embodiment of the present application;

[0072] Figure 17 1 is a schematic diagram of a second overlapping region and surrounding film layer structure provided in an embodiment of the present application;

[0073] Figure 18 This is a structural diagram of a driving backplane provided in an embodiment of the present application;

[0074] Figure 19 This is a top view of a driving backplane provided in an embodiment of the present application;

[0075] Figure 20 Schematic diagram of a film structure of a display panel provided in an embodiment of the present application;

[0076] Figure 21 This is a structural diagram of a display panel provided in an embodiment of the present application;

[0077] Figure 22 This is a structural diagram of a driving backplane provided in an embodiment of the present application. DETAILED DESCRIPTION

[0078] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0079] The transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode and the drain is referred to as the second electrode; alternatively, the drain can be referred to as the first electrode and the source can be referred to as the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, and the two ends are the source and drain respectively.

[0080] Please refer to Figure 1 and Figure 2 , Figure 1 is a top view of a driving backplane provided in an embodiment of the present application, Figure 2 This is a structural layout of a driving backplane provided in an embodiment of the present application. The driving backplane 100 may include a substrate 01, and multiple pixel driving circuits 02, multiple first data lines DT1, and multiple second data lines DT2 located on one side of the substrate 01. The driving backplane 100 may include multiple sub-pixel regions, each corresponding to a plurality of pixel driving circuits 02, and the pixel driving circuits 02 may be located within the corresponding sub-pixel regions.

[0081] The plurality of pixel driving circuits 02 may be arranged in a plurality of columns along the first direction X and in a plurality of rows along the second direction Y.

[0082] The extension directions of the first data line DT1 and the second data line DT2 may both be parallel to the second direction Y. Multiple columns of pixel driving circuits 02 may correspond to multiple first data lines DT1 and multiple second data lines DT2. A portion of the pixel driving circuits 02 in a column of pixel driving circuits 02 may be electrically connected to a corresponding first data line DT1, and another portion of the pixel driving circuits 02 may be electrically connected to a corresponding second data line DT2.

[0083] A column of pixel driving circuits 02 may include multiple first pixel driving circuits 021 and multiple second pixel driving circuits 022, and the multiple first pixel driving circuits 021 and the multiple second pixel driving circuits 022 may be arranged alternately. The multiple first pixel driving circuits 021 in a column of pixel driving circuits 02 may each be electrically connected to a corresponding first data line DT1, and the multiple second pixel driving circuits 022 in a column of pixel driving circuits 02 may each be electrically connected to a corresponding second data line DT2, and a first data line DT1 and a second data line DT2 may be located on both sides of the corresponding column of pixel driving circuits 02.

[0084] In this way, a column of pixel driving circuits 02 can correspond to a first data line DT1 and a second data line DT2, and these two data lines can provide data signals to multiple first pixel driving circuits 021 and multiple second pixel driving circuits 022 respectively, thereby ensuring that each pixel driving circuit 02 has sufficient charging time, thereby improving the display effect of the display panel.

[0085] Any pixel driving circuit 02 may have a signal output point 023, that is, both the first pixel driving circuit 021 and the second pixel driving circuit 022 may have a signal output point 023. The signal output point 023 may be used to electrically connect to a light-emitting device. In this way, the pixel driving circuit 02 can drive the light-emitting device to emit light. Multiple pixel driving circuits 02 can drive multiple light-emitting devices to emit light, thereby allowing the display panel to display a corresponding image.

[0086] The signal output points 023 in the first pixel driving circuit 021 and / or the second pixel driving circuit 022 can be distributed between the corresponding first data line DT1 and the corresponding second data line DT2 in the first direction X. This ensures a large distance between the first data line DT1 and the second data line DT2, preventing mutual influence between the first data line DT1 and the second data line DT2. Furthermore, in the first direction X, the minimum distance between the signal output point 023 and the corresponding first data line DT1 can be greater than zero, and the minimum distance between the signal output point 023 and the corresponding second data line DT2 can also be greater than zero. This ensures a certain distance between the signal output point 023 and both the first data line DT1 and the second data line DT2, thereby reducing the impact of the data signals loaded on the first data line DT1 and the second data line DT2 on the signal output point 023. This ensures a relatively stable potential at the signal output point 023, further improving the display effect.

[0087] In summary, an embodiment of the present application provides a driving backplane, which may include a substrate, and a plurality of pixel driving circuits, a plurality of first data lines, and a plurality of second data lines located on one side of the substrate. A plurality of first pixel driving circuits in a column of pixel driving circuits may be electrically connected to a corresponding first data line, and a plurality of second pixel driving circuits in a column of pixel driving circuits may be electrically connected to a corresponding second data line. In this way, the two data lines may respectively provide data signals to different pixel driving circuits, thereby ensuring that each pixel driving circuit has sufficient charging time, thereby improving the display effect of the display panel. At the same time, the signal output points in the first pixel driving circuit and / or the second pixel driving circuit may be distributed between the corresponding first data line and the corresponding second data line in the first direction, and in the first direction, the minimum distance between the signal output point and the corresponding first data line, and the minimum distance between the signal output point and the corresponding second data line may both be greater than 0. In this way, it is possible to ensure that the distance between the first data line and the second data line is large, thereby avoiding mutual influence between the first data line and the second data line; it is also possible to ensure that there is a certain distance between the signal output point and the first data line and the second data line, thereby reducing the influence of the data signal loaded on the first data line and the second data line on the signal output point, making the potential of the signal output point more stable, and further improving the display effect.

[0088] In one possible implementation, see Figure 2 For any first pixel driving circuit 021 , in the first direction X, the minimum distance between the signal output point 023 in the first pixel driving circuit 021 and the first data line DT1 may be greater than or equal to the minimum distance between the signal output point 023 in the first pixel driving circuit 021 and the second data line DT2 ;

[0089] And / or, for any second pixel driving circuit 022, in the first direction X, the minimum distance between the signal output point 023 in the second pixel driving circuit 022 and the second data line DT2 may be greater than or equal to the minimum distance between the signal output point 023 in the second pixel driving circuit 022 and the first data line DT1.

[0090] In this way, the distance between the signal output point 023 in the first pixel driving circuit 021 and / or the second pixel driving circuit 022 and the first data line DT1 and the second data line DT2 in the first direction X can be relatively large, thereby further reducing the impact of the data signal loaded on the first data line DT1 and the second data line DT2 on the signal output point 023, making the potential of the signal output point 023 more stable, and further improving the display effect. At the same time, in the first direction X, the distance between the signal output point 023 in the first pixel driving circuit 021 and the first data line DT1, and the distance between the signal output point 023 in the second pixel driving circuit 022 and the second data line DT2 can also be relatively large, thereby allowing other wiring to be arranged between the signal output point 023 in the first pixel driving circuit 021 and the first data line DT1, and between the signal output point 023 in the second pixel driving circuit 022 and the second data line DT2.

[0091] Please refer to Figure 3 The first pixel driving circuit 021 and / or the second pixel driving circuit 022 may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor C1.

[0092] The first transistor T1 may be a first reset transistor. The gate of the first transistor T1 is electrically connected to the first reset signal line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial power line VINIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The first transistor T1 can respond to a first reset signal provided by the first reset signal line RST1 and transmit the first initial power signal provided by the first initial power line VINIT1 to the first node N1, thereby resetting the first node N1. In an embodiment of the present application, the first transistor T1 may be a dual-gate transistor, that is, the first transistor T1 may include two transistors connected in series.

[0093] The second transistor T2 may be a compensation transistor. The gate of the second transistor T2 is electrically connected to the gate signal line GATE, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the first node N1. The second transistor T2 may adjust the potentials of the first node N1 and the third node N3 in response to the gate drive signal provided by the gate signal line GT. In an embodiment of the present application, the second transistor T2 may be a dual-gate transistor, that is, the second transistor T2 may include two transistors connected in series.

[0094] The third transistor T3 may be a driving transistor. A gate of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 may transmit a driving signal to the third node N3 in response to the potentials of the first node N1 and the second node N2.

[0095] The fourth transistor T4 can be a data write transistor. The gate of the fourth transistor T4 is electrically connected to the gate signal line GATE, the first electrode of the fourth transistor T4 is electrically connected to the corresponding first data line DT1 or second data line DT2, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The fourth transistor T4 can respond to the gate drive signal provided by the gate signal line GT and transmit the data signal provided by the corresponding first data line DT1 or second data line DT2 to the second node N2.

[0096] The fifth transistor T5 may be a first light emission control transistor. A gate of the fifth transistor T5 is electrically connected to the light emission control signal line EM, a first electrode of the fifth transistor T5 is electrically connected to the driving power supply line VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2. The fifth transistor T5 may transmit a first light emission control signal to the second node N2 in response to a light emission control signal provided by the light emission control signal line EM.

[0097] The sixth transistor T6 may be a second light emission control transistor. A gate of the sixth transistor T6 is electrically connected to the light emission control signal line EM, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the signal output point O23. The sixth transistor T6 can respond to a light emission control signal provided by the light emission control signal line EM and transmit a drive signal from the third node N3 to the signal output point O23. The light emitting device can be electrically connected to the signal output point O23, thereby emitting light under the drive signal.

[0098] The seventh transistor T7 can be a second reset transistor. A gate of the seventh transistor T7 is electrically connected to the second reset signal line RST2, a first electrode of the seventh transistor T7 is electrically connected to the second initial power line VINIT2, and a second electrode of the seventh transistor T7 is electrically connected to the signal output point O23. In response to a second reset signal provided by the second reset signal line RST2, the seventh transistor T7 can transmit the second initial power signal provided by the second initial power line VINIT2 to the signal output point O23, thereby resetting the potential of the signal output point O23.

[0099] The storage capacitor C1 may have two capacitor electrodes. A first capacitor electrode of the storage capacitor C1 is electrically connected to the first power line VDD, and a second capacitor electrode of the storage capacitor C1 is electrically connected to the first node N1. The storage capacitor C1 can stabilize the potential of the first node N1, thereby improving the stability of the first node N1.

[0100] Please refer to Figure 4 , Figure 4 Figure 1 is a schematic diagram of the film layer structure of a driver backplane provided in an embodiment of the present application. The driver backplane 100 may include: a substrate 01, and stacked on the substrate 01 in a direction perpendicular to and away from the substrate 01: a light shielding layer BSM, a buffer layer 03, an active layer POLY, a first gate insulating layer 04, a first gate layer GATE1, a second gate insulating layer 05, a second gate layer GATE2, an interlayer dielectric layer 06, a first conductive layer SD1, a first planarizing layer 07, a second conductive layer SD2, and a second planarizing layer 08.

[0101] The pixel driving circuit 02 may include at least a portion of the film layers of the driving backplane 100. Specifically, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the pixel driving circuit 02 may each include an active layer POLY, a first gate layer GATE1, and a first conductive layer SD1. The storage capacitor C1 in the pixel driving circuit 02 may include a first gate layer GATE1 and a second gate layer GATE2. Furthermore, the plurality of first data lines DT1 and the plurality of second data lines DT2 may be located within the second conductive layer SD2.

[0102] It should be noted that Figure 4 It is only for illustrating the stacking relationship of each film layer of the driving backplane 100, and is not used to indicate a specific cross-sectional view of the driving backplane 100 or the connection relationship of each transistor in the pixel driving circuit 02. Figures 5 to 10 , the structural layout of each film layer superimposed on each other can refer to Figures 11 to 16 .in, Figure 5 It is the structural layout of the light-shielding layer BSM; Figure 6 This is the structural layout of the active layer POLY; Figure 7 This is the structural layout of the first gate layer GATE1; Figure 8 This is the structural layout of the second gate layer GATE2; Figure 9 It is the structural layout of the first conductive layer SD1;

[0103] Figure 10 It is the structural layout of the second conductive layer SD2; Figure 11 It is a structural layout in which the light shielding layer BSM, the active layer POLY and the first gate layer GATE1 are superimposed; Figure 12 The active layer POLY, the first gate layer GATE1, the second gate layer GATE2, the first conductive layer SD1 and the second conductive layer SD2 are superimposed on each other; Figure 13 It is a structural layout in which the light shielding layer BSM, the active layer POLY, the first gate layer GATE1 and the first conductive layer SD1 are superimposed; Figure 14 It is a structural layout in which the light-shielding layer BSM and the active layer POLY are superimposed; Figure 15 It is a structural layout in which the light shielding layer BSM, the active layer POLY, the first gate layer GATE1 and the second gate layer GATE2 are superimposed; Figure 16 It is a structural layout in which a light shielding layer BSM, an active layer POLY, a first gate layer GATE1, a second gate layer GATE2 and a first conductive layer SD1 are superimposed.

[0104] The following embodiments all take the first pixel driving circuit 021 as an example to schematically illustrate the positional relationship between nodes and wirings in the first pixel driving circuit 021 .

[0105] Please refer to Figure 6 and Figure 11 At least a portion of the third node N3 in the first pixel driving circuit 021 may be located in the active layer POLY. The third node N3 may include a first body portion 10 and a second body portion 20. The first body portion 10 may extend along a first direction X, and the second body portion 20 may extend along a second direction Y. The first body portion 10 and the second body portion 20 may be electrically connected to each other. One end of the first body portion 10 may be electrically connected to the second body portion 20, and the other end of the first body portion 10 may be electrically connected to the first electrode of the third transistor T3. One end of the second body portion 20 may be electrically connected to the first electrode of the second transistor T2, and the other end of the second body portion 20 may be electrically connected to the first electrode of the sixth transistor T6.

[0106] For any first pixel driving circuit 021, if the orthographic projection of the second body portion 20 in the first pixel driving circuit 021 on the substrate 01 coincides with the orthographic projection of the second data line DT2 on the substrate 01, that is, the overlapping area of ​​the orthographic projection of the second body portion 20 on the substrate 01 and the orthographic projection of the second data line DT2 on the substrate 01 is large, the data signal loaded on the second data line DT2 will have a greater impact on the third node N3, and a larger coupling capacitance will be generated between the second body portion 20 and the second data line DT2, resulting in a larger total capacitance of the third node N3, affecting the display effect.

[0107] Therefore, in the embodiments of this application, please refer to Figure 12 For any first pixel driving circuit 021, the orthographic projection of the second body portion 20 in the first pixel driving circuit 021 on the substrate 01 is ensured not to overlap with the orthographic projection of the second data line DT2 on the substrate 01. This ensures that a certain distance exists between the second body portion 20 and the second data line DT2 in the first direction X, thereby preventing a large overlap between the orthographic projection of the second body portion 20 on the substrate 01 and the orthographic projection of the second data line DT2 on the substrate 01. This reduces the influence of the data signal loaded on the second data line DT2 on the third node N3, ensures the stability of the potential of the third node N3, and reduces the total capacitance of the third node N3, thereby improving afterimages and enhancing the display quality of the display panel.

[0108] In one possible case, for any first pixel driving circuit 021, the data signal loaded on the second data line DT2 has a greater impact on the signal output point 023 than the impact of the data signal loaded on the second data line DT2 on the second body 20. Therefore, Figure 12 As shown, in the first direction X, the minimum distance between the signal output point 023 in the first pixel driving circuit 021 and the second data line DT2 can be greater than or equal to the minimum distance between the second body portion 20 in the first pixel driving circuit 021 and the second data line DT2. In this way, the distance between the signal output point 023 in the first pixel driving circuit 021 and the second data line DT2 can be greater in the first direction X, thereby reducing the influence of the data signal loaded on the second data line DT2 on the signal output point 023 and reducing the coupling capacitance generated between the second data line DT2 and the signal output point 023. Therefore, the potential of the signal output point 023 can be made more stable, thereby improving the display effect of the display panel.

[0109] Please refer to Figure 12For any first pixel driving circuit 021, the orthographic projection of the first body portion 10 in the first pixel driving circuit 021 on the substrate 01 may have a first overlapping region S1 with the orthographic projection of the second data line DT2 on the substrate 01. This creates a coupling capacitance between the second data line DT2 and the first body portion 10, thereby affecting the total capacitance of the third node N3 and causing the potential of the third node N3 to become unstable.

[0110] Please refer to Figure 8 and Figure 12 In this embodiment of the present application, the first power line VDD may have a first shielding portion P1. The first shielding portion P1 may be located between the first body portion 10 and the second data line DT2 in a direction perpendicular to the substrate 01, and the first overlapping region S1 may be located within the orthographic projection of the first shielding portion P1 on the substrate 01. In this manner, the first shielding portion P1 can shield the coupling capacitance generated between the first body portion 10 and the second data line DT2, thereby reducing the impact of the data signal carried by the second data line DT2 on the third node N3 and ensuring the stability of the potential of the third node N3. Furthermore, the total capacitance of the third node N3 can be reduced, thereby improving afterimages and enhancing display quality.

[0111] It should be noted that, please combine Figures 8 to 10 as well as Figure 12 In the embodiment of the present application, the first power line VDD can be located within the first conductive layer SD1, the second conductive layer SD2, and the second gate layer GATE2. The multiple first power lines VDD located within the first conductive layer SD1 and the second conductive layer SD2 can extend along the second direction Y, and the orthographic projections of the multiple first power lines VDD located within the first conductive layer SD1 and the second conductive layer SD2 on the substrate 01 can overlap, thereby increasing the cross-sectional area of ​​the first power line VDD and reducing losses during first power transmission. The multiple first power lines VDD located within the second gate layer GATE2 can extend along the first direction X, and the orthographic projections of the multiple first power lines VDD located within the second gate layer GATE2 on the substrate 01 can overlap with the orthographic projections of the first power lines VDD located within the first conductive layer SD1 and the second conductive layer SD2 on the substrate 01, thereby electrically connecting the first power lines VDD located in different layers. The first shielding portion P1 can be located within the second gate layer GATE2.

[0112] The light shielding layer BSM in the driving backplane 100 can also be electrically connected to the first power line VDD. In this way, the light shielding layer BSM can also serve as the routing of the first power signal, thereby increasing the area of ​​the first power signal routing and reducing the voltage loss during the transmission process. The light shielding layer BSM can also be used to protect the channel area of ​​the transistor to prevent light from directly irradiating the channel area and affecting the normal opening and closing of the transistor. The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 in the pixel driving circuit 02 mainly control the writing of data signals, which are important for the normal operation of the pixel driving circuit 02. Therefore, Figure 11 and Figure 14 As shown, the orthographic projections of the channel regions of the four transistors on the substrate 01 can all be located within the orthographic projection of the light shielding layer BSM on the substrate 01, thereby better protecting the channel regions of the four transistors from direct exposure to light and ensuring the normal operation of the four transistors.

[0113] Please combine Figure 5 and Figure 11 The light-shielding layer BSM may include a first light-shielding trace B1 and a second light-shielding trace B2. The overall extension direction of the first light-shielding trace B1 is parallel to the first direction X, and the overall extension direction of the second light-shielding trace B2 is parallel to the second direction Y. The first light-shielding trace B1 may intersect with the second light-shielding trace B2. Since the first body portion 10 of the first pixel driving circuit 021 also extends along the first direction X, if the orthographic projection of the first light-shielding trace B1 on the substrate 01 coincides with the orthographic projection of the first body portion 10 on the substrate 01, that is, the orthographic projection of the first light-shielding trace B1 on the substrate 01 and the orthographic projection of the first body portion 10 on the substrate 01 have a large overlapping area, a large coupling capacitance will be generated between the first light-shielding trace B1 and the first body portion 10, thereby resulting in a large total capacitance of the third node N3.

[0114] Therefore, in the embodiments of this application, please refer to Figure 14 , ensuring that the orthographic projection of the first light-shielding trace B1 on the substrate 01 does not overlap with the orthographic projection of the first body portion 10 on the substrate 01. Thus, in the second direction Y, a certain distance exists between the first light-shielding trace B1 and the first body portion 10, thereby preventing a large overlap between the orthographic projection of the first light-shielding trace B1 on the substrate 01 and the orthographic projection of the first body portion 10 on the substrate 01. This reduces the coupling capacitance generated between the first light-shielding trace B1 and the first body portion 10, thereby reducing the total capacitance of the third node N3, thereby improving afterimages and enhancing the display quality of the display panel.

[0115] In one possible implementation, see Figure 9The driving backplane 100 may include a power auxiliary line SIP, and the power auxiliary line SIP may be located on the first conductive layer SD1. There may be multiple power auxiliary lines SIP, and the overall extension direction of the multiple power auxiliary lines SIP may be parallel to the second direction Y. The power auxiliary line SIP may be connected to the second power line VSS. Optionally, the second power supply may be a cathode power supply, and the power auxiliary line SIP may be a cathode power auxiliary line. Since the resistance value of the cathode layer in the display panel is relatively high, the farther away from the second power supply point, the more obvious the voltage drop is, which may easily cause uneven light emission of the display panel. Multiple power auxiliary lines SIP may be connected to the cathode layer, increasing the number and density of the second power supply points on the cathode layer, thereby reducing the voltage drop and improving the uneven light emission of the display panel.

[0116] Please refer to Figure 12 For any first pixel driver circuit 021, in the first direction X, the signal output point 023 in the first pixel driver circuit 021 is located between the corresponding first data line DT1 and the second data line DT2, and the distance between the signal output point 023 and the corresponding first data line DT1 is greater than or equal to the distance between the signal output point 023 and the corresponding second data line DT2. Therefore, in the first direction X, there is space between the signal output point 023 and the first data line DT1 for arranging other wiring. The auxiliary power line SIP can have an auxiliary line segment 001, so the auxiliary line segment 001 can be distributed between the first data line DT1 and the signal output point 023 in the first pixel driver circuit 021 in the first direction X. That is, in the first direction X, the signal output point 023 of the first pixel driver circuit 021 can be located between the auxiliary line segment 001 and the second data line DT2.

[0117] A certain distance must be maintained between the auxiliary line segment 001 and the signal output point 023 in the first pixel driver circuit 021 to prevent the second power signal carried by the auxiliary line segment 001 from lowering the potential of the signal output point 023. Because the data signal carried by the second data line DT2 is a transition signal, the second data line DT2 has a greater impact on the signal output point 023 than the auxiliary line segment 001. Therefore, in the embodiment of the present application, it is necessary to ensure that the minimum distance between the auxiliary line segment 001 and the signal output point 023 in the first pixel driver circuit 021 in the first direction X is less than or equal to the minimum distance between the second data line DT2 and the signal output point 023 in the first pixel driver circuit 021. This minimizes the impact of the second data line DT2 and the auxiliary line segment 001 on the signal output point 023, ensuring a stable potential at the signal output point 023.

[0118] Please refer to Figure 5 、 Figure 9 and Figure 13The overall extension direction of the auxiliary power supply line SIP can be parallel to the second direction Y, and the overall extension direction of the second light-shielding trace B2 of the light-shielding layer BSM can also be parallel to the second direction Y. That is, the auxiliary power supply line SIP can be generally parallel to the second light-shielding trace B2. To increase transmittance, the orthographic projection of the auxiliary power supply line SIP on the substrate 01 can be overlapped as much as possible with the orthographic projection of the second light-shielding trace B2 on the substrate 01. In this way, the area of ​​the orthographic projection of the trace on the substrate 01 can be reduced, thereby increasing the transmittance of the display panel and improving the display effect. At the same time, due to the increased light transmittance, the sensitivity of the optical fingerprint hole under the screen is also improved, thereby improving the user experience. In addition, since both the power auxiliary line SIP and the second light-shielding trace B2 can be used as power lines, and the distance between the power auxiliary line SIP and the second light-shielding trace B2 is large in the direction perpendicular to the substrate 01, the power auxiliary line SIP and the second light-shielding trace B2 are overlapped in their orthographic projections on the substrate 01, and there will not be much mutual influence between the power auxiliary line SIP and the second light-shielding trace B2.

[0119] Please combine Figure 11 and Figure 12 At least a portion of a first node N1 in the first pixel driving circuit 021 may be located in the active layer POLY and the first conductive layer SD1. The first node N1 may include a first portion L1, a second portion L2, and a third portion L3. At least portions of the first portion L1 and the second portion L2 may be located in the active layer POLY, and at least a portion of the third portion L3 may be located in the first conductive layer SD1. A first end of the first portion L1, a second end of the second portion L2, and a first end of the third portion L3 are electrically connected to each other. The second end of the first portion L1 is electrically connected to the second electrode of the first transistor T1, the second end of the second portion L2 is electrically connected to the second electrode of the second transistor T2, and the second end of the third portion L3 is electrically connected to the gate of the third transistor T3.

[0120] The orthographic projection of the first portion L1 in the first pixel driving circuit 021 on the substrate 01 may overlap with the orthographic projection of the second light-shielding trace B2 of the light-shielding layer BSM on the substrate 01. Since one capacitor electrode of the storage capacitor C1 is electrically connected to the first power line VDD, the other capacitor electrode of the storage capacitor C1 is electrically connected to the N1 node, and the second light-shielding trace B2 is electrically connected to the first power line VDD, within the overlapping region of the orthographic projection, the second light-shielding trace B2 and the first portion L1 in the first pixel driving circuit 021 may also form a storage capacitor C1, thereby increasing the capacitance value of the storage capacitor C1.

[0121] Since the orthographic projection of the power auxiliary line SIP on the substrate 01 can overlap with the orthographic projection of the second light shielding line B2 on the substrate 01, and the orthographic projection of the second light shielding line B2 on the substrate 01 can overlap with the orthographic projection of the first part L1 of the first pixel driving circuit 021 on the substrate 01. Therefore, in a possible case, please refer to Figure 12 The orthographic projection of the first part L1 in the first pixel driving circuit 021 on the substrate 01 may have a second overlapping area S2 with the orthographic projection of the power auxiliary line SIP on the substrate 01, and the second overlapping area S2 may be located in the area where the second light-shielding trace B2 overlaps with the orthographic projection of the first part L1 on the substrate 01.

[0122] However, in the second overlapping area S2, the second power signal loaded on the power auxiliary line SIP will pull down the potential of the first node N1 in the first pixel driving circuit 021. Therefore, in the embodiment of the present application, Figure 9 As shown, the first power line VDD may further include a second shielding portion P2. The second shielding portion P2 may be located within the second gate layer GATE2. The second shielding portion P2 may be located between the first portion L1 of the first pixel driving circuit 021 and the auxiliary power line SIP in a direction perpendicular to the substrate 01. The second overlapping region S2 may be located within the orthographic projection of the second shielding portion P2 on the substrate 01. In this way, the second shielding portion P2 may shield the first node N1 of the first pixel driving circuit 021 from the influence of the second power signal carried on the auxiliary power line SIP, thereby ensuring the stability of the potential of the first node N1 of the first pixel driving circuit 021.

[0123] In one of the possible scenarios described above, in a direction perpendicular to the substrate 01, the second shielding portion P2 is located between the first portion L1 in the first pixel driving circuit 021 and the auxiliary power line SIP, and the signal loaded on the second shielding portion P2 is the first power signal. In this way, the overlapping portion of the first portion L1 and the second shielding portion P2 in the first pixel driving circuit 021 can also constitute the storage capacitor C1, and the capacitance of the storage capacitor C1 is increased, thereby further ensuring the stability of the first node N1 in the first pixel driving circuit 021.

[0124] like Figure 17 As shown, the film layer structure at the second overlapping area S2 may include a substrate 01, and located on one side of the substrate 01 and stacked in a direction perpendicular to and away from the substrate 01: a second light-shielding trace B2, a buffer layer 03, a first part L1 of the first node N1 in the first pixel driving circuit 021, a first gate insulating layer 04, a second gate insulating layer 05, a second shielding portion P2, an interlayer dielectric layer 06, a power auxiliary line SIP, a first planar layer 07 and a second planar layer 08.

[0125] from Figure 17 It can be seen that in the direction perpendicular to the substrate 01, the power auxiliary line SIP overlaps with the second light-shielding wiring B2, thereby improving the transmittance of the display panel; the second shielding portion P2 is located between the first portion L1 in the first pixel driving circuit 021 and the power auxiliary line SIP, so that the second shielding portion P2 can shield the influence of the power auxiliary line SIP on the first portion L1 in the first pixel driving circuit 021; and the first portion L1 in the first pixel driving circuit 021 is located between the second light-shielding wiring B2 and the second shielding portion P2, so that the first portion L1 in the first pixel driving circuit 021 can form a storage capacitor C1 with the second light-shielding wiring B2 and the second shielding portion P2 respectively, thereby improving the capacitance value of the storage capacitor C1.

[0126] It should also be noted that, please combine Figure 5 、 Figure 7 and Figure 11 The light shielding layer BSM may further include a light shielding block B3. A first light shielding trace B1 and a second light shielding trace B2 may be connected to a light shielding block B3 at their intersection. The orthographic projection of the light shielding block B3 on the substrate 01 may overlap with the orthographic projection of the first gate layer GATE1 on the substrate 01. Since the light shielding block B3 is also electrically connected to the first power line VDD, the light shielding block B3 and the first gate layer GATE1 in the overlapping area may also form a storage capacitor C1, thereby further increasing the capacitance value of the storage capacitor C1 and better ensuring the stability of the first node N1 in the first pixel driving circuit 021.

[0127] Please combine Figure 8 and Figure 12 The orthographic projection of the auxiliary power supply line SIP on substrate 01 also includes a transition region M connected to the second overlapping region S2. This transition region M is located outside the orthographic projection of the second light-shielding trace B2 on substrate 01. Therefore, to improve transmittance, the transition region M can be overlapped with the orthographic projection of the second shielding portion P2 on substrate 01. This can reduce the area of ​​the orthographic projection of the trace on substrate 01, thereby improving the transmittance of the display panel and enhancing the display effect. At the same time, in a direction perpendicular to substrate 01, the second shielding portion P2 is located between the auxiliary power supply line SIP and substrate 01. Therefore, the second shielding portion P2 can shield the auxiliary power supply line SIP from affecting the trace located between the second shielding portion P2 and substrate 01, ensuring the normal operation of the pixel drive circuit 02.

[0128] Please refer to Figure 6 and Figure 11At least a portion of the second node N2 in the first pixel driving circuit 021 is located in the active layer POLY. The second node N2 may include a third body portion 30 and a fourth body portion 40. The third body portion 30 may extend along the first direction X, and the fourth body portion 40 may extend along the second direction Y. The third body portion 30 may be electrically connected to the fourth body portion 40. One end of the third body portion 30 may be electrically connected to the fourth body portion 40, and the other end of the third body portion 30 may be electrically connected to the second electrode of the third transistor T3. One end of the fourth body portion 40 may be electrically connected to the second electrode of the fourth transistor T4, and the other end of the fourth body portion 40 may be electrically connected to the second electrode of the fifth transistor T5.

[0129] For any first pixel driving circuit 021, if the orthographic projection of the fourth body portion 40 in the first pixel driving circuit 021 on the substrate 01 coincides with the orthographic projection of the first data line DT1 on the substrate 01, that is, the overlapping area of ​​the orthographic projection of the fourth body portion 40 in the first pixel driving circuit 021 on the substrate 01 and the orthographic projection of the first data line DT1 on the substrate 01 is large, which will cause a large coupling capacitance to be generated between the fourth body portion 40 and the first data line DT1, and the data signal loaded on the first data line DT1 will have a greater impact on the second node N2 in the first pixel driving circuit 021, affecting the display effect.

[0130] Therefore, in the embodiments of this application, please refer to Figure 12 For any first pixel driving circuit 021, it is ensured that the orthographic projection of the fourth body portion 40 in the first pixel driving circuit 021 on the substrate 01 does not overlap with the orthographic projection of the first data line DT1 on the substrate 01. In this way, it is ensured that a certain distance exists between the fourth body portion 40 in the first pixel driving circuit 021 and the first data line DT1 in the first direction X, thereby preventing a large overlap between the orthographic projection of the fourth body portion 40 on the substrate 01 and the orthographic projection of the first data line DT1 on the substrate 01. This can reduce the influence of the data signal loaded on the first data line DT1 on the second node N2 in the first pixel driving circuit 021, ensure the stability of the potential of the second node N2, and thus improve the display effect of the display panel.

[0131] like Figure 12 As shown, for any first pixel driving circuit 021, the orthographic projection of the third body portion 30 in the first pixel driving circuit 021 on the substrate 01 may have a third overlapping area S3 with the orthographic projection of the first data line DT1 on the substrate 01. Thus, a coupling capacitance is generated between the first data line DT1 and the third body portion 30 in the first pixel driving circuit 021, thereby affecting the total capacitance of the second node N2 in the first pixel driving circuit 021, causing instability in the potential of the second node N2.

[0132] In the embodiment of the present application, the first power line VDD may further include a third shielding portion P3. The third shielding portion P3 may also be located within the second gate layer GATE2 and may be electrically connected to the first shielding portion P1. The third shielding portion P3 may be located between the third body portion 30 in the first pixel driver circuit 021 and the first data line DT1 in a direction perpendicular to the substrate 01, and the third overlapping region S3 may be located within the orthographic projection of the third shielding portion P3 on the substrate 01. In this manner, the third shielding portion P3 may shield the coupling capacitance generated between the third body portion 30 in the first pixel driver circuit 021 and the first data line DT1, thereby reducing the impact of the data signal carried by the first data line DT1 on the second node N2 in the first pixel driver circuit 021, ensuring a stable potential at the second node N2, and improving the display quality of the display panel.

[0133] In one possible case, the power auxiliary line SIP and the fourth body portion 40 in the first pixel driving circuit 021 have a certain distance in the first direction X, so as to avoid a large overlapping area of ​​the positive projection of the power auxiliary line SIP and the fourth body portion 40 in the first pixel driving circuit 021 on the substrate 01, reduce the influence of the second power signal loaded on the power auxiliary line SIP on the second node N2 in the first pixel driving circuit 021, and ensure that the potential of the second node N2 is relatively stable. At the same time, there may be a fourth overlapping area S4 between the orthographic projection of the power auxiliary line SIP on the substrate 01 and the orthographic projection of the third body portion 30 in the first pixel driving circuit 021 on the substrate 01. In the direction perpendicular to the substrate 01, the third shielding portion P3 is also located between the power auxiliary line SIP and the third body portion 30 in the first pixel driving circuit 021. The fourth overlapping area S4 may be located at the orthographic projection of the third shielding portion P3 on the substrate 01. In this way, the third shielding portion P3 can shield the influence of the second power signal loaded on the power auxiliary line SIP on the second node N2 in the first pixel driving circuit 021, thereby further ensuring the stability of the potential of the second node N2.

[0134] In one possible implementation, in the second direction Y, the third shielding portion P3 can be located between the fourth transistor T4 and the fifth transistor T5. Furthermore, the orthographic projection of the third body portion 30 in the first pixel driving circuit 021 on the substrate 01 can be completely located within the orthographic projection of the third shielding portion P3 on the substrate 01, while at least a portion of the orthographic projection of the fourth body portion 40 in the first pixel driving circuit 021 on the substrate 01 can be located within the orthographic projection of the third shielding portion P3 on the substrate 01. In this manner, the third shielding portion P3 can effectively shield the third and fourth body portions 30 and 40 in the first pixel driving circuit 021 from the effects of the first data line DT1 and the auxiliary power line SIP. In other words, the third shielding portion P3 can effectively shield the second node N2 in the first pixel driving circuit 021 from the effects of the first data line DT1 and the auxiliary power line SIP, thereby ensuring a stable potential at the second node N2. Furthermore, the width of the third shielding portion P3 in the second direction Y can be prevented from being excessively large, which would otherwise hinder transmittance.

[0135] It should be noted that the driving backplane 100 can have multiple periodic partitions, and eight pixel driving circuits 02 can be distributed within one periodic partition, and the eight pixel driving circuits 02 can be arranged in two rows and four columns. Within the same periodic partition, the two pixel driving circuits 02 arranged in the second direction Y are respectively: a first pixel driving circuit 021 and a second pixel driving circuit 022; the four pixel driving circuits 02 arranged in the first direction X are respectively: two first pixel driving circuits 021 distributed continuously and two second pixel driving circuits 022 distributed continuously. In this way, the multiple pixel driving circuits 02 in the driving backplane 100 can be periodically arranged with eight pixel driving circuits 02 as one arrangement period.

[0136] For example, please refer to Figure 18 , Figure 18 The figure shows eight pixel driving circuits 02 distributed in one periodic partition. The eight pixel driving circuits 02 are: pixel driving circuit M1, pixel driving circuit M2, pixel driving circuit M3, pixel driving circuit M4, pixel driving circuit M5, pixel driving circuit M6, pixel driving circuit M7 and pixel driving circuit M8.

[0137] Here, the pixel driving circuit M1, the pixel driving circuit M2, the pixel driving circuit M3 and the pixel driving circuit M4 are arranged in sequence in a row along the first direction X, and the pixel driving circuit M5, the pixel driving circuit M6, the pixel driving circuit M7 and the pixel driving circuit M8 are arranged in sequence in a row along the first direction X; the pixel driving circuit M1 and the pixel driving circuit M5 are arranged in a column along the second direction Y, the pixel driving circuit M2 and the pixel driving circuit M6 are arranged in a column along the second direction Y, the pixel driving circuit M3 and the pixel driving circuit M7 are arranged in a column along the second direction Y, and the pixel driving circuit M4 and the pixel driving circuit M8 are arranged in a column along the second direction Y.

[0138] The pixel driving circuit M1, the pixel driving circuit M2, the pixel driving circuit M7, and the pixel driving circuit M8 may all be the first pixel driving circuit 021, and the pixel driving circuit M3, the pixel driving circuit M4, the pixel driving circuit M5, and the pixel driving circuit M6 may all be the second pixel driving circuit 022. Thus, in the second direction Y, the first pixel driving circuits 021 and the second pixel driving circuits 022 are alternately arranged, that is, in the second direction Y, any two adjacent pixel driving circuits 02 are of different types.

[0139] Since the fourth transistor T4 in each pixel driving circuit 02 needs to be connected to a data line, and the fourth transistor T4 in the first pixel driving circuit 021 needs to be connected to the first data line DT1, and the fourth transistor T4 in the second pixel driving circuit 022 needs to be connected to the second data line DT2, the two different types of pixel driving circuits 02 need to be connected to different types of data lines. In order to ensure that the loads of the first data line DT1 and the second data line DT2 are substantially the same, so that the driving effects of the two data lines on the different types of pixel driving circuits 02 are relatively consistent, it is necessary to ensure that the lengths of the two data lines are substantially the same.

[0140] For a column of pixel driving circuits 02, the positions of the two data lines corresponding to the column of pixel driving circuits 02 are distributed differently. Therefore, the positions of the signal output points 023 in the first pixel driving circuit 021 and the second pixel driving circuit 022 can be adjusted to ensure that the loads of the first data line DT1 and the second data line DT2 are the same.

[0141] Please refer to Figure 18 In the first direction X, the fourth transistor T4 in the first pixel driving circuit 021 can be located on a side of the corresponding first data line DT1 away from the signal output point 023 in the first pixel driving circuit 021, and the fourth transistor T4 in the second pixel driving circuit 022 can be located on a side of the corresponding second data line DT2 away from the signal output point 023 in the second pixel driving circuit 022.

[0142] In the first direction X, the minimum distance between the fourth transistor T4 in the first pixel driving circuit 021 and the corresponding first data line DT1 may be equal to the minimum distance between the fourth transistor T4 in the second pixel driving circuit 022 and the corresponding second data line DT2.

[0143] In this way, it can be ensured that the positions of the fourth transistor T4 in the first pixel driving circuit 021 and the fourth transistor T4 in the second pixel driving circuit 022 are distributed relatively symmetrically in the first direction X, so that the path of the first data line DT1 corresponding to the first pixel driving circuit 021 connected to the fourth transistor T4 of the first pixel driving circuit 021 is relatively consistent with the path of the second data line DT2 corresponding to the second pixel driving circuit 022 connected to the fourth transistor T4 of the second pixel driving circuit 022, thereby ensuring that the lengths of the first data line DT1 and the second data line DT2 are substantially the same and the loads are also substantially the same.

[0144] To this end, the pattern of the POLY layer in the first pixel driving circuit 021 and the pattern of the POLY layer in the second pixel driving circuit 022 can be symmetrically distributed in the first direction X, so that the fourth transistor T4 in the first pixel driving circuit 021 and the fourth transistor T4 in the second pixel driving circuit 022 are symmetrically distributed in the first direction X. In this way, the path for the first data line DT1 to access the first pixel driving circuit 021 and the path for the second data line DT2 to access the second pixel driving circuit 022 can be consistent without changing the position and length of the second data line DT2.

[0145] At the same time, the data line will overlap with some other lines, which will generate coupling capacitance, affecting the load of the data line and may also affect the capacitance of the node. Therefore, it is necessary to set a shielding part between the film layer where the data line is located and the film layer where the other lines are located to shield the coupling capacitance. In the first pixel driving circuit 021, please refer to Figure 8 The first shielding portion P1, the second shielding portion P2, and the third shielding portion P3 can all be located on the GATE2 layer. The sizes and locations of the three shielding portions vary based on various routing and node considerations. Furthermore, for a column of pixel driver circuits 02, the locations of the two data lines corresponding to that column of pixel driver circuits 02 are also different.

[0146] Therefore, in order to ensure that the loads of the first data line DT1 and the second data line DT2 are basically consistent, the shielding part in the first pixel driving circuit 021 and the shielding part in the second pixel driving circuit 022 can also be symmetrically distributed in the first direction X, that is, the part of the GATE2 layer in the first pixel driving circuit 021 and the part of the GATE2 layer in the second pixel driving circuit 022 are symmetrically distributed in the first direction X.

[0147] For example, please combine Figure 8 and Figure 18 In the pixel driving circuit M2, also known as the first pixel driving circuit 021, a portion of the first data line DT1 overlaps with the third shielding portion P3, and a portion of the second data line DT2 overlaps with both the first shielding portion P1 and the second shielding portion P2. In the pixel driving circuit M3, also known as the second pixel driving circuit 022, a portion of the second data line DT2 overlaps with the third shielding portion P3, and a portion of the first data line DT1 overlaps with both the first shielding portion P1 and the second shielding portion P2. That is, the three shielding portions in the pixel driving circuit M2 are symmetrically distributed with the three shielding portions in the pixel driving circuit M3. The first power line VDD has multiple second shielding portions P2, each corresponding to a plurality of pixel driving circuits 02. The second shielding portions P2 and the corresponding pixel driving circuits 02 can be distributed within the same sub-pixel region.

[0148] For two second shielding portions P2 arranged adjacent to each other in the second direction Y within the same periodic partition, the orthographic projection of one second shielding portion P2 on the substrate 01 overlaps with the orthographic projection of the first data line DT1 on the substrate 01, and does not coincide with the orthographic projection of the second data line DT2 on the substrate 01; the orthographic projection of the other second shielding portion P2 on the substrate 01 overlaps with the orthographic projection of the second data line DT2 on the substrate 01, and does not coincide with the orthographic projection of the first data line DT1 on the substrate 01.

[0149] For example, please refer to Figure 18 ,for Figure 18 In the periodic partition shown, the orthographic projection of the second shielding part P2 corresponding to the pixel driving circuit M1 on the substrate 01 overlaps with the orthographic projection of the second data line DT2 on the substrate 01, and does not coincide with the orthographic projection of the first data line DT1 on the substrate 01; the orthographic projection of the second shielding part P2 corresponding to the pixel driving circuit M5 on the substrate 01 overlaps with the orthographic projection of the first data line DT1 on the substrate 01, and does not coincide with the orthographic projection of the second data line DT2 on the substrate 01.

[0150] For the two second shielding portions P2 arranged adjacent to each other in the first direction X within the same periodic partition, the orthographic projection of the second shielding portion P2 corresponding to the pixel driving circuit M2 on the substrate 01 overlaps with the orthographic projection of the second data line DT2 on the substrate 01, and does not overlap with the orthographic projection of the first data line DT1 on the substrate 01. Combined with the overlapping of the second shielding portion P2 corresponding to the pixel driving circuit M1 with the first data line DT1 and the second data line DT2, it can be seen that the second shielding portion P2 corresponding to the pixel driving circuit M1 is not connected to the second shielding portion P2 corresponding to the pixel driving circuit M2.

[0151] If the second shielding portion P2 corresponding to the pixel driving circuit M1 is connected to the second shielding portion P2 corresponding to the pixel driving circuit M2, the orthographic projection of the first data line DT1 corresponding to the pixel driving circuit M2 on the substrate O1 will overlap with the second shielding portion P2, thereby increasing the overlapping area between the first data line DT1 and the second shielding portion P2, resulting in an increase in the load of the first data line DT1.

[0152] To this end, in the embodiment of the present application, it is necessary to ensure that the second shielding portion P2 corresponding to the pixel driving circuit M1 is not connected to the second shielding portion P2 corresponding to the pixel driving circuit M2. Similarly, the second shielding portion P2 corresponding to the pixel driving circuit M3 is not connected to the second shielding portion P2 corresponding to the pixel driving circuit M4, the second shielding portion P2 corresponding to the pixel driving circuit M5 is not connected to the second shielding portion P2 corresponding to the pixel driving circuit M6, the second shielding portion P2 corresponding to the pixel driving circuit M6 is not connected to the second shielding portion P2 corresponding to the pixel driving circuit M7, and the second shielding portion P2 corresponding to the pixel driving circuit M7 is not connected to the second shielding portion P2 corresponding to the pixel driving circuit M8.

[0153] It should also be noted that the second shielding portion P2 corresponding to the pixel driving circuit M2 and the second shielding portion P2 corresponding to the pixel driving circuit M3 can be connected, which will not affect the overlapping area between the data line and the second shielding portion P2, and can also reduce the load of the second shielding portion P2.

[0154] Since a portion of the POLY layer in the first pixel driving circuit 021 and a portion of the POLY layer in the second pixel driving circuit 022 are symmetrically distributed in the first direction X, a portion of the GATE2 layer in the first pixel driving circuit 021 and a portion of the GATE2 layer in the second pixel driving circuit 022 are symmetrically distributed in the first direction X, in order to ensure that the overall driving effects of the first pixel driving circuit 021 and the second pixel driving circuit 022 are relatively consistent, other wirings in the pixel driving circuit 02, such as the power auxiliary line SIP, a portion of the power auxiliary line SIP in the first pixel driving circuit 021 and a portion of the power auxiliary line SIP in the second pixel driving circuit 022 also need to be ensured to be symmetrically distributed in the first direction X.

[0155] Therefore, for the first pixel driving circuit 021 and the second pixel driving circuit 022 arranged adjacent to each other in a column of pixel driving circuits 02, the pattern in the sub-pixel area where the first pixel driving circuit 021 is located and the pattern in the sub-pixel area where the second pixel driving circuit 022 is located are basically symmetrically distributed in the first direction X.

[0156] For example, please refer to Figure 18For the pixel driving circuit M1 and the pixel driving circuit M5 that are adjacently arranged in the second direction Y, the pattern within the sub-pixel region where the pixel driving circuit M1 is located and the pattern within the sub-pixel region where the pixel driving circuit M5 is located are symmetrically distributed in the first direction X. Similarly, the pixel driving circuit M2 and the pixel driving circuit M6 are symmetrically distributed, the pixel driving circuit M3 and the pixel driving circuit M7 are symmetrically distributed, and the pixel driving circuit M4 and the pixel driving circuit M8 are symmetrically distributed.

[0157] It should also be noted that in Figure 18 In one arrangement cycle shown, in the first direction X, the patterns within the sub-pixel regions where a row of pixel driver circuits 02 are located can be symmetrically distributed about a central first power line VDD. That is, the pixel driver circuits M1 and M4 are symmetrically distributed, the pixel driver circuits M2 and M3 are symmetrically distributed, the pixel driver circuits M5 and M8 are symmetrically distributed, and the pixel driver circuits M6 and M7 are symmetrically distributed.

[0158] Therefore, the routing and node distribution of the second pixel driving circuit 022 are similar to those of the first pixel driving circuit 021 , and reference may be made to the description of the first pixel driving circuit 021 in the above embodiment, which will not be repeated here.

[0159] Please refer to Figure 19 The driving backplane 100 may include a display area 100a and a non-display area 100b distributed around the display area 100a. A plurality of pixel driving circuits 02, a plurality of first data lines DT1, and a plurality of second data lines DT2 are all located at least within the display area 100a.

[0160] The driver backplane 100 may further include: a multiplexer 110 and a plurality of bonding pads 120. Both the multiplexer 110 and the plurality of bonding pads 120 may be located within the non-display area 100b, with the multiplexer 110 being closer to the display area 100a than the plurality of bonding pads 120. One end of the multiplexer 110 may be electrically connected to a corresponding data line, and the other end may be electrically connected to a corresponding plurality of bonding pads 120. Simultaneously, the plurality of bonding pads 120 may be electrically connected to a plurality of pads of the driver chip. In this way, the driver chip may transmit data signals to the data lines via the plurality of bonding pads 120 and the multiplexer 110, thereby turning on the pixel driver circuit 02 and charging the pixel driver circuit 02.

[0161] It should be noted that the side of the multiplexer 110 facing the display area 100a may have multiple first ports 111, and the side of the multiplexer 110 facing away from the display area 100a may have multiple second ports 112, and the number of second ports 112 may be less than the number of first ports 111. The multiple first ports 111 may be electrically connected to the multiple first data lines DT1 and the multiple second data lines DT2, and the multiple second ports 112 may be electrically connected to the multiple bonding pads 120. In this way, the driver chip can provide data signals to the multiple first data lines DT1 and the multiple second data lines DT2 via the multiple bonding pads 120 and the multiplexer 110. At the same time, since the number of second ports 112 is small, the number of bonding pads 120 electrically connected to the second ports 112 is small, and thus the number of pads of the driver chip electrically connected to the bonding pads 120 is also reduced.

[0162] In summary, an embodiment of the present application provides a driving backplane, which may include a substrate, and a plurality of pixel driving circuits, a plurality of first data lines, and a plurality of second data lines located on one side of the substrate. A plurality of first pixel driving circuits in a column of pixel driving circuits may be electrically connected to a corresponding first data line, and a plurality of second pixel driving circuits in a column of pixel driving circuits may be electrically connected to a corresponding second data line. In this way, the two data lines may respectively provide data signals to different pixel driving circuits, thereby ensuring that each pixel driving circuit has sufficient charging time, thereby improving the display effect of the display panel. At the same time, the signal output points in the first pixel driving circuit and / or the second pixel driving circuit may be distributed between the corresponding first data line and the corresponding second data line in the first direction, and in the first direction, the minimum distance between the signal output point and the corresponding first data line, and the minimum distance between the signal output point and the corresponding second data line may both be greater than 0. In this way, it is possible to ensure that the distance between the first data line and the second data line is large, thereby avoiding mutual influence between the first data line and the second data line; it is also possible to ensure that there is a certain distance between the signal output point and the first data line and the second data line, thereby reducing the influence of the data signal loaded on the first data line and the second data line on the signal output point, making the potential of the signal output point more stable, and further improving the display effect.

[0163] Please refer to Figures 1 to 2 as well as Figures 20 to 21 The embodiment of the present application further provides a display panel 000 , which may include the driving backplane 100 in the above embodiment, and a plurality of light-emitting devices 200 , and the plurality of light-emitting devices 200 may be electrically connected to the driving backplane 100 .

[0164] The driving backplane 100 may include a substrate 01 , and a plurality of pixel driving circuits 02 , a plurality of first data lines DT1 , and a plurality of second data lines DT2 located on one side of the substrate 01 .

[0165] Multiple pixel driving circuits 02 can be arranged in multiple columns along a first direction X and in multiple rows along a second direction Y. The extension directions of the first data lines DT1 and the second data lines DT2 can both be parallel to the second direction Y. Multiple columns of pixel driving circuits 02 can correspond to multiple first data lines DT1 and multiple second data lines DT2. A column of pixel driving circuits 02 can include multiple first pixel driving circuits 021 and multiple second pixel driving circuits 022, and the multiple first pixel driving circuits 021 and the multiple second pixel driving circuits 022 can be arranged alternately. The multiple first pixel driving circuits 021 in a column of pixel driving circuits 02 can each be electrically connected to a corresponding first data line DT1, and the multiple second pixel driving circuits 022 in a column of pixel driving circuits 02 can each be electrically connected to a corresponding second data line DT2, and a first data line DT1 and a second data line DT2 can be located on both sides of the corresponding column of pixel driving circuits 02.

[0166] In this way, a column of pixel driving circuits 02 can correspond to a first data line DT1 and a second data line DT2, and these two data lines can respectively provide data signals to different pixel driving circuits 02, thereby ensuring that each pixel driving circuit 02 has sufficient charging time, thereby improving the display effect of the display panel 000.

[0167] Any pixel driving circuit 02 may have a signal output point 023 , and the signal output point 023 may be used to electrically connect to the light emitting device 200 .

[0168] The signal output points 023 in the first pixel driving circuit 021 and / or the second pixel driving circuit 022 can be distributed between the corresponding first data line DT1 and the corresponding second data line DT2 in the first direction X. This ensures a large distance between the first data line DT1 and the second data line DT2, preventing mutual influence between the first data line DT1 and the second data line DT2. Furthermore, in the first direction X, the minimum distance between the signal output point 023 and the corresponding first data line DT1 can be greater than zero, and the minimum distance between the signal output point 023 and the corresponding second data line DT2 can also be greater than zero. This ensures a certain distance between the signal output point 023 and both the first data line DT1 and the second data line DT2, thereby reducing the impact of the data signals loaded on the first data line DT1 and the second data line DT2 on the signal output point 023. This ensures a relatively stable potential at the signal output point 023, further improving the display effect.

[0169] The light-emitting device 200 can be located on one side of the driver backplane 100. The light-emitting device 200 can include: an anode 201, a light-emitting layer 202, and a cathode 203, which are stacked vertically and away from the driver backplane 100. There can be multiple anodes 201. When a corresponding voltage is applied to the anode 201 and the cathode 203, the light-emitting layer 202 located between the anode 201 and the cathode 203 can emit light.

[0170] Multiple light-emitting devices 200 are electrically connected to multiple pixel driving circuits 02 of the driving backplane 100 in a one-to-one correspondence. The signal output point 023 of the pixel driving circuit 02 can be electrically connected to the first electrode 201 of the light-emitting device 200, so that the pixel driving circuit 02 can load the corresponding voltage to the first electrode 201 of the corresponding light-emitting device 200 through the signal output point 023, thereby driving the corresponding light-emitting device 200 to emit light.

[0171] The multiple light-emitting devices 200 can be of different types, and different types of light-emitting devices 200 can emit light of different colors. The multiple pixel driving circuits 02 can drive multiple different types of light-emitting devices 200 to emit light. The emitted light of different colors is mixed and superimposed, so that the display panel 000 can present a corresponding display image.

[0172] Please refer to Figure 21 The display panel 000 may further include a plurality of separately arranged first electrode blocks 300 , the plurality of first electrode blocks 300 may correspond to the plurality of light-emitting devices 200 , and the anode 201 in the light-emitting device 200 may be at least part of the corresponding first electrode block 300 .

[0173] Please combine Figure 21 and Figure 22 The driving backplane 100 may include a first power line VDD, which may include: a plurality of first sub-power lines VDD1 extending along the second direction Y, and a plurality of second sub-power lines VDD2 extending along the first direction X, and the first sub-power lines VDD1 and the second sub-power lines VDD2 may be electrically connected at an intersection.

[0174] Optionally, the orthographic projection of the first electrode block 300 on the substrate 01 overlaps with the orthographic projections of the adjacent first data line DT1 and the second data line DT2 on the substrate 01, and also overlaps with the orthographic projections of two adjacent first sub-power lines VDD1 on the substrate 01.

[0175] In the first direction X, the adjacent first data line DT1 and the second data line DT2 are distributed between the two adjacent first sub-power lines VDD1. That is, the orthographic projections of the two adjacent first sub-power lines VDD1 on the substrate 01 overlap with the edge of the orthographic projection of the first electrode block 300 on the substrate 01. Furthermore, in the first direction X, the width of the first sub-power line VDD1 is greater than the width of the first data line DT1 and greater than the width of the second data line DT2. This allows the edge of the first electrode block 300 to be formed relatively smooth, improving the flatness of the first electrode block 300.

[0176] In summary, an embodiment of the present application provides a display panel, which may include a driving backplane and a plurality of light-emitting devices electrically connected to the driving backplane. A plurality of first pixel driving circuits in a column of pixel driving circuits may be electrically connected to a corresponding first data line, and a plurality of second pixel driving circuits in a column of pixel driving circuits may be electrically connected to a corresponding second data line. In this way, the two data lines may respectively provide data signals to different pixel driving circuits, thereby ensuring that each pixel driving circuit has sufficient charging time, thereby improving the display effect of the display panel. At the same time, the signal output points in the first pixel driving circuit and / or the second pixel driving circuit may be distributed between the corresponding first data line and the corresponding second data line in the first direction, and in the first direction, the minimum distance between the signal output point and the corresponding first data line, and the minimum distance between the signal output point and the corresponding second data line may both be greater than 0. In this way, it is possible to ensure that the distance between the first data line and the second data line is large, thereby avoiding mutual influence between the first data line and the second data line; it is also possible to ensure that there is a certain distance between the signal output point and the first data line and the second data line, thereby reducing the influence of the data signal loaded on the first data line and the second data line on the signal output point, making the potential of the signal output point more stable, and further improving the display effect.

[0177] The embodiment of the present application further provides a display device, which can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0178] The display device may include a driver chip and a display panel, wherein the display panel may be the display panel 000 in the above embodiment, and the driver chip may be electrically connected to the display panel 000 to drive the display panel 000 to display images.

[0179] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0180] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless expressly limited otherwise.

[0181] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A driving backplane, characterized in that: The device comprises: a substrate, and a plurality of pixel driving circuits, a plurality of first data lines and a plurality of second data lines located on one side of the substrate; The plurality of pixel driving circuits are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction; the first data lines and the second data lines extend in directions parallel to the second direction; a column of the pixel driving circuits includes a plurality of first pixel driving circuits and a plurality of second pixel driving circuits, the plurality of first pixel driving circuits are electrically connected to one first data line, the plurality of second pixel driving circuits are electrically connected to one second data line, and the first data line and the second data line are located on both sides of the column of the pixel driving circuits; The first pixel driving circuit and the second pixel driving circuit both have a signal output point, and the signal output point is used to be electrically connected to the light emitting device; The signal output points in the first pixel driving circuit and / or the second pixel driving circuit are distributed between the first data line and the second data line in the first direction, and in the first direction, the minimum distance between the signal output point and the first data line, and the minimum distance between the signal output point and the second data line are both greater than 0.

2. The driving backplane according to claim 1, characterized in that: In the first direction, a minimum distance between a signal output point in the first pixel driving circuit and the first data line is greater than or equal to a minimum distance between a signal output point in the first pixel driving circuit and the second data line; And / or, in the first direction, the minimum distance between the signal output point in the second pixel driving circuit and the second data line is greater than or equal to the minimum distance between the signal output point in the second pixel driving circuit and the first data line.

3. The driving backplane according to claim 1, characterized in that: The first pixel driving circuit and / or the second pixel driving circuit includes: a first transistor, wherein a gate of the first transistor is electrically connected to a first reset signal line, a first electrode of the first transistor is electrically connected to a first initial power line, and a second electrode of the first transistor is electrically connected to a first node; a second transistor, wherein a gate of the second transistor is electrically connected to the gate signal line, a first electrode of the second transistor is electrically connected to the third node, and a second electrode of the second transistor is electrically connected to the first node; a third transistor, wherein a gate of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the second node; a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the gate signal line, a first electrode of the fourth transistor is electrically connected to the first data line or the second data line, and a second electrode of the fourth transistor is electrically connected to the second node; a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the light emission control signal line, a first electrode of the fifth transistor is electrically connected to the first power line, and a second electrode of the fifth transistor is electrically connected to the second node; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the light emission control signal line, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the signal output point; a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the second reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial power line, and a second electrode of the seventh transistor is electrically connected to the signal output point; A storage capacitor, wherein a first capacitor electrode of the storage capacitor is connected to the first power line, and a second capacitor electrode of the storage capacitor is electrically connected to the first node.

4. The driving backplane according to claim 3, characterized in that: The third node includes a first body portion and a second body portion, the first body portion extends along the first direction, and the second body portion extends along the second direction; one end of the first body portion is electrically connected to the second body portion, the other end of the first body portion is electrically connected to the first electrode of the third transistor, one end of the second body portion is electrically connected to the first electrode of the second transistor, and the other end of the second body portion is electrically connected to the first electrode of the sixth transistor; The orthographic projection of the second body portion in the first pixel driving circuit on the substrate does not overlap with the orthographic projection of the second data line on the substrate.

5. The driving backplane according to claim 4, characterized in that: An orthographic projection of a first body portion in the first pixel driving circuit on the substrate and an orthographic projection of the second data line on the substrate have a first overlapping area; The first power line has a first shielding portion, which is located between the first body portion and the second data line in a direction perpendicular to the substrate, and the first overlapping area is located within an orthographic projection of the first shielding portion on the substrate.

6. The driving backplane according to claim 4, characterized in that: In the first direction, a minimum distance between a signal output point in the first pixel driving circuit and the second data line is greater than or equal to a minimum distance between a second body portion in the first pixel driving circuit and the second data line.

7. The driving backplane according to claim 4, characterized in that: The driving backplane further includes: a light shielding layer electrically connected to the first power line; orthographic projections of the channel regions of the first transistor, the second transistor, the third transistor, and the fourth transistor on the substrate are all located within the orthographic projection of the light shielding layer on the substrate; The light-shielding layer has a first light-shielding trace, the overall extension direction of the first light-shielding trace is parallel to the first direction, and the orthographic projection of the first light-shielding trace on the substrate does not overlap with the orthographic projection of the first strip portion on the substrate.

8. The driving backplane according to any one of claims 3 to 7, characterized in that: The driving backplane further includes: a power auxiliary line, wherein the overall extension direction of the power auxiliary line is parallel to the second direction, and the power auxiliary line has: an auxiliary line segment distributed between the first data line and the signal output point in the first pixel driving circuit in the first direction; In the first direction, the minimum distance between the signal output point of the first pixel driving circuit and the auxiliary line segment is less than or equal to the minimum distance between the signal output point of the first pixel driving circuit and the second data line.

9. The driving backplane according to claim 8, characterized in that: The driving backplane further includes: a light shielding layer, the light shielding layer being electrically connected to the first power line; The light-shielding layer has a second light-shielding trace, the overall extension direction of the second light-shielding trace is parallel to the second direction, and the orthographic projection of the second light-shielding trace on the substrate overlaps with the orthographic projection of the power auxiliary line on the substrate.

10. The driving backplane according to claim 9, characterized in that: The first node includes a first portion, a second portion, and a third portion, wherein a first end of the first portion, a first end of the second portion, and a first end of the third portion are electrically connected to each other, a second end of the first portion is electrically connected to a second electrode of the first transistor, a second end of the second portion is electrically connected to a second electrode of the second transistor, and a second end of the third portion is electrically connected to a gate of the third transistor; The orthographic projection of the second light-shielding trace on the substrate overlaps with the orthographic projection of the first portion on the substrate.

11. The driving backplane according to claim 10, characterized in that: There is a second overlapping area between the orthographic projection of the first portion on the substrate and the orthographic projection of the power auxiliary line on the substrate; The first power line further has a second shielding portion, which is located between the first portion and the auxiliary power line in a direction perpendicular to the substrate, and the second overlapping area is located within an orthographic projection of the second shielding portion on the substrate.

12. The driving backplane according to claim 11, characterized in that: The power auxiliary line also has a transition area connected to the second overlapping area in the orthographic projection of the power auxiliary line on the substrate. The transition area is located outside the orthographic projection of the second light-shielding line on the substrate and overlaps with the orthographic projection of the second shielding part on the substrate.

13. The driving backplane according to any one of claims 3-7 and 9-12, characterized in that: The second node includes a third body and a fourth body, the third body extending along the first direction, and the fourth body extending along the second direction; one end of the third body is electrically connected to the fourth body, the other end of the third body is electrically connected to the second electrode of the third transistor, one end of the fourth body is electrically connected to the second electrode of the fourth transistor, and the other end of the fourth body is electrically connected to the second electrode of the fifth transistor; The orthographic projection of the third body portion of the first pixel driving circuit on the substrate and the orthographic projection of the first data line on the substrate have a third overlapping area; The first power line further has a third shielding portion, which is located between the third body portion and the first data line in a direction perpendicular to the substrate, and the third overlapping area is located within an orthographic projection of the third shielding portion on the substrate.

14. The driving backplane according to any one of claims 3-7 and 9-12, characterized in that: In the first direction, the fourth transistor in the first pixel driving circuit is located on a side of the first data line away from a signal output point in the first pixel driving circuit, and the fourth transistor in the second pixel driving circuit is located on a side of the second data line away from a signal output point in the second pixel driving circuit; In the first direction, a minimum distance between the fourth transistor in the first pixel driving circuit and the first data line is equal to a minimum distance between the fourth transistor in the second pixel driving circuit and the second data line.

15. The driving backplane according to any one of claims 1-7, 9-12, characterized in that: The driving backplane has a plurality of periodic partitions, eight pixel driving circuits are distributed in one of the periodic partitions, and the eight pixel driving circuits are arranged in two rows and four columns; Among them, within the same periodic partition, the two pixel driving circuits arranged in the second direction are respectively: one first pixel driving circuit and one second pixel driving circuit; the four pixel driving circuits arranged in the first direction are respectively: two first pixel driving circuits distributed continuously and two second pixel driving circuits distributed continuously.

16. The driving backplane according to claim 15, characterized in that: The driving backplane further includes: a first power line; the first power line has a plurality of second shielding portions, the plurality of second shielding portions corresponding to the plurality of pixel driving circuits, and the second shielding portions and the corresponding pixel driving circuits are distributed in the same sub-pixel area; Among them, for the two second shielding parts arranged adjacent to each other in the second direction within the same periodic partition, the orthographic projection of one second shielding part on the substrate overlaps with the orthographic projection of the first data line on the substrate, and does not coincide with the orthographic projection of the second data line on the substrate; the orthographic projection of the other second shielding part on the substrate overlaps with the orthographic projection of the second data line on the substrate, and does not coincide with the orthographic projection of the first data line on the substrate.

17. The driving backplane according to any one of claims 1-7, 9-12, characterized in that: The driving backplane has a display area and a non-display area distributed around the display area; The plurality of pixel driving circuits, the plurality of first data lines and the plurality of second data lines are all at least located in the display area; The driving backplane further includes: a multiplexer and a plurality of binding pads, wherein the multiplexer and the plurality of binding pads are both located in the non-display area, and the multiplexer is closer to the display area than the plurality of binding pads; The multiplexer has a plurality of first ports on a side facing the display area, and a plurality of second ports on a side facing away from the display area; the plurality of first ports are electrically connected to the plurality of first data lines and the plurality of second data lines, and the plurality of second ports are electrically connected to the plurality of binding pads.

18. A display panel, characterized in that: include: A driving backplane according to any one of claims 1 to 17, and a plurality of light-emitting devices electrically connected to the driving backplane.

19. The display panel according to claim 18, wherein: The display panel further includes: a plurality of first electrode blocks that are separately arranged; the plurality of first electrode blocks correspond to the plurality of light-emitting devices, and the anodes of the light-emitting devices are at least part of the corresponding first electrode blocks; The driving backplane further includes: a first power line; the first power line includes: a plurality of first sub-power lines extending along the second direction, and a plurality of second sub-power lines extending along the first direction; the first sub-power lines are electrically connected to the second sub-power lines at an intersection; in the first direction, the width of the first sub-power line is greater than the width of the first data line, and greater than the width of the second data line; In which, the orthographic projection of the first electrode block on the substrate overlaps with the orthographic projections of the adjacently arranged first data line and the second data line on the substrate, and overlaps with the orthographic projections of two adjacently arranged first sub-power lines on the substrate; in the first direction, the adjacently arranged first data line and the second data line are distributed between two adjacent first sub-power lines.

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