High voltage level shift circuit and high side drive circuit

Abstract

The invention relates to the technical field of integrated chips, and discloses a high-voltage level shifting circuit and a high-side driving circuit. The high-voltage level shift circuit comprises a narrow pulse generation circuit used for converting an input low-voltage square wave signal into a low-voltage narrow pulse signal; the high-voltage level shifter is connected with the output end of the narrow pulse generating circuit and used for converting the low-voltage narrow pulse signal into a high-voltage pulse signal; the digital common-mode filter is connected with the output end of the high-voltage level shifter and is used for filtering common-mode noise in the high-voltage pulse signal; the input end of the RS trigger is connected with the output end of the digital common-mode filter, and the RS trigger is used for latching the high-voltage pulse signal after filtering the common-mode noise as a high-voltage square wave signal; the input end of the auxiliary circuit is connected with the output end of the RS trigger, the output end of the auxiliary circuit is connected with the output end of the high-voltage level shifter, and the auxiliary circuit is used for providing positive feedback for the high-voltage level shifter. When the high-voltage square wave signal is converted, common-mode noise can be avoided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, for example, to a high-voltage level shift circuit and a high-side drive circuit. Background Art

[0002] At present, the half-bridge driver chip is composed of a high-side driver circuit and a low-side driver circuit, which respectively control the opening and closing of the high-side power transistor and the low-side power transistor. The high-side driver circuit includes a high-voltage level shift circuit and a driver circuit connected to the output end of the high-voltage level shift circuit.

[0003] In the related art, usually by Figure 1 The high voltage level shift circuit shown realizes voltage conversion of a square wave signal from a low voltage domain to a high voltage domain.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] Through Figure 1 When the high-voltage level shift circuit shown converts a low-voltage square wave signal into a high-voltage square wave signal, when the voltage of the high-side floating ground VS increases, points V1 and V2 will generate negative pulses relative to the high-side floating ground VS; when the voltage of the high-side floating ground VS decreases, points V1 and V2 will generate positive pulses relative to the high-side floating ground VS. That is, when a low-voltage square wave signal is converted into a high-voltage square wave signal, common-mode noise (i.e., dv / dt noise) will appear. Common-mode noise is an erroneous logic signal. When a high-voltage square wave signal including common-mode noise is output to a high-side power transistor through a driving circuit, it may cause the high-side power transistor to turn on or off prematurely, causing the high-side power transistor to burn out. Therefore, in the process of converting a low-voltage square wave signal into a high-voltage square wave signal, how to avoid the generation of common-mode noise has become a technical problem that needs to be solved urgently.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a high-voltage level shift circuit and a high-side driving circuit, which can avoid generating common-mode noise during the process of converting a low-voltage square wave signal into a high-voltage square wave signal.

[0009] In some embodiments, a high-voltage level shifting circuit includes: a narrow pulse generating circuit, which is used to convert an input low-voltage square wave signal into a low-voltage narrow pulse signal; a high-voltage level shifter, which is connected to the output end of the narrow pulse generating circuit, and is used to convert the low-voltage narrow pulse signal into a high-voltage pulse signal; a digital common-mode filter, which is connected to the output end of the high-voltage level shifter, and is used to filter out the common-mode noise in the high-voltage pulse signal due to the rapid changes of the high-side floating power supply and the high-side floating ground; an RS trigger, whose input end is connected to the output end of the digital common-mode filter, and whose output end is used to be connected to the gate of the high-side power transistor to be driven through a driving circuit; the RS trigger is used to latch the high-voltage pulse signal after filtering out the common-mode noise as a high-voltage square wave signal; an auxiliary circuit, whose input end is connected to the output end of the RS trigger, and whose output end is connected to the output end of the high-voltage level shifter, and the auxiliary circuit is used to provide positive feedback for the high-voltage level shifter.

[0010] Optionally, the low-voltage narrow pulse signal includes a low-voltage rising edge pulse signal and a low-voltage falling edge pulse signal; the narrow pulse generating circuit includes: a first inverter, the input end of the first inverter is the input end of the narrow pulse generating circuit; a falling edge processing branch, connected to the input end of the first inverter, used to process the falling edge in the low-voltage square wave signal into a low-voltage falling edge pulse signal; a rising edge processing branch, connected to the output end of the first inverter, used to process the rising edge in the low-voltage square wave signal into a low-voltage rising edge pulse signal; wherein, the output end of the rising edge processing branch and the output end of the falling edge processing branch are used together as the output end of the narrow pulse generating circuit.

[0011] Optionally, the falling edge processing branch includes: a second inverter, a third inverter, a fourth inverter, a first capacitor and a first AND gate; the input ends of the second inverter and the fourth inverter are connected to the input end of the first inverter, and the output end of the second inverter is connected to the input end of the third inverter; the output end of the third inverter is connected to the first input end of the first AND gate; the output end of the fourth inverter is connected to the second input end of the first AND gate; one end of the first capacitor is connected to the output end of the second inverter, and the other end is grounded;

[0012] The rising edge processing branch includes: a fifth inverter, a sixth inverter, a seventh inverter, a second capacitor and a second AND gate; the input ends of the fifth inverter and the seventh inverter are connected to the output end of the first inverter, and the output end of the fifth inverter is connected to the input end of the sixth inverter; the output end of the sixth inverter is connected to the first input end of the second AND gate; the output end of the seventh inverter is connected to the second input end of the second AND gate; one end of the second capacitor is connected to the output end of the fifth inverter, and the other end is grounded.

[0013] Optionally, the high-voltage level shifter includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first resistor, and a second resistor;

[0014] The gates of the first MOS tube and the second MOS tube serve as the input end of the high-voltage level shifter, the sources of the first MOS tube and the second MOS tube are grounded, the drain of the first MOS tube is connected to the source of the third MOS tube, and the drain of the second MOS tube is connected to the source of the fourth MOS tube; the gates of the third MOS tube and the fourth MOS tube are connected to the input end of the low-voltage power supply, the drain of the third MOS tube is connected to the drain of the fifth MOS tube, and the drain of the fourth MOS tube is connected to the drain of the sixth MOS tube; the gates of the fifth MOS tube and the sixth MOS tube are connected to the high-side floating ground, the source of the fifth MOS tube is connected to the gate of the eighth MOS tube and the first end of the second resistor, the source of the sixth MOS tube is connected to the gate of the seventh MOS tube and the first end of the first resistor; the source of the seventh MOS tube is connected to the source of the eighth MOS tube, the drain of the seventh MOS tube is connected to the second end of the second resistor, and the drain of the eighth MOS tube is connected to the second end of the first resistor; wherein the gates of the seventh MOS tube and the eighth MOS tube are the output ends of the high-voltage level shifter.

[0015] Optionally, the auxiliary circuit includes:

[0016] An auxiliary pull-down circuit comprises a ninth MOS tube and a tenth MOS tube, wherein the gates of the ninth MOS tube and the tenth MOS tube are connected to the output end of the RS trigger as input ends of the auxiliary pull-down circuit, the sources of the ninth MOS tube and the tenth MOS tube are connected to the high-side floating ground, and the drains of the ninth MOS tube and the tenth MOS tube are connected to the output end of the high-voltage level shifter as output ends of the auxiliary pull-down circuit;

[0017] The auxiliary pull-up circuit comprises an eleventh MOS tube and a twelfth MOS tube, wherein the gates of the eleventh MOS tube and the twelfth MOS tube are connected to the output end of the RS trigger as the input end of the auxiliary pull-up circuit, the sources of the eleventh MOS tube and the twelfth MOS tube are connected to the high-side floating power supply, and the drains of the eleventh MOS tube and the twelfth MOS tube are connected to the output end of the high-voltage level shifter as the output end of the auxiliary pull-up circuit.

[0018] Optionally, the digital common mode filter comprises:

[0019] a first filtering branch, comprising an eighth inverter, a ninth inverter, a tenth inverter and a first OR gate; an input end of the eighth inverter is connected to a first output end of the high-voltage level shifter, an output end of the eighth inverter is connected to a first output end of the first OR gate, an input end of the ninth inverter is connected to a second output end of the high-voltage level shifter, an output end of the ninth inverter is connected to an input end of the tenth inverter, and an output end of the tenth inverter is connected to a second input end of the first OR gate;

[0020] a second filtering branch, comprising an eleventh inverter, a twelfth inverter, a thirteenth inverter and a second OR gate; an input end of the eleventh inverter is connected to a first output end of the high-voltage level shifter, an output end of the eleventh inverter is connected to an input end of the twelfth inverter, an output end of the twelfth inverter is connected to a first input end of the second OR gate, an input end of the thirteenth inverter is connected to a second output end of the high-voltage level shifter, and an output end of the thirteenth inverter is connected to a second input end of the second OR gate;

[0021] The output ends of the first OR gate and the second OR gate are used as the output ends of the digital common mode filter.

[0022] In some embodiments, a high-side driving circuit includes: a high-voltage level shifting circuit as described above; a driving circuit, wherein an input end is connected to an output end of the high-voltage level shifting circuit, and an output end is used to connect to a gate of a high-side power transistor to be driven, and the driving circuit is used to output a high-voltage square wave signal output by the high-voltage level shifting circuit to the gate of the high-side power transistor to be driven in the form of high voltage and large current.

[0023] Optionally, the high-side driving circuit further includes: an undervoltage protection circuit connected to the driving circuit, and configured to output an enable to the driving circuit to perform undervoltage protection on the high-side power transistor connected to the driving circuit.

[0024] Optionally, the undervoltage protection circuit includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a fourteenth inverter, a fifteenth inverter, a first diode, and a second diode;

[0025] The first end of the third resistor is connected to the high-side floating ground, the second end of the third resistor is connected to the drain of the thirteenth MOS tube, the drain of the thirteenth MOS tube is connected to the gate, the sources of the thirteenth MOS tube and the fourteenth MOS tube are connected to the high-side floating power supply, the drain of the fourteenth MOS tube is connected to the positive electrode of the second diode, the negative electrode of the second diode is connected to the positive electrode of the first diode and the gate of the nineteenth MOS tube, and the negative electrode of the first diode is connected to the high-side floating ground; the first end of the sixth resistor is connected to the high-side floating power supply, the second end of the sixth resistor is connected to the drain of the fifteenth MOS tube, the gate of the eighteenth MOS tube and the first end of the fifth resistor, the second end of the fifth resistor is connected to the source of the fifteenth MOS tube and the first end of the fourth resistor, and the second end of the fourth resistor is connected to the high-side floating ground; the gate of the twentieth MOS tube is connected to the gate of the thirteenth MOS tube, and the source of the twentieth MOS tube is connected to the high-side floating ground. The 20th MOS tube is connected to the power supply, the drain of the 20th MOS tube is connected to the source of the 18th MOS tube and the 19th MOS tube, the drain of the 18th MOS tube is connected to the gate and the drain of the 16th MOS tube and the gate of the 17th MOS tube, the sources of the 16th MOS tube and the 17th MOS tube are connected to the high-side floating ground, the drain of the 19th MOS tube is connected to the drain of the 17th MOS tube and the gate of the 21st MOS tube; the source of the 21st MOS tube is connected to the high-side floating ground, the drain of the 21st MOS tube is connected to the drain of the 22nd MOS tube and the input end of the 14th inverter, the gate of the 22nd MOS tube is connected to the gate of the 13th MOS tube, and the source of the 22nd MOS tube is connected to the high-side floating ground; the output end of the 14th inverter is connected to the gate of the 15th MOS tube and the input end of the 15th inverter, and the output end of the 15th inverter serves as the output end of the undervoltage protection circuit.

[0026] Optionally, the protection threshold voltage of the undervoltage protection circuit is calculated by the following expression:

[0027] V PROTECT =2V D ×R4 / (R4+R6);

[0028] The recovery threshold voltage of the undervoltage protection circuit is calculated by the following expression:

[0029] V RECOVER =2V D ×(R4+R5) / (R4+R5+R6)

[0030] Among them, V PROTECT To protect the threshold voltage, V RECOVER To restore the threshold voltage, V D is the voltage drop when the first diode and the second diode are turned on, and R4, R5 and R6 are the resistance values ​​of the fourth resistor, the fifth resistor and the sixth resistor respectively.

[0031] The high-voltage level shift circuit and high-side drive circuit provided by the embodiments of the present disclosure can achieve the following technical effects:

[0032] In the embodiment of the present disclosure, a high-voltage level shifting circuit including a narrow pulse generating circuit, a high-voltage level shifter, a digital common-mode filter, an RS trigger and an auxiliary circuit is designed. After the low-voltage square wave signal is converted into a high-voltage pulse signal through the narrow pulse generating circuit and the high-voltage level shifter in sequence, the high-voltage pulse signal will be input into the digital common-mode filter to filter out the common-mode noise. And after the filtering is completed, the high-voltage pulse signal after filtering out the common-mode noise will be latched into a high-voltage square wave signal through the RS filter, and the high-voltage pulse signal after filtering out the common-mode noise will be fed back to the output end of the high-voltage level shifter through the auxiliary circuit, providing positive feedback for the high-voltage level shifter, and suppressing the generation of common-mode noise when the high-voltage level shifter is working. Therefore, the high-voltage level shifting circuit provided in the embodiment of the present disclosure can avoid the generation of common-mode noise in the process of converting the low-voltage square wave signal into a high-voltage square wave signal.

[0033] In addition, the use of a digital common-mode filter to filter out common-mode noise has lower delay and power consumption than traditional filtering methods (e.g., RC filtering), and by providing an auxiliary circuit to provide positive feedback to the high-voltage level shifter, the level flipping of the high-voltage level shifter can be accelerated. Therefore, the high-voltage level shift circuit provided in the embodiment of the present disclosure can also reduce the power consumption during the conversion process and reduce the delay of the obtained high-voltage square wave signal during the process of converting a low-voltage square wave signal into a high-voltage square wave signal.

[0034] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0036] Figure 1 is a schematic diagram of a high voltage level shift circuit in the related art;

[0037] Figure 2 is a schematic diagram of a high-voltage level shift circuit provided by an embodiment of the present disclosure;

[0038] Figure 3 is a schematic diagram of a narrow pulse generating circuit provided by an embodiment of the present disclosure;

[0039] Figure 4 is a schematic diagram of a high-voltage level shifter provided by an embodiment of the present disclosure;

[0040] Figure 5 is a schematic diagram of another high-voltage level shift circuit provided by an embodiment of the present disclosure;

[0041] Figure 6 is a schematic diagram of a digital common mode filter provided by an embodiment of the present disclosure;

[0042] Figure 7 is a schematic diagram of a high-side drive circuit provided by an embodiment of the present disclosure;

[0043] Figure 8 is a schematic diagram of another high-side driving circuit provided by an embodiment of the present disclosure;

[0044] Fig. 9 Schematic diagram of an undervoltage protection circuit provided by an embodiment of the present disclosure.

[0045] Description of reference numerals:

[0046] 10. High voltage level shift circuit;

[0047] 100, narrow pulse generating circuit; INV1, first inverter; 110, falling edge processing branch; INV2, second inverter; INV3, third inverter; INV4, fourth inverter; C1, first capacitor; AND1, first AND gate; 120, rising edge processing branch; INV5, fifth inverter; INV6, sixth inverter; INV7, seventh inverter; C2, second capacitor; AND2, second AND gate;

[0048] 200, high-voltage level shifter; M1, first MOS tube; M2, second MOS tube; M3, third MOS tube; M4, fourth MOS tube; M5, fifth MOS tube; M6, sixth MOS tube; M7, seventh MOS tube; M8, eighth MOS tube; R1, first resistor; R2, second resistor;

[0049] 300, digital common mode filter; 310, first filter branch; INV8, eighth inverter; INV9, ninth inverter; INV10, tenth inverter; OR1, first OR gate; 320, second filter branch; INV11, eleventh inverter; INV12, twelfth inverter; INV13, thirteenth inverter; OR2, second OR gate;

[0050] 400, RS trigger;

[0051] 500, auxiliary circuit; 510, auxiliary pull-down circuit; M9, ninth MOS tube; M10, tenth MOS tube; 520, auxiliary pull-up circuit; M11, eleventh MOS tube; M12, twelfth MOS tube;

[0052] 20. high-side driving circuit; 600. driving circuit;

[0053] 700, undervoltage protection circuit; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; M13, thirteenth MOS tube; M14, fourteenth MOS tube; M15, fifteenth MOS tube; M16, sixteenth MOS tube; M17, seventeenth MOS tube; M18, eighteenth MOS tube; M19, nineteenth MOS tube; M20, twentieth MOS tube; M21, twenty-first MOS tube; M22, twenty-second MOS tube; INV14, fourteenth inverter; INV15, fifteenth inverter; D1, first diode; D2, second diode. DETAILED DESCRIPTION

[0054] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0055] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0056] Unless otherwise stated, the term "plurality" of a feature means two or more.

[0057] In the embodiment of the present disclosure, the character " / " feature indicates that the preceding and following objects are in an "or" relationship. For example, the A / B feature indicates: A or B.

[0058] The term "and / or" is a description of the association relationship between objects, and the characteristic indicates that there can be three relationships. For example, A and / or B, the characteristic indicates: A or B, or, A and B.

[0059] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0060] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0061] Combination Figure 2 As shown, the high-voltage level shift circuit 10 provided in the embodiment of the present disclosure includes: a narrow pulse generating circuit 100, a high-voltage level shifter 200, a digital common-mode filter 300, an RS trigger 400 and an auxiliary circuit 500. The narrow pulse generating circuit 100 is used to convert the input low-voltage square wave signal into a low-voltage narrow pulse signal. The high-voltage level shifter 200 is connected to the output end of the narrow pulse generating circuit 100, and is used to convert the low-voltage narrow pulse signal into a high-voltage pulse signal. The digital common-mode filter 300 is connected to the output end of the high-voltage level shifter 200, and is used to filter out the common-mode noise generated by the rapid change of the high-side floating power supply and the high-side floating ground in the high-voltage pulse signal. The input end of the RS trigger 400 is connected to the output end of the digital common-mode filter 300, and the output end of the RS trigger 400 is used to connect to the gate of the high-side power transistor to be driven through the driving circuit 600; the RS trigger 400 is used to latch the high-voltage pulse signal after filtering out the common-mode noise as a high-voltage square wave signal. The input end of the auxiliary circuit 500 is connected to the output end of the RS trigger 400 , and the output end of the auxiliary circuit 500 is connected to the output end of the high-voltage level shifter 200 . The auxiliary circuit 500 is used to provide positive feedback for the high-voltage level shifter 200 .

[0062] Specifically, by setting up the narrow pulse generating circuit 100 to convert the low-voltage square wave signal into a low-voltage narrow pulse signal, it helps to reduce energy dispersion and unnecessary interference in the subsequent signal conversion process, and provide a clear and stable signal for the subsequent high-voltage level shifter 200.

[0063] Specifically, by setting the digital common mode filter 300 to process the high voltage pulse signal output by the high voltage level shifter 200, the common mode noise generated by the rapid changes of the high side floating power supply and the high side floating ground in the high voltage pulse signal can be removed.

[0064] Specifically, by setting the RS trigger 400, the high-voltage pulse signal after filtering out the common-mode noise can be latched into a high-voltage square wave signal. In this way, the stability of the signal output by the high-voltage level shift circuit 10 to the driving circuit 600 can be ensured, and the anti-interference ability of the signal output by the high-voltage level shift circuit 10 is enhanced.

[0065] Specifically, by setting the auxiliary circuit 500 to provide positive feedback for the high-voltage level shifter 200, the generation of common-mode noise when the high-voltage level shifter 200 is working can be suppressed, the level flipping of the high-voltage level shifter 200 can be accelerated, and after the input pulse becomes a low level, the high voltage level of the high-voltage level shifter 200 can be latched.

[0066] In the embodiment of the present disclosure, a high-voltage level shifting circuit 10 is designed, which includes a narrow pulse generating circuit 100, a high-voltage level shifter 200, a digital common-mode filter 300, an RS trigger 400, and an auxiliary circuit 500. After the low-voltage square wave signal is converted into a high-voltage pulse signal by the narrow pulse generating circuit 100 and the high-voltage level shifter 200 in sequence, the high-voltage pulse signal will be input into the digital common-mode filter 300 to filter out the common-mode noise. After the filtering is completed, the high-voltage pulse signal after filtering out the common-mode noise will be latched into a high-voltage square wave signal through the RS filter, and the high-voltage pulse signal after filtering out the common-mode noise will be fed back to the output end of the high-voltage level shifter 200 through the auxiliary circuit 500, providing positive feedback for the high-voltage level shifter 200, and suppressing the generation of common-mode noise when the high-voltage level shifter 200 is working. Therefore, the high-voltage level shifting circuit 10 provided in the embodiment of the present disclosure can avoid the generation of common-mode noise in the process of converting the low-voltage square wave signal into the high-voltage square wave signal.

[0067] In addition, through Figure 1 When the high-voltage level shift circuit shown converts a low-voltage square wave signal into a high-voltage square wave signal, the MOS tube M23 or M24 needs to be in the on state for a long time, and the charging and discharging current needs to be increased or the delay of the pulse filter needs to be increased by reducing the resistance values ​​of the resistors R7 and R8. This results in a large power consumption in the process of converting the low-voltage square wave signal into a high-voltage square wave signal, and the delay of the obtained high-voltage square wave signal is high.

[0068] In the embodiment of the present disclosure, a digital common mode filter 300 is used to filter out the common mode noise, which has lower delay and power consumption than the traditional filtering method (for example, RC filtering). And by setting the auxiliary circuit 500 to provide positive feedback for the high voltage level shifter 200, the level flipping of the high voltage level shifter 200 can be accelerated. Therefore, the high voltage level shift circuit 10 provided in the embodiment of the present disclosure can also reduce the power consumption in the conversion process and reduce the delay of the obtained high voltage square wave signal in the process of converting the low voltage square wave signal into the high voltage square wave signal.

[0069] In some embodiments, the low voltage narrow pulse signal includes a low voltage rising edge pulse signal and a low voltage falling edge pulse signal. Figure 3As shown, the narrow pulse generating circuit 100 includes: a first inverter INV1, a falling edge processing branch 110 and a rising edge processing branch 120. The input end of the first inverter INV1 is the input end of the narrow pulse generating circuit 100. The falling edge processing branch 110 is connected to the input end of the first inverter INV1, and is used to process the falling edge in the low-voltage square wave signal into a low-voltage falling edge pulse signal. The rising edge processing branch 120 is connected to the output end of the first inverter INV1, and is used to process the rising edge in the low-voltage square wave signal into a low-voltage rising edge pulse signal. Among them, the output end of the rising edge processing branch 120 and the output end of the falling edge processing branch 110 are used together as the output end of the narrow pulse generating circuit 100.

[0070] Specifically, since the falling edge processing branch 110 is used to process the falling edge in the low-voltage square wave signal into a low-voltage falling edge pulse signal, and the rising edge processing branch 120 is used to process the rising edge in the low-voltage square wave signal into a low-voltage rising edge pulse signal, it is necessary to set a first inverter INV1, input the low-voltage square wave signal after the inversion processing by the first inverter INV1 into the rising edge processing branch 120, and input the low-voltage square wave signal that has not been inverted by the first inverter INV1 into the falling edge processing branch 110.

[0071] Alternatively, if Figure 3 As shown, the falling edge processing branch 110 includes: a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first capacitor C1 and a first AND gate AND1. The input ends of the second inverter INV2 and the fourth inverter INV4 are connected to the input end of the first inverter INV1, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3. The output end of the third inverter INV3 is connected to the first input end of the first AND gate AND1. The output end of the fourth inverter INV4 is connected to the second input end of the first AND gate AND1. One end of the first capacitor C1 is connected to the output end of the second inverter INV2, and the other end is grounded.

[0072] In this embodiment, the low-voltage square wave signal passes through the second inverter INV2, the first capacitor C1 and the third inverter INV3 to generate a falling edge delay signal of the low-voltage square wave signal, and the low-voltage square wave signal passes through the fourth inverter INV4 to generate a falling edge inverted signal of the low-voltage square wave signal. The falling edge delay signal and the falling edge inverted signal form a narrow pulse signal at the falling edge of the low-voltage square wave signal through the logic of the first AND gate AND1, that is, a low-voltage falling edge pulse signal.

[0073] Alternatively, if Figure 3As shown, the rising edge processing branch 120 includes: a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, a second capacitor C2 and a second AND gate AND2. The input ends of the fifth inverter INV5 and the seventh inverter INV7 are connected to the output end of the first inverter INV1, and the output end of the fifth inverter INV5 is connected to the input end of the sixth inverter INV6. The output end of the sixth inverter INV6 is connected to the first input end of the second AND gate AND2. The output end of the seventh inverter INV7 is connected to the second input end of the second AND gate AND2. One end of the second capacitor C2 is connected to the output end of the fifth inverter INV5, and the other end is grounded.

[0074] In this embodiment, the low-voltage square wave signal processed by the first inverter INV1 generates a rising edge delay signal of the low-voltage square wave signal through the fifth inverter INV5, the second capacitor C2 and the sixth inverter INV6, and the low-voltage square wave signal processed by the first inverter INV1 generates a rising edge inverted signal of the low-voltage square wave signal through the seventh inverter INV7. The rising edge delay signal and the rising edge inverted signal form a narrow pulse signal at the rising edge of the low-voltage square wave signal through the logic of the second AND gate AND2, that is, a low-voltage rising edge pulse signal.

[0075] In some embodiments, Figure 4 As shown, the high-voltage level shifter 200 includes: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a first resistor R1, and a second resistor R2. The gates of the first MOS transistor M1 and the second MOS transistor M2 serve as the input end of the high-voltage level shifter 200, the sources of the first MOS transistor M1 and the second MOS transistor M2 are grounded, the drain of the first MOS transistor M1 is connected to the source of the third MOS transistor M3, and the drain of the second MOS transistor M2 is connected to the source of the fourth MOS transistor M4. The gates of the third MOS transistor M3 and the fourth MOS transistor M4 are connected to the input end of the low-voltage power supply, the drain of the third MOS transistor M3 is connected to the drain of the fifth MOS transistor M5, and the drain of the fourth MOS transistor M4 is connected to the drain of the sixth MOS transistor M6. The gates of the fifth MOS tube M5 and the sixth MOS tube M6 are connected to the high-side floating ground, the source of the fifth MOS tube M5 is connected to the gate of the eighth MOS tube M8 and the first end of the second resistor R2, the source of the sixth MOS tube M6 is connected to the gate of the seventh MOS tube M7 and the first end of the first resistor R1. The source of the seventh MOS tube M7 is connected to the source of the eighth MOS tube M8, the drain of the seventh MOS tube M7 is connected to the second end of the second resistor R2, and the drain of the eighth MOS tube M8 is connected to the second end of the first resistor R1. The gates of the seventh MOS tube M7 and the eighth MOS tube M8 are the output ends of the high-voltage level shifter 200.

[0076] Specifically, the first MOS tube M1 and the second MOS tube M2 are low voltage NMOS transistors, the third MOS tube M3 and the fourth MOS tube M4 are high voltage NMOS transistors, the fifth MOS tube M5 and the sixth MOS tube M6 are high voltage PMOS transistors, and the seventh MOS tube M7 and the eighth MOS tube M8 are high voltage isolated well PMOS transistors.

[0077] Specifically, Figure 4 In the figure, VS represents the high-side floating ground, and VDDL represents the low-voltage power supply.

[0078] In this embodiment, the first MOS tube M1 and the second MOS tube M2 are respectively used to control the rapid opening and closing of the left and right branches of the high-voltage level shifter 200. The third MOS tube M3 and the fourth MOS tube M4 are used to isolate the low-voltage domain and the high-voltage domain. The fifth MOS tube M5 and the sixth MOS tube M6 are used to clamp the high-voltage domain. The seventh MOS tube M7, the eighth MOS tube M8, the first resistor R1 and the second resistor R2 form a positive feedback to achieve rapid level flipping, and after the input low-voltage narrow pulse signal becomes a low level, the left and right branches of the high-voltage level shifter 200 are both turned off, and the static power consumption is reduced to 0. Therefore, the following is adopted: Figure 4 The structure of the high-voltage level shifter 200 shown can reduce power consumption in the process of converting a low-voltage square wave signal into a high-voltage square wave signal.

[0079] In some embodiments, Figure 5 As shown, the auxiliary circuit 500 includes: an auxiliary pull-down circuit 510 and an auxiliary pull-up circuit 520. The auxiliary pull-down circuit 510 includes: a ninth MOS tube M9 and a tenth MOS tube M10, the gates of the ninth MOS tube M9 and the tenth MOS tube M10 are connected to the output end of the RS trigger 400 as the input end of the auxiliary pull-down circuit 510, the sources of the ninth MOS tube M9 and the tenth MOS tube M10 are connected to the high-side floating ground, and the drains of the ninth MOS tube M9 and the tenth MOS tube M10 are connected to the output end of the high-voltage level shifter 200 as the output end of the auxiliary pull-down circuit 510. The auxiliary pull-up circuit 520 includes: an eleventh MOS tube M11 and a twelfth MOS tube M12, the gates of the eleventh MOS tube M11 and the twelfth MOS tube M12 are connected to the output end of the RS trigger 400 as the input end of the auxiliary pull-up circuit 520, the sources of the eleventh MOS tube M11 and the twelfth MOS tube M12 are connected to the high-side floating power supply, and the drains of the eleventh MOS tube M11 and the twelfth MOS tube M12 are connected to the output end of the high-voltage level shifter 200 as the output end of the auxiliary pull-up circuit 520.

[0080] Specifically, Figure 5 VS in the figure represents the high-side floating ground, and VB represents the high-side floating power supply.

[0081] Specifically, the ninth MOS transistor M9 and the tenth MOS transistor M10 are high-voltage isolation well NMOS transistors.

[0082] Specifically, for the auxiliary pull-down circuit 510 , the drain of the ninth MOS transistor M9 is connected to the gate of the eighth MOS transistor M8 of the high-voltage level shifter 200 , and the drain of the tenth MOS transistor M10 is connected to the gate of the seventh MOS transistor M7 of the high-voltage level shifter 200 .

[0083] Specifically, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are high-voltage isolated well PMOS transistors.

[0084] Specifically, for the auxiliary pull-up circuit 520 , the drain of the eleventh MOS transistor M11 is connected to the gate of the eighth MOS transistor M8 of the high-voltage level shifter 200 , and the drain of the twelfth MOS transistor M12 is connected to the gate of the seventh MOS transistor M7 of the high-voltage level shifter 200 .

[0085] In this embodiment, by providing an auxiliary circuit 500 including an auxiliary pull-up circuit 520 connected to a high-side floating power supply and an auxiliary pull-down circuit 510 connected to a high-side floating ground, positive feedback can be provided for the high-voltage level shifter 200, thereby accelerating the level flipping of the high-voltage level shifter 200 and reducing the delay of the high-voltage square wave signal finally obtained.

[0086] In some embodiments, Figure 6As shown, the digital common mode filter 300 includes: a first filter branch 310 and a second filter branch 320. The first filter branch 310 includes: an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10 and a first OR gate OR1. The input end of the eighth inverter INV8 is connected to the first output end of the high voltage level shifter 200, the output end of the eighth inverter INV8 is connected to the first output end of the first OR gate OR1, the input end of the ninth inverter INV9 is connected to the second output end of the high voltage level shifter 200, the output end of the ninth inverter INV9 is connected to the input end of the tenth inverter INV10, and the output end of the tenth inverter INV10 is connected to the second input end of the first OR gate OR1. The second filter branch 320 includes: an eleventh inverter INV11, a twelfth inverter INV12, a thirteenth inverter INV13 and a second OR gate OR2. The input end of the eleventh inverter INV11 is connected to the first output end of the high-voltage level shifter 200, the output end of the eleventh inverter INV11 is connected to the input end of the twelfth inverter INV12, the output end of the twelfth inverter INV12 is connected to the first input end of the second OR gate OR2, the input end of the thirteenth inverter INV13 is connected to the second output end of the high-voltage level shifter 200, and the output end of the thirteenth inverter INV13 is connected to the second input end of the second OR gate OR2. The output ends of the first OR gate OR1 and the second OR gate OR2 are used as the output ends of the digital common mode filter 300.

[0087] In this embodiment, when a common-mode positive pulse or negative pulse appears in the high-voltage level shifter 200, the output signals of the two output terminals of the high-voltage level shifter 200 pass through the combination logic of the inverter and the OR gate in the first filter branch 310 and the second filter branch 320, and the final outputs are all output to a high level. Therefore, the common-mode noise can be filtered out by the digital common-mode filter 300. In addition, the digital common-mode filter 300 is always in a holding state for the RS trigger 400 through the above circuit structure, so it has a lower delay than the traditional filtering method.

[0088] Combination Figure 7 As shown, the high-side driving circuit 20 provided by the embodiment of the present disclosure includes: the high-voltage level shifting circuit 10 and the driving circuit 600 as described above. The input end of the driving circuit 600 is connected to the output end of the high-voltage level shifting circuit 10, and the output end of the driving circuit 600 is used to be connected to the gate of the high-side power transistor to be driven. The driving circuit 600 is used to output the high-voltage square wave signal output by the high-voltage level shifting circuit 10 to the gate of the high-side power transistor to be driven in the form of high voltage and large current.

[0089] Since the high-side driving circuit 20 provided in the embodiment of the present disclosure is provided with the high-voltage level shifting circuit 10 as described above, the same technical effect as the above embodiment is achieved. The embodiment of the present disclosure will not be described in detail here.

[0090] In some embodiments, Figure 8 As shown, the high-side driving circuit 20 further includes an undervoltage protection circuit 700. The undervoltage protection circuit 700 is connected to the driving circuit 600 and is used to output an enable to the driving circuit 600 to perform undervoltage protection on the high-side power transistor connected to the driving circuit 600.

[0091] Alternatively, if Fig. 9As shown, the undervoltage protection circuit 700 includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a twenty-second MOS tube M22, a fourteenth inverter INV14, a fifteenth inverter INV15, a first diode D1 and a second diode D2. A first end of the third resistor R3 is connected to the high-side floating ground, a second end of the third resistor R3 is connected to the drain of the thirteenth MOS tube M13, the drain of the thirteenth MOS tube M13 is connected to the gate, the sources of the thirteenth MOS tube M13 and the fourteenth MOS tube M14 are connected to the high-side floating power supply, the drain of the fourteenth MOS tube M14 is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the anode of the first diode D1 and the gate of the nineteenth MOS tube M19, and the cathode of the first diode D1 is connected to the high-side floating ground; The first end of the sixth resistor R6 is connected to the high-side floating power supply, the second end of the sixth resistor R6 is connected to the drain of the fifteenth MOS tube M15, the gate of the eighteenth MOS tube M18 and the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the source of the fifteenth MOS tube M15 and the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the high-side floating ground; the gate of the twentieth MOS tube M20 is connected to the gate of the thirteenth MOS tube M13, the source of the twentieth MOS tube M20 is connected to the high-side floating power supply, and the second The drain of the tenth MOS tube M20 is connected to the source of the eighteenth MOS tube M18 and the nineteenth MOS tube M19, the drain of the eighteenth MOS tube M18 is connected to the gate and drain of the sixteenth MOS tube M16 and the gate of the seventeenth MOS tube M17, the sources of the sixteenth MOS tube M16 and the seventeenth MOS tube M17 are connected to the high-side floating ground, the drain of the nineteenth MOS tube M19 is connected to the drain of the seventeenth MOS tube M17 and the gate of the twenty-first MOS tube M21; the source of the twenty-first MOS tube M21 is connected to the high-side floating ground. The drain of the twenty-first MOS tube M21 is connected to the drain of the twenty-second MOS tube M22 and the input end of the fourteenth inverter INV14, the gate of the twenty-second MOS tube M22 is connected to the gate of the thirteenth MOS tube M13, and the source of the twenty-second MOS tube M22 is connected to the high-side floating ground; the output end of the fourteenth inverter INV14 is connected to the gate of the fifteenth MOS tube M15 and the input end of the fifteenth inverter INV15, and the output end of the fifteenth inverter INV15 serves as the output end of the undervoltage protection circuit 700.

[0092] Specifically, Fig. 9 VS in the figure represents the high-side floating ground, and VB represents the high-side floating power supply.

[0093] Specifically, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, the twentieth MOS transistor M20 and the twenty-second MOS transistor M22 are high-voltage isolated well PMOS transistors. The fifteenth MOS transistor M15, the sixteenth MOS transistor M16, the seventeenth MOS transistor M17 and the twenty-first MOS transistor M21 are high-voltage isolated well NMOS transistors.

[0094] Specifically, the first diode D1 and the second diode D2 are used in series to form a voltage reference source. When the first diode D1 and the second diode D2 are turned on, a relatively constant voltage drop will be exhibited, and this voltage drop is the reference voltage.

[0095] Specifically, the third resistor R3 , the fourth resistor R4 , the fifth resistor R5 and the sixth resistor R6 together form a voltage divider network for sampling the floating voltage difference between the high-side floating power supply and the high-side floating ground.

[0096] Specifically, some MOS transistors (such as the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, and the twentieth MOS transistor M20), the fourteenth inverter INV14, and the fifteenth inverter INV15 in the undervoltage protection circuit 700 together constitute a comparator for comparing the floating voltage difference with the reference voltage. If the floating voltage difference is less than the reference voltage, the comparator will output an enable signal, indicating that the power supply voltage is lower than the preset threshold, thereby triggering the undervoltage protection mechanism.

[0097] Specifically, some MOS transistors in the undervoltage protection circuit 700 (such as the sixteenth MOS transistor M16, the seventeenth MOS transistor M17 and the twenty-first MOS transistor M21) constitute an analog switch, through which a protection mechanism based on hysteresis voltage can prevent the undervoltage protection circuit 700 from frequently switching near the protection threshold.

[0098] Specifically, the hysteresis voltage is a voltage value between the protection threshold voltage and the recovery threshold voltage of the undervoltage protection circuit 700 .

[0099] Optionally, the protection threshold voltage of the undervoltage protection circuit is calculated by the following expression:

[0100] V PROTECT =2V D ×R4 / (R4+R6);

[0101] The recovery threshold voltage of the undervoltage protection circuit is calculated by the following expression:

[0102] V RECOVER =2V D×(R4+R5) / (R4+R5+R6)

[0103] Among them, V PROTECT To protect the threshold voltage, V RECOVER To restore the threshold voltage, V D is the voltage drop when the first diode and the second diode are turned on, and R4, R5 and R6 are the resistance values ​​of the fourth resistor, the fifth resistor and the sixth resistor respectively.

[0104] In this embodiment, by providing an undervoltage protection circuit 700 capable of outputting an enable signal to the driving circuit 600, the floating voltage difference (the voltage difference between the high-side floating power supply and the high-side floating ground) can be compared with the reference voltage to determine whether to send an enable signal to the driving circuit 600. In this way, when the power supply voltage of the high-side floating power supply is low, the driving circuit 600 will not output a driving voltage to the high-side power transistor to be driven, thereby achieving undervoltage protection for the high-side power transistor.

[0105] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

Claims

1. A high voltage level shift circuit, characterized in that: include: A narrow pulse generating circuit is used to convert an input low-voltage square wave signal into a low-voltage narrow pulse signal; A high-voltage level shifter is connected to the output end of the narrow pulse generating circuit and is used to convert the low-voltage narrow pulse signal into a high-voltage pulse signal; A digital common mode filter is connected to the output end of the high voltage level shifter and is used to filter out common mode noise generated by rapid changes of a high side floating power supply and a high side floating ground in a high voltage pulse signal; An RS trigger, an input end of which is connected to an output end of the digital common mode filter, and an output end of which is used to be connected to a gate of a high-side power transistor to be driven through a driving circuit; The RS trigger is used to latch the high-voltage pulse signal after filtering out the common-mode noise into a high-voltage square wave signal; The auxiliary circuit has an input end connected to the output end of the RS trigger, and an output end connected to the output end of the high-voltage level shifter. The auxiliary circuit is used to provide positive feedback for the high-voltage level shifter.

2. The high voltage level shift circuit according to claim 1, characterized in that: The low-voltage narrow pulse signal includes a low-voltage rising edge pulse signal and a low-voltage falling edge pulse signal; The narrow pulse generating circuit includes: A first inverter, wherein an input end of the first inverter is an input end of a narrow pulse generating circuit; A falling edge processing branch, connected to the input end of the first inverter, for processing the falling edge in the low-voltage square wave signal into a low-voltage falling edge pulse signal; A rising edge processing branch, connected to the output end of the first inverter, for processing the rising edge in the low-voltage square wave signal into a low-voltage rising edge pulse signal; The output end of the rising edge processing branch and the output end of the falling edge processing branch are used together as the output end of the narrow pulse generating circuit.

3. The high voltage level shift circuit according to claim 2, characterized in that: The falling edge processing branch includes: a second inverter, a third inverter, a fourth inverter, a first capacitor and a first AND gate; the input ends of the second inverter and the fourth inverter are connected to the input end of the first inverter, and the output end of the second inverter is connected to the input end of the third inverter; the output end of the third inverter is connected to the first input end of the first AND gate; the output end of the fourth inverter is connected to the second input end of the first AND gate; one end of the first capacitor is connected to the output end of the second inverter, and the other end is grounded; The rising edge processing branch includes: a fifth inverter, a sixth inverter, a seventh inverter, a second capacitor and a second AND gate; the input ends of the fifth inverter and the seventh inverter are connected to the output end of the first inverter, and the output end of the fifth inverter is connected to the input end of the sixth inverter; the output end of the sixth inverter is connected to the first input end of the second AND gate; the output end of the seventh inverter is connected to the second input end of the second AND gate; one end of the second capacitor is connected to the output end of the fifth inverter, and the other end is grounded.

4. The high voltage level shift circuit according to any one of claims 1 to 3, characterized in that: A high-voltage level shifter, comprising: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a first resistor and a second resistor; The gates of the first MOS tube and the second MOS tube serve as input terminals of the high-voltage level shifter, the sources of the first MOS tube and the second MOS tube are grounded, the drain of the first MOS tube is connected to the source of the third MOS tube, and the drain of the second MOS tube is connected to the source of the fourth MOS tube; The gates of the third MOS tube and the fourth MOS tube are connected to the input end of the low voltage power supply, the drain of the third MOS tube is connected to the drain of the fifth MOS tube, and the drain of the fourth MOS tube is connected to the drain of the sixth MOS tube; The gates of the fifth MOS tube and the sixth MOS tube are connected to the high-side floating ground, the source of the fifth MOS tube is connected to the gate of the eighth MOS tube and the first end of the second resistor, and the source of the sixth MOS tube is connected to the gate of the seventh MOS tube and the first end of the first resistor; The source of the seventh MOS tube is connected to the source of the eighth MOS tube, the drain of the seventh MOS tube is connected to the second end of the second resistor, and the drain of the eighth MOS tube is connected to the second end of the first resistor; The gates of the seventh MOS tube and the eighth MOS tube are output ends of the high-voltage level shifter.

5. The high voltage level shift circuit according to any one of claims 1 to 3, characterized in that: Auxiliary circuits include: An auxiliary pull-down circuit comprises a ninth MOS tube and a tenth MOS tube, wherein the gates of the ninth MOS tube and the tenth MOS tube are connected to the output end of the RS trigger as input ends of the auxiliary pull-down circuit, the sources of the ninth MOS tube and the tenth MOS tube are connected to the high-side floating ground, and the drains of the ninth MOS tube and the tenth MOS tube are connected to the output end of the high-voltage level shifter as output ends of the auxiliary pull-down circuit; The auxiliary pull-up circuit comprises an eleventh MOS tube and a twelfth MOS tube, wherein the gates of the eleventh MOS tube and the twelfth MOS tube are connected to the output end of the RS trigger as the input end of the auxiliary pull-up circuit, the sources of the eleventh MOS tube and the twelfth MOS tube are connected to the high-side floating power supply, and the drains of the eleventh MOS tube and the twelfth MOS tube are connected to the output end of the high-voltage level shifter as the output end of the auxiliary pull-up circuit.

6. The high voltage level shift circuit according to any one of claims 1 to 3, characterized in that: Digital common mode filters include: a first filtering branch, comprising an eighth inverter, a ninth inverter, a tenth inverter and a first OR gate; an input end of the eighth inverter is connected to a first output end of the high-voltage level shifter, an output end of the eighth inverter is connected to a first output end of the first OR gate, an input end of the ninth inverter is connected to a second output end of the high-voltage level shifter, an output end of the ninth inverter is connected to an input end of the tenth inverter, and an output end of the tenth inverter is connected to a second input end of the first OR gate; a second filtering branch, comprising an eleventh inverter, a twelfth inverter, a thirteenth inverter and a second OR gate; an input end of the eleventh inverter is connected to a first output end of the high-voltage level shifter, an output end of the eleventh inverter is connected to an input end of the twelfth inverter, an output end of the twelfth inverter is connected to a first input end of the second OR gate, an input end of the thirteenth inverter is connected to a second output end of the high-voltage level shifter, and an output end of the thirteenth inverter is connected to a second input end of the second OR gate; The output ends of the first OR gate and the second OR gate are used as the output ends of the digital common mode filter.

7. A high-side drive circuit, characterized in that: include: The high voltage level shift circuit as claimed in any one of claims 1 to 6; The driving circuit has an input end connected to the output end of the high-voltage level shift circuit, and an output end used to be connected to the gate of the high-side power transistor to be driven. The driving circuit is used to output the high-voltage square wave signal output by the high-voltage level shift circuit to the gate of the high-side power transistor to be driven in the form of high voltage and large current.

8. The high-side driving circuit according to claim 7, characterized in that: The high-side driver circuit also includes: The undervoltage protection circuit is connected to the driving circuit and is used to output an enable to the driving circuit to perform undervoltage protection on the high-side power transistor connected to the driving circuit.

9. The high-side driving circuit according to claim 8, characterized in that: The undervoltage protection circuit includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a fourteenth inverter, a fifteenth inverter, a first diode, and a second diode: The first end of the third resistor is connected to the high-side floating ground, the second end of the third resistor is connected to the drain of the thirteenth MOS tube, the drain of the thirteenth MOS tube is connected to the gate, the sources of the thirteenth MOS tube and the fourteenth MOS tube are connected to the high-side floating power supply, the drain of the fourteenth MOS tube is connected to the positive electrode of the second diode, the negative electrode of the second diode is connected to the positive electrode of the first diode and the gate of the nineteenth MOS tube, and the negative electrode of the first diode is connected to the high-side floating ground; the first end of the sixth resistor is connected to the high-side floating power supply, the second end of the sixth resistor is connected to the drain of the fifteenth MOS tube, the gate of the eighteenth MOS tube and the first end of the fifth resistor, the second end of the fifth resistor is connected to the source of the fifteenth MOS tube and the first end of the fourth resistor, and the second end of the fourth resistor is connected to the high-side floating ground; the gate of the twentieth MOS tube is connected to the gate of the thirteenth MOS tube, and the source of the twentieth MOS tube is connected to the high-side floating ground. The 20th MOS tube is connected to the power supply, the drain of the 20th MOS tube is connected to the source of the 18th MOS tube and the 19th MOS tube, the drain of the 18th MOS tube is connected to the gate and the drain of the 16th MOS tube and the gate of the 17th MOS tube, the sources of the 16th MOS tube and the 17th MOS tube are connected to the high-side floating ground, the drain of the 19th MOS tube is connected to the drain of the 17th MOS tube and the gate of the 21st MOS tube; the source of the 21st MOS tube is connected to the high-side floating ground, the drain of the 21st MOS tube is connected to the drain of the 22nd MOS tube and the input end of the 14th inverter, the gate of the 22nd MOS tube is connected to the gate of the 13th MOS tube, and the source of the 22nd MOS tube is connected to the high-side floating ground; the output end of the 14th inverter is connected to the gate of the 15th MOS tube and the input end of the 15th inverter, and the output end of the 15th inverter serves as the output end of the undervoltage protection circuit.

10. The high-side driving circuit according to claim 9, characterized in that: The protection threshold voltage of the undervoltage protection circuit is calculated by the following expression: V PROTECT =2V D ×R4 / (R4+R6); The recovery threshold voltage of the undervoltage protection circuit is calculated by the following expression: V RECOVER =2V D ×(R4+R5) / (R4+R5+R6) Among them, V PROTECT To protect the threshold voltage, V RECOVER To restore the threshold voltage, V D is the voltage drop when the first diode and the second diode are turned on, and R4, R5 and R6 are the resistance values ​​of the fourth resistor, the fifth resistor and the sixth resistor respectively.

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