Semiconductor device

Abstract

A semiconductor device includes a bit line, a channel, a first capping pattern, a gate insulating pattern, a gate electrode, and a capacitor. The bit lines are on the substrate, and each of the bit lines extends in a first direction. The bit lines are spaced apart from each other in the second direction. The channels are spaced apart from each other in the first direction. A first capping pattern is on sidewalls of each of the channels. The gate insulating pattern is on a sidewall of the first capping pattern. The gate electrode is on a sidewall of the gate insulating pattern. The capacitors are electrically connected to respective ones of the channels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0124616 filed in the Korean Intellectual Property Office on September 19, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to semiconductor devices. More particularly, example embodiments of the present disclosure relate to memory devices including vertical channels. Background Art

[0004] In order to improve the integration of semiconductor devices, memory devices including vertical channel transistors have been developed. The vertical channel transistors include a channel including an oxide semiconductor material, and when the semiconductor device is manufactured, the channel may be damaged. Summary of the invention

[0005] Example embodiments provide a semiconductor device having improved electrical characteristics.

[0006] According to example embodiments, a semiconductor device is provided. The semiconductor device may include a bit line, a channel, a first capping pattern, a gate insulating pattern, a gate electrode, and a capacitor. The bit line may be located on a substrate, and each of the bit lines may extend in a first direction substantially parallel to an upper surface of the substrate. The bit lines may be spaced apart from each other in a second direction, the second direction being substantially parallel to an upper surface of the substrate and intersecting the first direction. A channel is located on each of the bit lines, and the channels may be spaced apart from each other. The first capping pattern may be located on a sidewall of each of the channels. The gate insulating pattern may be located on a sidewall of the first capping pattern. The gate electrode may be located on a sidewall of the gate insulating pattern. The capacitor may be electrically connected to a corresponding channel in the channel.

[0007] According to example embodiments, a semiconductor device is provided. The semiconductor device may include a bit line, a channel, a gate insulation pattern, a gate electrode, a capacitor, a molding, and a first capping pattern. The bit line may be located on a substrate, and each of the bit lines may extend in a first direction substantially parallel to an upper surface of the substrate. The bit lines may be spaced apart from each other in a second direction, the second direction being substantially parallel to an upper surface of the substrate and intersecting the first direction. The channels on each of the bit lines may be spaced apart from each other in the first direction. The gate insulation pattern may be located on a first sidewall of each of the channels. The gate electrode may be located on a sidewall of the gate insulation pattern. The capacitor may be electrically connected to a corresponding channel in the channel. The molding may be located between the channels in the channel, and the molding may contact a corresponding second sidewall of a corresponding channel in the channel. The first capping pattern may contact a sidewall of each of the moldings, and a sidewall of each of the channels may contact a corresponding molding in the moldings.

[0008] According to example embodiments, a semiconductor device is provided. The semiconductor device may include a bit line, a bit line shield, a channel, a first capping pattern, a gate insulating pattern, a gate electrode, a capacitor, a molding, a second insulating pattern, and a second capping pattern. The bit line may be located on a substrate, and each of the bit lines may extend in a first direction substantially parallel to an upper surface of the substrate. The bit lines may be spaced apart from each other in a second direction, the second direction being substantially parallel to an upper surface of the substrate and intersecting the first direction. The bit line shield may be located between the bit lines, and each of the bit line shields may extend in the first direction. The channels on each of the bit lines may be spaced apart from each other. The first capping pattern may be located on a first sidewall of each of the channels. The gate insulating pattern may be located on a sidewall of the first capping pattern. The gate electrode may be located on a sidewall of the gate insulating pattern. The capacitor may be electrically connected to a corresponding channel in the channel. The molding may be located between the channels in the channel on each of the bit lines, and each of the moldings may contact a second sidewall of a corresponding channel in the channel. The second insulating pattern may be located on each of the bit line shields, and each of the second insulating patterns may be located between adjacent moldings in the moldings. The second capping pattern may be located on a sidewall of each of the moldings, and a sidewall of each of the channels contacts an adjacent molding in the moldings.

[0009] In a semiconductor device according to example embodiments, a first capping layer and a molding layer may be sequentially formed on a channel layer, an anisotropic etching process may be performed to divide the channel layer into a plurality of channels, a second capping layer may be formed on the channel, an insulating interlayer may be formed on the second capping layer, and an isotropic etching process may be performed to transform the insulating interlayer into an insulating interlayer pattern. Thus, during the formation of the channel and subsequent processes, the channel may be protected by the first capping layer and the second capping layer, so that the semiconductor device including the channel may have enhanced electrical characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 4 are a perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a semiconductor device according to example embodiments.

[0011] Figures 5 to 68 are a perspective view, a plan view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0012] Figures 69 to 72 are a perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a semiconductor device according to example embodiments.

[0013] Figure 73 to Figure 76 are a perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0014] Figures 77 to 80 are a perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a semiconductor device according to example embodiments.

[0015] Figures 81 to 88 are a perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0016] Figures 89 to 92 are a perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a semiconductor device according to example embodiments.

[0017] Fig.93 is a perspective view illustrating a semiconductor device according to example embodiments.

[0018] Figures 94 to 98 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0019] Fig.99 and Fig.100 are a perspective view and a vertical cross-sectional view illustrating a semiconductor device according to example embodiments.

[0020] Fig.101 and Fig.102are a perspective view and a vertical cross-sectional view illustrating a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0021] The above and other aspects and features of the semiconductor device and the method for manufacturing the semiconductor device according to the example embodiment will become easily understood from the detailed description below with reference to the accompanying drawings. It will be understood that although the terms "first", "second" and / or "third" etc. can be used in this article to describe various materials, layers, regions, pads, electrodes, patterns, structures and / or processes, these various materials, layers, regions, pads, electrodes, patterns, structures and / or processes should not be limited by these terms. These terms are only used to distinguish a material, layer, region, pad, electrode, pattern, structure or process from another material, layer, region, pad, electrode, pattern, structure or process. Therefore, "first", "second" and / or "third" etc. can be selectively or interchangeably used for each material, layer, region, electrode, pad, pattern, structure or process.

[0022] Hereinafter, two directions that may intersect each other among horizontal directions substantially parallel to the upper surface of the substrate may be referred to as a first direction D1 and a second direction D2, respectively, and a direction substantially perpendicular to the upper surface of the substrate may be referred to as a third direction D3. In example embodiments, the first direction D1 and the second direction D2 may be substantially perpendicular to each other. Each of the first to third directions D1, D2, and D3 may include not only the directions shown in the drawings, but also the directions opposite to the directions shown.

[0023] Figures 1 to 4 1 is a perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view showing a semiconductor device according to an example embodiment. Figure 1 It is a stereogram. Figure 2 is a horizontal cross-section diagram, Figure 3 Including along Figure 2 A cross-sectional view taken along lines AA' and BB', and Figure 4 Including along Figure 2 Cross-sectional view taken along lines CC' and EE'. Figure 2 yes Figure 3 and Figure 4 Horizontal cross-section at a height H.

[0024] Reference Figures 1 to 4 The semiconductor device may include a second gate electrode 475 , a second gate insulating pattern 455 , a channel 385 , first capping patterns 395 , second capping patterns 435 and fourth capping patterns 510 , a landing pad 535 , and a capacitor 570 on a substrate 100 .

[0025] The semiconductor device may also include an isolation layer 110, a first gate structure 160, a gate spacer 170, a first contact plug 190, a second contact plug 195 and a third contact plug 240, a first wiring 210, a second wiring 250, a third wiring 300 and a fourth wiring 340, a first insulating pattern 230, a second insulating layer 260, a third insulating pattern 280, a fifth insulating pattern 325, a sixth insulating pattern 330, a seventh insulating pattern 350 and an eighth insulating pattern 360, a first molding 370, a first insulating interlayer 120, a second insulating interlayer 180, a third insulating interlayer 200, a fourth insulating interlayer 220 and a fifth insulating interlayer 270, a sixth insulating interlayer pattern 445, a seventh insulating interlayer pattern 505 and an eighth insulating interlayer pattern 540, an etching stop pattern 495, and a first supporting layer 550 and a second supporting layer 560.

[0026] The substrate 100 may include silicon, germanium, silicon germanium, or a III-V compound semiconductor such as GaP, GaAs, GaSb, etc. In example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0027] The isolation layer 110 may be disposed on the substrate 100, and the active region 105 may be defined by the isolation layer 110. The isolation layer 110 may include an oxide, for example, silicon oxide.

[0028] The first gate structure 160 may be disposed on the substrate 100 and may include a first gate insulating pattern 130, a first gate electrode 140, and a gate mask 150 sequentially stacked in the third direction D3, and a gate spacer 170 may be disposed on a sidewall of the first gate structure 160. A plurality of first gate structures 160 may be spaced apart from each other in each of the first direction D1 and the second direction D2. Each of the first gate structures 160 together with the source / drain region at the upper portion of the active region 105 may form a transistor. In example embodiments, the transistor may be part of a sense amplifier (S / A).

[0029] The first gate insulating pattern 130 may include an oxide such as silicon oxide, the first gate electrode 140 may include a conductive material (e.g., metal, metal nitride, metal silicide, doped polysilicon, etc.), and each of the gate mask 150 and the gate spacer 170 may include an insulating nitride such as silicon nitride.

[0030] The first insulating interlayer 120 can be set on the active area 105 and the isolation layer 110, and can cover the sidewalls of the gate spacer 170 on the sidewalls of the first gate structure 160, overlap with the sidewalls of the gate spacer 170 on the sidewalls of the first gate structure 160, or be located on the sidewalls of the gate spacer 170 on the sidewalls of the first gate structure 160.

[0031] The second insulating interlayer 180 can be set on the first insulating interlayer 120, the first gate structure 160 and the gate spacer 170, the first contact plug 190 can extend through the first insulating interlayer 120 and the second insulating interlayer 180 to contact the upper surface of the active area 105 (for example, the source / drain region), and the second contact plug 195 can extend through the second insulating interlayer 180 and the gate mask 150 to contact the upper surface of the first gate electrode 140.

[0032] The third insulating interlayer 200 may be disposed on the second insulating interlayer 180 and the first and second contact plugs 190 and 195, and the first wiring 210 may extend through the third insulating interlayer 200. In example embodiments, the first wiring 210 may extend in the first direction D1, and a plurality of first wirings 210 may be spaced apart from each other in the second direction D2. Each of the first wirings 210 may contact an upper surface of a corresponding one of the first and second contact plugs 190 and 195.

[0033] The fourth insulating interlayer 220 may be disposed on the third insulating interlayer 200 and the first wiring 210, and the first insulating pattern 230 and the second wiring 250 may be sequentially stacked on the fourth insulating interlayer 220. In example embodiments, each of the first insulating pattern 230 and the second wiring 250 may extend in the second direction D2. A plurality of first insulating patterns 230 may be spaced apart from each other in the first direction D1, and a plurality of second wirings 250 may be spaced apart from each other in the first direction D1.

[0034] The third contact plug 240 may extend through the first insulation pattern 230 and the fourth insulation interlayer 220 , and may contact an upper surface of a corresponding one of the first wirings 210 and a lower surface of a corresponding one of the second wirings 250 .

[0035] The second insulating layer 260 can be set on the fourth insulating interlayer 220, and can cover the side walls and upper surface of the second wiring 250 and the side walls of the first insulating pattern 230, overlap with the side walls and upper surface of the second wiring 250 and the side walls of the first insulating pattern 230, or be located on the side walls and upper surface of the second wiring 250 and the side walls of the first insulating pattern 230.

[0036] The fifth insulating interlayer 270 may be disposed on the second insulating layer 260 , and may fill a space between the second wirings 250 adjacent in the first direction D1 among the second wirings 250 .

[0037] The third insulating pattern 280 and the third wiring 300 may be sequentially stacked on the fifth insulating interlayer 270. In example embodiments, each of the third insulating pattern 280 and the third wiring 300 may extend in the first direction D1. A plurality of third insulating patterns 280 may be spaced apart from each other in the second direction D2, and a plurality of third wirings 300 may be spaced apart from each other in the second direction D2. In example embodiments, each of the third wirings 300 may serve as a bit line of a semiconductor device.

[0038] The fourth contact plug 290 may extend through the third insulation pattern 280 , the fifth insulation interlayer 270 , and the second insulation layer 260 , and may contact a lower surface of a corresponding one of the third wirings 300 and an upper surface of a corresponding one of the second wirings 250 .

[0039] The fifth insulating pattern 325 may extend in the first direction D1 between the third wirings 300 adjacent in the second direction D2 and between the third insulating patterns 280 adjacent in the second direction D2 among the third wirings 300, and may contact the sidewalls of the third wirings 300 and the third insulating patterns 280. In example embodiments, the fifth insulating pattern 325 may extend through an upper portion of the fifth insulating interlayer 270, and thus, a lower surface of the fifth insulating pattern 325 may be lower than a lower surface of the third insulating pattern 280. In example embodiments, a cross-sectional view of the fifth insulating pattern 325 in the second direction D2 may have a cup shape, or a U shape, having a lower surface and sidewalls.

[0040] The sixth insulation pattern 330 may be disposed on the fifth insulation pattern 325, and the sidewall and the lower surface of the sixth insulation pattern 330 may be covered by the fifth insulation pattern 325, overlap with the fifth insulation pattern 325, or be located on the fifth insulation pattern 325. A cross-sectional view of the sixth insulation pattern 330 in the second direction D2 may have a cup shape having a lower surface and sidewalls, or a U shape.

[0041] The fourth wiring 340 may be disposed on the sixth insulation pattern 330, and the sidewall and the lower surface of the fourth wiring 340 may be covered by the sixth insulation pattern 330 or overlapped with the sixth insulation pattern 330. The seventh insulation pattern 350 may be disposed on the fourth wiring 340, and the sidewall of the seventh insulation pattern 350 may be covered by the sixth insulation pattern 330 or overlapped with the sixth insulation pattern 330. In example embodiments, each of the fourth wiring 340 and the seventh insulation pattern 350 may extend in the first direction D1. A plurality of fourth wirings 340 may be spaced apart from each other in the second direction D2, and a plurality of seventh insulation patterns 350 may be spaced apart from each other in the second direction D2.

[0042] In example embodiments, the fourth wiring 340 may be disposed between the third wirings 300 serving as bit lines, and may serve as a bit line shield.

[0043] The eighth insulation pattern 360 and the first molding 370 may be sequentially stacked on the third wiring 300, the fifth insulation pattern 325, and the sixth insulation pattern 330. A plurality of eighth insulation patterns 360 may be spaced apart from each other in each of the first direction D1 and the second direction D2, and a plurality of first moldings 370 may be spaced apart from each other in each of the first direction D1 and the second direction D2.

[0044] The sixth insulating interlayer pattern 445 may be disposed on the seventh insulating pattern 350 and may extend in the first direction D1. A plurality of sixth insulating interlayer patterns 445 may be spaced apart from each other in the second direction D2 between first moldings 370 adjacent in the second direction D2. Sidewalls of the sixth insulating interlayer pattern 445 in the second direction D2 and lower surfaces of the sixth insulating interlayer pattern 445 may be covered by the second capping pattern 435 or overlapped with the second capping pattern 435.

[0045] The channel 385 may be disposed between first molding members 370 adjacent in the first direction D1 among the first molding members 370 located on the third wiring 300 extending in the first direction D1, and a plurality of channels 385 may be spaced apart from each other in the first direction D1. Sidewalls of the channel 385 opposite to the first molding member 370 and upper surfaces of portions of the channel 385 located on the third wiring 300 may be covered by or overlapped with the first capping pattern 395. In example embodiments, a cross-section of each of the channel 385 and the first capping pattern 395 in the first direction D1 may have a cup shape having a lower surface and sidewalls, or a U shape.

[0046] In example embodiments, the channel 385 may include an oxide semiconductor material. The oxide semiconductor material may include zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x 、In 2 O 3 ), tin oxide (SnO 2 ), titanium oxide (TiO x ), zinc oxynitride (Zn x Oy z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O a ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a )、Zirconium oxide zinc tin (Zr x Zn y Sn z Oa ) and / or at least one of indium gallium silicon oxide (InGaSiO).

[0047] The second capping pattern 435 may be disposed on the first capping pattern 395. In example embodiments, the second capping pattern 435 may cover the opposite sidewalls of the first molding 370 in the second direction D2, the opposite sidewalls of the channel 385 in the second direction D2 on each of the opposite sidewalls of the first molding 370 in the first direction D1, and the sidewalls of the first capping pattern 395 in the first direction D1 on the sidewalls of the channel 385 in the first direction D1, and the opposite sidewalls of the first molding 370 in the second direction D2, and the opposite sidewalls of the first molding 370 in the first direction D1. The relative side walls of the channel 385 in the second direction D2 and the first capping pattern 395 located on the side walls of the channel 385 in the first direction D1 overlap, or the relative side walls of the first molding 370 in the second direction D2, the relative side walls of the channel 385 in the second direction D2 on each of the relative side walls of the first molding 370 in the first direction D1, and the first capping pattern 395 located on the side walls of the channel 385 in the first direction D1 are on the side walls in the first direction D1.

[0048] Each of the first and second capping patterns 395 and 435 may include an insulating material, for example, silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, aluminum oxide, etc. In example embodiments, the first and second capping patterns 395 and 435 may include substantially the same material and may be merged with each other in some cases.

[0049] The second gate insulating pattern 455 may extend in the second direction D2 on the second capping pattern 435 and the sixth insulating interlayer pattern 445, and a plurality of second gate insulating patterns 455 may be spaced apart from each other in the first direction D1. In example embodiments, a cross-section of the second gate insulating pattern 455 in the first direction D1 may have a cup shape having a lower surface and sidewalls, or a U shape.

[0050] In an example embodiment, in a plan view, a first side wall of the second gate insulation pattern 455 facing the sixth insulation interlayer pattern 445 in the first direction D1 may have a convex shape toward the sixth insulation interlayer pattern 445, and a groove may be formed on a second side wall of the second gate insulation pattern 455 opposite to the first side wall of the second gate insulation pattern 455.

[0051] The second gate insulating pattern 455 may include an oxide, eg, silicon oxide.

[0052] The second gate electrode 475 may be disposed on the inner sidewall of the second gate insulating pattern 455 and may extend in the second direction D2. A plurality of second gate electrodes 475 may be spaced apart from each other in the first direction D1. The second gate electrodes 475 may be disposed on inner sidewalls respectively opposite to each other and may face each other in the first direction D1. Each of the second gate electrodes 475 may serve as a word line.

[0053] The second gate electrode 475 and the second gate insulating pattern 455 may collectively form a second gate structure.

[0054] The etch stop pattern 495 may be disposed between the second gate electrodes 475 adjacent in the first direction D1 and may extend in the second direction D2. A lower surface of the etch stop pattern 495 may contact an upper surface of the second gate insulating pattern 455. The etch stop pattern 495 may include an insulating nitride such as silicon nitride.

[0055] The seventh insulation interlayer pattern 505 may be disposed on the etch stop pattern 495 and may extend in the second direction D2 . The seventh insulation interlayer pattern 505 may fill a space defined by the etch stop pattern 495 .

[0056] In example embodiments, uppermost surfaces of the seventh insulating interlayer pattern 505 , the etch stop pattern 495 , and the second gate electrode 475 may be lower than an uppermost surface of the second gate insulating pattern 455 .

[0057] The fourth capping pattern 510 may be disposed on the etch stop pattern 495 , the second gate electrode 475 , and the second gate insulating pattern 455 , and may extend in the second direction D2 .

[0058] The landing pad 535 may include a lower portion contacting the upper surface of the channel 385 and an upper portion on the lower portion. A plurality of landing pads 535 may be spaced apart from each other in each of the first direction D1 and the second direction D2. The landing pad 535 may have a shape such as a circle, an ellipse, a polygon, a polygon with rounded corners, etc.

[0059] In example embodiments, a lower surface of the landing pad 535 and an uppermost surface of the channel 385 may be lower than uppermost surfaces of the first and second capping patterns 395 and 435 and the second gate insulating pattern 455. In example embodiments, a lower surface of the landing pad 535 may be lower than uppermost surfaces of the seventh insulating interlayer pattern 505, the etch stop pattern 495, and the second gate electrode 475, however, the inventive concept may not be limited thereto.

[0060] The eighth insulating interlayer pattern 540 may be disposed on the first molding member 370, the sixth insulating interlayer pattern 445, the second and fourth capping patterns 435 and 510, and the second gate insulating pattern 455, and may cover, overlap, or be located on the sidewalls of the landing pad 535. A lower surface of the eighth insulating interlayer pattern 540 may be lower than a lower surface of the landing pad 535. In example embodiments, a lower surface of the eighth insulating interlayer pattern 540 may be lower than an uppermost surface of the second gate insulating pattern 455 and higher than a lower surface of the fourth capping pattern 510.

[0061] The first supporting layer 550 may be disposed on the eighth insulating interlayer pattern 540 and the landing pad 535. The second supporting layer 560 may be disposed on the first supporting layer 550 and may be spaced apart from the first supporting layer 550 in the third direction D3. Each of the first supporting layer 550 and the second supporting layer 560 may include insulating nitride, for example, silicon nitride.

[0062] The capacitor 570 may be disposed on the landing pad 535, and at least a portion of the lower end and the upper end of the capacitor 570 may be covered by the first support layer 550 and the second support layer 560 or overlapped with the first support layer 550 and the second support layer 560 to be supported by the first support layer 550 and the second support layer 560. The capacitor 570 may include a lower electrode, a dielectric layer, and an upper electrode, and a plurality of capacitors 570 may be disposed in each of the first direction D1 and the second direction D2. Each of the lower electrode and the upper electrode may include a conductive material, and the dielectric layer may include a metal oxide having a high dielectric constant, for example, hafnium oxide, zirconium oxide, etc. The capacitor 570 may have a shape such as a circle, an ellipse, a polygon, a polygon with rounded corners, etc.

[0063] Each of the second gate electrode 475 , the first to third contact plugs 190 , 195 , and 240 , the first to fourth wirings 210 , 250 , 300 , and 340 , and the landing pad 535 may include a conductive material, for example, metal, metal nitride, metal silicide, or the like.

[0064] Each of the first insulating pattern 230, the third insulating pattern 280, the fifth insulating pattern 325 and the eighth insulating pattern 360, the second insulating layer 260, the second insulating interlayer 180 and the third insulating interlayer 200, the fourth capping pattern 510 and the eighth insulating interlayer pattern 540 may include an insulating nitride, such as silicon nitride, and each of the first insulating interlayer 120, the fourth insulating interlayer 220 and the fifth insulating interlayer 270, the sixth insulating pattern 330 and the seventh insulating pattern 350, the first mold 370, and the sixth insulating interlayer pattern 445 and the seventh insulating interlayer pattern 505 may include an oxide, such as silicon oxide.

[0065] The semiconductor device may include a first capping pattern 395 covering the sidewalls of the channel 385 in the first direction D1 or overlapping with the sidewalls of the channel 385 in the first direction D1, and a second capping pattern 435 covering the sidewalls of the channel 385 in the second direction D2 or overlapping with the sidewalls of the channel 385 in the second direction D2, and as shown below, when the semiconductor device is manufactured, the channel 385 can be protected by the first capping pattern 395 and the second capping pattern 435 from being damaged, so that the semiconductor device can have enhanced electrical characteristics.

[0066] Figures 5 to 68 are a perspective view, a plan view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0067] Specifically, Figure 5 , Fig. 9 , Fig.13 , Fig.16 , Fig. 20 , Fig.24 , Fig.28 , Fig.32 , Fig.36 , Fig.40 , Fig.44 , Fig.48 , Fig.52 , Fig.56 , Fig.59 , Fig.63 and Fig.66 It is a stereogram. Figure 6 , Fig.10 and Fig.17 It is a floor plan. Fig.21 , Fig.25 , Fig.29 , Fig.33 , Fig.37 , Fig.41 , Fig.45 , Fig.49 , Fig.53 and Fig.60 is a horizontal cross-section diagram, Figure 7 , Fig.11 , Fig.14 , Fig.18 , Fig. 22 , Fig.26 , Fig.30 , Fig.34 , Fig.38 , Fig.42 , Fig.46 , Fig.50 , Fig.54 , Fig.57 , Fig.61 , Fig.64 and Fig.67 Each of the above includes cross-sectional views taken along lines AA' and BB' of the corresponding plan view or horizontal cross-sectional view, respectively, and Figure 8 , Fig.12 , Fig.15 , Fig.19 , Fig.23 , Fig. 27 , Fig.31 , Fig.35 , Fig.39 , Fig.43 , Fig.47 , Fig.51 , Fig.55 , Fig.58 , Fig.62 , Fig.65 and Fig.68 Each of includes cross-sectional views taken along lines CC' and EE' of the corresponding plan view or horizontal cross-sectional view, respectively.

[0068] The horizontal cross-sectional views are views at a height H of the corresponding vertical cross-sectional views, respectively. However, when an empty space exists at the height H, the horizontal cross-sectional views show elements below the empty space.

[0069] Reference Figures 5 to 8 , an upper portion of the substrate 100 may be removed to form a first recess so that the active region 105 may be defined, and an isolation layer 110 may be formed to partially or completely fill the first recess so that a sidewall of the active region may be covered by or overlapped with the isolation layer 110 .

[0070] A first gate structure 160 may be formed on the active region 105 and the isolation layer 110, and a gate spacer 170 may be formed on a sidewall of the first gate structure 160. In example embodiments, the first gate structure 160 may include a first gate insulating pattern 130, a first gate electrode 140, and a gate mask 150 sequentially stacked in the third direction D3.

[0071] Impurities may be implanted into an upper portion of the active region 105 adjacent to the first gate structure 160 to form a source / drain region, and the first gate structure 160 and the source / drain region may together form a transistor. In example embodiments, the transistor may be part of a sense amplifier (S / A).

[0072] A first insulating interlayer 120 may be formed on the active region 105 and the isolation layer 110 so that the first insulating interlayer 120 covers the sidewalls of the gate spacer 170, overlaps with the sidewalls of the gate spacer 170, or is located on the sidewalls of the gate spacer 170, a second insulating interlayer 180 may be formed on the first insulating interlayer 120, the first gate structure 160, and the gate spacer 170, and a first contact plug 190 and a second contact plug 195 may be formed, the first contact plug 190 extending through the first insulating interlayer 120 and the second insulating interlayer 180 to contact the upper surface of the source / drain region, and the second contact plug 195 extending through the second insulating interlayer 180 and the gate mask 150 to contact the upper surface of the first gate electrode 140.

[0073] In example embodiments, the first insulating interlayer 120 may include an oxide, eg, silicon oxide, and the second insulating interlayer 180 may include an insulating nitride, eg, silicon nitride.

[0074] A third insulating interlayer 200 may be formed on the second insulating interlayer 180 and the first and second contact plugs 190 and 195, and a first wiring 210 may be formed to pass through the third insulating interlayer 200. In example embodiments, the first wiring 210 may extend in the first direction D1, and a plurality of first wirings 210 may be spaced apart from each other in the second direction D2. Each of the first wirings 210 may contact an upper surface of a corresponding one of the first and second contact plugs 190 and 195. In example embodiments, the third insulating interlayer 200 may include an insulating nitride such as silicon nitride, and thus may be merged with the second insulating interlayer 180 in some cases.

[0075] Reference Figures 9 to 12 , a fourth insulating interlayer 220 and the first insulating layer may be sequentially formed on the third insulating interlayer 200 and the first wiring 210 , and a third contact plug 240 may be formed through the fourth insulating interlayer 220 to contact an upper surface of the first wiring 210 .

[0076] In example embodiments, the fourth insulating interlayer 220 may include an oxide, eg, silicon oxide, and the first insulating layer may include an insulating nitride, eg, silicon nitride.

[0077] A second wiring layer may be formed on the first insulating layer and the third contact plug 240, and the second wiring layer and the first insulating layer may be patterned to form a second wiring 250 and a first insulating pattern 230, respectively. In example embodiments, the second wiring 250 may extend in the second direction D2, and a plurality of second wirings 250 may be spaced apart from each other in the first direction D1. Each of the second wirings 250 may contact an upper surface of the third contact plug 240.

[0078] The second insulating layer may be formed to cover, overlap, or be on the second wiring 250 and the first insulating pattern 230. In example embodiments, the second insulating layer 260 may include an insulating nitride, and thus may be merged with the first insulating pattern 230 in some cases.

[0079] Reference Figures 13 to 15 , a fifth insulating interlayer 270 and a third insulating layer may be sequentially stacked on the second insulating layer 260 , and a fourth contact plug 290 may be formed to pass through the third insulating layer, the fifth insulating interlayer 270 , and the second insulating layer 260 to contact an upper surface of the second wiring 250 .

[0080] A fourth contact plug 290, a third wiring layer and a fourth insulating layer can be sequentially stacked on the third insulating layer, and an etching process can be performed on the fourth insulating layer, the third wiring layer and the third insulating layer to form a fourth insulating pattern 310, a third wiring 300 and a third insulating pattern 280, respectively, and during the etching process, an upper portion of the fifth insulating interlayer 270 can also be removed.

[0081] In example embodiments, the third wirings 300 may extend in the first direction D1, and a plurality of the third wirings 300 may be spaced apart from each other in the second direction D2. Each of the third wirings 300 may be electrically connected to a corresponding one of the second wirings 250 through a fourth contact plug 290. In example embodiments, each of the third wirings 300 may function as a bit line.

[0082] In example embodiments, the fifth insulating interlayer 270 may include an oxide, eg, silicon oxide, and each of the third insulating pattern 280 and the fourth insulating pattern 310 may include an insulating nitride, eg, silicon nitride.

[0083] A fifth insulating layer 320 may be formed on the fifth insulating interlayer 270, the third and fourth insulating patterns 280 and 310, and the third wiring 300. In example embodiments, the fifth insulating layer 320 may include an insulating nitride such as silicon nitride, and thus may be merged with the third insulating pattern 280 and / or the fourth insulating pattern 310 in some cases.

[0084] Reference Figures 16 to 18 , you can Figures 13 to 15 A sixth insulating layer and a fourth wiring layer are sequentially formed on the fifth insulating layer 320 shown in FIG. 1 , and an upper portion of the fourth wiring layer may be removed by, for example, an etch-back process to form a fourth wiring 340 .

[0085] A seventh insulating layer may be formed on the fourth wiring 340 and the sixth insulating layer, and a planarization process may be performed on the sixth and seventh insulating layers until an upper surface of the third wiring 300 is exposed to form sixth and seventh insulating patterns 330 and 350 , respectively.

[0086] During the planarization process, the upper portion of the fifth insulating layer 320 may be removed to form a plurality of fifth insulating patterns 325 spaced apart from each other in the second direction D2, and the fourth insulating pattern 310 may be removed. Each of the sixth insulating pattern 330 and the seventh insulating pattern 350 and the fourth wiring 340 may extend in the first direction D1. A plurality of sixth insulating patterns 330 may be spaced apart from each other in the second direction D2, a plurality of seventh insulating patterns 350 may be spaced apart from each other in the second direction D2, and a plurality of fourth wirings 340 may be spaced apart from each other in the second direction D2. In example embodiments, the fourth wiring 340 may be disposed adjacent to the third wiring 300 used as a bit line, and may be used as a bit line shield. A cross-section of each of the fifth insulating pattern 325 and the sixth insulating pattern 330 in the second direction D2 may have a cup shape or a U shape having a lower surface and a side wall.

[0087] Reference Figure 20 to Figure 23 , an eighth insulating layer and a first molding layer may be sequentially formed on the fifth insulating pattern 325, the sixth insulating pattern 330, the seventh insulating pattern 350 and the third wiring 300, and the first molding layer and the eighth insulating layer may be patterned by an etching process to form a first molding 370 and an eighth insulating pattern 360, respectively, and during the etching process, the upper portions of the fifth insulating pattern 325, the sixth insulating pattern 330, the seventh insulating pattern 350 and the third wiring 300 may also be removed.

[0088] In example embodiments, each of the first molding 370 and the eighth insulation pattern 360 may extend in the second direction D2. A plurality of first moldings 370 may be spaced apart from each other in the first direction D1, and a plurality of eighth insulation patterns 360 may be spaced apart from each other in the first direction D1.

[0089] The channel layer 380 may be formed to cover, overlap, or be on the first mold 370 and the eighth insulation pattern 360 , and a first capping layer 390 may be formed on the channel layer 380 .

[0090] In example embodiments, the channel layer 380 may include an oxide semiconductor material such as indium gallium zinc oxide (IGZO), and the first capping layer 390 may include an insulating material such as silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, aluminum oxide, or the like.

[0091] Reference Figure 24 to Figure 27 , a second mold layer and a mask layer can be sequentially formed on the first capping layer 390, the mask layer can be patterned to form a plurality of masks 410, each of the plurality of masks 410 can extend in the first direction D1 and be spaced apart from each other in the second direction D2, and a dry etching process can be performed using the mask 410 as an etching mask to pattern the second mold layer, the first capping layer 390, the channel layer 380, the first mold 370 and the eighth insulating pattern 360, so that the opening 420 can be formed to expose the upper surface of the seventh insulating pattern 350.

[0092] Therefore, the second molding layer may be divided into a plurality of second moldings 400, each of which may extend in the first direction D1 and be spaced apart from each other in the second direction D2. The first capping layer 390 may be divided into first capping patterns, each of which may extend in the first direction D1 and be spaced apart from each other in the second direction D2, and the channel layer 380 may be divided into channels, each of which may extend in the first direction D1 and be spaced apart from each other in the second direction D2. The first molding 370 extending in the second direction D2 may be divided into a plurality of portions spaced apart from each other in the second direction D2, and the eighth insulating pattern 360 extending in the second direction D2 may be divided into a plurality of portions spaced apart from each other in the second direction D2.

[0093] The second molding member 400 may include, for example, a spin-on hard mask (SOH) or an amorphous carbon layer (ACL), and the mask 410 may include, for example, silicon nitride.

[0094] Reference Figure 28 to Figure 31, the mask 410 and the second molding 400 may be removed, and thus the upper surface of the first capping pattern 395 may be exposed.

[0095] In example embodiments, the mask 410 may be removed by an etching process, and the second molding 400 may be removed by, for example, an ashing process and / or a stripping process. During removal of the second molding 400, the channel 385 may be covered by or overlapped with the first capping pattern 395 so that the channel 385 is not damaged.

[0096] Reference Figure 32 to Figure 35 A second capping layer 430 may be formed on the first capping pattern 395 , the channel 385 , the first molding 370 , and the seventh and eighth insulation patterns 350 and 360 , and a sixth insulation interlayer 440 may be formed on the second capping layer 430 .

[0097] The second capping layer 430 may include insulating nitride, for example, silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, aluminum oxide, etc. In example embodiments, the second capping layer 430 may include substantially the same material as the first capping pattern 395 , and thus may be merged with the first capping pattern 395 .

[0098] In example embodiments, the sixth insulating interlayer 440 may partially or completely fill a portion of the opening 420 between stacked structures, and may cover, overlap, or be located on each of the opposite sidewalls of the stacked structures in the first direction D1, each of which may include the eighth insulating pattern 360, the first molding 370, the channel 385, the first capping pattern 395, and a portion of the second capping layer 430 located on the upper surface and sidewalls of the eighth insulating pattern 360, the first molding 370, the channel 385, and the first capping pattern 395. A plurality of second recesses 447 may be formed on a portion of the sixth insulating interlayer 440 between the stacked structures spaced apart from each other in the first direction D1, and each of the plurality of second recesses 447 may extend in the second direction D2 and be spaced apart from each other in the first direction D1.

[0099] Reference Figure 36 to Figure 39 , an isotropic etching process such as a wet etching process may be performed on the sixth insulating interlayer 440 to form a sixth insulating interlayer pattern 445 .

[0100] In an example embodiment, when an isotropic etching process is performed, the upper surface of the second capping layer 430 can be exposed, and most of the portion of the sixth insulating interlayer 440 located between the stacked structures spaced apart from each other in the first direction D1 can be removed, and the upper portion of the portion of the sixth insulating interlayer 440 located between the stacked structures spaced apart from each other in the second direction D2 can be removed.

[0101] Thus, in example embodiments, an upper surface of the sixth insulation interlayer pattern 445 may be lower than an upper surface of the channel 385 and higher than a lower surface of the channel 385 , however, the inventive concept may not be limited thereto.

[0102] During the isotropic etching process, the channel 385 may be protected by the first capping pattern 395 and the second capping layer 430 so as not to be damaged.

[0103] The second recess 447 may be expanded into a third recess 449 having a width and a depth greater than those of the second recess 447 .

[0104] Reference Figure 40 to Figure 43 , a second gate insulating layer 450 may be formed on the second capping layer 430 and the sixth insulating interlayer pattern 445 .

[0105] The second gate insulating layer 450 may include insulating nitride, for example, silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, aluminum oxide, etc. In example embodiments, the second gate insulating layer 450 may include substantially the same material as the second capping layer 430 , and thus may be merged with the second capping layer 430 .

[0106] Reference Figures 44 to 47 , a second gate electrode layer 470 and a third capping layer 480 may be sequentially formed on the second gate insulating layer 450 .

[0107] The third capping layer 480 may include insulating nitride, for example, silicon nitride.

[0108] Reference Figures 48 to 51 , an anisotropic etching process may be performed on the third capping layer 480 and the second gate electrode layer 470 to form a third capping pattern 485 and a second gate electrode 475, respectively.

[0109] In example embodiments, each of the third capping pattern 485 and the second gate electrode 475 may extend in the second direction D2 on the second gate insulating layer 450. A plurality of third capping patterns 485 may be spaced apart from each other in the first direction D1, and a plurality of second gate electrodes 475 may be spaced apart from each other in the first direction D1.

[0110] Each of the second gate electrodes 475 may be formed on a portion of the second gate insulating layer 450 located on the sidewall in the first direction D1 of each of the stacked structures adjacent in the first direction D1, and the second gate electrodes 475 in the third recess 449 may face each other in the first direction D1. Through the anisotropic etching process, the upper surface and sidewall of the upper portion of the second gate insulating layer 450 and the upper surface of the portion of the second gate insulating layer 450 located on the bottom of the third recess 449 may be exposed.

[0111] Sidewalls and a lower surface of the third capping pattern 485 may be covered by or overlapped with the second gate electrode 475 .

[0112] Reference Figure 52 to Figure 55 An etch stop layer 490 may be formed on the second gate insulating layer 450 , the second gate electrode 475 , and the third capping pattern 485 , and a seventh insulating interlayer 500 may be formed on the etch stop layer 490 to partially or completely fill the third recess 449 .

[0113] The etch stop layer 490 may include insulating nitride, for example, silicon nitride. In example embodiments, the etch stop layer 490 may include substantially the same material as the third capping pattern 485 and thus may be merged with the third capping pattern 485. The seventh insulating interlayer 500 may include an oxide, for example, silicon oxide.

[0114] Reference Figure 56 to Figure 58 , a planarization process such as an etch-back process may be performed on the seventh insulating interlayer 500 until an upper surface of the etch stop layer 490 is exposed to form a seventh insulating interlayer pattern 505 .

[0115] In example embodiments, the seventh insulation interlayer pattern 505 may extend in the second direction D2, and a plurality of seventh insulation interlayer patterns 505 may be spaced apart from each other in the first direction D1.

[0116] Reference Figure 59 to Figure 62 , a planarization process may be performed on the seventh insulating interlayer pattern 505 , the etch stop layer 490 , the second gate insulating layer 450 , the second capping layer 430 , the first capping pattern 395 , and upper portions of the channel 385 .

[0117] The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0118] Through the planarization process, the etch stop layer 490, the second gate insulation layer 450, and the second capping layer 430 may be transformed into an etch stop pattern 495, a second gate insulation pattern 455, and a second capping pattern 435, respectively. Each of the etch stop pattern 495 and the second gate insulation pattern 455 may extend in the second direction D2. A plurality of etch stop patterns 495 may be spaced apart from each other in the first direction D1, and a plurality of second gate insulation patterns 455 may be spaced apart from each other in the first direction D1. The second gate electrode 475 and the second gate insulation pattern 455 may form a second gate structure together.

[0119] The channel 385 extending in the first direction D1 may be divided into a plurality of portions spaced apart from each other in the first direction D1.

[0120] Reference Figure 63 to Figure 65 , an etching process may be performed to remove an upper portion of the seventh insulation interlayer pattern 505 to form a fourth recess, and a fourth capping pattern 510 may be formed in the fourth recess.

[0121] In example embodiments, during the etching process, upper surfaces of the second gate electrode 475 and the etch stop pattern 495 may be exposed, or upper portions of the second gate electrode 475 and the etch stop pattern 495 may also be removed.

[0122] An upper portion of the channel 385 may be removed to form a fifth recess, and a landing pad layer 530 may be formed on the first molding member 370, the channel 385, the first capping pattern 395 and the second capping pattern 435, the second gate insulation pattern 455, the sixth insulation interlayer pattern 445 and the seventh insulation interlayer pattern 505, the second gate electrode 475, the etch stop pattern 495 and the fourth capping pattern 510 to partially or completely fill the fifth recess.

[0123] In example embodiments, a portion of the landing pad layer 530 located in the fifth recess may contact an upper surface of the channel 385 .

[0124] Reference Figure 66 to Figure 68 , an etching process can be performed to form a sixth recess, which passes through the landing pad layer 530, and the first molding 370, the channel 385, the first capping pattern 395 and the second capping pattern 435, the second gate insulation pattern 455, the sixth insulation interlayer pattern 445 and the upper portion of the fourth capping pattern 510, and an eighth insulation interlayer pattern 540 can be formed in the sixth recess.

[0125] Through the etching process, the landing pad layer 530 may be divided into a plurality of landing pads 535 spaced apart from each other in each of the first direction D1 and the second direction D2. In example embodiments, each of the landing pads 535 may have a shape such as a circle, an ellipse, a polygon, a polygon with rounded corners, etc. in a plan view, and may contact the upper surface of the channel 385 through a lower portion of the landing pad 535 in the fifth recess.

[0126] Return to reference Figures 1 to 3 , a first supporting layer 550 and a second supporting layer 560 may be formed on the eighth insulating interlayer pattern 540 and the landing pad 535, and a capacitor 570 may be formed to pass through the first supporting layer 550 and the second supporting layer 560 to contact the upper surfaces of the landing pad 535, respectively, to complete the manufacture of the semiconductor device.

[0127] As shown above, a first capping layer 390 may be formed on the channel layer 380, a second molding layer may be formed on the first capping layer 390, a mask 410 may be formed on the second molding layer, and a dry etching process may be performed using the mask 410 as an etching mask to pattern the second molding layer, the first capping layer 390, and the channel layer 380, so that the channel layer 380 may be divided into a plurality of channels 385, each of the plurality of channels 385 may extend in the first direction D1 and be spaced apart from each other in the second direction D2.

[0128] Additionally, a second capping layer 430 may be formed on the channel 385, a sixth insulating interlayer 440 may be formed on the second capping layer 430, and an isotropic etching process such as a wet etching process may be performed on the sixth insulating interlayer 440 to form a sixth insulating interlayer pattern 445. During the isotropic etching process, the channel 385 may be protected by the first capping pattern 395 so that the second capping layer 430 is not damaged.

[0129] As a result, the channel 385 may be protected by the first capping pattern 395 and the second capping layer 430 during formation of the channel 385 and subsequent processes, so that a semiconductor device including the channel 385 may have enhanced electrical characteristics.

[0130] Figures 69 to 72 can be separated with Figures 1 to 4 A perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view of a semiconductor device according to example embodiments are shown accordingly.

[0131] In addition to some components, the semiconductor device can be Figures 1 to 4 The semiconductor devices are substantially the same or similar, and thus repeated explanation is omitted herein.

[0132] Reference Figures 69 to 72, the semiconductor device may not include the first capping pattern 395 .

[0133] Therefore, sidewalls of the channel 385 not in contact with sidewalls of the first molding 370 in the first direction D1 may be covered by or overlapped with the second capping pattern 435 but not covered by or overlapped with the first capping pattern 395 .

[0134] Figure 73 to Figure 76 are a perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0135] The method may include referring to Figures 5 to 68 and Figures 1 to 4 Those processes are substantially the same or similar to those shown, and thus repeated explanations thereof are omitted herein.

[0136] Reference Figure 73 to Figure 76 , can be executed and referenced Figures 5 to 23 Processes that are substantially the same or similar to those shown.

[0137] However, the first capping layer 390 may not be formed on the channel layer 380 .

[0138] Can be executed and referenced Figures 24 to 68 and Figures 1 to 4 Processes substantially the same or similar to those shown may be used to complete the fabrication of a semiconductor device.

[0139] Figures 77 to 80 can be separated with Figures 1 to 4 A perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view of a semiconductor device according to example embodiments are shown accordingly.

[0140] In addition to some components, the semiconductor device can be Figures 1 to 4 The semiconductor devices are substantially the same or similar, and thus repeated explanation is omitted herein.

[0141] Reference Figures 77 to 80 , the semiconductor device may not include the first capping pattern 395 .

[0142] The sixth insulation interlayer pattern 445 may include a material substantially the same as that of the sixth insulation pattern 330 and the first molding member 370, and thus the sixth insulation interlayer pattern 445, the sixth insulation pattern 330 and the first molding member 370 may be merged with each other to form a single structure (ie, the sixth insulation interlayer pattern 445).

[0143] Thus, a first sidewall of the channel 385 in the first direction D1 may be covered by or overlapped with the first capping pattern 395 , and a second sidewall of the channel 385 in the first direction D1 and an opposite sidewall of the channel 385 in the second direction D2 may contact the sixth insulating interlayer pattern 445 .

[0144] Figures 81 to 88 are a perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0145] The method may include referring to Figures 5 to 68 and Figures 1 to 4 Those processes are substantially the same or similar to those shown, and thus repeated explanations thereof are omitted herein.

[0146] Reference Figure 81 to Figure 84 , can be executed and referenced Figures 5 to 35 Processes that are substantially the same or similar to those shown.

[0147] However, the second capping layer 430 may not be formed on the first capping pattern 395, the channel 385, the first mold 370, and the seventh and eighth insulation patterns 350 and 360, and the sixth insulating interlayer 440 may be formed on the first capping pattern 395, the channel 385, the first mold 370, and the seventh and eighth insulation patterns 350 and 360.

[0148] The sixth insulating interlayer 440 may include an oxide such as silicon oxide. In example embodiments, the sixth insulating interlayer 440 may include substantially the same material as the sixth insulating pattern 330 and the first molding 370, and thus may be merged with each other to form a single structure. Hereinafter, the merged structure may be referred to as the sixth insulating interlayer 440.

[0149] Reference Figure 85 to Figure 88 , can be executed and referenced Figure 36 to Figure 39 Processes substantially the same as or similar to those illustrated, ie, an isotropic etching process may be performed to form the sixth insulation interlayer pattern 445 .

[0150] During the isotropic etching process, the channel 385 may be protected by the first capping pattern 395 on the upper surface of the channel 385 .

[0151] Reference Figures 77 to 80 , can be executed and referenced Figures 40 to 68 and Figures 1 to 6 Processes substantially the same or similar to those shown may be used to complete the fabrication of a semiconductor device.

[0152] Figures 89 to 92 can be separated with Figures 77 to 80A perspective view, a horizontal cross-sectional view, and a vertical cross-sectional view of a semiconductor device according to example embodiments are shown accordingly.

[0153] In addition to some components, the semiconductor device can be Figures 77 to 80 The semiconductor devices are substantially the same or similar, and thus repeated explanation is omitted herein.

[0154] Reference Figures 89 to 92 , the semiconductor device may not include the first capping pattern 395 .

[0155] Thus, all of the opposing sidewalls of the channel 385 in the first direction D1 and the opposing sidewalls of the channel 385 in the second direction D2 may contact the sixth insulation interlayer pattern 445 .

[0156] Fig.93 It is possible to Figure 1 Correspondingly, a perspective view of a semiconductor device according to example embodiments is shown.

[0157] In addition to some components, the semiconductor device can be Figures 1 to 4 The semiconductor devices are substantially the same or similar, and thus repeated explanation is omitted herein.

[0158] Reference Fig.93 In the semiconductor device, a plurality of first moldings 370 may be spaced apart from each other in the second direction D2, and each of the first moldings 370 may include a lower portion extending in the second direction D2 and a plurality of upper portions spaced apart from each other in the second direction D2. The eighth insulating pattern 360 may also extend in the second direction D2 under the first molding 370, and an upper surface of the seventh insulating pattern 350 under the eighth insulating pattern 360 may not contact a lower surface of the first molding 370.

[0159] Fig.93 The semiconductor device can be such that Figures 1 to 4 A variation of the semiconductor device is obtained by forming each of the first molding members 370 to extend in the second direction D2, instead of forming a plurality of first molding members 370 spaced apart from each other in each of the first direction D1 and the second direction D2, and the inventive concept may not be limited thereto. For example, Figure 69 to Figure 72 , Figures 77 to 80 or Figures 89 to 92 A semiconductor device of any variation of the semiconductor device may be within the scope of the present invention.

[0160] Figures 94 to 98 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0161] The method may include referring to Figures 5 to 68 and Figures 1 to 4 Those processes are substantially the same or similar to those shown, and thus repeated explanations thereof are omitted herein.

[0162] Reference Fig.94 , can be executed and referenced Figures 5 to 27 Processes that are substantially the same or similar to those shown.

[0163] However, the opening 420 may extend through only the upper portion of the first molding 370, and thus only the upper portion of the first molding 370 may be divided into a plurality of portions spaced apart from each other in the second direction D2, and the lower portion of the first molding 370 may not be divided but may extend in the second direction D2. Therefore, the opening 420 may not extend through the eighth insulation pattern 360, and may not expose the upper surface of a portion of the seventh insulation pattern 350 below the eighth insulation pattern 360.

[0164] Reference Fig.95 , can be executed and referenced Figure 28 to Figure 31 Processes substantially the same or similar to those shown are performed to expose the upper surface of the first capping pattern 395 .

[0165] Reference Fig.96 , can be executed and referenced Figure 32 to Figure 35 Processes substantially the same as or similar to those shown are performed to form the second capping layer 430 , and a sixth insulating interlayer 440 may be formed on the second capping layer 430 .

[0166] Reference Fig.97 , can be executed and referenced Figure 36 to Figure 39 Processes substantially the same or similar to those shown are performed to form the sixth insulation interlayer pattern 445 , and the second recess 447 may be expanded into a third recess 449 having a greater width and depth than those of the second recess 447 .

[0167] Reference Fig.98 , can be executed and referenced Figures 40 to 47 Processes substantially the same as or similar to those shown may allow the second gate insulating layer 450 , the second gate electrode layer 470 , and the third capping layer 480 to be sequentially formed.

[0168] Return to reference Fig.93 , can be executed and referenced Figures 48 to 68 and Figures 1 to 4 Processes substantially the same or similar to those shown may be used to complete the fabrication of a semiconductor device.

[0169] Fig.99 and Fig.100 It is possible to Figure 1 and Figure 4A perspective view and a vertical cross-sectional view respectively illustrate a semiconductor device according to example embodiments.

[0170] In addition to some components, the semiconductor device can be Figures 1 to 4 The semiconductor devices are substantially the same or similar, and thus repeated explanation is omitted herein.

[0171] Reference Fig.99 and Fig.100 , an upper surface of the first molding 370 adjacent to the channel 385 and a lower surface of the landing pad 535 thereon may be substantially coplanar with an uppermost surface of the channel 385 , and a lower surface of the eighth insulating interlayer pattern 540 may be lower than an uppermost surface of the channel 385 .

[0172] Additionally, the eighth insulation interlayer pattern 540 may extend through the fourth capping pattern 510 , and upper portions of the seventh insulation interlayer pattern 505 and the etch stop pattern 495 .

[0173] The semiconductor device can be manufactured by the following steps: Figure 63 to Figure 65 The illustrated process removes the upper portion of the trench 385 to form the fifth recess before removing the upper portion, removes the upper portion of the first molding member 370 to form a seventh recess exposing the upper sidewall of the trench 385, removes the upper sidewall of the trench 385 to expand the seventh recess, and forms a landing pad layer 530 in the expanded seventh recess.

[0174] The eighth insulating interlayer pattern 540 may have a lower surface lower than that of the landing pad layer 530 to divide the landing pad layer 530 , and may extend through the fourth capping pattern 510 , and upper portions of the seventh insulating interlayer pattern 505 and the etch stop pattern 495 .

[0175] Fig.101 and Fig.102 It is possible to Figure 1 and Figure 4 A perspective view and a vertical cross-sectional view respectively illustrate a semiconductor device according to example embodiments.

[0176] In addition to some components, the semiconductor device can be Figures 99 to 100 are substantially the same or similar, and thus repeated explanation is omitted herein.

[0177] Reference Fig.101 and Fig.102 , a lower surface of a portion of the landing pad 535 contacting the upper surface of the first molding 370 may be higher than a lower surface of a portion of the landing pad 535 contacting the uppermost surface of the channel 385 .

[0178] The semiconductor device can be manufactured by the following steps: after forming the seventh recess to expose the upper surface of the channel 385, when removing the upper sidewall of the channel 385 exposed by the seventh recess, the channel 385 is formed so that the uppermost surface of the channel 385 can be lower than the upper surface of the first molding 370.

[0179] As used in this article, the terms "comprise", "include", "contain", "have", "have" and any other variations thereof specifically refer to the presence of stated features, steps, operations, elements, parts and / or groups thereof, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or groups thereof. In addition, it will be understood that although the terms first, second, etc. may be used in this article to describe various elements, these elements should not be limited by these terms. On the contrary, these terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be named a second element, and similarly, a second element may be named a first element.

[0180] The above is an illustration of exemplary embodiments and should not be construed as limiting thereof. Although some exemplary embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, means-plus-function statements are intended to cover structures described herein as performing the stated functions, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the above is an illustration of various exemplary embodiments and should not be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device comprising: bit lines located on a substrate, wherein each of the bit lines extends in a first direction substantially parallel to an upper surface of the substrate, and wherein the bit lines are spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and intersecting the first direction; a channel located on each of the bit lines, wherein the channels are spaced apart from each other in the first direction; a first capping pattern located on a sidewall of each of the channels; a gate insulating pattern, which is located on a sidewall of the first capping pattern; a gate electrode located on a sidewall of the gate insulating pattern; and A capacitor is electrically connected to a corresponding one of the channels. 2 . The semiconductor device of claim 1 , further comprising a second capping pattern on the first capping pattern.

3. The semiconductor device according to claim 2, wherein: The second capping pattern is located between the first capping pattern and the gate insulating pattern.

4. The semiconductor device according to claim 2, further comprising: a molding located between the channels in the channel, wherein the molding is located on the bit line, and Wherein, the second capping pattern contacts a sidewall of the molding and a sidewall of the channel.

5. The semiconductor device according to claim 2, further comprising: bit line shields located between the bit lines, wherein each of the bit line shields extends in the first direction; and A first insulating pattern is located between corresponding ones of the bit lines and corresponding ones of the bit line shields.

6. The semiconductor device according to claim 5, further comprising: a molding located between the trenches in the trenches, wherein the molding is located on the bit lines; and A second insulating pattern is located on each of the bit line shields, wherein each of the second insulating patterns is located between adjacent ones of the moldings.

7. The semiconductor device according to claim 6, wherein: The second capping pattern extends between the molding and an adjacent one of the second insulation patterns.

8. The semiconductor device according to claim 2, wherein: The first capping pattern and the second capping pattern include substantially the same material.

9. The semiconductor device according to claim 1, wherein: Each of the channels has a lower surface and a side wall in a cross section in the first direction.

10. The semiconductor device according to claim 9, wherein A cross-section of the first capping pattern in the first direction has a lower surface and sidewalls, and the first capping pattern contacts an upper surface and sidewalls of each of the channels.

11. The semiconductor device according to claim 1, wherein A channel in the channel includes an oxide semiconductor material, and the first capping pattern includes silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, or aluminum oxide.

12. A semiconductor device comprising: bit lines located on a substrate, wherein each of the bit lines extends in a first direction substantially parallel to an upper surface of the substrate, and wherein the bit lines are spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and intersecting the first direction; a channel located on each of the bit lines, wherein the channels are spaced apart from each other in the first direction; a gate insulating pattern located on a first sidewall of each of the channels; a gate electrode, which is located on a sidewall of the gate insulating pattern; a capacitor electrically connected to a corresponding one of the channels; a molding member located between channels of the channels, wherein the molding member contacts respective second sidewalls of respective channels of the channels in the first direction; and a first capping pattern contacting a side wall of each of the moldings, Wherein, a sidewall of each of the channels contacts a corresponding one of the moldings.

13. The semiconductor device according to claim 12, further comprising a second capping pattern located on the first sidewall of each of the trenches, in, The second capping pattern contacts the gate insulating pattern.

14. The semiconductor device according to claim 13, wherein: The first capping pattern contacts a sidewall of the second capping pattern.

15. The semiconductor device according to claim 12, further comprising: bit line shields located between the bit lines, wherein each of the bit line shields extends in the first direction; a first insulating pattern located between corresponding ones of the bit lines and corresponding ones of the bit line shields; and A second insulating pattern is located on each of the bit line shields, wherein each of the second insulating patterns is located between adjacent ones of the moldings.

16. The semiconductor device according to claim 15, wherein: The first capping pattern extends between the molding and an adjacent second insulation pattern of the second insulation patterns.

17. A semiconductor device comprising: bit lines located on a substrate, wherein each of the bit lines extends in a first direction substantially parallel to an upper surface of the substrate, and wherein the bit lines are spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and intersecting the first direction; bit line shields located between the bit lines, wherein each of the bit line shields extends in the first direction; a channel located on each of the bit lines, wherein the channels are spaced apart from each other in the first direction; a first capping pattern located on a first sidewall of each of the channels; a gate insulating pattern, which is located on a sidewall of the first capping pattern; a gate electrode, which is located on a sidewall of the gate insulating pattern; a capacitor electrically connected to a corresponding one of the channels; a molding member located between channels of the channels, wherein each of the molding members contacts a second sidewall of a corresponding channel of the channels; a second insulating pattern on each of the bit line shields, wherein each of the second insulating patterns is located between adjacent ones of the moldings; and A second capping pattern is located on a sidewall of each of the moldings, wherein a sidewall of each of the channels contacts an adjacent one of the moldings.

18. The semiconductor device according to claim 17, wherein: The second capping pattern contacts a sidewall of the first capping pattern.

19. The semiconductor device according to claim 18, wherein: The second capping pattern contacts a sidewall of the first capping pattern.

20. The semiconductor device according to claim 17, wherein The first capping pattern contacts a sidewall of each of the second insulating patterns.

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