An electric energy meter signal processing system and its circuit based on a differential resistance voltage dividing network

Abstract

The present application relates to an electric energy meter signal processing system and its circuit based on a differential resistance voltage dividing network, and relates to the technical field of circuit differential resistance adjustment. It includes: a positive terminal signal analysis module that collects and analyzes the voltage output signal of the positive input terminal of the differential voltage dividing network to determine the signal waveform deviation value; a waveform deviation analysis module that analyzes the signal waveform deviation value through a preset mirror resistance analysis strategy to determine the mirror resistance value of the positive input terminal of the voltage dividing network; a negative terminal resistance adjustment module that extracts the corresponding negative terminal resistance adjustment instruction from a preset adjustable resistance database according to the mirror resistance value; and controls the resistance value of the negative terminal adjustable resistance in the differential voltage dividing network through the negative terminal resistance adjustment instruction. The present application has the effect of improving the stability during detection in the test circuit.

Description

Technical Field

[0001] The present application relates to the technical field of circuit differential resistance regulation, and particularly to an electric energy meter signal processing system and its circuit based on a differential resistance voltage division network. Background Art

[0002] The differential voltage division network is a voltage signal test circuit with good anti-interference characteristics and is widely used in the measurement circuits of electrical equipment.

[0003] In the related art, the differential resistance network consists of a voltage input module, a voltage division module, a voltage signal sampling module, an analog-to-digital conversion module, and a sampling value output module. When the differential resistance network is connected to the power supply under test, the measured voltage signal is transmitted to the voltage division module through the voltage input module for voltage division processing, and then transmitted to the voltage signal sampling module through the voltage division module. After signal sampling by the voltage signal sampling module, the sampled signal is transmitted to the analog-to-digital conversion module for sampling value conversion, and the converted sampling value is output through the sampling value output module.

[0004] In view of the above related art, in the signal test circuit of the differential voltage division network, when there are interference signal waves in the connected line, it is easy to affect the stability of the measured signal, resulting in large fluctuations in the sampling value data obtained during continuous sampling in the test circuit. Summary of the Invention

[0005] In order to improve the stability during detection in the test circuit, the present application provides an electric energy meter signal processing system and its circuit based on a differential resistance voltage division network.

[0006] In a first aspect, the present application provides an electric energy meter signal processing system based on a differential resistance voltage division network, adopting the following technical solution:

[0007] An electric energy meter signal processing system based on a differential resistance voltage division network includes:

[0008] A positive terminal signal analysis module that collects and analyzes the voltage output signal at the positive input terminal of the differential voltage division network to determine the signal waveform deviation value;

[0009] A waveform deviation analysis module that analyzes the signal waveform deviation value through a preset mirror resistance analysis strategy to determine the mirror resistance at the positive input terminal of the voltage division network;

[0010] A negative terminal resistance adjustment module that extracts the corresponding negative terminal resistance adjustment instruction from a preset adjustable resistance database according to the mirror resistance;

[0011] Controls the resistance value of the negative terminal adjustable resistance in the differential voltage division network through the negative terminal resistance adjustment instruction.

[0012] Optionally, the mirror resistance value analysis strategy includes:

[0013] Obtain the signal deviation value between the positive terminal input electrical signal and the positive terminal output electrical signal, and substitute the signal deviation value into a preset deviation analysis model for analysis to determine the waveform deviation characteristics;

[0014] Calculate the waveform deviation value based on the waveform deviation characteristics, and construct a difference gain model according to the waveform deviation value. The expression of the difference gain model is , where represents the deviation gain value, represents the characteristic value of the waveform deviation characteristics, which is generated by comparing data through a preset database, represents the deviation amplitude corresponding to the waveform deviation characteristics;

[0015] Calculate the mirror resistance value according to the deviation gain value and the pre-constructed current mirror. The following formula is used during the calculation:

[0016] ,

[0017] ,

[0018] ,

[0019] where, represents the output voltage, represents the differential mode gain value, represents the voltage at the positive input terminal, represents the voltage at the negative input terminal, represents the drain current of the constructed metal oxide semiconductor field effect transistor, represents the gate-source voltage of the metal oxide semiconductor field effect transistor, represents the threshold voltage of the metal oxide semiconductor field effect transistor, represents the channel width-to-length ratio of the metal oxide semiconductor field effect transistor, represents the mobility of carriers in the channel, represents the gate oxide capacitance per unit area, represents the mirror resistance value, represents the power supply voltage of the metal oxide semiconductor field effect transistor.

[0020] Optionally, when determining the mirror resistance value at the positive input terminal of the voltage divider network, it further includes:

[0021] Simulate the resistance input at the negative input terminal of the differential voltage divider network to determine the analog input voltage signal;

[0022] Analyze based on the analog input voltage signal and the voltage input signal at the positive input terminal of the differential voltage divider network to determine the input voltage difference corresponding to the voltage of the voltage signal;

[0023] When the input voltage difference is not within the preset good difference range, calculate the resistance at the positive input terminal of the differential voltage divider network according to the preset difference comprehensive adjustment strategy to determine the corrected mirror resistance value.

[0024] Optionally, when calculating the resistance at the positive input terminal of the differential voltage divider network according to the preset difference comprehensive adjustment strategy, it includes:

[0025] Calculate based on the differential mode gain and the analysis formula of the output voltage and input differential voltage of the preset differential voltage network to determine the theoretical common mode voltage. The analysis formula of the output voltage and input differential voltage of the differential voltage network is as follows:

[0026] ,

[0027] ,

[0028] ,

[0029] ;

[0030] Among them, represents the common mode voltage of the differential circuit, represents the differential mode gain, represents the negative terminal input voltage, represents the positive terminal input voltage, and respectively represent the detected negative terminal input current and positive terminal input current, and respectively represent the simulated negative terminal resistance and positive terminal resistance, represents the voltage influence coefficient of the circuit elements in the differential circuit.

[0031] Optionally, when determining the corrected mirror resistance value, it also includes:

[0032] Input a preset fluctuation signal into the differential resistance voltage divider network and collect and analyze the positive terminal output signal and the negative terminal output signal to determine the positive terminal output waveform and the negative terminal output model;

[0033] Simulate based on the positive terminal output signal and the negative terminal output signal to determine the positive terminal simulated output waveform and the negative terminal simulated output waveform;

[0034] Calculate and analyze the positive terminal deviation waveform of the positive terminal output waveform and the positive terminal simulated output waveform, and the negative terminal deviation waveform of the negative terminal output waveform and the negative terminal simulated waveform;

[0035] Analyze the positive terminal deviation waveform and the negative terminal deviation waveform to determine the output waveform deviation, and match the preset resistance value adjustment database to output the resistance value optimization coefficient corresponding to the output waveform deviation;

[0036] Generate a resistance value optimization adjustment instruction based on the resistance value optimization coefficient.

[0037] Optionally, when controlling the resistance value of the negative terminal adjustable resistor in the differential voltage dividing network, it further includes:

[0038] Analyze the negative terminal analog waveform and the positive terminal analog waveform to determine the waveform symmetry;

[0039] Match the symmetry influence factor corresponding to the waveform symmetry in the preset waveform deviation database, and compare it with the preset reference influence factor;

[0040] When the symmetry influence factor is greater than the preset reference influence factor, perform waveform correction with the preset interference adjustment strategy.

[0041] Optionally, the preset interference adjustment strategy includes:

[0042] Perform numerical calculation based on the symmetry influence factor and the preset reference influence factor to determine the symmetry influence factor difference;

[0043] Match the resistance value feedback adjustment parameter corresponding to the symmetry influence factor difference in the preset dynamic fine-tuning database;

[0044] Adjust the multi-stage adjustable resistor based on the resistance value feedback adjustment parameter and collect the feedback waveform for waveform symmetry analysis. When the symmetry influence factor of the waveform symmetry is less than the preset reference influence factor, generate an adjustment end instruction.

[0045] Optionally, it further includes:

[0046] First, sequentially adjust the multi-stage adjustable resistor with the preset resistance value test parameters to determine the resistance adjustment state of the multi-stage adjustable resistor;

[0047] When the resistance adjustment state is inconsistent with the preset effective adjustment state, screen the ineffective adjustment resistors to determine the effective adjustment resistors;

[0048] Perform resistance value adjustment analysis based on the effective adjustment resistors to determine the adjustable mirror resistance value range.

[0049] In a second aspect, the present application provides an electric energy meter signal processing circuit based on a differential resistance voltage dividing network, adopting the following technical solution:

[0050] An electric energy meter signal processing circuit based on a differential resistance voltage dividing network, comprising:

[0051] A positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. A first positive resistor is formed between the positive input terminal and the positive output terminal, a first negative resistor is formed between the negative input terminal and the negative output terminal, a second positive resistor is disposed between the positive output terminal and the ground terminal, and a second negative resistor is disposed between the negative output terminal and the ground terminal. The resistance values of the first negative resistor and the first positive resistor are the same, and the resistance values of the second negative resistor and the second positive resistor are the same;

[0052] The first negative resistor is a multi-stage adjustable resistor, and the second negative resistor is an adjustable resistor

[0053] In summary, the present application includes at least one of the following beneficial technical effects:

[0054] 1. By analyzing and simulating the voltage signal at the positive output terminal to determine the mirror resistor required to balance the negative terminal voltage, and then adjusting the multi-stage adjustable resistor pre-connected to the negative terminal according to the mirror resistor, so that the positive terminal and the negative terminal maintain the same resistance value, which helps to stabilize the voltage signal of the differential network. When the differential voltage divider network detects the access circuit, stable test data can be obtained;

[0055] 2. By establishing a current mirror in the differential voltage divider network and calculating the mirror resistance value according to the differential mode gain of the current mirror, the consistency of the resistance value used when adjusting the resistance value at the negative input terminal and the positive input terminal is further improved, which helps to reduce the signal fluctuation amplitude between the positive input terminal and the negative input terminal of the voltage divider network.

[0056] 3. Before adjusting the mirror resistance value of the multi-stage adjustable resistor, a resistance adjustment test is pre-performed, so as to screen out the resistor that causes adjustment failure, and adjust the mirror resistance value of the adjustable resistor with effective adjustment, thereby improving the accuracy of adjusting the mirror resistance value of the resistor with adjustment failure. Description of the Drawings

[0057] Figure 1 is the flowchart of the method of steps S1 to S4 in the present application.

[0058] Figure 2 is the flowchart of the method of steps S201 to S202 in the present application.

[0059] Figure 3 is the flowchart of the method of steps S203 to S206 in the present application.

[0060] Figure 4 is the flowchart of the method of steps S2051 to S2054 in the present application.

[0061] Figure 5 is the flowchart of the method of steps S401 to S403 in the present application.

[0062] Figure 6 It is the flowchart of the method from step S4031 to S4033 in this application.

[0063] Figure 7 It is the flowchart of the method from step S500 to S502 in this application.

[0064] Figure 8 It is the simplified equivalent circuit diagram of the watt-hour meter signal processing circuit of the differential resistance voltage dividing network in this application.

[0065] Figure 9 It is the broken line graph of the sampling value fluctuation ratio of the differential network sampling and the single-ended network sampling in this application.

[0066] Figure 10 It is the data fluctuation graph of the first sampling channel after the mirror resistance of the differential network is adjusted in this application.

[0067] Figure 11 It is the data fluctuation graph of the second sampling channel after the mirror resistance of the differential network is adjusted in this application. Detailed implementation manners

[0068] In order to make the purpose, technical solutions and advantages of this application clearer, the following further details this application in conjunction with the appended Figures 1-11 drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0069] The following further describes the embodiments of the present invention in detail in conjunction with the drawings of the specification.

[0070] The embodiment of this application discloses a watt-hour meter signal processing system based on a differential resistance voltage dividing network, analyzes the voltage signal at the positive input end of the differential voltage dividing network, and analyzes the corresponding resistance value at the positive input end. After forming a mirror resistance value according to the resistance value at the positive input end, the multi-stage adjustable resistance at the negative input end is adjusted, so that the negative input end and the positive input end can have resistors with the same resistance value. Since its positive and negative ends are completely symmetrical, the interference signals introduced on the transmission cable are attenuated by the same amplitude, and interference signals with the same amplitude are retained in the sampling signal. After entering the differential voltage dividing network, their amplitudes cancel each other out, which helps to improve the accuracy and stability of the measurement.

[0071] Refer to Figure 1 , the method flow of the watt-hour meter signal processing system based on the differential resistance voltage dividing network includes the following steps:

[0072] Step S1: The positive terminal signal analysis module collects and analyzes the voltage output signal at the positive input end of the differential voltage dividing network to determine the signal waveform deviation value;

[0073] The differential voltage divider network consists of a positive input terminal, a negative input terminal, a positive output terminal, a negative output terminal, and voltage-dividing resistors. The voltage signal is transmitted from the outside to the positive and negative input terminals, and then is divided by the voltage-dividing resistors, and finally the voltage signal is output from the positive and negative output terminals respectively.

[0074] By analyzing the amplitude and phase of the voltage input signal continuously input to the positive input terminal, generating a waveform diagram of the input signal, and analyzing the phase difference of the waveform deviation between the waveform diagram and the sine alternating current image, this difference is defined as the signal waveform deviation value for subsequent further analysis.

[0075] Step S2: The waveform deviation analysis module analyzes the signal waveform deviation value through a preset mirror resistance value analysis strategy to determine the mirror resistance value of the positive input terminal of the voltage divider network.

[0076] The mirror resistance value analysis strategy is a strategy for obtaining the mirror resistance value by calculating and analyzing the input voltage signal of the positive input terminal in the differential voltage divider network. The specific strategy will be further described in the subsequent steps. The purpose of obtaining the mirror resistance value is to facilitate subsequent resistance value adjustment of the negative input terminal so that the input and output signals in the two parallel input lines of the differential voltage divider network are symmetric.

[0077] Step S3: The negative terminal resistance adjustment module extracts the corresponding negative terminal resistance adjustment instruction from the preset adjustable resistance value database according to the mirror resistance value.

[0078] Step S4: Control the resistance value of the negative terminal adjustable resistor in the differential voltage divider network through the negative terminal resistance adjustment instruction.

[0079] The multi-stage adjustable resistor is an adjustable resistor pre-arranged in the differential voltage divider network, and there are multiple adjustable resistors, and the multiple adjustable resistors form a voltage-dividing connection. When calculating, divide the mirror resistance value by the resistance value adjustment upper limit of the multiple adjustable resistors, take the obtained resistance value as the adjustment sub-parameter of the corresponding adjustable resistor, record the multiple adjustment sub-parameters to form a resistance value distribution parameter, and send out a burden resistance adjustment instruction prompt signal to prompt the multi-stage adjustable resistor to adjust the resistance value.

[0080] Step S4: Based on the negative terminal resistance adjustment instruction, adjust the resistance value of the multi-stage adjustable resistor according to the resistance value distribution parameter to form a negative terminal mirror resistance that stabilizes the waveform of the differential voltage divider network.

[0081] After receiving the negative terminal resistance adjustment instruction, make corresponding adjustments according to the resistance value distribution parameter, so that symmetric mirror resistance values are formed in the corresponding lines of the positive input terminal and the negative input terminal, so that when the external power supply signal passes through the two lines, it has the same current and voltage signals, forming a relatively stable signal data channel.

[0082] Reference Figure 2 , the mirror resistance analysis strategy includes:

[0083] Step S201: Obtain the signal deviation value between the positive terminal input electrical signal and the positive terminal output electrical signal, and substitute the signal deviation value into a preset deviation analysis model for analysis to determine the waveform deviation characteristics;

[0084] Step S202: Calculate the waveform deviation value based on the waveform deviation characteristics, and construct a difference gain model according to the waveform deviation value. The expression of the difference gain model is , where represents the deviation gain value, represents the characteristic value of the waveform deviation characteristics, which is generated by data comparison through a preset database, represents the deviation amplitude corresponding to the waveform deviation characteristics;

[0085] Step S203: Calculate the mirror resistance according to the deviation gain value and a pre-constructed current mirror. The following formula is used during the calculation:

[0086] ,

[0087] ,

[0088] ,

[0089] where, where, represents the output voltage, represents the differential mode gain value, represents the voltage at the positive input terminal, represents the voltage at the negative input terminal, represents the drain current of the constructed metal oxide semiconductor field effect transistor, represents the gate-source voltage of the metal oxide semiconductor field effect transistor, represents the threshold voltage of the metal oxide semiconductor field effect transistor, represents the channel width-to-length ratio of the metal oxide semiconductor field effect transistor, represents the mobility of carriers in the channel, represents the gate oxide capacitance per unit area, represents the mirror resistance, represents the power supply voltage of the metal oxide semiconductor field effect transistor.

[0090] Reference Figure 3 , when determining the mirror resistance at the positive input terminal of the voltage divider network, it also includes:

[0091] Step S203: Simulate the resistance input at the negative input terminal of the differential voltage divider network to determine the simulated input voltage signal;

[0092] By pre - establishing a data calculation simulation network model, a mapping relationship is formed between the voltage signal and the resistance value. When the resistance value changes, the output voltage signal changes accordingly. When different resistance values are input into the data calculation simulation network model, different voltage signals are output, and this voltage signal is defined as the analog input voltage signal.

[0093] Step S204: Analyze based on the analog input voltage signal and the voltage input signal at the positive input terminal of the differential voltage divider network to determine the input voltage difference corresponding to the voltage of the voltage signal.

[0094] By comparing and calculating the analog input voltage signal and the positive input terminal signal, the difference can be analyzed and obtained. When there is no interference in the differential voltage divider network, the input voltage signal and the output signal are equal.

[0095] Step S205: When the input voltage difference is not within the preset good difference range, calculate the resistance at the positive input terminal of the differential voltage divider network according to the preset difference comprehensive adjustment strategy to determine the corrected mirror resistance value.

[0096] The good difference range is a preset numerical range, indicating that the input voltage difference is small and within a reasonable fluctuation range. When the input voltage difference is not within the good difference range, it indicates that the voltage difference is large. At this time, further calculation is performed to correct the mirror resistance value so that after the adjustable resistance at the negative end is adjusted, the resistance values of the lines where the positive input terminal and the negative input terminal are located can be kept consistent. The difference comprehensive adjustment strategy represents the method steps for adjusting the resistance value, which will be further elaborated in the subsequent steps.

[0097] Step S206: Replace the mirror resistance value according to the corrected mirror resistance value.

[0098] Replace and update the corrected mirror resistance value so that corresponding correction is made before the negative input terminal adjusts the multi - stage adjustable resistance, which helps to improve the adjustment accuracy.

[0099] Refer to Figure 4 , when performing step S205: calculating the resistance at the positive input terminal of the differential voltage divider network according to the preset difference comprehensive adjustment strategy includes:

[0100] Step S2051: Calculate based on the differential mode gain and the analysis formula of the output voltage and input differential voltage of the preset differential voltage network to determine the theoretical common - mode voltage. The analysis formula of the output voltage and input differential voltage of the differential voltage network is as follows:

[0101] ,

[0102] ,

[0103] ,

[0104] ;

[0105] Among them, represents the common-mode voltage of the differential circuit, and the value of the common-mode voltage can be determined by measuring the differential circuit. represents the differential-mode gain. represents the negative-terminal input voltage, which can be obtained by detection. represents the positive-terminal input voltage. and respectively represent the detected negative-terminal input current and positive-terminal input current. and respectively represent the simulated negative-terminal resistance and positive-terminal resistance. represents the voltage influence coefficient of the circuit elements in the differential circuit.

[0106] When performing step S205: determining the corrected mirror resistance value, it further includes:

[0107] Step S2052: Input a preset fluctuation signal into the differential resistor voltage-dividing network and collect and analyze the positive-terminal output signal and the negative-terminal output signal to determine the positive-terminal output waveform and the negative-terminal output model;

[0108] Step S2053: Perform simulation based on the positive-terminal output signal and the negative-terminal output signal to determine the positive-terminal simulated output waveform and the negative-terminal simulated output waveform;

[0109] Step S2054: Calculate and analyze the positive-terminal deviation waveform of the positive-terminal output waveform and the positive-terminal simulated output waveform, and the negative-terminal deviation waveform of the negative-terminal output waveform and the negative-terminal simulated waveform;

[0110] Step S2055: Analyze based on the positive-terminal deviation waveform and the negative-terminal deviation waveform to determine the output waveform deviation, and match the preset resistance value adjustment database to output the resistance value optimization coefficient corresponding to the output waveform deviation;

[0111] Step S2056: Generate a resistance value optimization adjustment instruction based on the resistance value optimization coefficient.

[0112] Step S2052: Perform waveform simulation based on the voltage input signal at the positive input terminal and the simulated input voltage signal to determine the negative-terminal simulated waveform and the positive-terminal simulated waveform;

[0113] By simulating the waveforms of the analog input voltage signal and the voltage input signal at the positive input terminal, a waveform diagram corresponding to the voltage signal can be generated. At this time, the purpose of generating the waveform diagram is to further analyze whether the sine waveform of the waveform diagram is standard, so as to further analyze the signal stability effect of the mirror resistance on the differential network circuit after adjustment.

[0114] Step S2053: Identify the deviation waveform characteristics based on the negative-terminal analog waveform and the positive-terminal analog waveform to determine the negative-peak amplitude of the negative-terminal analog waveform and the positive-peak amplitude of the positive-terminal analog waveform.

[0115] By identifying and comparing the waveform characteristics of the waveform diagram, the peaks and valleys of the negative-terminal analog waveform and the positive-terminal analog waveform can be obtained, and the peaks of the analog waveforms are analyzed. The peak value of the negative-terminal analog waveform is defined as the negative-peak amplitude, and the peak value of the positive-terminal analog waveform is defined as the positive-peak amplitude.

[0116] Step S2054: Calculate based on the negative-peak amplitude and the positive-peak amplitude to determine the peak difference, and match the resistance optimization coefficient corresponding to the peak difference in the preset resistance value adjustment database.

[0117] By calculating the difference between the negative-peak amplitude and the positive-peak amplitude, the calculated value is defined as the peak difference. The peak difference in the resistance value adjustment database is a pre-established database for looking up the resistance optimization coefficient, which stores different peak differences and the corresponding resistance optimization coefficients with a mapping relationship. When the corresponding peak difference is input, the mapped resistance optimization coefficient is automatically searched and output. Among them, the resistance optimization coefficient represents the coefficient value for optimizing the mirror resistance to reduce the peak difference. By looking up the corresponding resistance optimization coefficient.

[0118] Step S2055: Issue a mirror resistance optimization instruction based on the resistance optimization coefficient.

[0119] Issue a mirror resistance optimization instruction according to the found optimization coefficient to optimize the adjustment of the mirror resistance, so that the mirror resistance is closer to the line resistance at the positive input terminal, thereby eliminating the influence of inconsistent resistance values on the signal in the differential network.

[0120] Refer to Figure 5 , when forming the negative-terminal mirror resistance of the stable differential voltage divider network waveform, it also includes:

[0121] Step S401: Analyze the negative-terminal analog waveform and the positive-terminal analog waveform to determine the waveform symmetry.

[0122] By analyzing the symmetry of the waveform diagrams of the negative-terminal analog waveform and the positive-terminal analog waveform, the symmetry of the waveform can be obtained, which is convenient for further analyzing whether there are large differences in amplitude and phase in the follow-up.

[0123] Step S402: Match the symmetry impact factor corresponding to the waveform symmetry in the preset waveform deviation database, and compare it with the preset reference impact factor;

[0124] The waveform deviation database is pre-established by the staff, and stores different deviation values and the corresponding symmetry impact factors with mapping relationships. The symmetry impact factor represents the weight value of the data detection impact on the differential network circuit when the waveform is asymmetric. The reference impact factor represents the upper limit weight value when the waveform asymmetry affects the differential network circuit to be less than the requirement. When the symmetry impact factor is less than the reference impact factor, it indicates that the generated waveform deviation is small and will not cause signal transmission impact. Otherwise, it indicates that the signal transmission is affected.

[0125] Step S403: When the symmetry impact factor is greater than the preset reference impact factor, perform waveform correction with the preset interference adjustment strategy.

[0126] By performing interference adjustment on the waveform, the impact on the signal transmission stability in the differential network is reduced. The interference adjustment strategy is a method step of feedback adjustment of the resistance value, and the specific strategy will be further elaborated in the subsequent steps.

[0127] Refer to Figure 6 , the preset interference adjustment strategy includes:

[0128] Step S4031: Perform numerical calculation based on the symmetry impact factor and the preset reference impact factor to determine the symmetry impact factor difference;

[0129] By calculating the symmetry impact factor difference, it can be known the value of the symmetry impact factor that needs to be adjusted when the symmetry impact factor of the signal waveform is restored to symmetry.

[0130] Step S4032: Match the resistance value feedback adjustment parameter corresponding to the symmetry impact factor difference in the preset dynamic fine-tuning database;

[0131] The resistance value feedback adjustment parameter represents the adjustment value and the up and down adjustment directions when fine-tuning the mirror resistance value. By adjusting the resistance value up and down according to the adjustment value, the waveform change of the output signal can be obtained. The dynamic fine-tuning database is pre-established by the staff, and stores different resistance value feedback adjustment parameters, and stores the symmetry impact factor differences corresponding to the resistance value feedback adjustment parameters. When the symmetry impact factor difference is input, the corresponding resistance value feedback adjustment parameter is matched and found.

[0132] Step S4033: Adjust the multi-stage adjustable resistor based on the resistance value feedback adjustment parameter and collect the feedback waveform for waveform symmetry analysis. When the symmetry impact factor of the waveform symmetry is less than the preset reference impact factor, generate an adjustment end instruction.

[0133] After finding the corresponding resistance feedback adjustment parameter, the resistance of the multi-stage adjustable resistor is adjusted, and the symmetry of the signal waveform of the output signal after adjustment is analyzed again. Then, by comparing and analyzing the symmetry influence factor and the reference influence factor, it can be known whether the signal waveform is in a symmetric state at this time, so as to reflect that the output signal is not interfered by other factors, and an adjustment end instruction is generated to indicate the stop of feedback adjustment.

[0134] In addition, it also includes:

[0135] Step S500: First, sequentially adjust the multi-stage adjustable resistor with a preset resistance test parameter to determine the resistance adjustment state of the multi-stage adjustable resistor;

[0136] The resistance test parameter is the resistance adjustment parameter for testing the multi-stage adjustable resistor. After adjustment, it can be determined whether the resistance can be adjusted according to the output signal. By analyzing the amplitude and phase of the output signal, it can be known whether an effective adjustment is generated for a single corresponding resistor in the multi-stage adjustable resistor, and thus this adjustment behavior is defined as the resistance adjustment state, including an effective adjustment state and an ineffective adjustment state.

[0137] Step S501: When the resistance adjustment state is inconsistent with the preset effective adjustment state, screen the ineffective adjustment resistors to determine the effective adjustment resistors;

[0138] When the resistance adjustment state is inconsistent with the set effective adjustment state, it means that when the corresponding adjustable resistor is tested for resistance adjustment, it cannot respond to the resistance adjustment. Then, screen multiple adjustable resistors, and mark the adjustable resistors with the same resistance adjustment state and effective adjustment state as effective adjustment resistors for subsequent further adjustment.

[0139] Step S502: Based on the effective adjustment resistors, perform resistance adjustment analysis to determine the adjustable mirror resistance range.

[0140] By calculating and summing the resistance adjustment ranges of the effective adjustment resistors, the total resistance adjustment range can be known, so that when performing mirror resistance adjustment, the maximum resistance adjustment range can be analyzed, and thus ineffective adjustment is not easily generated.

[0141] Refer to Figure 8 , based on the same inventive concept, an embodiment of the present invention provides an electric energy meter signal processing circuit for a differential resistance voltage dividing network, including:

[0142] A positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. A first positive resistor is formed between the positive input terminal and the positive output terminal, and a first negative resistor is formed between the negative input terminal and the negative output terminal. A second positive resistor is provided between the positive output terminal and the ground terminal, and a second negative resistor is provided between the negative output terminal and the ground terminal. The resistance values of the first negative resistor and the first positive resistor are the same, and the resistance values of the second negative resistor and the second positive resistor are the same. The first negative resistor is a multi-stage adjustable resistor, and the second negative resistor is an adjustable resistor.

[0143] It should be noted that the first positive resistor includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9 connected in sequence. The first negative resistor includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a fourteenth resistor R14. The second positive resistor is an adjustable resistor R10, and the second negative resistor is an adjustable resistor R15. V+ represents the positive input terminal, Vs+ represents the positive output terminal, V- represents the negative input terminal, and Vs- represents the negative output terminal.

[0144] Among them, referring to Figure 9 and Figure 10 , when using the power meter signal processing circuit of the differential resistor voltage division network for differential sampling, the fluctuation of the sampling signal is smaller than that of the single-ended sampling. When the corresponding resistance values of the differential voltage division network are adjusted, among multiple sampling channels, the sampling fluctuations during data stability detection are as Figure 10 shown. The sampling fluctuations within half an hour can all remain in a relatively stable state and are not likely to generate large fluctuations.

[0145] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above-mentioned division of each functional module is used as an example. In actual applications, the above-mentioned functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the specific working processes of the above-described system, device, and unit, reference can be made to the corresponding processes in the foregoing method embodiments, and details are not described herein again.

[0146] An embodiment of the present invention provides a computer-readable storage medium storing a computer program that can be loaded and executed by a processor for a power meter signal processing system based on a differential resistor voltage division network.

[0147] Computer storage media include, for example: USB flash drives, external hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs, and other various media that can store program codes.

[0148] Based on the same inventive concept, an embodiment of the present invention provides an intelligent terminal, including a memory and a processor. A computer program capable of being loaded and executed by the processor for a watt-hour meter signal processing system based on a differential resistor voltage dividing network is stored on the memory.

[0149] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above division of each functional module is used as an example. In actual applications, the above functions can be assigned to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working processes of the above-described system, device, and unit can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0150] The above are all preferred embodiments of the present application. The protection scope of the present application is not limited thereby. Any feature disclosed in this specification (including the abstract and drawings), unless specifically described, can be replaced by other equivalent or similar-purpose alternative features. That is, unless specifically described, each feature is only an example in a series of equivalent or similar features.

Claims

1. An electric energy meter signal processing system based on a differential resistor voltage division network, characterized in that, Including: A positive terminal signal analysis module that collects and analyzes the voltage output signal of the positive input terminal of the differential voltage divider network to determine the signal waveform deviation value; A waveform deviation analysis module that analyzes the signal waveform deviation value through a preset mirror resistance analysis strategy to determine the mirror resistance of the positive input terminal of the voltage divider network; The mirror resistance analysis strategy includes: Obtaining the signal deviation value between the positive terminal input electrical signal and the positive terminal output electrical signal, and bringing the signal deviation value into a preset deviation analysis model for analysis to determine the waveform deviation characteristics; Calculate the waveform deviation value according to the waveform deviation characteristics, and construct a difference gain model based on the waveform deviation value. The expression of the difference gain model is , where represents the deviation gain value, represents the characteristic value of the waveform deviation characteristic, which is generated by comparing data through a preset database, represents the deviation amplitude corresponding to the waveform deviation characteristic; Calculating the mirror resistance according to the deviation gain value and a pre-constructed current mirror. The following formula is used during the calculation: ， , ， Among them, among them, represents the output voltage, represents the differential mode gain value, represents the voltage of the positive input terminal, represents the voltage of the negative input terminal, represents the drain current of the metal oxide semiconductor field effect transistor, represents the gate-source voltage of the metal oxide semiconductor field effect transistor, represents the threshold voltage of the metal oxide semiconductor field effect transistor, represents the channel width-to-length ratio of the metal oxide semiconductor field effect transistor, represents the mobility of carriers in the channel, represents the gate oxide capacitance per unit area, represents the mirror resistance value, represents the power supply voltage of the metal oxide semiconductor field effect transistor; A negative terminal resistance adjustment module that extracts the corresponding negative terminal resistance adjustment instruction from a preset adjustable resistance database according to the mirror resistance; Controlling the resistance value of the negative terminal adjustable resistor in the differential voltage divider network through the negative terminal resistance adjustment instruction.

2. The signal processing system of an electric energy meter based on a differential resistor voltage dividing network according to claim 1, wherein When determining the mirror resistance of the positive input terminal of the voltage divider network, it also includes: Simulating the resistance value input of the negative input terminal of the differential voltage divider network to determine the simulated input voltage signal; Analyzing based on the simulated input voltage signal and the voltage input signal of the positive input terminal of the differential voltage divider network to determine the input voltage difference corresponding to the voltage of the voltage signal; When the input voltage difference is not within the preset good difference range, calculating the resistance of the positive input terminal of the differential voltage divider network according to a preset difference comprehensive adjustment strategy to determine the corrected mirror resistance.

3. A watt-hour meter signal processing system based on a differential resistor voltage dividing network according to claim 2, wherein, When calculating the resistance of the positive input terminal of the differential voltage divider network according to the preset difference comprehensive adjustment strategy, it includes: Calculating based on the differential mode gain and the analysis formula of the output voltage and input differential voltage of the preset differential voltage network to determine the theoretical common mode voltage. The analysis formula of the output voltage and input differential voltage of the differential voltage network is as follows: ， ， ， ； Among them, represents the common-mode voltage of the differential circuit, represents the differential-mode gain, represents the negative-terminal input voltage, represents the positive-terminal input voltage, and respectively represent the detected negative-terminal input current and positive-terminal input current, and respectively represent the analog negative-terminal resistance and positive-terminal resistance, represents the voltage influence coefficient of the circuit elements in the differential circuit, represents the change in the negative-terminal output voltage of the differential circuit, represents the theoretical common-mode voltage of the differential circuit.

4. A watt-hour meter signal processing system based on a differential resistance voltage dividing network according to claim 2, characterized in that, When determining the corrected mirror resistance, it also includes: Inputting a preset fluctuation signal into the differential resistor voltage divider network and collecting and analyzing the positive terminal output signal and the negative terminal output signal to determine the positive terminal output waveform and the negative terminal output model; Simulating based on the positive terminal output signal and the negative terminal output signal to determine the positive terminal simulated output waveform and the negative terminal simulated output waveform; Calculating and analyzing the positive terminal deviation waveform between the positive terminal output waveform and the positive terminal simulated output waveform, and the negative terminal deviation waveform between the negative terminal output waveform and the negative terminal simulated waveform; Analyzing based on the positive terminal deviation waveform and the negative terminal deviation waveform to determine the output waveform deviation, and matching the resistance value optimization coefficient corresponding to the output waveform deviation in the preset resistance value adjustment database; Generating a resistance value optimization adjustment instruction based on the resistance value optimization coefficient.

5. The signal processing system of an electric energy meter based on a differential resistor voltage dividing network according to claim 4, wherein, When controlling the resistance value of the negative terminal adjustable resistor in the differential voltage divider network, it also includes: Analyzing the negative terminal simulated waveform and the positive terminal simulated waveform to determine the waveform symmetry; Matching the symmetry influence factor corresponding to the waveform symmetry in the preset waveform deviation database, and comparing it with the preset reference influence factor; When the symmetry influence factor is greater than the preset reference influence factor, performing waveform correction with a preset interference adjustment strategy.

6. The signal processing system for an electric energy meter based on a differential resistor voltage division network according to claim 5, wherein The preset interference adjustment strategy includes: Performing numerical calculation according to the symmetry influence factor and the preset reference influence factor to determine the symmetry influence factor difference; Match the resistance feedback adjustment parameter corresponding to the difference in the symmetry influence factor in the preset dynamic fine-tuning database; Adjust the multi-stage adjustable resistor based on the resistance feedback adjustment parameter and collect the feedback waveform for waveform symmetry analysis. When the symmetry influence factor of the waveform symmetry is less than the preset reference influence factor, generate an adjustment end instruction.

7. A watt-hour meter signal processing system based on a differential resistance voltage dividing network according to claim 1 or 6, characterized in that, It also includes: First, sequentially adjust the multi-stage adjustable resistor with the preset resistance test parameters to determine the resistance adjustment state of the multi-stage adjustable resistor; When the resistance adjustment state is inconsistent with the preset effective adjustment state, screen the ineffective adjustment resistors to determine the effective adjustment resistors; Conduct resistance value adjustment analysis based on the effective adjustment resistors to determine the adjustable mirror resistance value range.

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