Display panel and electronic device having input sensing function

Abstract

The invention discloses a display panel with an input sensing function and an electronic device. The display panel includes: a scan line; light emitting pixels electrically connected to the scan lines and arranged in a first row; a light sensing pixel arranged in a first row, in which the light sensing pixel includes: a light sensor including a first electrode and a second electrode connected to a first node; a first transistor including a first electrode, a second electrode connected to the first node, and a gate electrode; a second transistor including a first electrode, a second electrode, and a gate electrode connected to the first node; and a third transistor including a first electrode connected to the second electrode of the second transistor, a second electrode connected to the sensing line, and a gate electrode, in which the light emitting pixel and the gate electrode of the third transistor are commonly electrically connected to the scan line.

Description

[0001] This application is a divisional application of invention patent application No. 202011330361.4, filed with the State Intellectual Property Office on November 24, 2020, with the invention name “Display panel and display device with input sensing function”. Technical Field

[0002] Exemplary embodiments of the present invention relate to a display device, and more particularly, to a display panel capable of sensing an external input and an electronic device including the display panel. Background Art

[0003] A display device is an output device for presenting information in a visual form. Example devices having a display device for displaying images are multimedia display devices such as televisions, mobile phones, tablet computers, navigation devices, and game consoles. In addition to general inputs such as buttons, keyboards, or mice, a display device may also include a touch screen for input. A touch screen is an input sensing panel that can provide a touch-based input method that allows a user to easily input information or commands in an intuitive and convenient manner.

[0004] Recently, fingerprints, which are one example of biometric information, have been proposed as a means of user authentication for online banking, product purchases, security, etc. Therefore, there is an increasing demand for touch screen display devices having a fingerprint recognition function. Summary of the invention

[0005] An exemplary embodiment of the present invention provides a display panel, which includes: a plurality of light-emitting pixels that emit light in response to a first scan signal, a second scan signal, and a light-emitting control signal; and a plurality of light-sensing pixels that output a sensing signal corresponding to external light in response to the first scan signal and the second scan signal, wherein each of the plurality of light-emitting pixels includes an organic light-emitting diode, the organic light-emitting diode includes an anode and a cathode, the cathode receives a first driving voltage, and each of the plurality of light-sensing pixels includes an organic photodiode, the organic photodiode includes a first electrode and a second electrode, and wherein the second electrode of the organic photodiode is electrically connected to the cathode of the organic light-emitting diode to receive the first driving voltage.

[0006] In an exemplary embodiment of the present invention, each of the plurality of light sensing pixels may further include: a first transistor including a first electrode configured to receive a second scanning signal, a second electrode connected to a charge storage node, and a gate electrode configured to receive the first scanning signal; a second transistor including a first electrode receiving a second driving voltage, a second electrode, and a gate electrode connected to the charge storage node; and a third transistor including a first electrode connected to the second electrode of the second transistor, a second electrode connected to a fingerprint sensing line, and a gate electrode configured to receive the second scanning signal.

[0007] In an exemplary embodiment of the present invention, the first electrode of the organic photodiode may be electrically connected to the charge storage node.

[0008] In an exemplary embodiment of the present invention, when the first scan signal turns on the first transistor, the second scan signal may have a voltage level higher than that of the first scan signal.

[0009] In an exemplary embodiment of the present invention, when the light emitting control signal is at an effective level, each of the plurality of light emitting pixels may emit light, and each of the plurality of light sensing pixels may store charges corresponding to external light in a charge storage node, output a fingerprint sensing signal corresponding to the charges stored in the charge storage node to the fingerprint sensing line when the second scanning signal is at an effective level, and reset the charge storage node when the first scanning signal is at an effective level.

[0010] In an exemplary embodiment of the present invention, each of the plurality of light-emitting pixels may further include: a first transistor including a first electrode receiving a data signal, a second electrode, and a gate electrode configured to receive a first scanning signal; a second transistor including a gate electrode configured to receive a light-emitting control signal; and a third transistor connected to the first transistor and the second transistor and configured to provide a driving current to the organic light-emitting diode.

[0011] In an exemplary embodiment of the present invention, each of the plurality of light emitting pixels may further include a fourth transistor including a gate electrode configured to receive the second scan signal and transmit the initialization voltage to the gate electrode of the third transistor.

[0012] In an exemplary embodiment of the present invention, each of the plurality of light emitting pixels may further include a fifth transistor connected between the third transistor and an anode of the organic light emitting diode and including a gate electrode configured to receive a light emitting control signal.

[0013] In an exemplary embodiment of the present invention, the plurality of light-emitting pixels may include a first color light-emitting pixel, a second color light-emitting pixel, and a third color light-emitting pixel.

[0014] In an exemplary embodiment of the present invention, the first color light-emitting pixel, at least one of the multiple light-sensing pixels, the second color light-emitting pixel, and at least one of the multiple light-sensing pixels can be sequentially arranged in a first row in a second direction intersecting the first direction, and at least one of the multiple light-sensing pixels and the third color light-emitting pixel can be sequentially arranged in a second row adjacent to the first row in the second direction.

[0015] An exemplary embodiment of the present invention provides a display device, which includes: a display panel, including a plurality of light-emitting pixels and a plurality of light-sensing pixels; and a fingerprint reading circuit, which controls the display panel and receives fingerprint sensing signals from the plurality of light-sensing pixels through a fingerprint sensing line, wherein each of the plurality of light-emitting pixels includes an organic light-emitting diode, the organic light-emitting diode includes an anode and a cathode, the cathode is connected to a first driving voltage line, and each of the plurality of light-sensing pixels includes an organic photodiode, the organic photodiode includes a first electrode and a second electrode, and wherein the second electrode of the organic photodiode is connected to the first driving voltage line.

[0016] In an exemplary embodiment of the present invention, each of the plurality of light-sensing pixels may further include: a reset transistor including a gate electrode configured to receive a first scanning signal, a first electrode configured to receive a second scanning signal, and a second electrode connected to a charge storage node; an amplifying transistor including a gate electrode connected to the charge storage node, a first electrode configured to receive a second driving voltage, and a second electrode; and an output transistor including a gate electrode configured to receive a second scanning signal, a first electrode connected to the second electrode of the amplifying transistor, and a second electrode connected to a fingerprint sensing line.

[0017] In an exemplary embodiment of the present invention, the first electrode of the organic photodiode may be electrically connected to the charge storage node.

[0018] In an exemplary embodiment of the present invention, when the first scan signal is at an active level, the second scan signal may have a voltage level higher than that of the first scan signal.

[0019] In an exemplary embodiment of the present invention, each of the plurality of light-emitting pixels may emit light in response to a first scan signal, a second scan signal, and a light-emitting control signal, and each of the plurality of light-sensing pixels may store charges corresponding to external light in a charge storage node, output a fingerprint sensing signal corresponding to the charges stored in the charge storage node to a fingerprint sensing line when the second scan signal is at an effective level, and reset the charge storage node when the first scan signal is at an effective level.

[0020] In an exemplary embodiment of the present invention, the display panel may further include a scan driver configured to output a first scan signal, a second scan signal, and a light emitting control signal.

[0021] An exemplary embodiment of the present invention provides a display device, which includes: a substrate layer; a light-emitting electronic device, which is arranged on the substrate layer; a light-sensing electronic device, which is arranged on the substrate layer; an organic light-emitting diode, which includes an anode electrically connected to the light-emitting electronic device, a cathode, and a light-emitting layer arranged between the anode and the cathode; and an organic photodiode, which includes a first electrode electrically connected to the light-sensing electronic device, a second electrode, and a photoelectric conversion layer arranged between the first electrode and the second electrode, wherein the second electrode of the organic photodiode and the cathode of the organic light-emitting diode are included in the same layer.

[0022] In an exemplary embodiment of the present invention, the base layer may include a display area and a non-display area adjacent to the display area, and the organic light emitting diode and the organic photodiode are disposed over the base layer in the display area.

[0023] In an exemplary embodiment of the present invention, at least one of the light-emitting electronic devices is configured to control the light emission of the organic light-emitting diode in response to a first scan signal, a second scan signal and a light-emitting control signal, and at least one of the light-sensing electronic devices stores the charge generated by the organic photodiode in a charge storage node, outputs a fingerprint sensing signal to the fingerprint sensing line when the second scan signal is at an effective level, and resets the charge storage node when the first scan signal is at an effective level, wherein the fingerprint sensing signal corresponds to the charge stored in the charge storage node.

[0024] In an exemplary embodiment of the present invention, the at least one light sensing electronic device may include: a reset transistor, including a gate electrode configured to receive a first scanning signal, a first electrode configured to receive a second scanning signal, and a second electrode connected to a charge storage node; an amplifying transistor, including a gate electrode connected to the charge storage node, a first electrode configured to receive a second driving voltage, and a second electrode; and an output transistor, including a gate electrode configured to receive a second scanning signal, a first electrode connected to the second electrode of the amplifying transistor, and a second electrode connected to a fingerprint sensing line, wherein the first electrode of the organic photodiode is connected to the charge storage node. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which: Figure 1 is a perspective view of a display device according to an exemplary embodiment of the present invention; Figure 2is a cross-sectional view of a display device according to an exemplary embodiment of the present invention; Figure 3 is a cross-sectional view of a display panel according to an exemplary embodiment of the present invention; Figure 4 yes Figure 1 A block diagram of a display device shown in FIG. Figure 5 is a plan view of a display panel according to an exemplary embodiment of the present invention; Figure 6 is a plan view of a touch sensing unit according to an exemplary embodiment of the present invention; Figure 7 Shows Figure 5 The connection relationship between a plurality of light-emitting pixels, a plurality of light-sensing pixels and signal lines of the display panel shown in FIG. Figure 8 Shows Figure 7 A circuit configuration of a light-emitting pixel among a plurality of light-emitting pixels and a corresponding light-sensing pixel among a plurality of light-sensing pixels shown in FIG. Fig. 9 Is used to describe Figure 8 A timing diagram of the operation of the light emitting pixel and the light sensing pixel shown in FIG. Fig.10 is an enlarged plan view of a portion of a display panel of an exemplary embodiment of the present invention; Fig.11 is an enlarged plan view of a portion of a display panel of an exemplary embodiment of the present invention; Fig.12 is an enlarged plan view of a portion of a display panel of an exemplary embodiment of the present invention; and Fig.13 is an enlarged cross-sectional view of a display panel according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0026] Here, it will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer, or intervening elements or layers may be present.

[0027] Throughout the specification, the same reference numerals may refer to the same elements. In the drawings, the thickness of layers, films or regions may be exaggerated for clarity.

[0028] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0029] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 is a perspective view of a display device DD according to an exemplary embodiment of the present invention. Figure 2 is a cross-sectional view of a display device DD according to an exemplary embodiment of the present invention.

[0031] like Figure 1 As shown in , the display device DD can display an image IM on a display surface DD-IS. The display surface DD-IS is parallel to a plane defined by the first direction axis DR1 and the second direction axis DR2. The normal direction of the display surface DD-IS (in other words, the thickness direction of the display device DD) is indicated by the third direction axis DR3.

[0032] The front surface (or top surface) and the rear surface (or bottom surface) of each member or unit described below are distinguished by the third directional axis DR3. However, the first directional axis DR1 to the third directional axis DR3 shown in this embodiment are only examples. Hereinafter, the first direction to the third direction are directions indicated by the first directional axis DR1 to the third directional axis DR3, respectively, and refer to the same reference numerals.

[0033] The display device DD is shown as having a flat display surface in the exemplary embodiment of the present invention, but is not limited thereto. The display device DD may also include a curved display surface. The display device DD may also include a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas indicating different directions, and may also include, for example, a polygonal columnar display surface.

[0034] The display device DD according to an exemplary embodiment of the present invention may be a rigid display device. However, the display device DD according to another exemplary embodiment of the present invention is not limited thereto and may be a flexible display device. The flexible display device may include a foldable display device or a curved display device having a bendable area.

[0035] In an exemplary embodiment of the present invention, Figure 1 The display device DD applicable to a mobile phone is exemplarily shown. It will be understood that the electronic module, camera module, power module, etc. mounted on the main board can be set in a bracket / casing together with the display device DD to constitute a mobile phone. The display device DD according to the exemplary embodiment of the present invention can be applied to large electronic devices such as televisions and monitors and to small and medium-sized electronic devices such as tablet computers, car navigation devices, game consoles, and smart watches.

[0036] like Figure 1As shown in FIG. 1 , the display surface DD-IS includes an image area DD-DA in which the image IM is displayed and a frame area DD-NDA adjacent to the image area DD-DA. The frame area DD-NDA is an area in which no image is displayed. Figure 1 An icon image is shown in FIG. 4 as an example of the image IM.

[0037] like Figure 1 As shown in , the image area DD-DA may have a substantially quadrilateral shape. The “substantially quadrilateral shape” may include not only a quadrilateral shape in a mathematical sense but also a quadrilateral shape in which a curved boundary is defined in a vertex area (or corner area) instead of a vertex.

[0038] The frame area DD-NDA may surround the image area DD-DA. However, exemplary embodiments of the present invention are not limited thereto, and the image area DD-DA and the frame area DD-NDA may have different shapes. The frame area DD-NDA may be provided only on one side of the image area DD-DA. Depending on the combination form of the display device DD and other components of the corresponding electronic device, the frame area DD-NDA may not be exposed to the outside.

[0039] The display device DD according to an exemplary embodiment of the present invention can sense a user input TC applied from the outside. The user input TC may be any one or a combination of various types of external inputs such as a part of the user's body, light, heat, and pressure. Although the user input TC is shown in this embodiment as a touch input applied to the front surface of the display device DD by the user's hand, this is merely exemplary, and the user input TC may be one of the various types of external inputs as described above. In addition, the display device DD may sense the user input TC applied to the side surface or rear surface of the display device DD according to its structure, and is not limited thereto.

[0040] In addition, the display device DD according to an exemplary embodiment of the present invention may sense a fingerprint, which is an example of biometric information, as one of the types of user input TC applied from the outside.

[0041] Figure 2 1 shows a cross section of the display device DD in a plane defined by the first direction axis DR1 and the third direction axis DR3. Figure 2 , components of the display device DD are schematically shown to describe their stacking relationship.

[0042] A display device DD according to an exemplary embodiment of the present invention may include a display panel DP, an input sensor ISL, an anti-reflector RPP, and a window WP. At least some of the display panel DP, the input sensor ISL, the anti-reflector RPP, and the window WP may be formed in a continuous process, or at least some of the components thereof may be combined with each other by an adhesive member ADS. The adhesive member ADS may be an optically transparent adhesive member, such as a pressure-sensitive adhesive film (PSA), an optically transparent adhesive film (OCA), and an optically transparent resin (OCR). The adhesive member to be described below may include a typical adhesive or a detachable adhesive. In an exemplary embodiment of the present invention, the anti-reflector RPP and the window WP may be replaced or omitted by other components.

[0043] exist Figure 2 In the embodiment, the input sensor ISL is directly disposed on the display panel DP. As used herein, "component B is directly disposed on component A" may mean that no separate adhesive layer / adhesive member is disposed between component A and component B. After component A has been formed, component B is formed on the substrate surface provided by component A through a continuous process.

[0044] In this exemplary embodiment, the anti-reflector RPP and the window WP are of a "panel" type, and the input sensor ISL is of a "layer" type. The "panel" type may include a base layer providing a base surface, such as a synthetic resin film, a composite film, and a glass substrate, but the base layer may be omitted in the "layer" type. In other words, a "layer" type component may be disposed on a base surface provided by another component. In an exemplary embodiment of the present invention, the anti-reflector RPP and the window WP may also be of a "layer" type. In an exemplary embodiment of the present invention, the input sensor ISL may be of a "panel" type. The "panel" type input sensor ISL may be manufactured in a separate process, and may then be directly disposed on the display panel DP or bonded to the display panel DP with an adhesive layer between the input sensor ISL and the display panel DP.

[0045] The display panel DP generates an image, and the input sensor ISL obtains coordinate information of an external input (e.g., a touch event). The display device DD according to an exemplary embodiment of the present invention may further include a protective member disposed on the bottom surface of the display panel DP. The protective member and the display panel DP may be combined by an adhesive member.

[0046] The display device DD according to an exemplary embodiment of the present invention includes the input sensor ISL disposed on the top surface of the display panel DP, but the invention is not limited thereto. In another exemplary embodiment of the present invention, the display device DD may not include the input sensor ISL.

[0047] The display panel DP according to an exemplary embodiment of the present invention may be a light-emitting display panel, but is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The above panels are classified according to the constituent materials of the light-emitting elements. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. In the following, the display panel DP is described as an organic light-emitting display panel.

[0048] The anti-reflector RPP reduces the reflectivity of external light incident from above the window WP. The anti-reflector RPP according to an exemplary embodiment of the present invention may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include a liquid crystal oriented in a predetermined orientation. The phase retarder and the polarizer may also include a protective film. The phase retarder and the polarizer themselves or the protective film may be the base layer of the anti-reflector RPP.

[0049] The anti-reflector RPP according to an exemplary embodiment of the present invention may include a color filter. The color filter has a predetermined arrangement. The arrangement of the color filter may be determined in consideration of the luminous color of the pixels included in the display panel DP. The anti-reflector RPP may further include a black matrix adjacent to the color filter.

[0050] The anti-reflector RPP according to an exemplary embodiment of the present invention may include a destructive interference structure. For example, the destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may destructively interfere with each other, thereby reducing the reflectivity of the external light.

[0051] The window WP according to an exemplary embodiment of the present invention includes a base layer WP-BS and a light shielding pattern WP-BZ. The base layer WP-BS may include a glass substrate, a synthetic resin film, etc. The base layer WP-BS is not limited to a single layer. The base layer WP-BS may include two or more films bonded by an adhesive member.

[0052] The light-shielding pattern WP-BZ partially overlaps with the base layer WP-BS. The light-shielding pattern WP-BZ may be disposed on the rear surface of the base layer WP-BS and may substantially define the frame area DD-NDA of the display device DD. In other words, the light-shielding pattern WP-BZ may be formed in the frame area DD-NDA of the display device DD. The area in which the light-shielding pattern WP-BZ is not disposed may be the image area DD-DA of the display device DD. When describing the window WP, the area in which the light-shielding pattern WP-BZ is disposed is the light-shielding area of ​​the window WP, and the area in which the light-shielding pattern WP-BZ is not disposed is the transmission area of ​​the window WP.

[0053] The light shielding pattern WP-BZ may have a multi-layer structure. The multi-layer structure may include a color layer having a color and a light shielding layer having a non-color (e.g., black). The color layer having a color and the light shielding layer having a non-color may be formed by a deposition, printing, or coating process. The window WP may also include a functional coating layer disposed on the front surface of the base layer WP-BS. The functional coating layer may include an anti-fingerprint layer, an anti-reflection layer, a hard coating layer, and the like.

[0054] Figure 3 is a cross-sectional view of a display panel DP according to an exemplary embodiment of the present invention.

[0055] like Figure 3 As shown in FIG. 1 , the display panel DP includes a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED and an upper insulating layer TFL disposed on the base layer BL. Figure 1 The display area DP-DA and the non-display area DP-NDA corresponding to the image area DD-DA and the frame area DD-NDA shown in the figure may be located in the display panel DP. As used herein, "an area / portion corresponds to another area / portion" may mean "two areas / portions overlap each other", but is not limited to having the same surface area and / or the same shape. In other words, the two overlapping areas / portions may not have the same surface area and / or the same shape.

[0056] The base layer BL may include at least one synthetic resin film. The base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, or the like.

[0057] The circuit element layer DP-CL includes at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel driving circuits, etc.

[0058] The display element layer DP-OLED includes at least an organic light emitting diode as a light emitting element. The display element layer DP-OLED may further include an organic layer such as a pixel defining film.

[0059] The upper insulating layer TFL includes a plurality of thin films. Some of the thin films are provided to enhance optical efficiency, while other thin films are provided to protect each of the organic light emitting diodes. A detailed description of the upper insulating layer TFL will be given later.

[0060] Figure 4 yes Figure 1 A block diagram of a display device DD is shown in FIG.

[0061] Reference Figure 4 , the display device DD may include a display module DM, a power module PM, a first electronic module EM1, and a second electronic module EM2. The display module DM, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0062] Figure 4 The display module DM shown in FIG. 1 may include Figure 2 In addition, the display module DM may further include a panel driving circuit PDC, an input sensing circuit ISC and a fingerprint reading circuit ROC.

[0063] The power module PM supplies power required for overall operations of the display device DD. The power module PM may include a battery module.

[0064] The first electronic module EM1 and the second electronic module EM2 include various functional modules for operating the display device DD. The first electronic module EM1 may be directly mounted on a motherboard electrically connected to the display module DM, or may be mounted on a separate board to be electrically connected to the motherboard through a connector or the like.

[0065] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, a sound input module AIM, a memory MM, and an external interface IF. Some of the modules may also be electrically connected to the motherboard through a flexible circuit board without being mounted on the motherboard.

[0066] The control module CM controls the overall operation of the display device DD. The control module CM may be a microprocessor. For example, the control module CM activates or deactivates the display module DM. The control module CM may control other modules (such as the image input module IIM and the sound input module AIM) based on a touch signal received from the display module DM. The control module CM may perform user authentication based on a fingerprint signal received from the fingerprint reading circuit ROC.

[0067] The wireless communication module TM can send a radio signal to another terminal / receive a radio signal from another terminal by using a Bluetooth or Wi-Fi channel. The wireless communication module TM is not limited to Bluetooth or Wi-Fi, and can send / receive radio signals via a variety of other short-range wireless technologies. The wireless communication module TM can send a voice signal to a repeater / receive a voice signal from a repeater by using a communication channel. The wireless communication module TM includes a sending component TM1 for modulating and sending a signal to be sent and a receiving component TM2 for demodulating a received signal.

[0068] The image input module IIM processes the image signal and converts the processed image signal into image data that can be displayed on the display module DM. The sound input module AIM receives an external sound signal using a microphone in a recording mode, a voice recognition mode, etc., and converts the received external sound signal into electrical voice data.

[0069] The external interface IF serves as an interface to which an external charger, a wired / wireless data port, a card (eg, a memory card and a Subscriber Identity Module (SIM) / User Identity Module (UIM) card) slot, etc. are connected.

[0070] The second electronic module EM2 may include an audio output module AOM, a light emitting module LM, a light receiving module LRM, a camera module CMM, etc. The above components may be directly mounted on a motherboard, may be mounted on a separate board to be electrically connected to the display module DM via a connector, etc., or may be electrically connected to the first electronic module EM1.

[0071] The sound output module AOM converts sound data received from the wireless communication module TM or stored in the memory MM, and outputs the converted sound data to the outside.

[0072] The light emitting module LM generates and outputs light. The light emitting module LM may output infrared rays. The light emitting module LM may include a light emitting diode (LED) element. The light receiving module LRM may sense infrared rays. When infrared rays having a predetermined level or higher are sensed, the light receiving module LRM may be activated. The light receiving module LRM may include a complementary metal oxide semiconductor (CMOS) sensor. After the infrared rays generated by the light emitting module LM are output, the infrared rays may be reflected by an external object (e.g., a finger or face of a user), and the reflected infrared rays may be incident on the light receiving module LRM. The camera module CMM captures external images.

[0073] Figure 5 is a plan view of a display panel DP according to an exemplary embodiment of the present invention.

[0074] like Figure 5As shown in FIG, the display panel DP may include a scan driving circuit SDC, a plurality of signal lines SGL (hereinafter referred to as signal lines SGL), a plurality of signal pads (or referred to as "pads" or "pads") DP-PD and ISL-PD (hereinafter referred to as signal pads DP-PD and ISL-PD), a plurality of light-emitting pixels PX (hereinafter referred to as light-emitting pixels PX), and a plurality of light-sensing pixels FX (hereinafter referred to as light-sensing pixels FX). The light-sensing pixels FX may be used to sense the light through a user input TC (see FIG. Figure 1 ) Fingerprint sensing pixels for sensing fingerprints.

[0075] The scan drive circuit SDC generates a plurality of scan signals (hereinafter referred to as scan signals) and sequentially outputs the scan signals to a plurality of scan lines SL (hereinafter referred to as scan lines SL) to be described later. The scan drive circuit SDC may also output another control signal to the drive circuit of each of the light-emitting pixels PX.

[0076] The scan drive circuit SDC may include a plurality of transistors formed by the same process as that of the drive circuit of each of the light-emitting pixels PX. In addition, each of the transistors included in the scan drive circuit SDC and the transistors included in the light-emitting pixels PX may be a P-type transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer or an N-type transistor having an oxide semiconductor as a semiconductor layer. In an exemplary embodiment of the present invention, some of the transistors included in the scan drive circuit SDC and the light-emitting pixels PX may be P-type transistors, and the other transistors may be N-type transistors.

[0077] The signal lines SGL include scan lines SL, data lines DL, power lines PL, fingerprint sensing lines FSL, and control signal lines CSL. Each of the scan lines SL is connected to a corresponding light-emitting pixel PX among the light-emitting pixels PX, and each of the data lines DL is connected to a corresponding light-emitting pixel PX among the light-emitting pixels PX. The power lines PL are connected to the light-emitting pixels PX. The control signal lines CSL can provide control signals to the scan drive circuit SDC.

[0078] In an exemplary embodiment of the present invention, the signal line SGL may further include an auxiliary line SSL. The auxiliary line SSL is connected to the input sensor ISL (see Figure 2 ). The auxiliary line SSL can be omitted.

[0079] The signal line SGL may include a plurality of portions disposed on different layers. Figure 51 and 2. The data lines DL each include two parts P1 and P2. The parts P1 and P2 may be connected to each other through one of the contact holes CNT. The auxiliary line SSL is connected to the input sensor ISL (see FIG. 1 ) to be described later through the corresponding contact hole CNT in the contact holes CNT. Figure 6 ) signal line.

[0080] The signal pads DP-PD and ISL-PD may include a first type signal pad DP-PD connected to the data line DL, the power line PL, and the control signal line CSL, and a second type signal pad ISL-PD connected to the auxiliary line SSL. The first type signal pad DP-PD and the second type signal pad ISL-PD are arranged adjacent to each other in the pad area NDA-PA in a portion of the non-display area DP-NDA. The stacked structures or constituent materials of the signal pads DP-PD and ISL-PD may not be distinguished from each other, and the signal pads DP-PD and ISL-PD may be formed by the same process.

[0081] The display area DP-DA may be an area in which light-emitting pixels PX and light-sensing pixels FX are arranged. A plurality of electronic components are provided in the display area DP-DA. The electronic components include a light-emitting pixel driving circuit connected to an organic light-emitting diode provided in each of the light-emitting pixels PX and a light-sensing pixel driving circuit connected to an organic photodiode provided in each of the light-sensing pixels FX. The scanning driving circuit SDC, the signal line SGL, the signal pads DP-PD and ISL-PD, the light-emitting pixel driving circuit, and the light-sensing pixel driving circuit may be included in Figure 3 The circuit element layer DP-CL is shown in FIG.

[0082] The light emitting pixel PX and the light sensing pixel FX will be described in detail later. Figure 5 Also shown is a circuit board PCB electrically connected to the display panel DP. The circuit board PCB may be a rigid circuit board or a flexible circuit board.

[0083] A panel drive circuit PDC for controlling the operation of the display panel DP may be provided on a circuit board PCB. In addition, a fingerprint reading circuit ROC and an input sensing circuit ISC for controlling an input sensor ISL may be provided on the circuit board PCB. Each of the panel drive circuit PDC, the input sensing circuit ISC and the fingerprint reading circuit ROC may be mounted on the circuit board PCB in the form of an integrated chip. In an exemplary embodiment of the present invention, the panel drive circuit PDC, the input sensing circuit ISC and the fingerprint reading circuit ROC may be mounted on the circuit board PCB in the form of a single integrated chip. The circuit board PCB may include a circuit board pad PCB-PD electrically connected to the signal pads DP-PD and ISL-PD. The circuit board PCB may also include a signal line connecting the circuit board pad PCB-PD to the panel drive circuit PDC and / or the input sensing circuit ISC. In addition, the circuit board pad PCB-PD may include at least one output pad and at least one input pad.

[0084] The fingerprint reading circuit ROC may receive a fingerprint sensing signal through the fingerprint sensing line FSL.

[0085] The signal pads DP-PD and ISL-PD of the display panel DP and the circuit board pad PCB-PD may be directly connected to each other. In another exemplary embodiment of the present invention, the signal pads DP-PD and ISL-PD and the circuit board pad PCB-PD may be electrically connected through a connection plate such as an anisotropic conductive film.

[0086] In an exemplary embodiment of the present invention, the panel driving circuit PDC may be installed in the non-display area DP-NDA of the display panel DP instead of the circuit board PCB.

[0087] Figure 5 A portion of the display panel DP shown in FIG. 1 may be bent. A portion of the non-display area DP-NDA may be bent and may be bent around a bending axis parallel to the second direction DR2. The bending axis may overlap a portion P2 of the data line DL and the auxiliary line SSL. Figure 5 A light emitting control line EL is also shown in FIG. 1 , and the light emitting control line EL may be connected to the light emitting pixel PX.

[0088] Figure 6 is a plan view of an input sensor ISL according to an exemplary embodiment of the present invention.

[0089] Reference Figure 6 , the input sensor ISL is set at Figure 5 The input sensor ISL can sense the user input TC (in Figure 1) to obtain the position or strength information of the external touch input. When viewed in a plane, the input sensor ISL may include a sensing area TA and a wiring area TSA. The sensing area TA may be an area in which the first sensing electrode SE1 and the second sensing electrode SE2 are arranged. In an exemplary embodiment of the present invention, the wiring area TSA may be provided along the edge of the sensing area TA. The sensing area TA and the wiring area TSA may be respectively connected to Figure 5 The display area DP-DA and the non-display area DP-NDA of the display panel DP shown in FIG.

[0090] In an exemplary embodiment of the present invention, the input sensor ISL may be a capacitive touch sensor. One of the first sensing electrode SE1 and the second sensing electrode SE2 receives a driving signal, and the other outputs a change in capacitance between the first sensing electrode SE1 and the second sensing electrode SE2 as a sensing signal.

[0091] Each of the first sensing electrodes SE1 has a shape extending in the second direction DR2. In addition, the first sensing electrodes SE1 may be sequentially arranged in the first direction DR1. The first sensing electrodes SE1 may include a plurality of first sensing patterns SP1 and a plurality of first connection patterns CP1.

[0092] Each of the second sensing electrodes SE2 has a shape extending in the first direction DR1. In addition, the second sensing electrodes SE2 may be sequentially arranged in the second direction DR2. The second sensing electrodes SE2 may include a plurality of second sensing patterns SP2 and a plurality of second connection patterns CP2.

[0093] The first sensing lines TL1-1 to TL1-a may include the same number of signal lines as the number of first sensing electrodes SE1. Each of the first sensing lines TL1-1 to TL1-a may be connected to at least one of the opposite ends of a corresponding one of the first sensing electrodes SE1. The second sensing lines TL2-1 to TL2-b may include the same number of signal lines as the number of second sensing electrodes SE2. Each of the second sensing lines TL2-1 to TL2-b may be connected to at least one of the opposite ends of a corresponding one of the second sensing electrodes SE2.

[0094] The first sensing lines TL1-1 to TL1-a may be connected to the pad areas NDA-PA (see FIG. 1 ) through corresponding ones of the contact holes CNT. Figure 5 ) on one side of the auxiliary line SSL (see Figure 5 The second sensing lines TL2-1 to TL2-b may be connected to the pad areas NDA-PA (see FIG. 1 ) through corresponding ones of the contact holes CNT. Figure 5) on the other side of the auxiliary line SSL (see Figure 5 )

[0095] The contact holes CNT penetrate the insulating layer disposed between the first and second sensing lines TL1 - 1 to TL1 - a and TL2 - 1 to TL2 - b and the auxiliary line SSL.

[0096] Figure 7 Shows Figure 5 FIG. 4 shows the connection relationship between the light emitting pixels PX, the light sensing pixels FX and the signal lines SGL of the display panel DP.

[0097] Reference Figure 7 , the panel driving circuit PDC provides the control signal CTRL to the scanning driving circuit SDC through the control signal line CSL. The scanning driving circuit SDC outputs a plurality of scanning signals SC0 to SCn to a plurality of scanning lines SL0 to SLn in response to the control signal CTRL. The plurality of scanning signals SC0 to SCn may be pulse signals having an effective level sequentially. The scanning driving circuit SDC outputs a plurality of light emitting control signals EM1 to EMn to a plurality of light emitting control lines EL1 to ELn in response to the control signal CTRL. The plurality of light emitting control signals EM1 to EMn may be pulse signals having an effective level sequentially. Here, m and n are both positive integers.

[0098] The panel driving circuit PDC outputs data signals DS1 to DSm to the plurality of data lines DL1 to DLm. The data signals DS1 to DSm may be signals having grayscale voltages corresponding to images to be displayed in the light emitting pixels PX.

[0099] The fingerprint reading circuit ROC receives fingerprint sensing signals FS1 to FSm from a plurality of fingerprint sensing lines FSL1 to FSLm.

[0100] The light-emitting pixels PX and the light-sensing pixels FX are arranged alternately and sequentially in the first direction DR1, and the light-emitting pixels PX and the light-sensing pixels FX are arranged alternately and sequentially in the second direction DR2. In other words, the light-sensing pixels FX may be respectively arranged on the left side, right side, upper side, and lower side of the specific light-emitting pixels PX. In addition, the light-emitting pixels PX may be respectively arranged on the left side, right side, upper side, and lower side of the specific light-sensing pixels FX. However, the arrangement order and repetition period of the light-emitting pixels PX and the light-sensing pixels FX are not limited to Figure 7 In an exemplary embodiment of the present invention, two light emitting pixels PX and one light sensing pixel FX may be alternately and sequentially arranged in the first direction DR1.

[0101] Each of the light-emitting pixels PX is connected to two adjacent scan lines among the scan lines SL0 to SLn, a corresponding light-emitting control line among the light-emitting control lines EL1 to ELn, a corresponding data line among the data lines DL1 to DLm, a first voltage line VL1, and a second voltage line VL2. The first voltage line VL1 and the second voltage line VL2 may include Figure 5 The first voltage line VL1 may be used to transmit the second driving voltage ELVDD (see Figure 8 ) voltage line, the second voltage line VL2 may be used to transmit the initialization voltage VINIT (see Figure 8 In addition to the first voltage line VL1 and the second voltage line VL2, the third voltage line VL3 (see Figure 8 ) can also be included in the power line PL (see Figure 5 ). The third voltage line VL3 may be electrically connected to both the light emitting pixel PX and the light sensing pixel FX to convert the first driving voltage ELVSS (see Figure 8 ) are provided to the light-emitting pixels PX and the light-sensing pixels FX.

[0102] Each of the light-sensing pixels FX is connected to two adjacent scan lines among the scan lines SL0 to SLn, a corresponding fingerprint sensing line among the fingerprint sensing lines FSL1 to FSLm, and a first voltage line VL1.

[0103] Figure 8 Shows Figure 7 2 is a circuit configuration of a light-emitting pixel PXij among a plurality of light-emitting pixels PX and a corresponding light-sensing pixel FXij among a plurality of light-sensing pixels FX shown in FIG.

[0104] Figure 7 Each of the plurality of light-emitting pixels PX shown in FIG. Figure 8 The circuit configuration of the luminescent pixel PXij shown in FIG. Figure 7 Each of the plurality of light sensing pixels FX shown in FIG. Figure 8 The circuit configuration of the light sensing pixel FXij shown in is the same circuit configuration.

[0105] Figure 8 The light-emitting pixel PXij shown in the figure is connected to the jth data line DLj among multiple data lines DL1 to DLm, the i-1th scan line SLi-1 and the i-th scan line SLi among multiple scan lines SL0 to SLn, and the i-th light-emitting control line ELi among multiple light-emitting control lines EL1 to ELn. Figure 8The light sensing pixel FXij shown in FIG. 1 is connected to a j-th fingerprint sensing line FSLj among the plurality of fingerprint sensing lines FSL1 to FSLm and an i-th scan line SLi and an i-1-th scan line SLi-1 among the plurality of scan lines SL0 to SLn.

[0106] The light-emitting pixel PXij includes an organic light-emitting diode LD and a light-emitting driving circuit LDC.

[0107] In an exemplary embodiment of the present invention, the light emitting driving circuit LDC of the light emitting pixel PXij includes seven transistors T1, T2, T3, T4, T5, T6 and T7 and a capacitor Cst. In addition, the first transistor T1 to the seventh transistor T7 may be a P-type transistor such as a p-type MOS (PMOS) transistor, but is not limited thereto. At least one of the first transistor T1 to the seventh transistor T7 may be an N-type transistor such as an n-type MOS (NMOS) transistor. In addition, the circuit configuration of the light emitting pixel PXij according to the exemplary embodiment of the present invention is not limited to Figure 8 The circuit configuration shown in FIG. Figure 8 The light emitting drive circuit LDC shown in FIG. 1 is merely an example, and the configuration of the light emitting drive circuit LDC may be modified.

[0108] Reference Figure 8 , according to the display device DD of the exemplary embodiment of the present invention (see Figure 1 ) may include first to seventh transistors T1 to T7 connected to the jth data line DLj, the i-1th scan line SLi-1, the i-th scan line SLi, the i-th emission control line ELi, and the first, second, and third voltage lines VL1, VL2, and VL3, a capacitor Cst, and at least one organic light emitting diode LD. In an exemplary embodiment of the present invention, an example in which one light emitting pixel PXij includes one organic light emitting diode LD is described.

[0109] The i-1th scan line SLi-1 may transmit the second scan signal SCi-1, and the i-th scan line SLi may transmit the first scan signal SCi. The first scan signal SCi and the second scan signal SCi-1 may transmit a gate-on voltage and a gate-off voltage capable of turning on and off the transistors T2, T3, T4, and T7 included in the pixel PXij. In an exemplary embodiment of the present invention, an example in which the i-1th scan line SLi-1 transmits a gate-on voltage at a timing earlier than that of the i-th scan line SLi will be mainly described.

[0110] The i-th light emitting control line ELi may transmit a light emitting control signal EMi capable of controlling light emission of the organic light emitting diode LD. The light emitting control signal EMi transmitted by the i-th light emitting control line ELi may have a waveform different from the waveforms of the first scan signal SCi and the second scan signal SCi-1 transmitted by the i-th scan line SLi and the i-1-th scan line SLi-1. The j-th data line DLj transmits a data signal DSj. The first voltage line VL1 transmits a second driving voltage ELVDD, the second voltage line VL2 transmits an initialization voltage VINIT, and the third voltage line VL3 transmits a first driving voltage ELVSS.

[0111] The gate electrode of the first transistor T1 is connected to the first end of the capacitor Cst, the source electrode of the first transistor T1 is connected to the first voltage line VL1 via the fifth transistor T5, and the drain electrode of the first transistor T1 is electrically connected to the anode AE ​​of the organic light emitting diode LD via the sixth transistor T6 (see Fig.13 ). The first transistor T1 may receive the data signal DSj transmitted by the j-th data line DLj according to the switching operation of the second transistor T2, and may supply a driving current to the organic light emitting diode LD.

[0112] A gate electrode of the second transistor T2 is connected to the i-th scan line SLi, a source electrode of the second transistor T2 is connected to the j-th data line DLj, a drain electrode of the second transistor T2 is connected to the source electrode of the first transistor T1, and is connected to the first voltage line VL1 via the fifth transistor T5. The second transistor T2 may be turned on according to the first scan signal SCi received through the i-th scan line SLi, and may transmit a data signal DSj transmitted through the j-th data line DLj to the source electrode of the first transistor T1.

[0113] The gate electrode of the third transistor T3 is connected to the i-th scan line SLi. The drain electrode of the third transistor T3 is connected to the drain electrode of the fourth transistor T4, the first end of the capacitor Cst and the gate electrode of the first transistor T1. The source electrode of the third transistor T3 is connected to the drain electrode of the first transistor T1 and is connected to the anode AE ​​of the organic light emitting diode LD via the sixth transistor T6 (see Fig.13 ).

[0114] The third transistor T3 may be turned on according to the first scan signal SCi received through the i-th scan line SLi, and may connect the gate electrode and the drain electrode of the first transistor T1 to each other to make the first transistor T1 diode-connected.

[0115] A gate electrode of the fourth transistor T4 is connected to the i-1th scan line SLi-1, a source electrode of the fourth transistor T4 is connected to the second voltage line VL2, and a drain electrode of the fourth transistor T4 is connected to the first end of the capacitor Cst, the gate electrode of the first transistor T1, and the drain electrode of the third transistor T3. The fourth transistor T4 may be turned on according to the second scan signal SCi-1 received through the i-1th scan line SLi-1, and may perform an initialization operation for initializing the voltage of the gate electrode of the first transistor T1 by transmitting the initialization voltage VINIT to the gate electrode of the first transistor T1.

[0116] A gate electrode of the fifth transistor T5 is connected to the i-th light emitting control line ELi, a source electrode of the fifth transistor T5 is connected to the first voltage line VL1, and a drain electrode of the fifth transistor T5 is connected to the source electrode of the first transistor T1 and the drain electrode of the second transistor T2.

[0117] The gate electrode of the sixth transistor T6 is connected to the i-th light emitting control line ELi, the source electrode of the sixth transistor T6 is connected to the drain electrode of the first transistor T1 and the source electrode of the third transistor T3, and the drain electrode of the sixth transistor T6 is electrically connected to the anode AE ​​of the organic light emitting diode LD (see Fig.13 ). The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the emission control signal EMi received through the i-th emission control line ELi, and as a result, the second driving voltage ELVDD may be compensated by the diode-connected first transistor T1 and transmitted to the organic light emitting diode LD.

[0118] The gate electrode of the seventh transistor T7 is connected to the i-1th scan line SLi-1, and the source electrode of the seventh transistor T7 is connected to the drain electrode of the sixth transistor T6 and the anode electrode AE ​​of the organic light emitting diode LD (see Fig.13 ), the drain electrode of the seventh transistor T7 is connected to the second voltage line VL2 and the source electrode of the fourth transistor T4.

[0119] As described above, the first terminal of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the second terminal of the capacitor Cst is connected to the first voltage line VL1. Fig.13 ) can be connected to a third voltage line VL3 transmitting the first driving voltage ELVSS. The structure of the light-emitting pixel PXij according to an exemplary embodiment of the present invention is not limited to Figure 8 In the structure shown in FIG. 1 , the number of transistors and the number of capacitors included in the light-emitting pixel PXij and the connection relationship can be variously modified.

[0120] The light sensing pixel FXij includes an organic photodiode OPD and a light sensing driving circuit ODC.

[0121] In this embodiment, the light sensing driving circuit ODC of the light sensing pixel FXij includes three transistors FT1, FT2 and FT3. In addition, the reset transistor FT1, the amplifying transistor FT2 and the output transistor FT3 may be P-type transistors such as PMOS transistors, but are not limited thereto. At least one of the reset transistor FT1, the amplifying transistor FT2 and the output transistor FT3 may be an N-type transistor. In addition, the circuit configuration of the light sensing pixel FXij according to an exemplary embodiment of the present invention is not limited to Figure 8 Circuit configuration. Figure 8 The light-sensing driving circuit ODC shown in FIG. 1 is merely an example, and the configuration of the light-sensing driving circuit ODC may be modified.

[0122] Reference Figure 8 , according to the display device DD of the exemplary embodiment of the present invention (see Figure 1 ) may include a reset transistor FT1, an amplifying transistor FT2, an output transistor FT3, and at least one organic photodiode OPD connected to the j-th fingerprint sensing line FSLj, the i-1-th scan line SLi-1, the i-th scan line SLi, the first voltage line VL1, and the third voltage line VL3. In this embodiment, an example in which one light sensing pixel FXij includes one organic photodiode OPD is described.

[0123] The gate electrode of the reset transistor FT1 is connected to the i-th scan line SLi, the source electrode of the reset transistor FT1 is connected to the i-1-th scan line SLi-1, and the drain electrode of the reset transistor FT1 is electrically connected to the charge storage node FN. The reset transistor FT1 can reset the charge storage node FN in response to the first scan signal SCi transmitted by the i-th scan line SLi.

[0124] The reset transistor FT1 may have a dual-gate structure connected in series. In other words, the reset transistor FT1 may include a first sub-transistor and a second sub-transistor. The reset transistor FT1 may have a structure in which the gate electrodes of the first sub-transistor and the second sub-transistor are connected to each other through wiring on a gate insulating layer, and a high-concentration region with high conductivity is provided between the gate electrodes as a gate common region. The drain electrode of the first sub-transistor and the source electrode of the second sub-transistor may be electrically connected to each other. In addition, the source electrode of the first sub-transistor may be connected to the i-1th scan line SLi-1, and the drain electrode of the second sub-transistor may be electrically connected to the charge storage node FN.

[0125] The gate electrode of the amplifying transistor FT2 is electrically connected to the charge storage node FN, the source electrode of the amplifying transistor FT2 is connected to the first voltage line VL1, and the drain electrode of the amplifying transistor FT2 is connected to the source electrode of the output transistor FT3. The amplifying transistor FT2 can be turned on by the voltage level of the charge storage node FN, and can transmit the second driving voltage ELVDD transmitted from the first voltage line VL1 to the source electrode of the output transistor FT3.

[0126] The gate electrode of the output transistor FT3 is connected to the i-1th scan line SLi-1. The source electrode of the output transistor FT3 is connected to the drain electrode of the amplifying transistor FT2. The drain electrode of the output transistor FT3 is connected to the jth fingerprint sensing line FSLj. The jth fingerprint sensing line FSLj can transmit a fingerprint sensing signal FSj.

[0127] Fig. 9 Is used to describe Figure 8 0 is a timing diagram of the operation of the light-emitting pixel PXij and the light-sensing pixel FXij shown in FIG.

[0128] Reference Figure 8 and Fig. 9 , the first scan signal SCi and the second scan signal SCi-1 may be provided in the i-th scan line SLi and the i-1-th scan line SLi-1 connected to the light-emitting pixel PXij, respectively, in one frame FR. One frame FR may include a non-light-emitting period NLEP and a light-emitting period LEP according to whether the organic light-emitting diode LD of the light-emitting pixel PXij emits light. The non-light-emitting period NLEP may include an initialization period in which the second scan signal SCi-1 is at a low level and a data writing and compensation period in which the first scan signal SCi is at a low level.

[0129] During the initialization period, the second scan signal SCi-1 having a low level is provided through the i-1th scan line SLi-1. The fourth transistor T4 is turned on in response to the second scan signal SCi-1 having a low level, and the initialization voltage VINIT is provided to the gate electrode of the first transistor T1 through the fourth transistor T4, and the first transistor T1 is initialized by the initialization voltage VINIT.

[0130] In addition, when the second scan signal SCi-1 with a low level is provided through the i-1 scan line SLi-1, the seventh transistor T7 is turned on. A portion of the driving current at the drain electrode of the first transistor T1 may flow into the second voltage line VL2 through the seventh transistor T7 due to the turned-on seventh transistor T7. Then, when the first scan signal SCi with a low level is provided through the i-th scan line SLi during the data writing and compensation period, the second transistor T2 and the third transistor T3 are turned on. At this time, the first transistor T1 is diode-connected by the turned-on third transistor T3 and is forward biased. Then, the compensation voltage (Di-Vth) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the data signal DSj provided by the j-th data line DLj is applied to the gate electrode of the first transistor T1. In other words, the gate voltage applied to the gate electrode of the first transistor T1 may be the compensation voltage (Di-Vth).

[0131] The second driving voltage ELVDD and the compensation voltage (Di-Vth) may be applied to both ends of the capacitor Cst, respectively, and charges corresponding to a voltage difference between the both ends may be stored in the capacitor Cst.

[0132] Next, the light emitting control signal EMi provided from the i-th light emitting control line ELi changes from a high level to a low level at the beginning of the light emitting period LEP, and is maintained at a low level during the light emitting period LEP. The fifth transistor T5 and the sixth transistor T6 are turned on by the light emitting control signal EMi having a low level during the light emitting period LEP. Then, a driving current is generated according to a voltage difference between a gate voltage of the gate electrode of the first transistor T1 and the second driving voltage ELVDD, and the driving current is supplied to the organic light emitting diode LD through the sixth transistor T6, so that the driving current flows through the organic light emitting diode LD. During the light emitting period LEP, the gate-source voltage (Vgs) of the first transistor T1 may be maintained at “ELVDD-(Di-Vth)” by the capacitor Cst, and the driving current may be proportional to the square of a value obtained by subtracting a threshold voltage from the gate-source voltage (in other words, “(ELVDD-Di)”) according to a current-voltage relationship of the first transistor T1. 2 ”). Therefore, the driving current can be determined regardless of the threshold voltage (Vth) of the first transistor T1.

[0133] One frame FR may include a sensing period SP, an initialization period IP, and an exposure period EP according to the operation of the light sensing pixel FXij. The sensing period SP, the initialization period IP, and the exposure period EP may be performed sequentially.

[0134] The exposure period EP of the light sensing pixel FXij may correspond to the light emission period LEP of the light emitting pixel PXij. In other words, the exposure period EP of the light sensing pixel FXij may overlap the light emission period LEP of the light emitting pixel PXij. The organic photodiode OPD is exposed to external light during the exposure period EP. The organic photodiode OPD may use charges as main charge carriers.

[0135] When there is a user input TC (see Figure 1 ), the organic photodiode OPD may generate photocharges corresponding to light reflected by the ridges of the fingerprint or the valleys between the ridges, and the generated photocharges may be accumulated in the charge storage node FN.

[0136] The amplification transistor FT2 may be a source follower amplifier that generates a source-drain current proportional to the amount of charge of the charge storage node FN input to the gate electrode of the amplification transistor FT2 .

[0137] During the sensing period SP, a second scanning signal SCi-1 having a low level is provided through the i-1th scanning line SLi-1. The first scanning signal SCi may have a high level during the sensing period SP. When the output transistor FT3 is turned on in response to the second scanning signal SCi-1 having a low level, a fingerprint sensing signal FSj corresponding to the current flowing through the amplifying transistor FT2 may be output to the jth fingerprint sensing line FSLj. The sensing period SP of the light sensing pixel FXij may correspond to the initialization period of the light emitting pixel PXij. In other words, the sensing period SP of the light sensing pixel FXij may overlap with the initialization period of the light emitting pixel PXij.

[0138] Next, when the first scan signal SCi having a low level is provided through the i-th scan line SLi during the initialization period IP, the reset transistor FT1 is turned on. In this case, since the second scan signal SCi-1 having a high level is provided to the source electrode of the reset transistor FT1, the second scan signal SCi-1 having a high level may be transmitted to the charge storage node FN to reset the charge storage node FN.

[0139] During the following exposure period EP, the organic photodiode OPD may generate photo charges corresponding to the received external light, and the generated photo charges may be accumulated in the charge storage node FN.

[0140] In this way, both the light-emitting pixel PXij and the light-sensing pixel FXij can be provided in the display panel DP, and the light-sensing pixel FXij can be driven using the first scan signal SCi and the second scan signal SCi-1 for driving the light-emitting pixel PXij. When the first scan signal SCi and the second scan signal SCi-1 have a low level, both the light-emitting pixel PXij and the light-sensing pixel FXij can be driven. Therefore, the display device DD (see Figure 1 ) is minimized, and since a separate circuit for driving the light sensing pixel FXij is unnecessary, the manufacturing cost can be reduced.

[0141] Fig.10 is an enlarged plan view of a portion of a display panel DP according to an exemplary embodiment of the present invention.

[0142] Reference Figure 7 and Fig.10 , the display panel DP includes light-emitting pixels PX11, PX12, PX21, PX22, PX31, PX32, PX41, and PX42 and light-sensing pixels FX11, FX12, FX21, FX22, FX31, FX32, FX41, and FX42. Each of the light-emitting pixels PX11 to PX42 includes an organic light-emitting diode LD and a light-emitting driving circuit LDC. Each of the light-sensing pixels FX11 to FX42 includes an organic photodiode OPD and a light-sensing driving circuit ODC.

[0143] The light-emitting pixels PX11 to PX42 and the light-sensing pixels FX11 to FX42 are alternately and sequentially arranged in the first direction DR1 and in the second direction DR2. For example, the light-emitting pixel PX11, the light-sensing pixel FX21, the light-emitting pixel PX31, and the light-sensing pixel FX41 are sequentially arranged in the first column in the first direction DR1. In addition, the light-emitting pixel PX11, the light-sensing pixel FX11, the light-emitting pixel PX12, and the light-sensing pixel FX12 are sequentially arranged in the first row in the second direction DR2. According to this arrangement, each of the light-sensing pixels FX11 to FX42 can be disposed adjacent to a corresponding one of the light-emitting pixels PX11 to PX42.

[0144] The light-emitting pixels of the same color are arranged in the same column in the first direction DR1. For example, the light-emitting pixels PX11 and PX31 including the organic light-emitting diode LD of the first color (e.g., red R) may be sequentially arranged in the first column, the light-emitting pixels PX21 and PX41 including the organic light-emitting diode LD of the second color (e.g., green G) may be sequentially arranged in the second column, and the light-emitting pixels PX12 and PX32 including the organic light-emitting diode LD of the third color (e.g., blue B) may be sequentially arranged in the third column. Although the light-emitting pixels PX11 and PX31 are sequentially arranged in the first column, the light-sensing pixel FX21 is arranged between the light-emitting pixels PX11 and PX31. Similarly, the light-sensing pixel FX31 is arranged between the light-emitting pixels PX21 and PX41 in the second column.

[0145] In the odd-numbered rows in the second direction DR2, light-emitting pixels including an organic light-emitting diode LD of a first color (e.g., red R) and light-emitting pixels including an organic light-emitting diode LD of a third color (e.g., blue B) may be sequentially arranged. For example, in the first row, a light-emitting pixel PX11 including an organic light-emitting diode LD of a first color (e.g., red R) and a light-emitting pixel PX12 including an organic light-emitting diode LD of a third color (e.g., blue B) are sequentially arranged. In the even-numbered rows in the second direction DR2, light-emitting pixels including an organic light-emitting diode LD of a second color (e.g., green G) may be sequentially arranged. For example, in the second row, light-emitting pixels PX21 and PX22 including an organic light-emitting diode LD of a second color (e.g., green G) are sequentially arranged.

[0146] In an exemplary embodiment of the present invention, each of the organic light emitting diode LD of the first color (e.g., red R) and the organic light emitting diode LD of the third color (e.g., blue B) may have a size larger than that of the organic light emitting diode LD of the second color (e.g., green G). In addition, the organic light emitting diode LD of the third color (e.g., blue B) may have a size larger than that of the organic light emitting diode LD of the first color (e.g., red R). The sizes of the organic light emitting diodes LD of the first color, the second color, and the third color (e.g., red R, green G, and blue B) are not limited thereto and may be modified and applied in various ways.

[0147] In addition, the organic photodiode OPD may have a size smaller than the size of the organic light emitting diode LD of the first color (e.g., red R) and the organic light emitting diode LD of the third color (e.g., blue B). The organic photodiode OPD may have a size similar to the size of the organic light emitting diode LD of the second color (e.g., green G). The size of the organic photodiode OPD is not limited thereto and may be modified and applied in various ways.

[0148] Fig.11 is an enlarged plan view of a portion of a display panel DP according to an exemplary embodiment of the present invention.

[0149] Fig.11 The display panel DP shown in FIG. 1 may include Fig.10 In other words, the light-emitting pixels PX11 and PX31 including only the organic light-emitting diode LD of the first color (e.g., red R) are arranged in the first column in the first direction DR1. No light-sensing pixels are arranged between the light-emitting pixels PX11 and PX31 in the first column in the first direction DR1. In addition, in the third column in the first direction DR1, only the light-emitting pixels PX12 and PX32 including the organic light-emitting diode LD of the third color (e.g., blue B) are arranged. No light-sensing pixels are arranged between the light-emitting pixels PX12 and PX32 in the third column in the first direction DR1.

[0150] Fig.12 is an enlarged plan view of a portion of a display panel DP according to an exemplary embodiment of the present invention.

[0151] Fig.12 The display panel DP shown in FIG. 1 may include Fig.10 . In other words, the light-emitting pixel PX11 including only the organic light-emitting diode LD of the first color (e.g., red R) and the light-emitting pixel PX12 including the organic light-emitting diode LD of the third color (e.g., blue B) are arranged in the first row in the second direction DR2. No light-sensing pixel is arranged between the light-emitting pixels PX11 and PX12 in the first row in the second direction DR2. In addition, the light-emitting pixel PX31 including only the organic light-emitting diode LD of the first color (e.g., red R) and the light-emitting pixel PX32 including the organic light-emitting diode LD of the third color (e.g., blue B) are arranged in the third row in the second direction DR2. No light-sensing pixel is arranged between the light-emitting pixels PX31 and PX32 in the third row in the second direction DR2.

[0152] The exemplary embodiments of the present invention are not limited to Fig.10 , Fig.11 and Fig.12 In the examples shown in FIG. 1 , the light-emitting pixels and the light-sensing pixels may be modified and arranged in various ways.

[0153] Fig.13 is an enlarged cross-sectional view of a display panel DP according to an exemplary embodiment of the present invention.

[0154] Reference Fig.13, the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. Each of the insulating layer, the semiconductor layer, and the conductive layer is formed by coating, vapor deposition, etc. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography. In this method, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED are formed.

[0155] The base layer BL may include a synthetic resin film. The synthetic resin film may include a thermosetting resin. The base layer BL may have a multilayer structure. For example, the base layer BL may have a three-layer structure of a synthetic resin film, an adhesive layer and a synthetic resin film. In particular, the synthetic resin film may be a polyimide resin layer, and its material is not particularly limited. The synthetic resin film may include acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin or perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc.

[0156] The light emitting electronic device and the light sensing electronic device are arranged on the base layer BL. The light emitting electronic device includes Figure 8 The light sensing electronic device includes transistors T1 to T7 and capacitor Cst in the light emitting drive circuit LDC shown in FIG. Figure 8 Transistors FT1 to FT3 in the light sensing drive circuit ODC shown in FIG.

[0157] At least one inorganic layer is formed on the top surface of the base layer BL. The inorganic layer may include aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, or hafnium oxide. The inorganic layer may be formed as a multilayer. The multilayer inorganic layer may constitute a barrier layer and / or a buffer layer. In this exemplary embodiment, the display panel DP is shown as including a buffer layer BFL.

[0158] The buffer layer BFL improves the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0159] The semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the semiconductor pattern is not limited thereto and may include amorphous silicon or metal oxide.

[0160] Fig.13The semiconductor pattern is partially shown, and another part of the semiconductor pattern may also be arranged in another area of ​​the pixel PX when viewed in a plane. The semiconductor pattern may be arranged in a specific rule across the light-emitting pixel PX and the light-sensing pixel FX. The semiconductor pattern has different electrical properties depending on whether its part is doped. The semiconductor pattern may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant.

[0161] The doped region has a higher conductivity than the non-doped region and can be used as an electrode or a signal line. The non-doped region corresponds to the active region (or channel) of the transistor. Hereinafter, the active region may be referred to as an "active region". In other words, the first portion of the semiconductor pattern may be the active region of the transistor, the second portion of the semiconductor pattern may be the source or drain of the transistor, and the third portion of the semiconductor pattern may be a connecting electrode or a connecting signal line.

[0162] like Fig.13 As shown in , the source S2, active area A2 and drain D2 of the second transistor T2 are formed by a semiconductor pattern, and the source FS1, active area FA1 and drain FD1 of the reset transistor FT1 are formed by a semiconductor pattern. When viewed in cross section, the source S2 and the drain D2 extend in opposite directions from the active area A2, and the source FS1 and the drain FD1 extend in opposite directions from the active area FA1. Fig.13 A portion of the connection signal lines SCL1 and SCL2 formed by the semiconductor pattern is shown. When viewed in a plane, the connection signal line SCL1 may be connected to the drain D2 of the second transistor T2, and the connection signal line SCL2 may be connected to the drain FD1 of the reset transistor FT1. Fig.13 In the embodiment, the reset transistor FT1 is provided between the connection signal lines SCL1 and SCL2.

[0163] The first insulating layer 10 is disposed on the buffer layer BFL. Figure 7 ) and multiple light sensing pixels FX (see Figure 7 ) is stacked and covers the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, or hafnium oxide. In this embodiment, the first insulating layer 10 may be a single layer of silicon oxide. In addition to the first insulating layer 10, the insulating layer of the circuit element layer DP-CL to be described later may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0164] The gates G2 and FG1 are disposed on the first insulating layer 10. The gates G2 and FG1 may be part of a metal pattern. The gates G2 and FG1 overlap the active areas A2 and FA1, respectively, and the first insulating layer 10 is between the gates G2 and FG1 and the active areas A2 and FA1. The gates G2 and FG1 are used as masks in the process of doping the semiconductor pattern.

[0165] The second insulating layer 20 covering the gates G2 and FG1 is disposed on the first insulating layer 10. The second insulating layer 20 is connected to the light-emitting pixel PX (see Figure 7 ) and light sensing pixel FX (see Figure 7 The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. In this embodiment, the second insulating layer 20 may be a single layer of silicon oxide.

[0166] The upper electrodes UE and FUE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the gate G2 and the active area A2 of the second transistor T2, and the upper electrode FUE may overlap the gate FG1 and the active area FA1 of the reset transistor FT1. The upper electrodes UE and FUE may be part of the metal pattern. A portion of the gate G2 and the upper electrode UE overlapping the portion of the gate G2 may form a capacitor Cst (see Figure 8 ). In an exemplary embodiment of the present invention, the upper electrode UE may be omitted.

[0167] A third insulating layer 30 covering the upper electrodes UE and FUE is disposed on the second insulating layer 20. In this embodiment, the third insulating layer 30 may be a single layer of silicon oxide. A first connection electrode CNE1 and a third connection electrode CNE3 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL1 through a contact hole CNT-1 penetrating the first insulating layer 10 to the third insulating layer 30. The third connection electrode CNE3 may be connected to the connection signal line SCL2 through a contact hole CNT-4 penetrating the first insulating layer 10 to the third insulating layer 30.

[0168] A fourth insulating layer 40 covering the first connection electrode CNE1 and the third connection electrode CNE3 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single layer of silicon oxide. A fifth insulating layer 50 is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. The second connection electrode CNE2 and the fourth connection electrode CNE4 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40 and the fifth insulating layer 50. For example, the second connection electrode CNE2 may directly contact the first connection electrode CNE1 via the contact hole CNT-2. The fourth connection electrode CNE4 may be connected to the third connection electrode CNE3 through a contact hole CNT-5 penetrating the fourth insulating layer 40 and the fifth insulating layer 50. For example, the fourth connection electrode CNE4 may directly contact the third connection electrode CNE3 via the contact hole CNT-5.

[0169] A sixth insulating layer 60 covering the second connection electrode CNE2 and the fourth connection electrode CNE4 is disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The anode AE ​​is disposed on the sixth insulating layer 60. The anode AE ​​is connected to the second connection electrode CNE2 through a contact hole CNT-3 penetrating the sixth insulating layer 60. An opening OP1 is disposed in the pixel defining film PDL. The opening OP1 of the pixel defining film PDL exposes at least a portion of the anode AE.

[0170] like Fig.13 As shown in the display area DP-DA (see Figure 3 ) may include a light emitting region PXA, a non-light emitting region NPXA, and a light sensing region FXA. The non-light emitting region NPXA may surround the light emitting region PXA and the light sensing region FXA. In this embodiment, the light emitting region PXA corresponds to a portion of the anode AE ​​exposed by the opening OP1. In other words, the region above the portion of the anode AE ​​exposed by the opening OP1 forms the light emitting region PXA.

[0171] The hole control layer HCL may be disposed in the light emitting region PXA and the non-light emitting region NPXA. The hole control layer HCL includes a hole transport layer and may further include a hole injection layer. The light emitting layer EML is disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the opening OP1. Therefore, the light emitting layer EML may be formed separately in each of the light emitting pixels PX.

[0172] The electron control layer ECL is disposed on the light emitting layer EML. The electron control layer ECL includes an electron transport layer and may further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be formed separately in a plurality of light emitting pixels PX using an open mask, or may be formed together in a plurality of light emitting pixels PX. The cathode CE is disposed on the electron control layer ECL. The cathode CE has an integral shape and is commonly disposed in a plurality of light emitting pixels PX (see Figure 7 )middle.

[0173] like Fig.13 As shown in , the upper insulating layer TFL is disposed on the cathode CE. The upper insulating layer TFL may include a plurality of thin films. A cap layer and a thin film encapsulation layer may be included in the upper insulating layer TFL. The thin film encapsulation layer may include a first inorganic layer, an organic layer, and a second inorganic layer.

[0174] The capping layer may include an organic material. The capping layer protects the cathode CE from subsequent processes such as a sputtering process and enhances the light emitting efficiency of the organic light emitting diode LD. The capping layer may have a refractive index greater than that of the first inorganic layer.

[0175] The first inorganic layer and the second inorganic layer protect the display element layer DP-OLED from moisture / oxygen, and the organic layer protects the display element layer DP-OLED from foreign matter such as dust particles. The first inorganic layer and the second inorganic layer may be any one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. In an exemplary embodiment of the present invention, the first inorganic layer and the second inorganic layer may include a titanium oxide layer, an aluminum oxide layer, etc. The organic layer may include an acrylic organic layer, and is not limited thereto.

[0176] In addition, the first electrode E1 of the organic photodiode OPD is disposed on the sixth insulating layer 60. The first electrode E1 is connected to the fourth connection electrode CNE4 through a contact hole CNT-6 penetrating the sixth insulating layer 60. An opening OP2 is disposed in the pixel defining film PDL. The opening OP2 of the pixel defining film PDL exposes at least a portion of the first electrode E1.

[0177] The hole transport layer HTL may be formed of the same material as the hole control layer HCL of the organic light emitting diode LD in the same process as the hole control layer HCL of the organic light emitting diode LD. The photoelectric conversion layer OPL is disposed on the hole transport layer HTL. The photoelectric conversion layer OPL may be disposed in a region corresponding to the opening OP2. Therefore, the photoelectric conversion layer OPL may be individually formed in each of the light sensing pixels FX.

[0178] The electron transport layer ETL is disposed on the photoelectric conversion layer OPL. The hole transport layer HTL and the electron transport layer ETL may be formed separately in a plurality of light sensing pixels FX using an open mask, or may be formed together in a plurality of light sensing pixels FX. In addition, the hole control layer HCL of the luminous pixel PX may be formed of the same material as the hole transport layer HTL of the light sensing pixel FX in the same process as the process of the hole transport layer HTL of the light sensing pixel FX. In addition, the electron control layer ECL of the luminous pixel PX may be formed of the same material as the electron transport layer ETL of the light sensing pixel FX in the same process as the process of the electron transport layer ETL of the light sensing pixel FX.

[0179] The second electrode E2 is disposed on the electron transport layer ETL. The second electrode E2 has an integral shape and is commonly disposed on a plurality of light sensing pixels FX (see Figure 7 ). In addition, the second electrode E2 has an integral shape and can be connected to a plurality of light-emitting pixels PX (see Figure 7 )'s cathode CE are commonly arranged.

[0180] In other words, the cathode CE of the organic light emitting diode LD in the plurality of light emitting pixels PX and the second electrode E2 of the organic photodiode OPD in the plurality of light sensing pixels FX can be formed of the same material in the same process. Figure 8 As shown in FIG. 1 , the cathode CE of the organic light emitting diode LD and the second electrode E2 of the organic photodiode OPD may be electrically connected to a third voltage line VL3 transmitting the first driving voltage ELVSS.

[0181] The display panel with such a structure includes light-emitting pixels having light-emitting elements and light-sensing pixels for sensing external light on the same substrate. Therefore, the display panel can not only display image information, but also sense the user's biometric fingerprint information.

[0182] By implementing light emitting pixels and light sensing pixels in a single panel, the volume of the display device may be minimized and the manufacturing cost of the display device may be reduced.

[0183] Exemplary embodiments of the present invention provide a display device including a display panel capable of sensing a biometric fingerprint input.

[0184] Although the present invention has been described with reference to exemplary embodiments thereof, it will be understood that various changes and modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display panel, comprising: Scan line; Light-emitting pixels, electrically connected to the scan lines and arranged in a first row; light sensing pixels, arranged in the first row, Wherein, the light sensing pixel comprises: a light sensor including a first electrode and a second electrode connected to the first node; a first transistor including a first electrode, a second electrode connected to the first node, and a gate electrode; a second transistor including a first electrode, a second electrode, and a gate electrode connected to the first node; and a third transistor including a first electrode connected to the second electrode of the second transistor, a second electrode connected to a sensing line, and a gate electrode, The light-emitting pixel and the gate electrode of the third transistor are electrically connected to the scan line in common.

2. The display panel according to claim 1, wherein: The light-emitting pixel comprises: a plurality of transistors; and a capacitor connected to at least one of the plurality of transistors, Among them, one transistor among the plurality of transistors includes a gate electrode connected to the scan line.

3. The display panel according to claim 1, wherein: The first electrode of the first transistor receives a first signal, and When the first transistor is turned on, the first node is reset to the first signal.

4. The display panel according to claim 1, wherein: The first electrode of the second transistor is connected to a voltage line.

5. The display panel according to claim 1, wherein: The light-emitting pixel includes a light-emitting diode, and the light-emitting diode includes a first electrode and a second electrode.

6. The display panel according to claim 5, wherein: The second electrode of the photosensor is electrically connected to the second electrode of the light emitting diode.

7. The display panel according to claim 5, wherein: The second electrode of the photosensor is electrically connected to the second electrode of the light emitting diode to receive a driving voltage.

8. An electronic device, comprising: A display panel including a plurality of light-emitting pixels and a plurality of light-sensing pixels; A scan driver configured to output a plurality of scan signals to the plurality of scan lines respectively; as well as a reading circuit, receiving a plurality of sensing signals from the light sensing pixels through a plurality of sensing lines, Wherein, each of the plurality of light sensing pixels comprises: a light sensor including a first electrode and a second electrode connected to the first node; a first transistor including a first electrode, a second electrode connected to the first node, and a gate electrode; a second transistor including a first electrode, a second electrode, and a gate electrode connected to the first node; and a third transistor including a first electrode connected to the second electrode of the second transistor, a second electrode connected to a corresponding sensing line among the plurality of sensing lines, and a gate electrode, Among them, the gate electrodes of the third transistors of the light-emitting pixels arranged in the first row among the multiple light-emitting pixels and the light-sensing pixels arranged in the first row among the multiple light-sensing pixels are commonly electrically connected to corresponding scan lines among the multiple scan lines.

9. The electronic device according to claim 8, wherein: Each of the plurality of light-emitting pixels comprises: a plurality of transistors; and a capacitor connected to at least one of the plurality of transistors, Among them, one transistor among the plurality of transistors includes a gate electrode connected to the corresponding scan line among the plurality of scan lines.

10. The electronic device according to claim 8, wherein: The first electrode of the first transistor receives a first signal, and When the first transistor is turned on, the first node is reset to the first signal.

11. The electronic device according to claim 8, wherein: The first electrode of the second transistor is connected to a voltage line.

12. The electronic device according to claim 8, wherein: Each of the plurality of light emitting pixels includes a light emitting diode including a first electrode and a second electrode connected to a driving voltage line.

13. The electronic device according to claim 12, wherein: The second electrode of the photosensor is connected to the driving voltage line.

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