NAND FLASH read function test method, system, device and host

Abstract

The present invention discloses a NAND FLASH read function test method, system, device, and host. The method includes: the NAND FLASH sends the read data of each port to a local parity check module according to a read function test instruction; controls the parity check module to generate read data to be verified based on the read data of each port; sends the read data to be verified to a test device via any port; receives a test result fed back by the test device; the test result includes a comparison result between the read data to be verified and preset verification data; and determines whether the read function of each port is normal and / or abnormal based on the test result. The present invention integrates the read data of each port through the parity check module to obtain the read data to be verified; enables the read data to be sent to the test device via any port, thereby completing the test; and completes the read function test of each port via any port, thereby improving test efficiency.

Description

Technical Field

[0001] The present invention relates to the field of electronic storage technology, and in particular to a NAND FLASH reading function testing method, system, device and host. Background Art

[0002] With the rapid development of electronic devices, the demand for memory read speed and reliability is becoming increasingly higher. Serial Peripheral Interface NAND Flash (SPI NAND Flash), a non-volatile memory, is widely used due to its small size, low power consumption, and fast read and write speeds. SPI NAND Flash has multiple ports for read operations. Therefore, during the SPI NAND Flash production process, all ports must be tested for read functionality.

[0003] However, the existing SPI NAND Flash test method can only perform read tests through a single port, making it impossible for SPI NAND Flash to implement multi-port parallel read tests, resulting in low SPI NAND Flash read test efficiency.

[0004] Therefore, there is still an urgent need for a method that can improve the efficiency of SPI NAND Flash read testing. Summary of the Invention

[0005] The main purpose of the present invention is to provide a NAND FLASH read function test method, system, device and host to solve the problem that the existing defective SPI NAND Flash cannot implement multi-port parallel read test and the read test efficiency is low.

[0006] To achieve the above object, the present invention provides a method for testing a NAND FLASH read function, the method comprising:

[0007] NAND FLASH sends the read data of each port to the local parity check module according to the read function test instruction;

[0008] Controlling the parity check module to generate read data to be verified according to the read data of each port;

[0009] Sending the read data to be verified to a test device via any port, wherein the test device is a device for detecting NAND FLASH read function;

[0010] Receive the test result fed back by the test device; the test result includes the comparison result of the read data to be verified and the preset verification data;

[0011] According to the test results, it is determined whether the reading function of each port is normal and / or abnormal.

[0012] In some embodiments, controlling the parity check module to generate read data to be verified according to the read data of each port includes:

[0013] Controlling the parity check module to add parity check data to the read data of each port to obtain parity check read data of each port;

[0014] The read data to be verified is generated according to the parity check read data of each port.

[0015] In some embodiments, receiving the test result fed back by the test device includes:

[0016] The comparison result fed back by the test device is received; the comparison result is obtained by the test device splitting the read data to be verified into parity check read data of each port, and comparing the parity check read data of each port with the preset verification data respectively.

[0017] In some embodiments, determining whether the reading function of each port is normal and / or abnormal according to the test result includes:

[0018] If the parity check data read from the port is consistent with the preset check data, it is determined that the reading function of the port is normal; and / or,

[0019] If the parity check data read from the port is inconsistent with the preset check data, it is determined that the reading function of the port is abnormal.

[0020] In some embodiments, after controlling the parity check module to add parity check data to the read data of each port to obtain the parity check read data of each port, the method further includes:

[0021] Performing cyclic redundancy check calculation on the parity check read data of each port to obtain a calculation result of each port;

[0022] The read data to be verified is generated according to the parity check read data of each port and the calculation result of each port.

[0023] In some embodiments, the preset check data includes preset parity check data and preset redundant check data; and the receiving of the test result fed back by the test device includes:

[0024] Receive the comparison result fed back by the test device; the comparison result is obtained by the test device splitting the read data to be verified into parity check read data of each port and calculation results of each port, and comparing the parity check read data of each port with the preset parity check data, and comparing the calculation results of each port with the preset redundant check data.

[0025] The present invention also proposes a NAND FLASH read function test system, which includes a NAND FLASH and a test device; the NAND FLASH includes multiple ports, a parity check module and a storage module; the parity check module is connected to the multiple ports and the storage module; the NAND FLASH communicates with the test device using any one of the ports; the NAND FLASH read function test system can execute any of the above-mentioned NAND FLASH read function test methods.

[0026] In some embodiments, the NAND FLASH further includes a cyclic redundancy check module; the cyclic redundancy check module is connected to the parity check module.

[0027] The present invention also provides a NAND FLASH reading function test device, comprising:

[0028] at least one processor; and,

[0029] a memory communicatively connected to the at least one processor; wherein,

[0030] The memory stores instructions to be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform any one of the above-mentioned methods for testing the NAND FLASH reading function.

[0031] The present invention also provides a NAND FLASH reading function test host, which includes a test host body and multiple NAND FLASH reading function test systems as described in any one of the above; multiple test devices are installed on the test host body.

[0032] The present invention provides a parity check module inside the NAND FLASH, and the parity check module is connected to each port of the NAND FLASH. When the NAND FLASH is read and tested, the read data of each port can be first sent to the parity check module, and the parity check module integrates the read data of each port to obtain the read data to be verified. The read data to be verified is then sent to the test equipment through any port, thereby completing the test. The test equipment can perform a read test on all ports of the NAND FLASH through any port of the NAND FLASH, thereby improving the NAND FLASH read test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the flow of the test method of the NAND FLASH reading function of the present invention;

[0034] Figure 2 Another flowchart of the method for testing the NAND FLASH read function of the present invention is shown;

[0035] Figure 3 Another flowchart of the method for testing the NAND FLASH read function of the present invention is shown;

[0036] Figure 4 A schematic diagram of the structure of a test system for NAND FLASH reading function of the present invention;

[0037] Figure 5 Another structural diagram of the test system for the NAND FLASH read function of the present invention;

[0038] Figure 6 Schematic diagram of the structure of a NAND FLASH reading function test device according to an embodiment of the present invention.

[0039] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings to clearly and completely describe the solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0041] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0042] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element.

[0043] In addition, the descriptions of "first", "second", etc. in the present invention are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0044] To achieve the above object, the present invention provides a method for testing a NAND FLASH read function, the method comprising:

[0045] Step S110, NAND FLASH sends the read data of each port to the local parity check module according to the read function test instruction;

[0046] Step S120, controlling the parity check module to generate read data to be verified according to the read data of each port;

[0047] Step S130, sending the read data to be verified to a test device via any port, wherein the test device is a device for detecting the NAND FLASH read function;

[0048] Step S140: receiving the test result fed back by the test equipment; the test result includes the comparison result of the read data to be verified and the preset verification data;

[0049] Step S150: determining whether the reading function of each port is normal and / or abnormal according to the test result.

[0050] In some embodiments, reference Figure 1 and Figure 4The NAND FLASH read function test method is applied to the NAND FLASH read function test system; wherein, NAND FLASH refers to SPI NAND Flash. The NAND FLASH read function test system may include NAND FLASH and a test device; wherein, the test device is a device for detecting the NAND FLASH read function. NAND FLASH includes multiple ports, a parity check module and a storage module, wherein, Figure 4 IO0 to IOn represent multiple ports.

[0051] It can be understood that, in this embodiment, the NAND FLASH sends the read data to be verified to the test equipment via any port, wherein any port is taken as IO0 for illustration.

[0052] First, connect any of the multiple ports of the NAND FLASH to a test device that detects the read function of the NAND FLASH. When the test device needs to detect the read function of each port of the NAND FLASH, it will send a read function test command to the NAND FLASH.

[0053] NAND FLASH will control the storage module to send the read data of each port to the local parity check module according to the read function test instruction; wherein, the local parity check module refers to the parity check module set inside the NAND FLASH.

[0054] It can be understood that, in this embodiment, the ports in the multi-ports of the NAND FLASH refer to ports provided on the surface of the NAND FLASH for connecting to external devices, wherein the external devices include test equipment, computers, and the like.

[0055] The storage module may be provided with multiple read interfaces; these read interfaces are used to directly read data stored in the storage module. When a port is directly connected to a read interface, the port can directly read data from the storage module via the read interface. In this embodiment, each read interface on the storage module is not directly connected to a corresponding port; instead, each read interface on the storage module is indirectly connected to a corresponding port via a parity check module. The data read by each port refers to the data obtained by that port from the corresponding read interface on the storage module.

[0056] The NAND FLASH control parity check module performs parity checking on the read data from each port and integrates the read data from each port to obtain the read data to be verified. When the read data from each port needs to be output through a single port, the read data from each port needs to be integrated. After the read data from each port is integrated, it can be output through any port.

[0057] The NAND FLASH sends the read data to be verified to the test equipment through any port. The test equipment compares the read data to the preset verification data, obtains the comparison results of the read function of each port, and then generates the test results based on the comparison results of the read function of each port. The test equipment also sends the test results back to the NAND FLASH.

[0058] NAND FLASH will receive the test results fed back by the test equipment; the test results are the comparison results between the read data to be verified and the preset verification data.

[0059] The NAND FLASH determines whether the read function of each port is normal and / or abnormal based on the test results. Three possible situations may occur. For example, the first situation: the read function of all ports is normal. The second situation: the read function of all ports is abnormal. The third situation: the read function of some ports is normal and the read function of some ports is abnormal.

[0060] This embodiment provides a parity check module inside the NAND FLASH, and the parity check module is connected to each port of the NAND FLASH. When the NAND FLASH is read, the read data of each port can be first sent to the parity check module. The parity check module integrates the read data of each port to obtain the read data to be verified. The read data to be verified is then sent to the test equipment through any port to complete the test. The test equipment can perform a read test on all ports of the NAND FLASH through any port of the NAND FLASH, thereby improving the efficiency of the NAND FLASH read test.

[0061] In some embodiments, the control parity check module generates the read data to be verified according to the read data of each port, including:

[0062] Step S160, controlling the parity check module to add parity check data to the read data of each port to obtain parity check read data of each port;

[0063] Step S161 : generating read data to be verified according to the parity check read data of each port.

[0064] In this embodiment, referring to Figure 2When NAND FLASH executes step S120, it controls the parity check module to perform parity check on the read data. NAND FLASH controls the parity check module to add corresponding parity check data to the read data of each port, so that the read data of each port is accompanied by corresponding parity check data, thereby obtaining parity check read data of each port. By checking the parity check data, the integrity and accuracy of the read data can be judged. NAND FLASH also integrates the parity check read data of each port to obtain the read data to be verified. Among them, the read data to be verified is a collection of the parity check read data of each port; if the read data to be verified is split, the parity check read data of each port can be obtained.

[0065] In some embodiments, the aforementioned step of receiving the test results fed back by the test device includes:

[0066] Receive the comparison result fed back by the test equipment; the comparison result is obtained by the test equipment splitting the read data to be verified into parity check read data of each port, and comparing the parity check read data of each port with the preset verification data respectively.

[0067] In this embodiment, the test results received by the NAND FLASH are the comparison results of the parity read data of each port with the preset verification data. The comparison results are obtained by the test equipment. The test equipment first splits the read data to be verified into the parity read data of each port, and then compares the parity read data of each port with the preset verification data to obtain the comparison results of the parity read data of each port.

[0068] In some embodiments, determining whether the reading function of each port is normal and / or abnormal according to the test results includes:

[0069] If the parity check data read from the port is consistent with the preset check data, it is determined that the reading function of the port is normal; and / or,

[0070] If the parity check data read from the port is inconsistent with the preset check data, it is determined that the reading function of the port is abnormal.

[0071] In this embodiment, after NAND FLASH receives the test results, it can determine whether the reading function of each port is normal and / or abnormal based on the test results. In the test results, there may be three situations. For example, the first one: the parity check read data of all ports is consistent with the preset verification data; in this case, it can be determined that the reading function of all ports is normal. The second one: the parity check read data of all ports is inconsistent with the preset verification data; in this case, it can be determined that the reading function of all ports is abnormal. The third one: the parity check read data of some ports is consistent with the preset verification data, and the parity check read data of other ports is inconsistent with the preset verification data; in this case, it can be determined that the reading function of the ports whose parity check read data is consistent with the preset verification data is normal, and the reading function of the ports whose parity check read data is inconsistent with the preset verification data is abnormal.

[0072] In some embodiments, after the parity check module is controlled to add parity check data to the read data of each port to obtain the parity check read data of each port, the method further includes:

[0073] Step S170, performing cyclic redundancy check calculation on the parity check read data of each port to obtain calculation results of each port;

[0074] Step S171 : generating read data to be verified according to the parity check read data of each port and the calculation result of each port.

[0075] In this embodiment, referring to Figure 3 and Figure 5 NAND FLASH can also include a cyclic redundancy check (CRC) module, which is connected to the parity check module. After the parity check module adds parity data to the read data from each port to obtain the parity read data for each port, the parity check module also sends the parity read data for each port to the CRC module. The CRC module performs a CRC calculation on the parity read data from each port to obtain the calculation results for each port. Each parity read data corresponds to a calculation result. By combining the parity read data from each port and its corresponding calculation result, the read data to be verified can be obtained.

[0076] In some embodiments, the preset check data includes preset parity check data and preset redundant check data; and the test result feedback received from the test device includes:

[0077] Receive the comparison result fed back by the test equipment; the comparison result is obtained by the test equipment splitting the read data to be verified into the parity check read data of each port and the calculation result of each port, and comparing the parity check read data of each port with the preset parity check data, and comparing the calculation result of each port with the preset redundant check data.

[0078] In this embodiment, the preset verification data includes preset parity check data and preset redundant check data. In this case, the comparison result includes comparison results for two types of data. The test device first splits the read data to be verified into parity check read data for each port and calculation results for each port; then, the parity check read data for each port is compared with the preset parity check data to obtain comparison results for the parity check data of each port; and the calculation results for each port are compared with the preset redundant check data to obtain comparison results for the redundant check data of each port. The comparison results of these two types of data are integrated to obtain a comparison result. The test device feeds the comparison result back to the NAND FLASH. The NAND FLASH receives the comparison result fed back by the test device.

[0079] In this embodiment, the NAND FLASH needs to determine that the parity check read data of the port is consistent with the preset check data and the calculation result of the port is consistent with the preset redundancy check data before determining that the reading function of the port is normal.

[0080] The present invention provides a parity check module inside the NAND FLASH, and the parity check module is connected to each port of the NAND FLASH. When the NAND FLASH is read and tested, the read data of each port can be first sent to the parity check module, and the parity check module integrates the read data of each port to obtain the read data to be verified. The read data to be verified is then sent to the test equipment through any port, thereby completing the test. The test equipment can perform a read test on all ports of the NAND FLASH through any port of the NAND FLASH, thereby improving the NAND FLASH read test efficiency.

[0081] The present invention also proposes a NAND FLASH read function test system, which includes a NAND FLASH and a test device; the NAND FLASH includes multiple ports, a parity check module and a storage module; the parity check module is connected to the multiple ports and the storage module; the NAND FLASH communicates with the test device using any port; the NAND FLASH read function test system can execute any of the above-mentioned NAND FLASH read function test methods.

[0082] In this embodiment, see Figure 4The NAND FLASH read function test system includes a NAND FLASH and a test device. The test device is a device for detecting the NAND FLASH read function. The NAND FLASH includes multiple ports, a parity check module, and a storage module. Figure 4 IO0 to IOn represent multiple ports; IO0 is connected to the test equipment for illustration. The parity check module is connected to multiple ports and the storage module; and the NAND FLASH communicates with the test equipment via IO0.

[0083] In some embodiments, the NAND FLASH further includes a cyclic redundancy check module; the cyclic redundancy check module is connected to the parity check module.

[0084] In this embodiment, see Figure 5 , NAND FLASH may also include a cyclic redundancy check module; the cyclic redundancy check module is connected to the parity check module; the cyclic redundancy check module may perform a secondary check on the data checked by the parity check module.

[0085] The present invention also proposes a NAND FLASH reading function test device, see Figure 6 , Figure 6 It is a structural diagram of a test device for NAND FLASH reading function in a hardware operating environment involved in an embodiment of the present invention.

[0086] The NAND FLASH read function test device of the embodiment of the present invention may be a processor capable of executing the NAND FLASH read function test method; there is at least one processor. Figure 6 As shown, the test device for the NAND FLASH reading function may include: a processor 1001 (such as a CPU), a network interface 1004, a user interface 1003, a memory 1005 and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0087] Those skilled in the art will understand that Figure 6The structure of the test device for the NAND FLASH read function shown in the figure does not constitute a limitation on the test device for the NAND FLASH read function, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0088] like Figure 6 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0089] exist Figure 6 In the NAND FLASH reading function test device shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the processor 1001 can be used to call the computer program stored in the memory 1005. When the computer program is called and executed by the processor 1001, the steps of the above-mentioned NAND FLASH reading function test method are implemented.

[0090] The present invention also provides a NAND FLASH reading function test host, which includes a test host body and multiple NAND FLASH reading function test systems as described above; multiple test devices are installed on the test host body.

[0091] In this embodiment, a NAND FLASH read function test host includes a test host body and multiple NAND FLASH read function test systems. Multiple test devices are mounted on the test host body. This allows the NAND FLASH read function test host to simultaneously test the read function of multiple NAND FLASHs, improving test efficiency.

[0092] Based on the computer program proposed in the aforementioned embodiment, the present invention further proposes a storage medium storing the computer program. When the computer program is executed by a controller, the NAND FLASH reading function test method described in the aforementioned embodiment is implemented.

[0093] The present invention further provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for testing the NAND FLASH reading function as described in any one of the above technical solutions are implemented.

[0094] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A method for testing NAND FLASH read function, characterized in that: The NAND FLASH read function test method includes: NAND FLASH sends the read data of each port to the local parity check module according to the read function test instruction; Controlling the parity check module to generate read data to be verified according to the read data of each port; Sending the read data to be verified to a test device via any port, wherein the test device is a device for detecting the NANDFLASH read function; Receive a test result fed back by the test device; the test result includes a comparison result of the read data to be verified and preset verification data; Determining whether the reading function of each port is normal and / or abnormal according to the test results; The controlling the parity check module to generate read data to be verified according to the read data of each port includes: Controlling the parity check module to add parity check data to the read data of each port to obtain parity check read data of each port; generating the read data to be verified according to the parity check read data of each port; The NAND FLASH includes multiple ports, a parity check module and a storage module. The storage module is provided with multiple read interfaces. Each of the read interfaces of the storage module is indirectly connected to each corresponding port through the parity check module.

2. The method for testing the NAND FLASH read function according to claim 1, wherein: The receiving of the test result fed back by the test device includes: The comparison result fed back by the test device is received; the comparison result is obtained by the test device splitting the read data to be verified into parity check read data of each port, and comparing the parity check read data of each port with the preset verification data respectively.

3. The method for testing the NAND FLASH read function according to claim 2, wherein: Determining whether the reading function of each port is normal and / or abnormal according to the test result includes: If the parity check data read from the port is consistent with the preset check data, it is determined that the reading function of the port is normal; and / or, If the parity check data read from the port is inconsistent with the preset check data, it is determined that the reading function of the port is abnormal.

4. The method for testing the NAND FLASH read function according to claim 1, wherein: After controlling the parity check module to add parity check data to the read data of each port to obtain the parity check read data of each port, the method further includes: Performing cyclic redundancy check calculation on the parity check read data of each port to obtain a calculation result of each port; The read data to be verified is generated according to the parity check read data of each port and the calculation result of each port.

5. The method for testing the NAND FLASH read function according to claim 4, wherein: The preset check data includes preset parity check data and preset redundant check data; The receiving of the test result fed back by the test device includes: receiving the comparison result fed back by the testing device; The comparison result is obtained by the test equipment splitting the read data to be verified into the parity check read data of each port and the calculation result of each port, and comparing the parity check read data of each port with the preset parity check data, and comparing the calculation result of each port with the preset redundant check data.

6. A NAND FLASH reading function test system, characterized in that: The NAND FLASH read function test system includes a NAND FLASH and a test device; the NAND FLASH includes multiple ports, a parity check module and a storage module; the parity check module is connected to multiple ports and the storage module; the NAND FLASH communicates with the test device using any one of the ports; the NAND FLASH read function test system can execute the NAND FLASH read function test method according to any one of claims 1 to 5.

7. The NAND FLASH read function test system according to claim 6, characterized in that: The NANDFLASH further includes a cyclic redundancy check module; the cyclic redundancy check module is connected to the parity check module.

8. A NAND FLASH reading function test device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions to be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the NAND FLASH reading function testing method according to any one of claims 1 to 5.

9. A NAND FLASH reading function test host, characterized in that: The NAND FLASH read function test host comprises a test host body and a plurality of NAND FLASH read function test systems according to any one of claims 6 to 7; and a plurality of the test devices are mounted on the test host body.

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