Method for realizing high-dynamic signal capture on FPGA (Field Programmable Gate Array) based on PMF-FFT algorithm

Abstract

The invention relates to a method for realizing high dynamic signal capture on an FPGA based on a PMF-FFT algorithm, and belongs to the technical field of satellite communication system signal capture. According to the method, a digital intermediate frequency signal source is generated by using Matlab and Vivado software, and I and Q paths of baseband signals are obtained through digital down-conversion and down-sampling processing. A plurality of parallel coherent integration modules are adopted to carry out partial correlation operation, and a result is stored in a ping-pong RAM (Random Access Memory). Through zero padding operation and FFT operation, an FFT output value is obtained, modular squaring is carried out, and a maximum peak value and an index value thereof are obtained through maximum and minimum value comparison. And finally, comparing the maximum peak value with a preset threshold value, and if the maximum peak value exceeds the preset threshold value, calculating a frequency offset estimation value. The FPGA platform is adopted, the PMF-FFT algorithm and the parallel processing technology are combined, and the problems that in the high dynamic environment, the signal capturing time is too long, the capturing frequency offset range is small, and hardware resource consumption is large are solved.

Description

Technical Field

[0001] The invention belongs to the technical field of satellite communication system signal capture, and relates to a method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm. Background Art

[0002] In the highly dynamic environment of satellite communications, large Doppler frequency deviation and Doppler frequency deviation change rate bring problems to the signal processing of the communication receiver; the carrier of the received signal generates a high Doppler frequency shift, which causes the pseudo-code correlation peak to drop sharply, resulting in a poor capture probability or the inability to find the signal. Traditional capture algorithms such as the time domain serial method are not suitable for high-dynamic scenarios due to the long capture time; the cyclic correlation algorithm based on frequency domain parallelism reduces the capture time by increasing hardware costs and reducing hardware utilization; the PMF-FFT algorithm is a code phase-Doppler two-dimensional parallel capture algorithm with fast search speed and can overcome the problem of severe attenuation of correlation peaks in high dynamic and large frequency deviations. It can not only quickly complete the code phase search, but also accurately estimate the frequency deviation when the Doppler frequency deviation is large.

[0003] However, although the theory of PMF-FFT capture algorithm and its improved algorithm is becoming more and more perfect, there is no universal hardware implementation method. The hardware implementation of PMF-FFT algorithm includes the parallel implementation of multiple partially matched filters (PMF), the implementation of FFT module and the implementation of storage module and other modules. If the total length of the matched filter is too long in the design, the direct matched filter design method will consume too many register resources and multiplier and adder resources, which is a design difficulty. When the FFT operation is implemented in hardware, it requires operation time. During the operation time, the FFT module cannot process data, but the partially matched filter is still generating data continuously. How to ensure that the data is not lost is also a design difficulty. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm. In view of the current situation that the capture time of the existing capture algorithm is too long, the capture frequency deviation range is small, and the hardware consumption resources are too large when capturing high dynamic satellites, a method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm is provided, by simulating and generating a digital intermediate frequency signal source, obtaining a local replica carrier mixing signal, multiplying the digital intermediate frequency signal with the local replica carrier mixing signal, obtaining a down-converted baseband signal, down-sampling the down-converted baseband signal, obtaining I and Q two-way down-sampled baseband signals, storing the two-way signals in a ping-pong buffer, and then inputting the data in the buffer into a partial matched filter module to obtain partial correlation values, storing the partial correlation values ​​in a memory, and performing a zero-filling operation, finally transmitting the zero-filled data to the FFT IP core for FFT operation, outputting the operation data, and obtaining the maximum peak value and its coordinate index value by taking the square of the modulus of the operation data, and performing a maximum value comparison, and finally comparing the maximum peak value with the threshold value, if it exceeds the threshold value, calculating the frequency deviation estimation value.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] Based on a signal source module, a digital down-conversion module, a down-sampling module, a data storage module, a pseudo code generation module, a partial coherence integration module, an FFT operation module, and a threshold decision module. The method includes:

[0007] Use Matlab and Vivado software to jointly generate the digital intermediate frequency signal source required for simulation;

[0008] The digital intermediate frequency signal is multiplied by the carrier signal generated by the local carrier generator, and a digital mixing operation is performed to down-convert the digital intermediate frequency signal into two I and Q baseband signals;

[0009] Down-sampling the generated digital baseband signal;

[0010] The downsampled data is stored in the ping-pong RAM, and the pseudo code generation module generates a pseudo code identical to the received signal with adjustable phase;

[0011] Inputting the signal with frequency offset and symbol phase offset into the partial coherence integration module to perform partial correlation operation to obtain a partial correlation value;

[0012] Send each partial correlation value into the ping-pong RAM in the specified order;

[0013] Perform n-point zero padding operation on the data stored in the ping-pong RAM;

[0014] The zero-filled data of each memory is sequentially transmitted to the FFT IP core for FFT operation and the operation data is output;

[0015] Take the square of the modulus of the operation data;

[0016] Compare the values ​​of the squared modulus to the maximum value and obtain the maximum peak value and its index value;

[0017] The maximum peak value is compared with a preset threshold value, and if it exceeds the preset threshold value, a frequency deviation estimation value is calculated;

[0018] Furthermore, the method for generating a signal source includes:

[0019] Use Matlab software to generate pseudo-random codes and sine-cosine waveforms and save the data as .coe files;

[0020] Use Vivado software to read the .coe file, and perform BPSK modulation on the generated pseudo-random code and sine and cosine waves to generate a digital intermediate frequency signal source;

[0021] Furthermore, the down-conversion and down-sampling method comprises:

[0022] Create a single-port ROM to generate a local carrier with the same frequency as the signal source;

[0023] Down-convert the received digital intermediate frequency signal and the generated local carrier to generate two I and Q baseband signals;

[0024] Perform mean downsampling processing on the two generated I and Q baseband signals;

[0025] Furthermore, the method further comprises:

[0026] Set the parameters of the PMF-FFT algorithm, including the total correlation length N and the partial matched filter length X, according to the pseudo-random code rate f c , the sampling rate of the pseudo-random code is f s , and the pseudo code length for matched filtering is L, the total correlation length N is obtained;

[0027] The length of the matched filter X depends on the actual frequency deviation range f of the system. d To determine, the frequency deviation range estimated by the algorithm is f d According to the frequency deviation range f d The frequency resolution Δf is obtained u =f d / N;

[0028] N=L*(f s / f c )

[0029] N is the total data length and also the total correlation length, and L is the pseudo code length used for matched filtering;

[0030] f d =f s / X

[0031] f d is the frequency deviation range that can be estimated by the PMF-FFT algorithm, f s is the sampling rate of the spread spectrum code, X is the length of the partial matched filter and the number of points for partial correlation operation;

[0032] Δf u =f d / Z

[0033] Δf u is the frequency resolution of the PMF-FFT algorithm, f d is the frequency deviation range that can be estimated by the PMF-FFT algorithm, and Z is the number of points for FFT after zero padding.

[0034] Furthermore, the design of the partial coherent integration module adopts multiple parallel correlation operation modules.

[0035] Furthermore, the method of the plurality of parallel related operation modules includes:

[0036] Step 1: Create 60 parallel correlators for I and Q paths respectively;

[0037] Step 2: Create a read-only memory ROM to store the sampled local pseudo code;

[0038] Step 3: The partial correlation operation module groups the N stored data into D groups, where D represents the number of partial matched filters in the partial correlation operation module, and each group has X data, that is, the length of each sub-matched filter, N=DX; the local pseudo code phase is slid, and each parallel correlator slides a code phase, so 60 parallel correlators can detect 60 code phases at a time, and each sliding code sequence is sent to the partial matched filter for correlation operation with the received signal to obtain the data after the correlation operation.

[0039] Furthermore, the data after the relevant operations are sequentially sent to the ping-pong cache, and the ping-pong cache address state machine controls the reading and writing of the data. The storage method includes:

[0040] The correlation operation data from the first correlator is stored in the 0th position of the ping RAM, the correlation operation data from the second correlator is stored in the Dth position of the ping RAM, the data from the third correlator is stored in the 2Dth position of the ping RAM, and the data from the last correlator is stored in the 60D-1 position of the ping RAM. After 2X clocks, the correlation operation data from the first correlator is stored in the 1st position of the RAM, the data from the second correlator is stored in the 2D+1th position of the RAM... All data are stored in the corresponding RAM positions in sequence.

[0041] Further, the method of sequentially transmitting the zero-filled data in the ping-pong RAM to the FFT IP core for FFT calculation includes:

[0042] First, the D correlation values ​​in the first RAM are padded with zeros to an integer power of 2 and then sent to the FFT IP core for FFT operation. After the operation is completed, switch to the second RAM and padded the D correlation values ​​in it to an integer power of 2 and then send them to the FFT IP core for FFT operation. After that, they are alternately sent to the FFT IP core in a pipeline manner.

[0043] The real and imaginary parts of the FFT output are further squared modulo each other to obtain the index value corresponding to each FFT output value.

[0044] Furthermore, the method for calculating the frequency offset estimation value includes:

[0045] Compare the maximum peak value with a preset threshold value;

[0046] If it is lower than the threshold, the acquisition is not successful; if it is higher than the threshold, the acquisition is successful. At this time, the index value of the corresponding coordinate of the peak is taken to obtain the frequency deviation estimation value:

[0047] f d =(Z*(1-Max_x / Z)+1) / (Z*X*(1 / f s ))

[0048] f d is the frequency offset estimate, Z is the number of fft points, Max_x is the index value corresponding to the highest peak, and X is the length of each matched filter.

[0049] The beneficial effects of the present invention are:

[0050] The present invention adopts FPGA as the hardware design platform, integrates the algorithm with FPGA, and fully combines the great advantages of the PMF-FFT algorithm in searching the Doppler frequency deviation range and capture time with the advantages of rich FPGA design resources and high-speed parallel data processing, and proposes a method for realizing signal capture on FPGA based on the PMF-FFT algorithm.

[0051] The present invention adopts a method of multiple parallel coherent integrators, which can search and perform coherent integration on multiple code phases at the same time, thereby accelerating the capture speed and shortening the capture time.

[0052] The present invention optimizes the address when storing data, improves data throughput, reduces resource conflicts, increases access speed, and ensures that data is not lost.

[0053] The PMF-FF algorithm includes main modules such as downsampling, multiple partially matched filters, cache, FFT operation and threshold judgment; this design cleverly controls the operation of each module so that the modules can cooperate with each other to ensure that the data is processed in an orderly manner and the correctness of data transmission is guaranteed.

[0054] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0056] Figure 1 It is the structure diagram of PMF-FFT capture algorithm;

[0057] Figure 2 It is the structure diagram of the signal source;

[0058] Figure 3 It is a structural diagram of down-conversion and down-sampling;

[0059] Figure 4 It is the internal logic diagram of the PMF-FFT algorithm;

[0060] Figure 5 is the parallel coherent integration graph;

[0061] Figure 6 It is a schematic diagram of the reading process;

[0062] Figure 7 It is a schematic diagram of the partial matching filtering result storage process;

[0063] Figure 8 Schematic diagram of the RAM zero-filling process. DETAILED DESCRIPTION

[0064] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0065] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0066] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0067] The parameters in the PMF-FFT capture system include the actual frequency deviation range f of the system. d , spreading code rate f c , sampling rate f s , the pseudo code length L for the matched filter, the total correlation length N, the length of the partially matched filter X, the number of partially matched filters D, the number of zero-filling points n, the number of points sent to the FFT after zero-filling is Z, and the frequency offset estimation range of the algorithm f d , frequency resolution Δf u .

[0068] like Figure 1 to Figure 4 The figure shows a method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm of the present invention, and the specific steps are as follows:

[0069] Step 1: Use Matlab and Vivado software to jointly generate the digital intermediate frequency signal source required for simulation.

[0070] Step 2: After the simulated intermediate frequency signal is down-converted through the local carrier, the I and Q baseband signals are output. The I and Q baseband signals are averaged down-sampled and then output to the ping-pong RAM for buffering.

[0071] Step 3: The cached data is passed through D partial matched filters in a pipeline manner. Each partial filter outputs a partial correlation value, and the D partial matched filters output D partial correlation values.

[0072] Step 4: Fill n points with 0. Fill n points with 0 to the power of 2 after the partial correlation value of point D in the previous step to form point Z.

[0073] Step 5: Perform Z-point FFT operation. Perform Z-point FFT operation on the Z-point data consisting of the partial correlation value of point D and the zero value of point n.

[0074] Step 6: Square the modulus. The output of the FFT operation is an imaginary number, including the real part and the imaginary part. The amplitude of the FFT operation result is required in the project, and the modulus operation on the imaginary number is equivalent to calculating the amplitude. Then the square operation is performed. There are two reasons for the square operation: (1) The value of the square of the modulus is positively correlated with the value of the modulus, which does not affect the peak judgment. (2) The square root operation is relatively complex in hardware implementation.

[0075] If the imaginary number is x = a + jb, then the modulus (that is, the amplitude) The square of the modulus x 2 =a 2 +b 2 .

[0076] Where a is the real part of the complex number and b is the imaginary part of the real number.

[0077] Step 6: Compare the extreme values ​​and obtain the extreme value size and its coordinate K.

[0078] Step 7: Threshold judgment. Compare the maximum peak value obtained in the previous step with the preset threshold value. If it is greater than the threshold value, it means that the capture is successful. Otherwise, it is less than the threshold value, which means that the capture is not successful.

[0079] Step 8: Doppler frequency shift estimation: If the capture is successful, the coordinate K value corresponding to the maximum value obtained in step 6 is used to obtain the Doppler frequency shift estimation.

[0080] f d =(Z*(1-Max_x / Z)+1) / (Z*X*(1 / f s ))

[0081] f dis the frequency offset estimate, Z is the number of fft points, Max_x is the index value corresponding to the highest peak, and X is the length of each matched filter.

[0082] like Figure 2 As shown in the figure, it is the structure diagram of the generated intermediate frequency signal source. The specific steps are as follows:

[0083] Step 1: Generate pseudo-random code and sine-cosine waveforms using Matlab software and save the data as a .coe file.

[0084] Step 2: Create two read-only memories ROM in Vivado and read the .coe file generated in step 1.

[0085] Step 3: Perform BPSK modulation on the generated pseudo-random code and sine and cosine waves to generate a modulated intermediate frequency signal.

[0086] like Figure 3 As shown in the figure, it is a down-conversion and down-sampling structure diagram, and the specific steps are as follows:

[0087] Step 1: Use the local carrier NCO to generate two sine and cosine signals with the same frequency as the intermediate frequency signal.

[0088] Step 2: Multiply the generated sine and cosine waves with the intermediate frequency signal respectively, and down-convert them into I and Q baseband signals.

[0089] Step 3: Perform mean downsampling processing on the I and Q baseband signals to obtain downsampled signals.

[0090] like Figure 4 As shown in the figure, it is the internal logic diagram of the PMF-FFT algorithm. The specific steps are as follows:

[0091] Step 1: Send the data in the cache to the partial coherent integration module for correlation calculation.

[0092] Step 2: Send the data after the partial correlation result to the ping-pong cache, and the address is controlled by the ping-pong cache state machine.

[0093] Step 3: Send the cached data to the FFT module for calculation to obtain the result.

[0094] like Figure 5 and Figure 6The figure shows a schematic diagram of parallel coherent integration. The partially coherent integration module groups the N stored data into D groups, where D represents the number of partial matching filters in the partial correlation operation module, and each group has X data, that is, the length of each sub-matching filter, N = DX; the local pseudo code phase is slid, and each parallel correlator slides a code phase, so 60 parallel correlators can detect 60 code phases at a time, and each sliding code sequence is sent to the partial matching filter for correlation operation with the received signal to obtain the data after the correlation operation.

[0095] like Figure 7 and Figure 8 As shown in the figure, it is a schematic diagram of the partial matched filtering result storage process and zero padding operation. After PMF completes the calculation of the partial correlation result, the result needs to be saved in RAM for subsequent FFT module processing. Since this design adopts the idea of ​​pipeline, the subsequent processing uses ping-pong operation, so two RAMs are needed to read and write alternately; the read and write operation can be divided into two stages. When the write operation is performed, the correlation operation data from the first partial correlator is stored in the 0th position in the "ping" RAM, the correlation operation data from the second correlator is stored in the Dth position in the "ping" RAM, the third correlator data is stored in the 2D position in the "ping" RAM, and the data from the last correlator correlation operation is stored in the 60D-1 position in the "ping" RAM. After 2X clocks, the correlation operation data from the first correlator is stored in the 1st position in the RAM, and the data from the second correlator is stored in the 2D+1 position in the RAM... All data are stored in the corresponding "ping" RAM positions in sequence. After the storage is completed, the first D data are padded with zeros to Z point (Z is a power of 2); when the second coherent integration is started, the value in the "ping" RAM is read and sent to the FFT, and the value of the second coherent integration is written into the "pong". During the subsequent coherent integration time, the RAM is read and written at the same time.

[0096] The FFT operation module is implemented using Vivado's own FFT IP Core, using Radix-2, Burst I / O structure, data format: Fixed Point, scaling option: scaled. Memory option: Block RAM, optimization option: complex multiplier: Use 3-multiplier structure.

[0097] The I and Q results read from the partial matched filter structure storage module are used as the input data of the real part and imaginary part of the FFT module under the action of the clock. When the input data valid is pulled high, the FFT IP core pulls the ready signal high, and data transmission can be carried out. After receiving the Z point data, it will perform calculations and no longer receive data. The real and imaginary parts of the FFT results are output and sent to the square root module and the FFT threshold judgment module.

[0098] In the present invention, since data is continuously input, and the number of RAM blocks inside the FPGA is limited, and the amount of data stored is limited, multiple caches (specifically two blocks, A and B) are used to access data in turn, and the data writing operation and the subsequent algorithm reading the data occur simultaneously, but the cache areas operated by each other are different, so there will be no data reading and writing conflicts. The design uses ping-pong RAM multiple times to greatly improve system resource consumption and alleviate the pressure on the capture algorithm operation to a large extent.

[0099] In the present invention, the PMF-FFT algorithm shortens the correlation integration time by 1 / X (X is the number of partially matched filters) compared with conventional methods such as serial capture or code phase parallel capture. Therefore, under the same capture decision threshold, its frequency analysis range is expanded by X times, and a large number of Doppler frequency deviations and high dynamic signals can be quickly captured.

[0100] In the present invention, compared with the FFT-based cyclic correlation algorithm, the hardware implementation of the present invention adopts an FFT core with a smaller number of points (128 points in the present invention), which can effectively save hardware resources.

[0101] In the present invention, the ping-pong reading and writing of partial matched filtering results can improve the utilization rate of the FFT IP core.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm, characterized in that: The steps include: Use Matlab and Vivado software to jointly generate the digital intermediate frequency signal source required for simulation; The digital intermediate frequency signal is multiplied by the carrier signal generated by the local carrier generator, and a digital mixing operation is performed to down-convert the digital intermediate frequency signal into two I and Q baseband signals; Down-sampling the generated digital baseband signal; The downsampled data is stored in the ping-pong RAM, and the pseudo code generation module generates a pseudo code identical to the received signal with adjustable phase; Inputting the signal with frequency offset and symbol phase offset into the partial coherence integration module to perform partial correlation operation to obtain a partial correlation value; Send each partial correlation value into the ping-pong RAM in the specified order; Perform n-point zero padding operation on the data stored in the ping-pong RAM; The zero-filled data of each memory is sequentially transmitted to the FFT IP core for FFT operation, and the operation data is output; Take the square of the modulus of the operation data; Compare the values ​​of the squared modulus to the maximum value and obtain the maximum peak value and its index value; The maximum peak value is compared with a preset threshold value. If it exceeds the threshold value, the frequency deviation estimate is calculated.

2. The method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm according to claim 1, characterized in that: The digital intermediate frequency signal source required for the generation simulation is specifically: Use Matlab software to generate pseudo-random codes and sine-cosine waveforms and save the data as .coe files; Use Vivado software to read the .coe file and perform BPSK modulation on the generated pseudo-random code and sine and cosine waves to generate a digital intermediate frequency signal source.

3. The method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm according to claim 1, characterized in that: The downsampling process of the generated digital baseband signal is specifically as follows: Create a single-port ROM to generate a local carrier with the same frequency as the signal source; Down-convert the received digital intermediate frequency signal and the generated local carrier to generate two I and Q baseband signals; The two generated I and Q baseband signals are subjected to mean downsampling processing.

4. The method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm according to claim 1, characterized in that: The method for capturing high dynamic signals also includes: Set the parameters of the PMF-FFT algorithm, including the total correlation length N and the partial matched filter length X, according to the pseudo-random code rate f c , the sampling rate of the pseudo-random code is f s , and the pseudo code length for matched filtering is L, the total correlation length N is obtained; The length of the matched filter X depends on the actual frequency deviation range f of the system. d To determine, the frequency deviation range estimated by the algorithm is f d According to the frequency deviation range f d The frequency resolution Δf is obtained u =f d / N; N=L*(f s / f c ) N is the total data length and also the total correlation length, and L is the pseudo code length used for matched filtering; f d =f s / X f d is the frequency deviation range that can be estimated by the PMF-FFT algorithm, f s is the sampling rate of the spread spectrum code, X is the length of the partial matched filter and the number of points for partial correlation operation; Δf u =f d / Z Δf u is the frequency resolution of the PMF-FFT algorithm, f d is the frequency deviation range that can be estimated by the PMF-FFT algorithm, and Z is the number of points for FFT after zero padding.

5. The method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm according to claim 1, characterized in that: The design of the partial coherent integration module adopts multiple parallel correlation operation modules.

6. The method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm according to claim 5, characterized in that: The use of multiple parallel related operation modules is specifically: 60 parallel correlators are created for each of the I and Q paths; Create a read-only memory ROM to store the sampled local pseudo code; The partial correlation operation module groups the N stored data into D groups, where D represents the number of partial matched filters in the partial correlation operation module, and each group has X data, that is, the length of each sub-matched filter, N=DX; the local pseudo code phase is slid, and each parallel correlator slides a code phase. 60 parallel correlators can detect 60 code phases at a time. Each sliding code sequence is sent to the partial matched filter for correlation operation with the received signal to obtain the data after the correlation operation.

7. The method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm according to claim 6, characterized in that: The data after the related operation is sequentially sent to the ping-pong cache, and the ping-pong cache address state machine controls the reading and writing of the data. The storage method includes: The correlation calculation data from the first correlator is stored in the 0th position in the ping-pong RAM, the correlation calculation data from the second correlator is stored in the Dth position in the ping-pong RAM, the data from the third correlator is stored in the 2Dth position in the ping-pong RAM, and the data from the correlation calculation of the last correlator is stored in the 60D-1 position in the ping-pong RAM; after 2X clocks, the correlation calculation data from the first correlator is stored in the 1st position in the RAM, the data from the second correlator is stored in the 2D+1th position in the RAM...all data are stored in the corresponding RAM positions in sequence.

8. The method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm according to claim 1, characterized in that: The method of sequentially transmitting the zero-filled data in the ping-pong RAM to the FFT IP core for FFT calculation includes: First, the D correlation values ​​in the first RAM are padded with zeros to an integer power of 2 and then sent to the FFT IP core for FFT operation. After the operation is completed, switch to the second RAM and padded the D correlation values ​​in it to an integer power of 2 and then send them to the FFT IP core for FFT operation. After that, they are alternately sent to the FFT IP core in a pipeline manner.

9. The method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm according to claim 1, characterized in that: The real part and the imaginary part of the FFT output result are squared modulo each other to obtain the index value corresponding to each FFT output value.

10. The method for realizing high dynamic signal capture on FPGA based on PMF-FFT algorithm according to claim 1, characterized in that: Methods for calculating the frequency offset estimate include: Compare the maximum peak value with a preset threshold value; If it is lower than the threshold, the acquisition is not successful; if it is higher than the threshold, the acquisition is successful. At this time, the index value of the corresponding coordinate of the peak is taken to obtain the frequency deviation estimation value: f d =(Z*(1-Max_x / Z)+1) / (Z*X*(1 / f s )) f d is the frequency offset estimate, Z is the number of fft points, Max_x is the index value corresponding to the highest peak, and X is the length of each matched filter.

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