Folding hash processing circuit applied to post quantum cryptography algorithm

Abstract

The invention discloses a folding hash processing circuit applied to a post quantum cryptography algorithm, and the circuit comprises a storage module which is used for splitting external input data into a plurality of pieces of intermediate data for respective storage, and sequentially outputting the intermediate data; the operation module is used for performing hash function operation processing on the intermediate data to generate result data; the address control module is used for providing address data to control external input data, and result data is input into the storage module; the counting module is used for recording in-cycle counting and inter-cycle counting of intermediate data output by the storage module; and transmitting the periodic inter-wheel count to the operation module and the address control module, and transmitting the periodic in-wheel count and the wheel constant control data to the operation module. According to the embodiment of the invention, the external input data is split, so that the size of the intermediate data in single operation is far less than 1600bit, the operation efficiency of the operation module is accelerated, and the practical application efficiency of the post quantum cryptography algorithm is improved.

Description

Technical Field

[0001] The present invention belongs to the field of post-quantum information security algorithms, hash algorithms, digital signal processing and circuit implementation, and in particular relates to a folded hash processing circuit applied to a post-quantum cryptographic algorithm. Background Art

[0002] The standardization of the third generation secure hash algorithm SHA-3 (Secure Hash Algorithm 3) was initiated by the National Institution of Science and Technology (NIST) of the United States, aiming to supplement and enhance the existing SHA-2 standard. The standardized SHA-3 function can also be called Keccak-f

[1600] , which absorbs any input length into 1600 bits and then processes it. It can be regarded as a 5×5×64 three-dimensional cube, or as a structure composed of 25 64-bit lanes. Each time a Keccak operation is performed, 24 sub-rounds need to be performed on the 1600 bits, where each sub-round contains five steps of θρπχι. The first four steps confuse the rows and columns of the 1600 bits, and the last step introduces a round constant to destroy the symmetry of the original transformation.

[0003] Among the existing post-quantum cryptographic algorithms to be standardized, SHA-3 has been widely used. For example, SHA-3 is used in the lattice-based public key encryption scheme Kyber and the digital signature scheme Dilithium to hash messages, generate key pairs, random numbers, etc. The security of the hash-based digital signature SPHINCS+ relies on the strong anti-collision property of the hash function to ensure the security of the signature and verification process. In the hardware implementation of these algorithms, the implementation of the SHA-3 module occupies the most resource overhead, which is directly related to the efficiency of the hardware implementation. However, in the actual application and implementation of post-quantum cryptographic algorithms, especially Internet of Things (IoT) devices and embedded systems, lightweight application scenarios often have strict restrictions on computing resources and energy consumption. Therefore, how to reduce the size of data required for calculation in the Keccak operation and thus improve the calculation efficiency is of great significance to the subsequent practical application of post-quantum cryptographic algorithms. Summary of the invention

[0004] The technical problem to be solved by the present invention is that, due to the problem of insufficient efficiency of existing hash processing circuits, the present invention provides a folded hash processing circuit applied to post-quantum cryptographic algorithms.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a folded hash processing circuit applied to a post-quantum cryptographic algorithm, including: a storage module, an operation module, an address control module and a counting module;

[0006] The storage module is used to split the external input data into a plurality of intermediate data for separate storage, and output the intermediate data in sequence;

[0007] The operation module is used to perform a hash function operation on the intermediate data to generate result data;

[0008] The address control module is used to provide address data to control the external input data and result data to be input into the storage module;

[0009] The counting module is used to record the intra-cycle count and inter-cycle count of the intermediate data output by the storage module; transmit the inter-cycle count to the operation module and the address control module, and transmit the intra-cycle count and wheel constant control data to the operation module.

[0010] Preferably, the storage module completes reading of all intermediate data in each cycle, and transmits the intermediate data to the operation module for hash function operation processing, and generates result data and transmits it back to the storage module; the storage module completes external input data operation processing once every 25 cycles;

[0011] In each round of cycles, each clock cycle completes the reading of a group of intermediate data; each time a clock cycle is completed, the counting module records the intra-cycle count once; each time a round of cycle operation processing is completed, the counting module records the inter-cycle count once.

[0012] Preferably, the storage module comprises: 25 groups of channels; the width of the 25 groups of channels is 16 bits;

[0013] Among them, the 25 groups of channels include 25-49 memories, and each group of channels includes at least one memory; the memories are connected in parallel; the memory width in each of the 25 groups of channels is controlled by the shift number of ρ steps in the hash function operation corresponding to the corresponding channel.

[0014] Preferably, the read addresses of the memories in the same group of channels in the storage module in each cycle are the same, and the write addresses are controlled by the number of shifts of the p steps in the hash function operation corresponding to the channel to which the memories belong; between different cycles, the read address of the memory in an even-numbered cycle will be used as the write address of the previous odd-numbered cycle, and the read address of the odd-numbered cycle will be used as the write address of the previous even-numbered cycle.

[0015] Preferably, the operation module comprises: a first unit, a second unit, a third unit, a first selector, a second selector and a third selector;

[0016] The first unit is used to run the x step and the ι step in the hash function; the second unit is used to run the θ step in the hash function; the third unit is used to run the ρ step and the π step in the hash function;

[0017] The first unit and the first selector input are connected to the storage module output; the output of the first unit is connected to the first selector and the second selector input; the first selector output is connected to the second unit input; the second unit output is connected to the second selector input; the second selector output is connected to the third unit input; the first selector, the second selector selection end, and the third selector selection end are connected to the counting module output; the third selector input is connected to the third unit and the second selector output; the third selector output is connected to the storage module input.

[0018] Preferably, the operation module further comprises a data preprocessing unit; the input end of the data preprocessing unit is connected to the output end of the third unit, and the output end is connected to the input end of the second unit;

[0019] The data preprocessing unit is used to select the last set of data from the output data of the third unit; and input the last set of data into the second unit after processing as the next round of input data of the second unit.

[0020] Preferably, the data preprocessing unit comprises: a plurality of parallel data preprocessing groups and a second XOR gate; the data preprocessing group comprises: a fourth selector, a register, a NOT gate, an AND gate, and a first XOR gate;

[0021] The fourth selector input is connected to the register output, and the output is connected to the register input; the register output is connected to the NOT gate input; the NOT gate output is connected to the AND gate input; the AND gate output and the register output are connected to the first XOR gate input; the first XOR gate output is connected to the second XOR gate input; the second XOR gate output is connected to the second unit input.

[0022] Preferably, the first unit comprises: a second NOT gate, a second AND gate and a third XOR gate;

[0023] The second NOT gate input terminal and the second AND gate input terminal are connected to the first unit input data; the second NOT gate output terminal is connected to the second AND gate input terminal; the second AND gate output terminal, the round constant data and the third XOR gate input terminal are connected.

[0024] Preferably, the second unit includes a fourth XOR gate, a fifth XOR gate, a sixth XOR gate and a seventh XOR gate;

[0025] The fourth XOR gate input terminal and the fifth XOR gate input terminal are connected to the second unit input data; the fourth XOR gate output terminal and the fifth XOR gate output terminal are connected to the sixth XOR gate input terminal; the sixth XOR gate output terminal is connected to the seventh XOR gate input terminal.

[0026] Preferably, the third unit is used to map and shift the third unit input data, and obtain the shift amount of the third unit input data.

[0027] Implementing the embodiments of the present invention has the following beneficial effects:

[0028] (1) The embodiment of the present invention splits the external input data into multiple intermediate data, outputs the intermediate data separately, and performs hash function operation on the single intermediate data, so that the size of the intermediate data of a single operation is much smaller than the initial external input data, thereby speeding up the operation efficiency of the operation module, thereby improving the efficiency of the actual application of the post-quantum cryptographic algorithm, and significantly reducing the resource overhead of the hash structure implementation, thereby achieving efficient utilization of system resources.

[0029] (2) The embodiment of the present invention designs the storage module and the operation module so that in different cycles, the memory alternately stores the output data of the operation module, and the operation module selects and adjusts the x step, ι step, θ step, ρ step and π step in the hash function operation. By performing different steps of the hash function operation on the output data of the storage module in different cycles, the hash function operation result of the external input data is accurately generated, and the data reading and writing and dependency problems in the folded hash structure are solved.

[0030] (3) The embodiment of the present invention sets up the operation module and adds a data preprocessing unit. The data preprocessing unit is used as a pre-data supplement device for the θ step. Before each round of the θ step, the required part of the data is calculated and sent to the θ step to participate in the calculation, so that the operation of the second unit reduces the redundant cycle and improves the operation efficiency of the second unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A folded hash processing circuit architecture diagram for a post-quantum cryptographic algorithm provided for the implementation of the present invention;

[0033] Figure 2A data preprocessing unit architecture diagram in a folded hash processing circuit applied to a post-quantum cryptographic algorithm provided for the implementation of the present invention;

[0034] Figure 3 A first unit architecture diagram in a folded hash processing circuit applied to a post-quantum cryptographic algorithm provided for the implementation of the present invention;

[0035] Figure 4 A diagram of the second unit architecture in a folded hash processing circuit for a post-quantum cryptographic algorithm provided for implementation of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0037] like Figure 1 As shown, the present embodiment discloses a folded hash processing circuit applied to a post-quantum cryptographic algorithm, and the folded hash processing circuit applied to a post-quantum cryptographic algorithm includes: a storage module 10, an operation module 20, an address control module 40 and a counting module 30. The storage module 10 is used to split the external input data into a plurality of intermediate data for storage, and output the intermediate data in sequence. The operation module 20 is used to perform a hash function (SHA-3 function) operation on the intermediate data to generate result data. The address control module 40 is used to provide address data, so as to control the external input data and the result data to be input into the storage module 10. The counting module 30 is used to record the cycle round count and the cycle round count of the intermediate data output by the storage module 10. The counting module 30 is also used to transmit the cycle round count to the operation module 20 and the address control module 40, and transmit the cycle round count and the round constant control data to the operation module 20.

[0038] Since the current SHA-3 functions all process 1600-bit external input data, this embodiment also processes 1600-bit data. However, the present invention can still be applied to the SHA-3 function of input data of other bits. And in this embodiment. The 1600-bit external input data is split into 4 intermediate data, which are stored separately and output in sequence. However, the present invention can still be applied to splitting the 1600-bit external input data into other numbers of intermediate data, which are stored separately and output in sequence. For example, splitting the 1600-bit external input data into 2, 8, 16, etc. nThe intermediate data can be divided into at most 64 pieces.

[0039] Specifically, the storage module 10 includes: 25 groups of channels 110. The width of the 25 groups of channels 110 is 16 bits. Among them, the 25 groups of channels 110 include: 25-49 memories 111. Each group of channels 110 includes at least one memory 111. The memories 111 are connected in parallel. The width of the memory 111 in each group of the 25 groups of channels 110 is controlled by the number of shifts of the p step in the SHA-3 function operation corresponding to the corresponding channel 110. The depth of the memory 111 is 8. The depth 0-3 positions of all the memories 111 of the 25 groups of channels 110 are used to receive 1600 bits of external input data. And the 1600 bits of external input data are divided into 4 groups of intermediate data according to the depth. The intermediate data will be transmitted to the operation module 20 for SHA-3 function operation processing, and the generated result data will be transmitted back to the storage module 10. Then the result data will be divided into 4 groups of intermediate data, and the 4 groups of intermediate data will be transmitted to the operation module 20 in sequence for SHA-3 function operation processing, and the generated result data will be transmitted back to the storage module 10. The storage module completes an external input data operation process every 25 cycles.

[0040] The storage module 10 completes the reading of the 4 groups of intermediate data in each cycle. In each clock cycle, a group of intermediate data is read out, and the counting module 30 records the cycle round count once, and uses 0-3 to represent the cycle round count of the reading of the 4 groups of intermediate data. When the 4 groups of intermediate data are read, the counting module 30 records the cycle round count once, that is, each time a cycle operation process is completed, the counting module 30 records the cycle round count once. The folded hash processing circuit applied to the post-quantum cryptographic algorithm completes a SHA-3 function processing of 1600bit external input data, and the counting module 30 will record 25 times, and use 0-24 to represent the 25 cycle round counts.

[0041] In the 25 rounds of cycle operations, the SHA-3 function executed by the operation module 20 is as follows:

[0042]

[0043] The x, ι, θ, ρ and π are respectively the x step, ι step, θ step, ρ step and π step in the SHA-3 function operation. The i is the periodic round count. The r i The SHA-3 function executed by the running module 20.

[0044] In one round of cycle operation, the read addresses of the memories 111 in the same group of channels in the storage module 10 are the same, and the write addresses are controlled by the shift number of the p step in the hash function operation corresponding to the channel to which the memory belongs. Between different cycles, the read address of the memory in the even-numbered cycle will be used as the write address of the previous odd-numbered cycle, and the read address of the odd-numbered cycle will be used as the write address of the previous even-numbered cycle. Specifically, the input 1600-bit external input data will be divided into 4 groups of intermediate data according to the depth. After each group of intermediate data of the 4 groups of intermediate data is transmitted, it will be transmitted to the depth 4-7 position of the memory 111. Until the 1600-bit external input data is transmitted from the depth 0-3 of all the memories 111 to the depth 4-7 of the memory 111, a round of cycle operation is completed. In the next round of cycle operation, the data in the storage module 10 will be read out from the depth 4-7 of the memory 111 and transmitted to the SHA-3 function executed by the operation module 20. Then the processed result data is transmitted to the depth 0-3 position of the memory 111. Between different cycles, the read address of the memory in an even-numbered cycle will be used as the write address of the previous odd-numbered cycle, and the read address of the odd-numbered cycle will be used as the write address of the previous even-numbered cycle.

[0045] The 25 groups of channels 110 include 25-49 memories 111. In this embodiment, the 25 groups of channels 110 are 49 memories 111. The width of each memory 111 is as follows:

[0046]

[0047]

[0048] Except for the Aba group, every two memories 111 form a group (such as Abe0 and Abe1), and each group of memories 111 stores corresponding data. The width of the memory 111 is determined by the mapping of the ρ and π steps in the SHA-3 function. For each group of channels, the read address of each cycle of the two memories 111 is the same, and the write address differs by 1. For example, the Abe group is mapped from the Age group, and the shift number of the Age group is 44, and the remainder of 16 is 12, so the widths of the two memories 111 corresponding to the Abe group are 4 and 12.

[0049] The operation module 20 includes: a first unit 210, a second unit 220, a third unit 230, a first selector 240, a second selector 250, a third selector 260 and a data preprocessing unit 270. The first unit 210 is used to run the x step and the ι step in the hash function. The second unit 220 is used to run the θ step in the hash function. The third unit 230 is used to run the ρ step and the π step in the hash function. The data preprocessing unit 270 is used to select the last group of data in the input data of the second unit 220. And the last group of data is input into the second unit 220 as the input data of the second unit 220 in the next round.

[0050] Specifically, the first unit 210 and the first selector 240 input end are connected to the storage module 10 output end. The output end of the first unit 210 is connected to the first selector 240 and the second selector 250 input end. The output end of the first selector 240 is connected to the second unit 220 input end. The output end of the second unit 220 is connected to the second selector 250 input end. The output end of the second selector 250 is connected to the third unit 230 input end. The first selector 240, the second selector 250 selection end, and the third selector 260 selection end are connected to the counting module 30 output end. The third selector 260 input end is connected to the third unit 230 and the second selector 250 output end. The third selector 260 output end is connected to the storage module 10 input end. The data pre-processing unit 270 input end is connected to the second unit 220 output end, and the output end is connected to the second unit 220 input end. The first selector 240, the second selector 250, and the third selector 260 are controlled by the cycle round count and the cycle round count output by the counting module 30 to select and control the execution of the first unit 210, the second unit 220, and the third unit 230. The output end of the counting module 30 is also connected to the first unit to output the wheel constant control data to the first unit 210, so as to control the wheel constant data added in the x step and the 1 step, so as to realize the selection of the wheel constant.

[0051] See also Figure 2 The data preprocessing unit 270 includes: a plurality of parallel data preprocessing groups and a second XOR gate 276; the data preprocessing group includes: a fourth selector 271, a register 272, a NOT gate 273, an AND gate 274, and a first XOR gate 275. The number of the data preprocessing groups is five.

[0052] The input end of the fourth selector 271 is connected to the output end of the register 272, and the output end is connected to the input end of the register 272. The output end of the register 272 is connected to the input end of the NOT gate 273. The output end of the NOT gate 273 is connected to the input end of the AND gate 274. The output end of the AND gate 274 and the output end of the register 272 are connected to the input end of the first XOR gate 275. The registers 272 of other groups are connected to the input end of the AND gate 274. The output end of the first XOR gate 275 of all groups is connected to the input end of the second XOR gate 276. The output end of the second XOR gate 276 is connected to the input end of the second unit 220. Since the calculation of the θ step of each intermediate data requires the last group of data of the previous one. The position of the last group of data of the intermediate data after the ι step is determined according to the position of the shift and rotation, and it is taken out after the calculation of ρ and π is completed in the corresponding round cycle, and enters the data preprocessing unit 270 for precalculation, and the calculation results (Bca, Bce, Bci, Bco, Bcu) are retained. In the first cycle of the next round of calculation, it is used as the input of the θ module. After the calculation is completed, the θ module also retains the result of the last slice for the calculation of the next cycle in the round. The data preprocessing unit 270 is used as a pre-data supplement device for the θ step. Before each round of the θ step, the required part of the data is calculated and sent to the θ step for calculation, so that the operation of the second unit 220 reduces redundant cycles and improves the operation efficiency of the second unit 220.

[0053] See also Figure 3 , the first unit 210 includes: a second NOT gate 211, a second AND gate 212 and a third XOR gate 213. The number of the second NOT gate 211, the second AND gate 212 and the third XOR gate 213 is determined by the size of the input intermediate data. When the intermediate data increases, the number of the second NOT gate 211, the second AND gate 212 and the third XOR gate 213 will also increase.

[0054] Specifically, the input end of the second NOT gate 211 and the input end of the second AND gate 212 are connected to the input data of the first unit 210. The output end of the second NOT gate 211 is connected to the input end of the second AND gate 212. The output end of the second AND gate 212 and the round constant data are connected to the input end of the third XOR gate 213.

[0055] The process of the x step and the ι step is as follows:

[0056] A′[x,y,z]=A[x,y,z]⊕(A[(x+1)mod5,y,z]⊕1)∧A[(x+2)mod5,y,z]

[0057] H[0,0,z]=A′[0,0,z]⊕RC(z)

[0058] Wherein, A′[x, y, z] is the result of step x; H[0, 0, z] is the result of step ι; RC(z) is the round constant data. The step x is used to perform an XOR confusion operation on the input data. The step ι is used to perform an XOR confusion operation on the result of step x and the round constant data.

[0059] The wheel constant data table is as follows:

[0060]

[0061] The simplified wheel constant control data control table is as follows:

[0062]

[0063]

[0064] The counting module 30 determines the position of data reading and writing and the order of calculation operations and determines the round constant control data through round-to-round counting, thereby realizing the control of the round constant data.

[0065] See also Figure 4 , the second unit 220 includes a fourth XOR gate 221, a fifth XOR gate 222, a sixth XOR gate 223 and a seventh XOR gate 224.

[0066] The fourth XOR gate 221 input terminal and the fifth XOR gate 222 input terminal are connected to the second unit 220 input data. The fourth XOR gate 221 input terminal is connected to the first selector 240 output data. The fifth XOR gate 222 input terminal is connected to the data preprocessing unit 270 output data. The fourth XOR gate 221 output terminal and the fifth XOR gate 222 output terminal are connected to the sixth XOR gate 223 input terminal. The seventh XOR gate 224 input terminal is connected to the sixth XOR gate 223 output terminal.

[0067] The process of the θ step is as follows:

[0068] C[x,z]=A[x,0,z]⊕A[x,1,z]⊕A[x,2,z]⊕A[x,3,z]⊕A[x,4,z]

[0069] D[x,z]=C[(x-1)mod 5,z])⊕C[(x+1)mod 5,(z-1)mod 64]

[0070] A′[x,y,z]=A[x,y,z]⊕D[x,z]

[0071] Wherein, C[x, z] is the operation result of the fourth XOR gate 221, D[x, z] is the operation result of the fifth XOR gate 222, and A′[x, y, z] is the operation result of the seventh XOR gate 224.

[0072] The third unit is used to map and shift the third unit input data, and obtain the shift amount of the third unit input data.

[0073] In summary, the folding hash processing circuit applied to the post-quantum cryptographic algorithm of the present invention adopts the method of splitting the external input data into multiple intermediate data and outputting the intermediate data respectively. A single intermediate data is processed by hash function operation, so that the size of the intermediate data of a single operation is much smaller than the initial external input data, thereby accelerating the operation efficiency of the operation module. The efficiency of the practical application of the post-quantum cryptographic algorithm is improved as a whole, and the resource overhead of the hash structure is significantly reduced, so as to achieve efficient utilization of system resources. And through the design of the storage module and the operation module, the memory alternately stores the output data of the operation module in different cycles, and the operation module selects and adjusts the x step, ι step, θ step, ρ step and π step in the hash function operation. By performing different step operations of hash function operation on the output data of the storage module of different cycles, the hash function operation result of the external input data is accurately generated, and the data reading and writing and dependency problems in the folded hash structure are solved.

[0074] What is disclosed above is only a preferred embodiment of the present invention, and it certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.

Claims

1. A folded hash processing circuit applied to a post-quantum cryptographic algorithm, characterized in that: include: Storage module, operation module, address control module and counting module; The storage module is used to split the external input data into a plurality of intermediate data for separate storage, and output the intermediate data in sequence; The operation module is used to perform a hash function operation on the intermediate data to generate result data; The address control module is used to provide address data to control the external input data and result data to be input into the storage module; The counting module is used to record the intra-cycle count and inter-cycle count of the intermediate data output by the storage module; transmit the inter-cycle count to the operation module and the address control module, and transmit the intra-cycle count and wheel constant control data to the operation module.

2. The folded hash processing circuit for post-quantum cryptographic algorithm according to claim 1, characterized in that: The storage module completes the reading of all intermediate data in each cycle, and transmits the intermediate data to the operation module for hash function operation processing, and generates result data and transmits it back to the storage module; the storage module completes the external input data operation processing once every 25 cycles; In each round of cycles, each clock cycle completes the reading of a group of intermediate data; each time a clock cycle is completed, the counting module records the intra-cycle count once; each time a round of cycle operation processing is completed, the counting module records the inter-cycle count once.

3. The folded hash processing circuit for post-quantum cryptographic algorithm according to claim 2, characterized in that: The storage module includes: 25 groups of channels; the width of the 25 groups of channels is 16 bits; Among them, the 25 groups of channels include 25-49 memories, and each group of channels includes at least one memory; the memories are connected in parallel; the memory width in each of the 25 groups of channels is controlled by the shift number of ρ steps in the hash function operation corresponding to the corresponding channel.

4. The folded hash processing circuit for post-quantum cryptographic algorithm according to claim 3, characterized in that: In each cycle, the read addresses of the memories in the same group of channels in the storage module are the same, and the write addresses are controlled by the shift number of the p steps in the hash function operation corresponding to the channel to which the memories belong; between different cycles, the read address of the memory in an even-numbered cycle will be used as the write address of the previous odd-numbered cycle, and the read address of the odd-numbered cycle will be used as the write address of the previous even-numbered cycle.

5. The folded hash processing circuit for post-quantum cryptographic algorithm according to claim 1, characterized in that: The operation module includes: a first unit, a second unit, a third unit, a first selector, a second selector and a third selector; The first unit is used to run the x step and the ι step in the hash function; the second unit is used to run the θ step in the hash function; the third unit is used to run the ρ step and the π step in the hash function; The first unit and the first selector input are connected to the storage module output; the output of the first unit is connected to the first selector and the second selector input; the first selector output is connected to the second unit input; the second unit output is connected to the second selector input; the second selector output is connected to the third unit input; the first selector, the second selector selection end, and the third selector selection end are connected to the counting module output; the third selector input is connected to the third unit and the second selector output; the third selector output is connected to the storage module input.

6. The folded hash processing circuit for post-quantum cryptographic algorithm according to claim 5, characterized in that: The operation module further includes a data preprocessing unit; the input end of the data preprocessing unit is connected to the output end of the third unit, and the output end is connected to the input end of the second unit; The data preprocessing unit is used to select the last set of data from the output data of the third unit; and input the last set of data into the second unit after processing as the next round of input data of the second unit.

7. The folded hash processing circuit for post-quantum cryptographic algorithm according to claim 6, characterized in that: The data preprocessing unit includes: a plurality of parallel data preprocessing groups and a second XOR gate; the data preprocessing group includes: a fourth selector, a register, a NOT gate, an AND gate, and a first XOR gate; The fourth selector input is connected to the register output, and the output is connected to the register input; the register output is connected to the NOT gate input; the NOT gate output is connected to the AND gate input; the AND gate output and the register output are connected to the first XOR gate input; the first XOR gate output is connected to the second XOR gate input; the second XOR gate output is connected to the second unit input.

8. The folded hash processing circuit for post-quantum cryptographic algorithm according to claim 5, characterized in that: The first unit includes: a second NOT gate, a second AND gate and a third XOR gate; The second NOT gate input terminal and the second AND gate input terminal are connected to the first unit input data; the second NOT gate output terminal is connected to the second AND gate input terminal; the second AND gate output terminal, the round constant data and the third XOR gate input terminal are connected.

9. The folded hash processing circuit for post-quantum cryptographic algorithm according to claim 5, characterized in that: The second unit includes a fourth XOR gate, a fifth XOR gate, a sixth XOR gate and a seventh XOR gate; The fourth XOR gate input terminal and the fifth XOR gate input terminal are connected to the second unit input data; the fourth XOR gate output terminal and the fifth XOR gate output terminal are connected to the sixth XOR gate input terminal; the sixth XOR gate output terminal is connected to the seventh XOR gate input terminal.

10. The folded hash processing circuit for post-quantum cryptographic algorithm according to claim 5, characterized in that: The third unit is used to map and shift the third unit input data, and obtain the shift amount of the third unit input data.

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