Time slot synchronization method and device in fine particle scene and network equipment

Abstract

The embodiment of the invention provides a time slot synchronization method and device in a fine particle scene and network equipment, and relates to the technical field of communication. The method comprises the following steps that: a CPU (Central Processing Unit) receives a message frame sent by a switching chip under the condition that the message frame is not identified; judging whether the message frame is a first time slot synchronization frame or not according to a plurality of stored first preset time slot synchronization frame formats; if yes, first time slot information is extracted from the message frame received this time, and the first time slot information is used for indicating the corresponding relation between the time slot of the receiving direction of the first target port of the home terminal corresponding to the message frame and the user; judging whether first time slot information corresponding to each time slot of a first target port of a home terminal corresponding to the message frame is obtained or not; if yes, a local second mapping table is verified and adjusted according to the obtained first mapping table, and the first mapping table comprises the extracted first time slot information. In this way, packet loss caused by the fact that time slot full synchronization is not carried out can be avoided, and rapid link establishment is facilitated.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a time slot synchronization method, device and network equipment in a fine-grained scenario. Background Art

[0002] With the continuous advancement of 5G network deployment, the integration and innovation of 5G and vertical industries continue to emerge, bringing a large number of small bandwidth, combination of soft and hard isolation, deterministic low latency, high security and high reliability bearer requirements.

[0003] In this demand context, SPN FGU (Fine Granularity Unit) inherits the efficient Ethernet core of SPN (Slicing Packer Network), integrates fine-grained slicing technology into the overall SPN architecture, and provides low-cost, refined, hard-isolated small-grained bearer pipelines. FGU refines the granularity of hard slices from 5G to 10M to meet the differentiated business bearer requirements of small bandwidth, high isolation, high security, etc. in scenarios such as 5G+ vertical industry applications and dedicated line services.

[0004] The small-grain slicing capability of the SPN bearer network will become a key force in supporting the deployment of 5G+ vertical industries and government and enterprise dedicated line applications.

[0005] The following five features of fine-grained FGU meet the carrying requirements of 5G vertical projects. 1. Bandwidth refinement, flexible allocation of any N*10M bandwidth, suitable for carrying requirements such as small and medium bandwidth. 2. Strict time division multiplexing. 3. Low latency and low jitter characteristics. 4. Each small-grained channel provides independent and complete OAM (Operation Administration and Maintenance) capabilities. 5. Supports lossless bandwidth adjustment of small-grained hard pipes to increase or decrease when user services are transmitted normally.

[0006] Currently, in fine-grained scenarios, overhead frames are used to encapsulate the mapping relationship between the user client and the time slot, so that the peer device can perform message recovery based on this. However, the overhead frames in fine-grained scenarios currently only encapsulate the adjusted mapping relationship between the client and the slot, and those that remain unchanged are not sent to save bandwidth. In this way, when the peer device mistakenly modifies the user message of some time slot mappings in the receiving direction, it will cause asymmetry with the time slot in the sending direction and cause packet loss for the user. For example, originally device A saved the correspondence between user 1 and time slot 1 in the receiving direction, but after device A is not modified, user 2 corresponds to time slot 1 in the receiving direction, so packet loss will occur for the user at device A. Summary of the invention

[0007] The embodiments of the present application provide a time slot synchronization method, apparatus, network equipment and readable storage medium in a fine-grained scenario, which can connect to the time slot synchronization messages of manufacturers using different preset time slot synchronization frame formats, and then verify and adjust the local second mapping table according to the obtained time slot synchronization message indicating the distribution of all time slots, thereby avoiding packet loss due to failure to perform full time slot synchronization, and facilitating rapid link establishment.

[0008] The embodiments of the present application can be implemented as follows:

[0009] In a first aspect, an embodiment of the present application provides a time slot synchronization method in a fine-grained scenario, which is applied to a CPU in a network device, wherein the network device also includes a switching chip that is communicatively connected to the CPU, and the method includes:

[0010] receiving a message frame sent by the switching chip when the switching chip fails to identify the message frame;

[0011] Determining whether the message frame is a first time slot synchronization frame, wherein whether it is a first time slot synchronization frame is determined according to a plurality of first preset time slot synchronization frame formats that are stored;

[0012] If the message frame is a first time slot synchronization frame, extracting the first time slot information from the message frame received this time, wherein the first time slot information is used to indicate the corresponding relationship between the time slot of the receiving direction of the first target port of the local end corresponding to the message frame and the user;

[0013] Determining whether first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained;

[0014] If so, the local second mapping table is checked and adjusted according to the obtained first mapping table, wherein the first mapping table includes the extracted first time slot information, and the second mapping table includes the locally stored correspondence between each time slot in the receiving direction of the first target port and the user.

[0015] In a second aspect, an embodiment of the present application provides a time slot synchronization device in a fine-grained scenario, which is applied to a CPU in a network device, wherein the network device also includes a switching chip that is communicatively connected to the CPU, and the device includes:

[0016] A receiving module, used for receiving a message frame sent by the switching chip when the switching chip fails to identify the message frame;

[0017] A judgment module, used for judging whether the message frame is a first time slot synchronization frame, wherein whether it is a first time slot synchronization frame is judged according to a plurality of first preset time slot synchronization frame formats that are saved;

[0018] An extraction module, configured to extract first time slot information from the message frame received this time when determining that the message frame is a first time slot synchronization frame, wherein the first time slot information is used to indicate a corresponding relationship between a time slot of a receiving direction of a first target port of the local end corresponding to the message frame and a user;

[0019] The judging module is further used to judge whether the first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained;

[0020] A processing module is used to verify and adjust a local second mapping table according to the obtained first mapping table when it is determined that the first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained, wherein the first mapping table includes the extracted first time slot information, and the second mapping table includes the correspondence between each time slot in the receiving direction of the first target port and the user stored locally.

[0021] In a third aspect, an embodiment of the present application provides a network device, including a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the time slot synchronization method in the fine-grained scenario described in the aforementioned embodiment.

[0022] In a fourth aspect, an embodiment of the present application provides a readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the time slot synchronization method in the fine-grained scenario as described in the aforementioned embodiment is implemented.

[0023] The time slot synchronization method, device, network equipment and readable storage medium in a fine-grained scenario provided by the embodiments of the present application, the CPU determines whether the message frame sent by the switching chip when it fails to identify it is a first time slot synchronization frame based on multiple saved first preset time slot synchronization frame formats, and extracts the first time slot information from the message frame received this time when it is determined to be so, the first time slot information is used to indicate the correspondence between the time slot in the receiving direction of the first target port of the local end corresponding to the message frame and the user; then, it is determined whether the first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained, and if so, the local second mapping table is checked and adjusted according to the obtained first mapping table including the first time slot information, wherein the second mapping table includes the correspondence between each time slot in the receiving direction of the first target port and the user stored locally. In this way, the CPU can connect to the time slot synchronization messages of manufacturers using different preset time slot synchronization frame formats based on the saved multiple first preset time slot synchronization frame formats, and then check and adjust the local second mapping table according to the obtained time slot synchronization message indicating the distribution of all time slots, thereby avoiding packet loss due to failure to perform full time slot synchronization, and facilitating rapid link establishment, making communication more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 This is a schematic diagram of the basic overhead frame of Flexe;

[0026] Figure 2 It is a schematic diagram of the overhead format of each basic unit of FGU;

[0027] Figure 3 A schematic diagram of a switching chip processing a time slot synchronization message frame;

[0028] Figure 4 A block diagram of a network device provided in an embodiment of the present application;

[0029] Figure 5 One of the flow charts of the time slot synchronization method in a fine-grained scenario provided in an embodiment of the present application;

[0030] Figure 6 A schematic diagram of a CPU processing a message frame provided in an embodiment of the present invention;

[0031] Figure 7 A second flowchart of a time slot synchronization method in a fine-grained scenario provided by an embodiment of the present application;

[0032] Figure 8 The third flowchart of the time slot synchronization method in a fine-grained scenario provided by an embodiment of the present application;

[0033] Fig. 9 A fourth flowchart of a time slot synchronization method in a fine-grained scenario provided in an embodiment of the present application;

[0034] Fig.10 A fifth flowchart of a time slot synchronization method in a fine-grained scenario provided in an embodiment of the present application;

[0035] Fig.11 One of the block diagrams of a time slot synchronization device in a fine-grained scenario provided by an embodiment of the present application;

[0036] Fig.12 The second block diagram of the time slot synchronization device in the fine-grained scenario provided in an embodiment of the present application.

[0037] Icons: 100 - network device; 110 - memory; 120 - processor; 130 - communication unit; 200 - time slot synchronization device in fine-grained scenario; 210 - receiving module; 220 - judgment module; 230 - extraction module; 240 - processing module; 250 - sending module. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0040] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0041] Both FGU and Flexe protocols support bandwidth adjustment by exchanging OH (overhead) frame messages, but the overhead frames defined by fine-grained FGU and Flexe are different.

[0042] like Figure 1The basic overhead frame of flexe is shown in the figure. The key bit fields in the flexe overhead frame are as follows: C: indicates that the current time slot uses the A / B table; CR: Calendar Request, time slot adjustment request; CA: Calendar Acknowledge, time slot adjustment response; Flexe Map: the number of the current slice sub-time slot (standard is 5G) in the entire bandwidth, such as 100G bandwidth, numbered 0-19; Client Calendar A: The bandwidth on the current sub-time slot A table is owned by the user number filled in Client Calendar A; Client Calendar B: The bandwidth on the current sub-time slot B table is owned by the user number filled in Client Calendar B.

[0043] In a Flexe basic overhead frame, such as Figure 1 As shown in the figure, the slice granularity of Flexe is 5G, and there is a client calendar A field in the overhead frame, which is used to describe user information, that is, the messages carried by this 5G bandwidth belong to this user. An overhead multiframe contains 10 basic overhead frames, which can carry information of 50G bandwidth. The multiframe can support up to 10 users, or 50G can belong to the same user, and only the same user number needs to be filled in the client calendar A field.

[0044] For 100G bandwidth, two overhead multiframes need to be sent, so that the client id (user number) information corresponding to the 100G bandwidth and 20 slots of the local end can be sent to the other end. After receiving the overhead multiframe, the other end parses the client calendar A / B field data, obtains the mapping relationship between the time slot and the user, and reassembles the message. It can be considered that the receiving direction of the other end can obtain all the time slots and user information mappings of the opposite sending direction in one overhead multiframe and adjust the time slot of the local direction according to the mapping relationship. If a larger bandwidth is carried, multiple oh overhead frames need to be sent based on the number of overhead frames of 50G bandwidth.

[0045] Based on the Flexe flexible Ethernet technology, FGU further divides the granularity of hard slices from 5G to 10M.

[0046] Figure 2The overhead format of each basic unit of FGU is shown, that is, the FGU oh overhead frame is shown. The key bit fields in the FGU overhead frame are as follows. Res: reserved bit, no need to pay attention; MFI: represents the order of the current overhead frame; Flag: 00 indicates that the current overhead frame is a message of time slot reconfiguration, 11 indicates that the current overhead frame is a gcc type message; S: time slot increase adjustment notification, this position is 1 when the time slot increase is issued; C: time slot effective indication, after C is set to 1, the next multi-frame switching work table; CR: time slot adjustment request, when the relationship between slot id and client id changes, this bit is 1, and a time slot adjustment request is issued to the receiving direction of the opposite end; CA: time slot adjustment response, this position is 1, indicating that the receiving direction has received the time slot adjustment and replied to the response; Client id: user number; Slot id: time slot number; Crc: check bit.

[0047] Considering that the granularity of fine-grained slices is lower and an FGU overhead frame only carries the bandwidth message of one slot (10M), if the Flexe overhead frame protocol is used to send user information of a bandwidth 5G port, Flexe only needs one overhead frame, while the FGU protocol requires 480 overhead frames, which greatly wastes bandwidth. At the same time, in the scenario where only a few time slots need to be adjusted, 480 overhead frames are still sent. Many overhead frames have no practical significance, and the switching chip may not be able to process them in time. Once the bandwidth increases, the overhead frame may not be transmitted when the data block has been sent, and the receiver cannot obtain all the overhead frames to adjust the bandwidth.

[0048] One of the significant advantages of small-granularity services is that they support lossless and rapid bandwidth adjustment during user service transmission. When the time slot occupied by a small-granularity client changes, it is expected that the small-granularity time slot adjustment process can be completed without damaging the service.

[0049] Therefore, the fine-grained protocol is optimized based on the Flexe overhead frame and is chosen in slot units, such as Figure 2 As shown in the figure, the overhead frame only encapsulates the adjusted mapping relationship between client and slot, and the unchanged relationship will not be sent again to save bandwidth. In a client dynamic time slot adjustment, the receiving device at the opposite end only knows the corresponding client messages of some slots that need to be adjusted, and can complete the lossless dynamic time slot adjustment without knowing the time slot distribution of all clients of the sending device.

[0050] However, a new problem arises. When user messages mapped to certain time slots in the receiving direction are modified by mistake, the time slots in the sending direction are asymmetric, resulting in packet loss for the user.

[0051] If dynamic time slot interaction is used to try to recover, since there is no time slot adjustment in the sending direction, no overhead information will be sent, and the receiving direction will not receive the correct time slot distribution, and it is still impossible to know the user message corresponding to this time slot, resulting in irreversible consequences.

[0052] Similarly, due to the lack of real-time synchronization and verification of the time slots between the two devices, during the communication process, when the link status is abnormal, the time slots are adjusted by dynamic interaction, but the time slots of all clients on both sides are restored for a long time after adjusting one client at a time. There is no mapping relationship between all time slots and users sent to the other end for full adjustment as in the Flexe protocol.

[0053] In order to solve the problem that fine granularity cannot obtain the distribution of all time slots in real time like Flexe, the inventor of the present application has found through research that a time slot table synchronization mechanism can be introduced to modify the standard time slot reconfiguration overhead frame, and all time slots and user message mapping tables of this port can be sent to the opposite end receiver through the modified time slot reconfiguration overhead frame, so that it can compare, verify and adjust in real time. However, the current full time slot synchronization message is not clearly specified in the FGU standard, and each manufacturer will have its own set of standards. There may be a solution to optimize the standard time slot reconfiguration overhead frame. In the time slot reconfiguration overhead frame, such as Figure 2 The following fields are shown. Flag = 00, indicating that the current frame is an overhead frame or a standard time slot reconfiguration frame; S: Time slot increase adjustment notification, this bit is set to 1 when the time slot increase is issued; C: Time slot effective indication, after C is set to 1, the next multi-frame switching work table; CR: Time slot adjustment request, when the relationship between slot id and client id changes, this bit is 1, and a time slot adjustment request is sent to the receiving direction of the opposite end; CA: Time slot adjustment response, this bit is 1, indicating that the receiving direction has received the time slot adjustment and replied with a response; Res: Reserved bit position; Client id: user number; Slot id: time slot number, 10M is the slice granularity.

[0054] The inventor of the present application has found through research that the overhead frame of the standard time slot reconfiguration can be optimized through the following scheme to send all the time slots and user message mapping tables of the current port to the opposite receiving party.

[0055] Solution 1: The four bits S / C / CR / CA are set to 1 at different stages of dynamic timeslot adjustment, but they are not set to 1 at the same time. The overhead frame of the standard timeslot is now optimized. All bits of the S / C / CR / CA field are set to 1 to indicate a timeslot synchronization frame. The filled client id and sub slot id fields are added to perform full timeslot synchronization.

[0056] Solution 2: According to the RES reserved bit in the FGU time slot reconfiguration overhead frame, a new 1 bit is defined, and the filled client id and sub slot id fields are added to perform full time slot synchronization.

[0057] Solution 3: Reconfigure the overhead frame according to the FGU time slot, fill the Flag field with 10 / 11, add the client id and sub slot id fields, and perform full time slot synchronization.

[0058] The main problem at present is that different manufacturers have their own customized implementation methods. After connecting with different manufacturers and selecting a set of protocols to solidify the protocols, the implementations of each manufacturer are different. The switching chip chooses to discard unrecognized messages, and this function still cannot be used.

[0059] like Figure 3 As shown, when connecting to equipment from other manufacturers, a fixed time slot synchronization frame is written in the switching chip logic, and all of them are recognized and processed by the switching chip. This method will bring the following disadvantages: there are too many customized protocols, and the switching chip cannot accommodate so many protocols. The customized protocols that the connected manufacturer uses that are not saved in the switching chip (that is, they are new customized protocols for the switching chip) are still not recognized. Since the switching chip cannot recognize them, it can only discard them. This is not universal and inflexible.

[0060] In view of the above situation, the embodiments of the present application provide a time slot synchronization method, device, network equipment and readable storage medium in a fine-grained scenario. The CPU can connect to the time slot synchronization messages of manufacturers using different preset time slot synchronization frame formats based on the saved multiple first preset time slot synchronization frame formats, and then verify and adjust the local second mapping table according to the obtained time slot synchronization message for indicating the distribution of all time slots in the receiving direction, thereby avoiding packet loss due to failure to perform full time slot synchronization, and facilitating rapid link establishment, making communication more reliable. It is worth noting that the defects existing in the existing solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of the present application for the above problems below should be the contributions made by the inventor to the present application in the process of the present application.

[0061] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0062] Please refer to Figure 4 , Figure 4A block diagram of a network device 100 provided in an embodiment of the present application. The network device 100 may be, but is not limited to, a switch, etc. The network device 100 includes a memory 110, a processor 120, and a communication unit 130. The memory 110, the processor 120, and the communication unit 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components may be electrically connected to each other via one or more communication buses or signal lines.

[0063] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0064] The processor 120 is used to read / write data or programs stored in the memory 110 and execute corresponding functions. For example, the memory 110 stores a time slot synchronization device 200 in a fine-grained scenario, and the time slot synchronization device 200 in the fine-grained scenario includes at least one software function module that can be stored in the memory 110 in the form of software or firmware. The processor 120 executes various functional applications and data processing by running software programs and modules stored in the memory 110, such as the time slot synchronization device 200 in the fine-grained scenario in the embodiment of the present application, that is, implementing the time slot synchronization method in the fine-grained scenario in the embodiment of the present application.

[0065] The communication unit 130 is used to establish a communication connection between the network device 100 and other communication terminals through the network, and to send and receive data through the network.

[0066] It should be understood that Figure 4 The structure shown is only a schematic diagram of the structure of the network device 100. The network device 100 may also include Figure 4 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1The components shown in the figure can be implemented by hardware, software or a combination thereof. That is to say, the implementation of the processing flow in the following embodiments is not limited to the processor reading and running a pure computer-readable program code from a memory, but can also be implemented by hardware or logic devices.

[0067] It should be understood here that improvements to a technology can be divided into hardware improvements (for example, improvements to circuit structures such as diodes, transistors, switches, etc.) and software improvements (improvements to method flows). However, with the development of technology, many improvements to method flows today can be regarded as direct improvements to hardware circuit structures. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement to a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and make a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. Among them, VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and Verilog are currently the most commonly used. Those skilled in the art should also be aware that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0068] Please refer to Figure 5 , Figure 5One of the flow diagrams of the time slot synchronization method in a fine-grained scenario provided in an embodiment of the present application. The network device includes a communication-connected CPU (Central Processing Unit) and a switching chip, and the above method can be applied to the CPU. The specific process of the time slot synchronization method in a fine-grained scenario is described in detail below. In this embodiment, the method may include steps S110 to S120 and steps S140 to S160.

[0069] Step S110: receiving a message frame sent by the switching chip when the switching chip fails to identify the message frame.

[0070] In this embodiment, the switching chip does not contain a custom protocol for implementing the first time slot synchronization frame. The first time slot synchronization frame is a frame obtained by modifying the standard time slot reconfiguration frame. Figure 6 As shown, after receiving the message frame, the switching chip determines whether the message frame can be identified. If the message frame cannot be identified, the message frame is sent to the CPU. Optionally, the switching chip can send the message frame to the CPU for processing via a DMA (Direct Memory Access) bus. It can be understood that in the case where the message frame is a first time slot synchronization frame, since the switching chip does not contain a custom protocol for implementing the time slot synchronization frame, the switching chip cannot identify the message frame as a first time slot synchronization frame.

[0071] Step S120, determining whether the message frame is a first time slot synchronization frame.

[0072] If the message frame is a first time slot synchronization frame, step S140 is executed.

[0073] Step S140: extracting the first time slot information from the message frame received this time.

[0074] In this embodiment, an interface for defining the first preset time slot synchronization frame format can be provided, and the staff can define multiple first preset time slot synchronization frame formats through the interface. Among them, the first preset time slot synchronization frame format can be used only in the receiving direction (i.e., determining whether the received message is a first time slot synchronization frame), and can also be used in the sending direction (i.e., used to send the first time slot synchronization frame to the opposite device), which can be determined in combination with actual needs. When the above interface is called, the frame format is recorded, and if it is not called, the time slot synchronization frame format cannot be determined.

[0075] After obtaining the CPU sent by the switching chip, the CPU can combine the saved multiple first preset time slot synchronization frame formats to determine whether the message frame is a first time slot synchronization frame corresponding to one of the multiple first preset time slot synchronization frame formats. If the message frame is not a first time slot synchronization frame, step S140 is not executed, that is, the message frame is not processed to extract the first time slot information. If the message frame is a first time slot synchronization frame, it means that there is time slot information that needs to be synchronized in the message frame, and the first time slot information can be extracted from the message frame.

[0076] The port of the device corresponding to the message frame of the first time slot synchronization frame received this time is used as the first target port. The first time slot information is used to indicate the correspondence between the time slot and the user in the receiving direction (i.e., RX (Receive) direction) of the first target port. Optionally, the first time slot information can be the corresponding slot number and user number of the receiving direction of the first target port.

[0077] Step S150, determining whether first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained.

[0078] If the first time slot information corresponding to each time slot in the receiving direction of the first target port of the local end corresponding to the message frame has been obtained, step S160 is executed.

[0079] Step S160: verify and adjust the local second mapping table according to the obtained first mapping table.

[0080] After extracting the first time slot information from the message frame received this time, it can be determined whether the first time slot information of each time slot in the receiving direction of the first target port has been obtained by extracting the first time slot information from the message frame. The specific judgment method can be determined in combination with actual needs. If it is determined that the first time slot information of each time slot in the receiving direction of the first target port has not been obtained, it is possible to wait for the reception of the message frame to obtain the first time slot information of each time slot in the receiving direction of the first target port. If it is determined that the first time slot information of each time slot in the receiving direction of the first target port has been obtained, the local second mapping table can be checked and adjusted according to the first mapping table to complete the full synchronization of the time slots. Among them, the first mapping table includes the extracted first time slot information, that is, the first mapping table includes the corresponding relationship between the time slots in the receiving direction extracted from the received multiple messages and the users, and the second mapping table is the corresponding relationship between the time slots in the receiving direction and the users stored locally.

[0081] In this way, the CPU can connect to the time slot synchronization messages of manufacturers using different preset time slot synchronization frame formats based on the saved multiple first preset time slot synchronization frame formats, and then check and adjust the local second mapping table according to the obtained time slot synchronization messages indicating the distribution of all time slots in the receiving direction, thereby avoiding packet loss due to failure to perform full time slot synchronization, and facilitating rapid link establishment when the link is abnormal.

[0082] In this embodiment, when the message frame is obtained, it can be determined whether the local device has enabled the time slot synchronization function. If enabled, it is determined whether the message frame is a first time slot synchronization frame. If the time slot synchronization function is not enabled, the message frame may not be processed, and the first time slot information may not be extracted from the message frame. In the case where the time slot synchronization function is not enabled, the message frame may also be directly discarded.

[0083] For example, the switching chip sends unrecognizable message frames to the CPU for processing through the DMA bus. When the time slot synchronization function is turned on, the CPU processes the interrupt after receiving the interrupt triggered by DMA to perform full time slot synchronization. If the time slot synchronization function is abandoned, the CPU can mask the interrupt after the DMA transfer is completed and will not call the interrupt processing function for time slot synchronization.

[0084] If a fixed time slot synchronization frame is written in the switching chip logic, and all of them are recognized and processed by the switching chip, in this way, when the time slot synchronization function is not needed, the switching chip still processes all overhead frame messages, and the invalid time slot synchronization frame occupies most of the time for the switching chip to process data, which greatly wastes the computing power. Compared with the switching chip processing all message frames, the above-mentioned method in this embodiment can greatly save the processing and computing pressure of the CPU and the switching chip.

[0085] In this embodiment, the first preset time slot synchronization frame format is obtained by modifying the standard time slot reconfiguration frame format. For example, the multiple first preset time slot synchronization frame formats include the following three formats. Format 1: Optimize the overhead frame of the standard time slot reconfiguration, set all the bits of the S / C / CR / CA field to 1 to indicate the time slot synchronization frame, plus the filled clientid and sub slot id fields, the time slot full synchronization can be performed; Format 2: According to the RES reserved bit in the time slot reconfiguration overhead frame of FGU, a new 1 bit is defined, plus the filled client id and sub slot id fields, the time slot full synchronization can be performed, wherein any 1 bit RES can be selected to be set to 1 or 0 to indicate whether it is a time slot synchronization frame; Format 3: According to the time slot reconfiguration overhead frame of FGU, fill the Flag field with 10 / 11, add the clientid and sub slot id fields, and the time slot full synchronization can be performed. According to the multiple first preset time slot synchronization frame formats obtained, it can be judged whether the message frame is the first time slot synchronization frame.

[0086] As a possible implementation, Figure 7 As shown, the method may further include step S115 and step S171 and step S172.

[0087] Step S115, determining whether the message frame is a time slot reconfiguration frame.

[0088] If the message frame is a time slot reconfiguration frame, step S171 is executed. If the message frame is not a time slot reconfiguration frame, step S120 is executed.

[0089] Step S171, deleting the message frame received this time and the first time slot information extracted from the historical message frame.

[0090] When the message frame is neither a time slot reconfiguration frame nor a first time slot synchronization frame, step S172 is executed.

[0091] Step S172, deleting the message frame received this time.

[0092] When the message frame is obtained, first, it is determined whether the message frame is a time slot reconfiguration frame according to the format of the standard time slot reconfiguration frame and the format of the message frame. If the format of the standard time slot reconfiguration frame is the same as the format of the message frame, the message frame is determined to be a time slot reconfiguration frame.

[0093] In general, frames used to achieve synchronization are sent to the opposite device in sequence. In the case where it is determined that the message frame is a time slot reconfiguration frame, the message frame received this time and the first time slot information extracted from the historical message frame currently stored can be deleted.

[0094] When it is determined that the message frame is not a time slot reconfiguration frame, it can be determined whether the message frame is a first time slot synchronization frame according to the saved multiple first preset time slot synchronization frame formats. Figure 2 The CPU can parse the format of the message frame, and then compare it with the multiple first preset time slot synchronization frame formats. If it conforms to one of the first preset time slot synchronization frame formats, it is determined that the message frame is a first time slot synchronization frame; if it does not conform to any of the first preset time slot synchronization frame formats, it is determined that the message frame is not a first time slot synchronization frame.

[0095] For example, assuming that the local first preset time slot synchronization frame format is defined as: S / C / CR / CA are all 1, and a reserved bit is 1, if the received message frame is flag=10 / 11, it can be considered inconsistent and the message frame is not the first time slot synchronization frame. It can be understood that if the first preset time slot synchronization frame format is not defined, it can be directly determined that the message frame is not the first time slot synchronization frame.

[0096] When it is determined that the message frame is not a time slot reconfiguration frame and is not a first time slot synchronization frame, the message frame received this time can be deleted, but the first time slot information currently saved from the historical message frame is still retained. The method of extracting the first time slot information from the historical message frame is the same as the method of analyzing and processing the current message frame to extract the first time slot information.

[0097] As described above, step S115 may be performed first, and step S120 may be performed if the message frame is not a time slot reconfiguration frame. Step S115 and step S120 may also be performed simultaneously, and the specific order may be determined in combination with actual needs.

[0098] Optionally, when it is determined that the message frame is a first time slot synchronization frame, the first time slot information may be directly extracted and saved.

[0099] To reduce unnecessary work, before extracting the first time slot information from the message frame received this time, Figure 8 As shown, the method may further include step S130.

[0100] Step S130, determining whether the current process is in the process of dynamically adjusting the time slot.

[0101] In this embodiment, it is determined whether the local end is currently in the process of dynamically adjusting the time slot. The specific determination method can be determined in combination with actual needs. For example, it is determined whether the local end and the opposite end device are currently in the state of negotiating the time slot of the first target port. If so, it can be determined that the current process is in the process of dynamically adjusting the time slot. If the current process is in the process of dynamically adjusting the time slot, it can be considered that all the first time slot synchronization frames currently received are in an untrustworthy state. At this time, it can be executed Figure 8 Step S180.

[0102] Step S180: Delete the message frame received this time and the first time slot information extracted from the historical message frame.

[0103] If the time slot is being dynamically adjusted, the message frame received this time is deleted, and the first time slot information extracted from the historical message frame received before the current time slot is deleted. This can avoid unnecessary adjustment of the local time slot-user correspondence based on the untrusted time slot-user correspondence.

[0104] If it is determined that the process of dynamically adjusting the time slot is not currently in progress, the client id and slot id fields in the message frame serving as the first time slot synchronization frame may be extracted to obtain the first time slot information in the message frame, and the first time slot information may be cached locally.

[0105] Among them, the above-mentioned step S120 and step S130 can be executed simultaneously, or step S120 can be executed first and then step S130, or step S130 can be executed first and then step S120. The specific execution order can be determined based on actual needs.

[0106] In this embodiment, a first time slot synchronization frame may include one piece of the first time slot information, that is, the information of the user corresponding to one time slot of the receiving direction of the first target port. When the first time slot information is extracted from the message frame received this time, it can be determined whether the first time slot synchronization frame corresponding to the receiving direction of the first target port has been fully received. Among them, the total number of time slots in the receiving direction of the first target port can be determined according to the bandwidth of the first target port, and then combined with the number of first time slot synchronization frames in the receiving direction of the first target port currently received in this round, it can be determined whether the first time slot synchronization frame in the receiving direction of the first target port has been fully received. If it is determined that it has not been fully received, step S160 may not be executed first, but waiting to continue receiving and processing message frames. If it is determined that it has been fully received, the second mapping table of the local receiving direction can be checked and adjusted in combination with the first time slot information extracted in this round.

[0107] To avoid unnecessary adjustments, when it is determined that the first time slot information corresponding to each time slot in the receiving direction of the first target port of the local end corresponding to the message frame has been obtained, it can be determined whether it is currently in dynamic interaction, and the dynamic interaction is used to adjust the correspondence between the time slot and the user. If it is currently in dynamic interaction, the time slot synchronization is stopped, and the first mapping table is deleted, that is, the first time slot information obtained in this round is deleted. If it is determined that it is not currently in dynamic interaction, the second mapping table is checked and adjusted.

[0108] The mapping of all time slot numbers and clients in the internal receiving end work table of the switching chip (i.e., the second mapping table) can be traversed and compared with the mapping relationship represented by the first mapping table (the first mapping table includes the extracted first time slot information). In the absence of errors, the client id read from the internal working table of the switching chip and the client id obtained from the first time slot synchronization frame corresponding to the same sub slot id should be consistent. In the case of determining that there is no difference between the first mapping table and the second mapping table, the stored first mapping table can be cleared.

[0109] If it is determined that the first mapping table is different from the second mapping table, the time slot adjustment is performed. The static switching mode can be turned on, the time slot table of the receiving direction is reconfigured (i.e., the second mapping table is reconfigured), and the upper layer adjusts the bandwidth according to the new time slot table, and finally the cached first mapping table is cleared, and the time slot synchronization adjustment is completed.

[0110] In this embodiment, the logic of how to synchronize time slots based on the message frame may be included in an interrupt processing function. The interrupt processing function may be located in the switching chip or in the CPU or other locations, and may be determined in combination with actual needs. As a possible implementation, the interrupt processing function may be located in the switching chip, and the interrupt processing function may be encapsulated in the switching chip software.

[0111] If only one type of time slot synchronization frame can be written into the switching chip logic, and all of them are recognized and processed by the switching chip, when the switching chip receives a time slot synchronization frame corresponding to a protocol that uses no message, it cannot be recognized and can only be discarded. To address this issue, in order to achieve universality, in this embodiment, the switching chip does not store content about the time slot synchronization frame format. The switching chip does not discard all unrecognized message frames, but sends them to the CPU for processing through the DMA bus. After the CPU receives the interrupt triggered by the DMA, it calls back the interrupt processing function encapsulated by the switching chip software, and the interrupt processing function processes them. The function can obtain the defined time slot synchronization frame format, parse the received message frames one by one, and discard the message frames that do not conform to the defined time slot synchronization frame format; for the message frames that conform to the defined time slot synchronization frame format, extract the time slot information and store it for subsequent verification.

[0112] The above process is as follows Figure 6 As shown in the figure, the switching chip and the CPU are connected via a DMA bus, and the switching chip provides a DMA interrupt processing function to the CPU. After the frame is transferred from the physical medium to the switching chip, the switching chip will collect and extract the frame without processing it. The switching chip uses the DMA bus between the CPU and the switching chip to send all the frames to the CPU for processing. When the transmission is completed, the DMA interrupt is triggered, the CPU responds to the interrupt, and executes the DMA interrupt processing function. The interrupt processing function identifies, responds to, or discards the frame.

[0113] The software where the interrupt processing function is located can provide three functional modules. The first functional module is used to define the time slot synchronization frame format, indicating that this fixed time slot synchronization frame will be used as the standard from now on. The second function is to send the time slot providing frame corresponding to the sending direction to the opposite device. The second functional module is used to traverse the mapping of all user information and time slot numbers in the sending direction of this port to form a complete mapping table, so that the opposite end can check and adjust the local mapping table based on this mapping table, and then restore the message; after obtaining the time slot mapping relationship of the sending direction of this end, based on the set time slot synchronization frame format, it is encapsulated into the corresponding time slot synchronization frame and sent to the opposite device. The third functional module is the DMA interrupt processing module in the receiving direction, which is used to: determine whether it is a time slot synchronization frame after receiving the message frame, if so, record the client and slot carried in the frame, otherwise discard the message frame; and, after receiving all the time slot information, perform verification and check, and adjust the traffic in time.

[0114] Compared with the switching chip processing all messages, the advantages of sending messages to the CPU and having the CPU software recognize them are: for messages that the switching chip cannot recognize, including time slot synchronization frames, there is no limit on the frame format. When sent to the CPU, the software can obtain all of them, and can connect to any time slot synchronization message of the manufacturer for flexible recognition. In addition, when the time slot synchronization function is abandoned, the CPU only needs to shield the interrupt after the DMA transfer is completed, and does not call the interrupt processing function. Compared with the switching chip processing all message frames, it greatly saves the processing and computing pressure of the CPU and the switching chip.

[0115] The above describes how to perform time slot synchronization in the receiving direction when the network device acts as a receiving end. The following describes how to perform time slot synchronization in the sending direction when the network device acts as a sending end.

[0116] Please refer to Fig. 9 , Fig. 9 This is a fourth flow chart of a time slot synchronization method in a fine-grained scenario provided by an embodiment of the present application. In this embodiment, the method may further include steps S230 to S240.

[0117] Step S230: Obtain a third mapping table corresponding to the second target port of the local end.

[0118] Step S240: Generate a corresponding second time slot synchronization frame according to at least one second preset time slot synchronization frame format stored in the local end and the third mapping table, and send the second time slot synchronization frame to the opposite end device.

[0119] In this embodiment, the CPU can determine when to send a time slot synchronization frame for time slot synchronization according to actual needs, and determine which port is the second target port for time slot synchronization. For example, if the link of a port on the local end is abnormal, the port can be used as the second target port, and then the corresponding time slot synchronization frame can be sent to quickly establish a link; for another example, each port can be periodically used as the second target port for time slot synchronization.

[0120] When the second target port of the local end is determined, all time slot numbers in the internal working table of the switching chip can be traversed to read the corresponding client id from the working table. When the time slot number is idle, the client id can be 0. In this way, a complete mapping table for the transmission direction (i.e., TX (Transport) direction) can be formed, that is, the third mapping table is obtained. That is, the third mapping table includes the corresponding relationship between each time slot and user in the transmission direction of the second target port. Figure 2 The client id and sub slot id fields of the FGU basic overhead frame are shown. Each sub slot id corresponds to a client id. For example, the current bandwidth of the second target port is 5G, that is, the sub slot id is numbered from 0 to 479, and a total of 480 mappings form a complete time slot mapping table.

[0121] At least one second preset time slot synchronization frame format may be stored in the network device. The at least one second preset time slot synchronization frame format may be defined through an interface. According to at least one second preset time slot synchronization frame format, such as the time slot synchronization frame format in which all bits of the S / C / CR / CA field defined as shown above are set to 1, plus the obtained mapping relationship between the sub slot id and the client id, it is filled into the client id and sub slot id fields to form a second time slot synchronization frame and send it to the peer device. Continuing with the example above, if the current bandwidth of the second target port is 5G, it is necessary to fill the obtained 480 time slot user mapping relationships into the client id and subslot id fields of the synchronization frame in turn, combined with the bits of the S / C / CR / CA field being all set to 1, to form 480 time slot synchronization frames and send them to the peer. After the peer receives the frame, time slot synchronization can be performed through the above steps S110 to S180.

[0122] Please refer to Fig.10 , Fig.10 The fifth flowchart of the time slot synchronization method in a fine-grained scenario provided by the embodiment of the present application is as follows. In this embodiment, before step S240, the method may further include step S210.

[0123] Step S210, determining whether a second preset time slot synchronization frame format is stored locally.

[0124] In this embodiment, the software can provide an interface for defining the time slot synchronization frame format. When this interface is called, the frame format is recorded in the software, that is, the second preset time slot synchronization frame format is stored. If it is not called, the time slot synchronization frame format cannot be determined and the second time slot synchronization frame cannot be sent.

[0125] Among them, optionally, a plurality of time slot synchronization frame formats can be defined through the above-mentioned interface, and whether the received message frame is a time slot synchronization frame can be determined based on the plurality of time slot synchronization frame formats, and a time slot synchronization frame format can be arbitrarily determined from the plurality of time slot synchronization frame formats or a time slot synchronization frame format can be specified for sending the time slot synchronization frame. Two interfaces can also be provided, one interface is used to set the time slot synchronization frame format used when sending the time slot synchronization frame, and the other interface is used to set the time slot synchronization frame format used when identifying whether the message frame is a time slot synchronization frame. It is worth noting that the above-mentioned method is only for example, and the specific method can be determined in combination with actual needs. It can be understood that when a device sends a time slot synchronization frame to a peer device, the peer device can store the time slot synchronization frame format used by the device.

[0126] To avoid sending unnecessary second time slot synchronization frames, before step S240, Fig.10 As shown, the method may further include step S220.

[0127] Step S220, determining whether the local time slot is in the modification process.

[0128] In this embodiment, it can be determined whether the device is currently in the process of negotiating to modify the time slot. Since the time slot synchronization in the sending direction is for the mapping relationship between the determined slot and the client, the time slot and client mapping that may change at any time cannot be sent to the other end. Therefore, if the device is currently in the process of negotiating to modify the time slot, the time slot synchronization can be stopped at present and sent after the time slot adjustment is completed.

[0129] It can also be determined whether the static switching time slot has been completed, that is, whether the mapping relationship between the time slot and the user is currently being manually modified. If so, the time slot synchronization can be stopped at present and sent again after the static switching time slot is completed.

[0130] When it is determined that the second preset time slot synchronization frame format is stored and the current time slot is not in the modification process, the second time slot synchronization frame can be encapsulated based on the obtained third mapping table and the second preset time slot synchronization frame format and sent to the opposite device.

[0131] The time slot synchronization method in the above-mentioned fine-grained scenario provided by the embodiment of the present application can be applied to the time slot synchronization frame format customized by each manufacturer, and the original internal logic processing of the switching chip is transformed into sending the frame to the CPU software processing through the DMA bus, and the overhead frame is flexibly processed. In addition, by using the time slot synchronization frame, the link can be quickly established and the time slot distribution can be checked under link abnormality, and the communication is more reliable.

[0132] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing a time slot synchronization device 200 in a fine-grained scenario is provided below. Optionally, the time slot synchronization device 200 in the fine-grained scenario can adopt the above Figure 4 The device structure of the network device 100 shown in FIG. Fig.11 , Fig.11 One of the block diagrams of the time slot synchronization device 200 in the fine-grained scenario provided in the embodiment of the present application. It should be noted that the basic principle and technical effect of the time slot synchronization device 200 in the fine-grained scenario provided in this embodiment are the same as those in the above-mentioned embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference can be made to the corresponding contents in the above-mentioned embodiments. In this embodiment, the time slot synchronization device 200 in the fine-grained scenario is applied to a CPU in a network device, and the network device also includes a switching chip that is communicatively connected to the CPU. The time slot synchronization device 200 in the fine-grained scenario may include a receiving module 210, a judgment module 220, an extraction module 230 and a processing module 240.

[0133] The receiving module 210 is used to receive the message frame sent by the switching chip when the switching chip fails to identify the message frame.

[0134] The judging module 220 is used to judge whether the message frame is a first time slot synchronization frame. Whether it is a first time slot synchronization frame is judged according to a plurality of first preset time slot synchronization frame formats that are stored.

[0135] The extraction module 230 is used to extract the first time slot information from the message frame received this time when determining that the message frame is a first time slot synchronization frame, wherein the first time slot information is used to indicate the corresponding relationship between the time slot of the receiving direction of the first target port of the local end corresponding to the message frame and the user.

[0136] The determining module 220 is further configured to determine whether the first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained.

[0137] The processing module 240 is used to verify and adjust the local second mapping table according to the obtained first mapping table when it is determined that the first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained. The first mapping table includes the extracted first time slot information, and the second mapping table includes the locally stored correspondence between each time slot in the receiving direction of the first target port and the user.

[0138] Please refer to Fig.12 , Fig.12 The second block diagram of the time slot synchronization device 200 in a fine-grained scenario provided by an embodiment of the present application. In this embodiment, the time slot synchronization device 200 in a fine-grained scenario may further include a sending module 250 .

[0139] The sending module 250 is used to: obtain a third mapping table corresponding to the second target port of this end, wherein the third mapping table includes the correspondence between each time slot in the sending direction of the second target port and the user; generate a corresponding second time slot synchronization frame according to at least one second preset time slot synchronization frame format saved by this end and the third mapping table, and send the second time slot synchronization frame to the opposite device.

[0140] Optionally, the above modules can be stored in the form of software or firmware. Figure 4 The memory 110 shown in the figure may be fixed in the operating system (OS) of the network device 100 and may be Figure 1 Meanwhile, the data and program codes required for executing the above modules may be stored in the memory 110.

[0141] An embodiment of the present application also provides a readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the time slot synchronization method in the fine-grained scenario is implemented.

[0142] In summary, the embodiments of the present application provide a time slot synchronization method, apparatus, network equipment and readable storage medium in a fine-grained scenario, wherein the CPU determines whether a message frame sent by the switching chip when it fails to identify the message frame is a first time slot synchronization frame based on a plurality of first preset time slot synchronization frame formats that are saved, and extracts the first time slot information from the message frame received this time when it is determined to be so, wherein the first time slot information is used to indicate the correspondence between the time slot in the receiving direction of the first target port of the local end corresponding to the message frame and the user; thereafter, it is determined whether the first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained, and if so, the local second mapping table is checked and adjusted according to the obtained first mapping table including the first time slot information, wherein the second mapping table includes the correspondence between each time slot in the receiving direction of the first target port and the user that is locally saved. In this way, the CPU can connect to the time slot synchronization messages of manufacturers using different preset time slot synchronization frame formats based on the saved multiple first preset time slot synchronization frame formats, and then check and adjust the local second mapping table according to the obtained time slot synchronization message indicating the distribution of all time slots, thereby avoiding packet loss due to failure to perform full time slot synchronization, and facilitating rapid link establishment, making communication more reliable.

[0143] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0144] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0145] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0146] The above description is only an optional embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A time slot synchronization method in a fine-grained scenario, characterized in that: A CPU applied to a network device, wherein the network device further comprises a switching chip in communication connection with the CPU, and the method comprises: receiving a message frame sent by the switching chip when the switching chip fails to identify the message frame; Determining whether the message frame is a first time slot synchronization frame, wherein whether it is a first time slot synchronization frame is determined according to a plurality of first preset time slot synchronization frame formats that are stored; If the message frame is a first time slot synchronization frame, extracting the first time slot information from the message frame received this time, wherein the first time slot information is used to indicate the corresponding relationship between the time slot of the receiving direction of the first target port of the local end corresponding to the message frame and the user; Determining whether first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained; If so, the local second mapping table is checked and adjusted according to the obtained first mapping table, wherein the first mapping table includes the extracted first time slot information, and the second mapping table includes the locally stored correspondence between each time slot in the receiving direction of the first target port and the user.

2. The method according to claim 1, characterized in that: The checking and adjusting the local second mapping table according to the obtained first mapping table includes: Determining whether a dynamic interaction is currently in progress, wherein the dynamic interaction is used to adjust the correspondence between the time slot and the user; If it is determined that the dynamic interaction is currently in progress, then the time slot synchronization is stopped and the first mapping table is deleted; If it is determined that the dynamic interaction is not currently in progress and there is a difference between the first mapping table and the second mapping table, the second mapping table is adjusted according to the first mapping table, and the first mapping table is deleted.

3. The method according to claim 1, characterized in that Before extracting the first time slot information in the message frame, the method further includes: Determine whether the current process is in the process of dynamically adjusting the time slot; If yes, the message frame received this time and the first time slot information extracted from the historical message frame are deleted; If not, execute the step of extracting the first time slot information from the message frame received this time.

4. The method according to claim 1, characterized in that: The method further comprises: According to the format of the time slot reconfiguration frame and the format of the message frame, determining whether the message frame is a time slot reconfiguration frame; If the message frame is a time slot reconfiguration frame, the message frame received this time and the first time slot information extracted from the historical message frame are deleted; If the message frame is not a time slot reconfiguration frame, executing the step of determining whether the message frame is a first time slot synchronization frame; If the message frame is not a time slot reconfiguration frame and is not a first time slot synchronization frame, the message frame received this time is deleted.

5. The method according to claim 1, characterized in that The determining whether the message frame is a first time slot synchronization frame comprises: In the case of determining to enable the time slot synchronization function, determining whether the message frame is a first time slot synchronization frame; The method further comprises: When it is determined that the time slot synchronization function is not enabled, the message frame is not processed, wherein the processing is used to extract the first time slot information.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: Obtaining a third mapping table corresponding to the second target port of the local end, wherein the third mapping table includes a correspondence between each time slot in the sending direction of the second target port and a user; According to at least one second preset time slot synchronization frame format stored in the local end and the third mapping table, a corresponding second time slot synchronization frame is generated, and the second time slot synchronization frame is sent to the opposite end device.

7. The method according to claim 6, characterized in that Before generating a corresponding second time slot synchronization frame according to at least one second preset time slot synchronization frame format stored in the local end and the third mapping table, the method further includes: Determine whether the local time slot is in the modification process; If the local time slot is in the process of modification, the time slot synchronization is currently stopped; If the local time slot is not in the modification process, the step of generating a corresponding second time slot synchronization frame according to at least one second preset time slot synchronization frame format stored in the local end and the third mapping table is executed.

8. The method according to claim 6, characterized in that Before obtaining the third mapping table corresponding to the second target port of the local end, the method further includes: Determining whether a second preset time slot synchronization frame format is stored locally; If the second preset time slot synchronization frame format is not stored locally, then the time slot synchronization is currently stopped; If the second preset time slot synchronization frame format is stored locally, the step of obtaining the third mapping table corresponding to the second target port of the local end is performed.

9. A time slot synchronization device in a fine-grained scenario, characterized in that: A CPU applied to a network device, wherein the network device further comprises a switching chip in communication connection with the CPU, and the device comprises: A receiving module, used for receiving a message frame sent by the switching chip when the switching chip fails to identify the message frame; A judgment module, used for judging whether the message frame is a first time slot synchronization frame, wherein whether it is a first time slot synchronization frame is judged according to a plurality of first preset time slot synchronization frame formats that are saved; An extraction module, configured to extract first time slot information from the message frame received this time when determining that the message frame is a first time slot synchronization frame, wherein the first time slot information is used to indicate a corresponding relationship between a time slot of a receiving direction of a first target port of the local end corresponding to the message frame and a user; The judging module is further used to judge whether the first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained; A processing module is used to verify and adjust a local second mapping table according to the obtained first mapping table when it is determined that the first time slot information corresponding to each time slot in the receiving direction of the first target port has been obtained, wherein the first mapping table includes the extracted first time slot information, and the second mapping table includes the correspondence between each time slot in the receiving direction of the first target port and the user stored locally.

10. A network device, characterized in that: It comprises a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the time slot synchronization method in a fine-grained scenario as described in any one of claims 1-8.

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