Solar cell and preparation method thereof

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a solar cell and a preparation method thereof, the solar cell comprises a substrate, the substrate is provided with a first surface and a second surface which are oppositely arranged, and the first surface is provided with metal regions and non-metal regions which are alternately arranged; the silicon oxide layer is positioned in the non-metal region of the first surface; the pore density of the silicon oxide layer is 5 * 10 <-6 >-5 * 10 <-4 >; the middle layer is positioned in the metal region of the first surface; the semiconductor doping layer is positioned on the surface of the intermediate layer; the anti-reflection layer is located on the semiconductor doping layer and on the surface of the silicon oxide layer; and the electrode is located on the anti-reflection layer corresponding to the metal region, and the electrode is electrically connected with the semiconductor doping layer. The solar cell provided by the embodiment of the invention at least can improve the photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] The embodiments of the present application relate to the photovoltaic field, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] At present, with the gradual depletion of fossil energy, solar cells are becoming more and more widely used as a new energy alternative. Solar cells are devices that convert sunlight into electrical energy. Solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0003] The current solar cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact), PERC cells (Passivated emitter and real cell) and heterojunction cells, etc. The photoelectric conversion efficiency of solar cells is improved by reducing optical losses and reducing the recombination of photogenerated carriers on the surface and in the body of the silicon substrate through different film layer settings and functional limitations.

[0004] However, the photoelectric conversion efficiency of current solar cells is still poor. Summary of the invention

[0005] The embodiments of the present application provide a solar cell and a method for preparing the same, which are at least beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0006] According to some embodiments of the present application, the embodiments of the present application provide a solar cell, comprising: a substrate, the substrate having a first surface and a second surface arranged opposite to each other, the first surface having metal areas and non-metal areas arranged alternately; a silicon oxide layer, the silicon oxide layer being located in the non-metal area of ​​the first surface; the pore density of the silicon oxide layer being 5×10 -6 ~5×10 -4 ; an intermediate layer, the intermediate layer is located in the metal area of ​​the first surface; a semiconductor doping layer, the semiconductor doping layer is located on the surface of the intermediate layer; an anti-reflection layer, the anti-reflection layer is located on the semiconductor doping layer and on the surface of the silicon oxide layer; an electrode, the electrode is located on the anti-reflection layer corresponding to the metal area, and the electrode is electrically connected to the semiconductor doping layer.

[0007] In some embodiments, the non-metallic region is recessed toward the second surface compared to the metal region to form a groove; the depth of the groove ranges from 3 μm to 4 μm.

[0008] In some embodiments, the silicon oxide layer includes a first part and a second part, the first part is located between the substrate and the second part, the silicon content in the first part is greater than the silicon content in the second part, and the oxygen content in the first part is less than the oxygen content in the second part.

[0009] In some embodiments, the silicon oxide layer has a thickness of 2 nm to 3 nm.

[0010] In some embodiments, the intermediate layer is a tunneling layer; the tunneling layer is a tunneling silicon oxide layer, and the density of the tunneling silicon oxide layer is greater than the density of the silicon oxide layer.

[0011] In some embodiments, the thickness of the tunneling silicon oxide layer is greater than the thickness of the silicon oxide layer.

[0012] In some embodiments, the intermediate layer is an intrinsic amorphous silicon layer.

[0013] In some embodiments, the method further includes: a transparent conductive layer, wherein the transparent conductive layer is located on the surface of the silicon oxide layer; and the transparent conductive layer is in contact with the semiconductor doping layer.

[0014] In some embodiments, the metal area is a polished surface, and the non-metal area has a suede structure.

[0015] According to some embodiments of the present application, the embodiments of the present application also provide a method for preparing a solar cell, comprising: providing a substrate, the substrate having a first surface and a second surface arranged opposite to each other, the first surface having metal areas and non-metal areas arranged alternately; forming a silicon oxide layer, the silicon oxide layer being located in the non-metal area of ​​the first surface; the pore density of the silicon oxide layer being 5×10 -6 ~5×10 -4 ; forming an intermediate layer and a semiconductor doping layer, wherein the intermediate layer is located in the metal area of ​​the first surface; the semiconductor doping layer is located on the surface of the intermediate layer; forming an anti-reflection layer, wherein the anti-reflection layer is located on the semiconductor doping layer and on the surface of the silicon oxide layer; forming an electrode, wherein the electrode is located on the anti-reflection layer corresponding to the metal area, and the electrode is electrically connected to the semiconductor doping layer.

[0016] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0017] The solar cell provided in the embodiment of the present application has a substrate with metal areas and non-metal areas arranged alternately, an intermediate layer and a semiconductor doping layer are arranged on the metal area; a silicon oxide layer is arranged on the non-metal area, and then an anti-reflection layer is arranged, the anti-reflection layer is located on the semiconductor doping layer and the silicon oxide layer, and the electrode is located in the anti-reflection layer and is in electrical contact with the semiconductor doping layer. In this way, for the non-metal area, no semiconductor doping layer is arranged, which can avoid the optical absorption problem caused by the thickness of the semiconductor doping layer and the carrier recombination problem caused by the high doping concentration of the semiconductor doping layer; the semiconductor doping layer on the metal area is in contact with the electrode, and the semiconductor doping layer can form a good contact with the electrode, thereby reducing the series resistance between the semiconductor doping layer and the electrode. Secondly, a silicon oxide layer is arranged on the substrate surface of the non-metal area, and the silicon oxide layer is an optically transparent layer, which will not sacrifice the optical incidence of the first surface; there are a large number of positive charges in the area where the silicon oxide layer contacts the substrate, which can improve the interface passivation, thereby improving the passivation effect of the battery and improving the photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by the figures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic structural diagram of a solar cell provided in the first embodiment of the present application;

[0020] Figure 2 Another structural schematic diagram of a solar cell provided in the first embodiment of the present application;

[0021] Figure 3 A schematic structural diagram of a solar cell provided in the second embodiment of the present application;

[0022] Figure 4 A schematic structural diagram of a solar cell provided in the third embodiment of the present application;

[0023] Figure 5 A schematic structural diagram of a solar cell provided in the fourth embodiment of the present application;

[0024] Figure 6 A schematic structural diagram of a solar cell provided in the fifth embodiment of the present application;

[0025] Figure 7 to Figure 12 A schematic diagram of the structure of a solar cell corresponding to each step in a method for preparing a solar cell provided in another embodiment of the present application;

[0026] Fig.13 A schematic structural diagram of a laminated battery provided in yet another embodiment of the present application;

[0027] Fig.14 A schematic structural diagram of a photovoltaic module provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0028] As can be seen from the background art, the photoelectric conversion efficiency of current solar cells is poor.

[0029] The embodiments of the present application provide a solar cell and a method for preparing the same, wherein the series resistance is reduced by forming an intermediate layer and a semiconductor doping layer on the metal area; and the recombination rate of the non-metal area is reduced without reducing the optical absorption efficiency by forming a silicon oxide layer on the non-metal area, thereby improving the photoelectric conversion efficiency of the battery.

[0030] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0031] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0032] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0033] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0034] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0035] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0036] In the accompanying drawings corresponding to the embodiments of the present application, the thickness and area of ​​the layer are magnified for better understanding and ease of description. When describing a component (such as a layer, film, region or substrate) on another component or on the surface of another component, the component can be "directly" located on the surface of another component, or there can be a third component between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0037] In the description of the embodiments of the present application, when a component "includes" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may exist in between. In addition, when a component such as a layer, film, region, or plate is "directly located on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located in between.

[0038] The terms used in the description of the various embodiments described herein are only used to describe specific embodiments and are not intended to be limiting. As used in the description of the various embodiments described and in the appended claims, "the part" is also intended to include the plural form unless the context clearly indicates otherwise. Among them, a component includes a layer, a film, a region, or a plate.

[0039] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0040] Figure 1 A schematic structural diagram of a solar cell provided in the first embodiment of the present application; Figure 2 Another structural schematic diagram of a solar cell provided in the first embodiment of the present application.

[0041] According to some embodiments of the present application, the present application provides a solar cell for improving photoelectric conversion efficiency. Figure 1 The solar cell includes a substrate 100, the substrate 100 has a first surface 101 and a second surface 102 arranged opposite to each other, and the first surface 101 has metal areas 11 and non-metal areas 12 arranged alternately. The solar cell includes a silicon oxide layer 113, and the silicon oxide layer 113 is located in the non-metal area 11 of the first surface 101. The solar cell includes an intermediate layer 111, and the intermediate layer 111 is located in the metal area 11 of the first surface 101. The solar cell includes a semiconductor doping layer 112, and the semiconductor doping layer 112 is located on the surface of the intermediate layer 111. The solar cell includes an anti-reflection layer 117, and the anti-reflection layer 117 is located on the semiconductor doping layer 112 and on the surface of the silicon oxide layer 113. The solar cell includes an electrode 118, and the electrode 118 is located on the anti-reflection layer 117 corresponding to the metal area 11, and the electrode 118 is electrically connected to the semiconductor doping layer 112.

[0042] Thus, for the non-metallic region 12, the semiconductor doping layer 112 is not provided, so that the optical absorption problem caused by the thickness of the semiconductor doping layer 112 and the carrier recombination problem caused by the high doping concentration of the semiconductor doping layer 112 can be avoided; the semiconductor doping layer 112 on the metal region 11 is in contact with the electrode 118, and the semiconductor doping layer 112 can form a good contact with the electrode 118, thereby reducing the series resistance between the semiconductor doping layer 112 and the electrode 118. Secondly, a silicon oxide layer 113 is provided on the substrate surface of the non-metallic region 12, and the silicon oxide layer 113 is an optically transparent layer, which will not sacrifice the optical incidence of the first surface 101; there are a large number of positive charges in the area where the silicon oxide layer 113 contacts the substrate 100, which can enhance the interface passivation, thereby enhancing the passivation effect of the battery and improving the photoelectric conversion efficiency.

[0043] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be in a single crystalline state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a single crystalline state and an amorphous state is referred to as a microcrystalline state), for example, silicon may be at least one of single crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0044] In some embodiments, the material of the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include but are not limited to silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenide and the like. The substrate 100 may also be a sapphire substrate, a silicon on insulator substrate or a germanium on insulator substrate.

[0045] In some embodiments, the substrate 100 may be an N-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any one of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0046] In some embodiments, the solar cell is a single-sided cell, the second surface 102 can be used as the light-receiving surface (front side) for receiving incident light, and the first surface 101 is used as the backlight surface (back side). The backlight surface can also receive incident light, but the efficiency of receiving the incident light is weaker than that of the light-receiving surface.

[0047] In some embodiments, the metal region 11 refers to the region where the orthographic projection of the electrode 118 on the substrate 100 is located, and the non-metal region 12 refers to the region other than the orthographic projection of the electrode 118 on the substrate 100. In order to ensure that the film layer contacted by the electrode 118 has a large doping concentration or the regions contacted by the electrode 118 are all high-concentration regions, thereby reducing the contact resistance, the area of ​​the metal region 11 is generally set to be greater than or equal to the area of ​​the orthographic projection of the electrode 118 on the substrate 100. In other words, the orthographic projection area of ​​the electrode 118 on the substrate 100 is smaller than the area of ​​the metal region and the orthographic projection position must be within the metal region.

[0048] In some embodiments, the second surface 102 of the substrate 100 has a velvet structure, which can improve the internal reflectivity of the incident light, thereby improving the photoelectric conversion efficiency. The velvet structure may include a plurality of protruding structures 101, which may be arranged adjacently or spaced apart, or stacked or partially overlapped. The embodiment of the present application does not limit the number, arrangement, and shape of the protruding structures 101.

[0049] In some embodiments, the first surface of the substrate 100 is a polished surface, which can enhance back reflection and reduce light loss; the polished surface can also provide good substrate surface quality, thereby improving the passivation effect of the substrate and the passivation film layer. The polished surface refers to a flat surface formed by removing surface unevenness and impurities through chemical etching or physical friction.

[0050] In some embodiments, reference Figure 1 The metal area 11 of the first surface 101a of the substrate 100a is a polished surface, and the non-metal area 12 of the first surface 101a of the substrate 100a is a polished surface.

[0051] In some embodiments, reference Figure 2 The metal area 11 of the first surface 101b of the substrate 100b is a polished surface, and the non-metal area 12 of the first surface 101b of the substrate 100b has a suede structure to improve the film quality of the intermediate layer 111 and the semiconductor doping layer 112 of the metal area 11, thereby improving the passivation effect. The non-metal area 12 can have a better light trapping effect and increase the light absorption rate.

[0052] In other embodiments, the metal area of ​​the base has a first tower base structure, and the non-metal area has a second tower base structure, and the first tower base structure and the second tower base structure have different sizes, heights, and specific surface areas. This application does not limit the first tower base structure and the second tower base structure, and those skilled in the art can further set the sizes, heights, and specific surface areas of the first tower base structure and the second tower base structure according to needs.

[0053] It should be noted that Figure 1The substrate 100a and Figure 2 The substrate 100b in the figure is the substrate 100, and different reference numerals are set to illustrate the two structures just to distinguish the different morphologies of the first surface of the substrate. Figure 1 The first surface 101a and Figure 2 The first surface 101b is only used to illustrate the different morphologies of the non-metallic regions.

[0054] In some embodiments, the metal region 11 of the first surface 101 is flush with the non-metal region 12 of the first surface 101 .

[0055] In some embodiments, the pore density of the silicon oxide layer 113 is 5×10 -6 ~5×10 -4 The high density of the silicon oxide layer 113 can provide a better passivation effect, reduce the recombination rate on the surface of the substrate 100, and thus improve the photoelectric conversion efficiency. The high density of the silicon oxide layer 113 can also make the silicon oxide layer 113 itself have a high light transmittance, thereby reducing the optical absorption of the incident light and improving the photoelectric conversion efficiency of the solar cell. Characterization of the density of the silicon oxide layer 113 can include three methods: infrared spectroscopy, refractive index method and corrosion rate method.

[0056] If the pore density of the silicon oxide layer 113 is less than 5×10 -6 , it means that the number of pinholes in the silicon oxide layer is too small, which will cause the carriers to be unable to be transmitted or the number of carriers transmitted is small, thereby affecting the photoelectric conversion efficiency of the battery; if the pore density of the silicon oxide layer 113 is greater than 5×10 -4 , it means that the number of pinholes in the silicon oxide layer 113 is large, that is, the film quality of the silicon oxide layer is poor and there are many defects, which will further reduce the passivation performance.

[0057] It should be noted that if the carrier transmission efficiency of the silicon oxide layer 113 is not considered, the pore density of the silicon oxide layer 113 can be set to be less than 5×10 -6 , but still greater than 1×10 -6 .

[0058] In summary, the pore density of the silicon oxide layer 113 is 5×10 -6 ~1×10 -5 , 1×10 -5 ~5×10 -5 , 5×10 -5 ~1×10 -4 or 1×10 -4 ~5×10 -4 The pore density of the silicon oxide layer 113 may be 7×10 -6 , 3×10 -5 , 8×10-5 or 3×10 -4 .

[0059] In some embodiments, the thickness of the silicon oxide layer 113 is in the range of 2 nm to 3 nm. When the thickness of the silicon oxide layer 113 is within this range, the light transmittance of the silicon oxide layer 113 is good, and the silicon oxide layer 113 can provide more positive charges, thereby reducing the carrier recombination rate on the surface of the substrate 100, improving good chemical passivation, and thereby improving the photoelectric conversion efficiency of the solar cell. Secondly, when the thickness of the silicon oxide layer 113 is within this range, the silicon oxide layer 113 can also serve as a tunneling layer, thereby allowing the majority carriers to perform quantum tunneling, and it is difficult for the minority carriers to pass through the silicon oxide layer 113, thereby increasing the carrier transmission rate.

[0060] The thickness of the silicon oxide layer 113 may range from 2 nm to 2.2 nm, 2.2 nm to 2.4 nm, 2.4 nm to 2.6 nm, 2.6 nm to 2.7 nm, or 2.8 nm to 3 nm. The thickness of the silicon oxide layer 113 may range from 2.1 nm, 2.3 nm, 2.5 nm, 2.7 nm, or 2.9 nm.

[0061] In some embodiments, the middle layer 111 is a tunneling layer. The semiconductor doped layer 112 may be a doped polysilicon layer, and a passivation contact structure is formed between the tunneling layer and the doped polysilicon layer. The doped polysilicon layer can form an energy band bending on the surface of the substrate 100. The tunneling layer causes an asymmetric shift in the energy band on the surface of the substrate 100, so that the barrier to the majority carriers among the carriers is lower than the barrier to the minority carriers among the carriers. Therefore, the majority carriers can easily perform quantum tunneling through the tunneling layer, while the minority carriers are difficult to pass through the tunneling layer, so as to realize the selective transmission of carriers.

[0062] In addition, the tunneling layer plays a role of chemical passivation. Specifically, due to the presence of interface state defects at the interface between the substrate 100 and the tunneling layer, the interface state density on the front side of the substrate 100 is relatively large, and the increase in the interface state density promotes the recombination of photogenerated carriers, increases the fill factor, short-circuit current and open-circuit voltage of the solar cell, and improves the photoelectric conversion efficiency of the solar cell.

[0063] In some embodiments, the thickness of the tunneling layer is 0.5 nm to 5 nm. The thickness of the tunneling layer ranges from 0.5 nm to 1.3 nm, 1.3 nm to 2.6 nm, 2.6 nm to 4.1 nm, or 4.1 nm to 5 nm. When the thickness of the tunneling layer is within any of the above ranges, the thickness of the tunneling layer is thinner, and majority carriers can more easily perform quantum tunneling through the tunneling layer, while minority carriers find it difficult to pass through the tunneling layer, so as to achieve selective transmission of carriers.

[0064] The doped polysilicon layer has a field passivation effect. Specifically, an electrostatic field pointing to the inside of the substrate 100 is formed on the surface of the substrate 100, so that minority carriers escape from the interface, thereby reducing the minority carrier concentration, so that the carrier recombination rate at the interface of the substrate 100 is reduced, thereby increasing the open circuit voltage, short circuit current and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0065] The doped polysilicon layer may be doped with the same type of doping elements as the substrate 100 . For example, the doping element type of the substrate 100 is N-type.

[0066] In some embodiments, the material of the tunneling layer includes silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0067] In some embodiments, the tunneling layer is a tunneling silicon oxide layer, and the density of the tunneling silicon oxide layer is greater than the density of the silicon oxide layer 113. In this way, the density of the tunneling silicon oxide layer is relatively large, which can prevent the electrode slurry from passing through the tunneling silicon oxide layer, thereby causing damage to the tunneling silicon oxide layer, thereby affecting the passivation effect of the tunneling silicon oxide layer. The tunneling silicon oxide layer can also serve as a barrier layer to avoid metal composite problems caused by the contact between the electrode slurry and the substrate 100, or even high series resistance problems.

[0068] In some embodiments, the thickness of the tunneling silicon oxide layer is greater than the thickness of the silicon oxide layer 113. The thickness of the tunneling silicon oxide layer is relatively large, which can block the electrode slurry from penetrating and reduce the electrical loss of the solar cell. The thickness of the silicon oxide layer 113 is relatively small, and the optical properties of the silicon oxide layer 113 are better, which can have lower optical absorption and improve the good chemical passivation effect to improve the photoelectric conversion efficiency.

[0069] In some embodiments, reference Figure 1 , the silicon oxide layer 113 is located in the non-metallic region 12. In other embodiments (not shown), the silicon oxide layer is not only located in the non-metallic region, but also located on the surface of the semiconductor doping layer, that is, between the semiconductor doping layer and the anti-reflection layer.

[0070] Continue to refer Figure 1 The second surface 102 of the solar cell has a doped layer 103 , and the doped layer 103 serves as an emitter of the solar cell.

[0071] The solar cell further includes a passivation layer 106 , which is located on the surface of the doping layer 103 .

[0072] The passivation layer 106 may be a single layer structure or a stacked layer structure, and the material of the passivation layer 106 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, titanium oxide, hafnium oxide or aluminum oxide. In the embodiment of the present application, the material of the passivation layer 106 is an aluminum oxide layer as an example.

[0073] The solar cell further includes a first anti-reflection layer 107 , which is located on the surface of the passivation layer 106 .

[0074] The first anti-reflection layer 107 may be a single-layer structure or a stacked-layer structure, and the material of the first anti-reflection layer 107 may be one or more materials selected from silicon nitride, silicon oxynitride, silicon carbon nitride oxide, and the like.

[0075] The anti-reflection layer 117 may also be a single-layer structure or a stacked-layer structure. The material of the anti-reflection layer 117 may be one or more materials selected from silicon nitride, silicon oxynitride, silicon carbon nitride oxide, and the like.

[0076] In some embodiments, the anti-reflection layer 117 and the first anti-reflection layer 107 are made of the same material, and the anti-reflection layer 117 and the first anti-reflection layer 107 can be prepared in the same preparation process.

[0077] In some embodiments, the electrode 118 can be sintered by a burn-through paste. The method of forming the electrode 118 includes: printing a metal paste on a surface of a portion of the anti-reflection layer 117 using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel. Then, the metal paste is subjected to a sintering process, and the metal paste contains a material with a highly corrosive component such as glass powder. In this way, during the sintering process, the corrosive component will corrode the anti-reflection layer 117, so that the metal paste penetrates into the anti-reflection layer 117 and is in electrical contact with the semiconductor doping layer 112.

[0078] In some embodiments, the electrode 118 may be formed by sintering LECO (Laser-enhanced contact optimization) slurry, and part of the LECO slurry corrodes the anti-reflection layer and penetrates into the semiconductor doping layer 112 or forms an electrical connection with the semiconductor doping layer 112 through crystals.

[0079] Continue to refer Figure 1 The solar cell further includes a first electrode 108 . The first electrode 108 is located on the first anti-reflection layer 107 . The first electrode 108 is in electrical contact with the doping layer 103 .

[0080] The first electrode 108 may be formed by sintering a fire-through slurry, or may be formed by sintering a LECO slurry.

[0081] In some embodiments, the orthographic projection of the first electrode 108 on the first surface 101 overlaps with the orthographic projection of the electrode 118 on the first surface 101. In other embodiments, the orthographic projection of the first electrode on the first surface and the orthographic projection of the electrode on the first surface are staggered, partially overlapped, or completely non-overlapped along the electrode arrangement direction.

[0082] In some embodiments, the first electrode 108 and the electrode 118 are made of the same material, and the first electrode 108 and the electrode 118 can be prepared in the same process step.

[0083] The solar cell provided in the embodiment of the present application has a substrate 100 having metal regions 11 and non-metal regions 12 arranged alternately, an intermediate layer 111 and a semiconductor doping layer 112 are arranged on the metal region 11; a silicon oxide layer 113 is arranged on the non-metal region 12, and then an anti-reflection layer is arranged, the anti-reflection layer is located on the semiconductor doping layer 112 and the silicon oxide layer 113, and the electrode is located on the anti-reflection layer and is in electrical contact with the semiconductor doping layer 112. In this way, for the non-metal region 12, the semiconductor doping layer 112 is not arranged, which can avoid the optical absorption problem caused by the thickness of the semiconductor doping layer 112 and the carrier recombination problem caused by the high doping concentration of the semiconductor doping layer 112; the semiconductor doping layer 112 on the metal region 11 is in contact with the electrode, and the semiconductor doping layer 112 can form a good contact with the electrode, thereby reducing the series resistance between the semiconductor doping layer 112 and the electrode. Secondly, a silicon oxide layer 113 is disposed on the surface of the substrate 100 in the non-metallic area 12. The silicon oxide layer 113 is an optically transparent layer and will not sacrifice the optical incidence of the first surface. A large amount of positive charge exists in the area where the silicon oxide layer 113 contacts the substrate 100, which can enhance interface passivation, thereby enhancing the passivation effect of the battery and improving the photoelectric conversion efficiency.

[0084] Accordingly, the second embodiment of the present application further provides a solar cell, which is similar to the first embodiment ( Figure 1 or Figure 2 ) is that the non-metallic area in the second embodiment is not flush with the metal area, and the non-metallic area is recessed toward the second surface compared to the metal area. Technical features that are the same or corresponding to the above embodiments will not be described in detail here.

[0085] Figure 3 A schematic structural diagram of a solar cell provided in the second embodiment of the present application.

[0086] refer to Figure 3The solar cell includes a substrate 200, the substrate 200 has a first surface 201 and a second surface 202 arranged opposite to each other, and the first surface 201 has metal areas 21 and non-metal areas 22 arranged alternately. The solar cell includes a silicon oxide layer 213, and the silicon oxide layer 213 is located in the non-metal area 21 of the first surface 201. The solar cell includes an intermediate layer 211, and the intermediate layer 211 is located in the metal area 21 of the first surface 201. The solar cell includes a semiconductor doping layer 212, and the semiconductor doping layer 212 is located on the surface of the intermediate layer 211. The solar cell includes an anti-reflection layer 217, and the anti-reflection layer 217 is located on the semiconductor doping layer 212 and on the surface of the silicon oxide layer 213. The solar cell includes an electrode 218, and the electrode 218 is located on the anti-reflection layer 217 corresponding to the metal area 21, and the electrode 218 is electrically connected to the semiconductor doping layer 212.

[0087] In some embodiments, the metal area of ​​the first surface of the substrate is a polished surface, and the non-metal area of ​​the first surface of the substrate is a polished surface. In other embodiments, the metal area of ​​the first surface of the substrate is a polished surface, and the non-metal area of ​​the first surface of the substrate has a velvet structure. In still other embodiments, the metal area of ​​the substrate has a first tower base structure, and the non-metal area has a second tower base structure, and the first tower base structure and the second tower base structure are different in size, height, and specific surface area.

[0088] refer to Figure 3 , the non-metallic area 22 of the first surface 201 is recessed toward the second surface 202 and forms a groove compared to the metal area 21 of the first surface 201. In this way, the first surface 201 of the substrate presents an uneven profile surface, the non-metallic area 22 is concave, and the metal area 21 is convex, and the unevenness between the two can improve the light trapping effect, thereby improving the light absorption rate.

[0089] In some embodiments, the distance h2 between the non-metallic area 22 of the first surface 201 and the metal area 21 of the first surface 201 ranges from 3 μm to 4 μm, that is, the depth of the groove formed on the first surface of the substrate ranges from 3 μm to 4 μm, so that the metal area 21 and the non-metallic area 22 can be better distinguished during the subsequent printing of the slurry, thereby avoiding the offset of the electrode 208. Secondly, based on the different heights of the non-metallic area 22 and the metal area 21, the concave structure formed can increase the internal reflection of the incident light, thereby improving the photoelectric conversion efficiency of the battery. Secondly, by etching the non-metallic area to a certain depth, some defects in the non-metallic area can be removed, thereby reducing the dead layer and the recombination center of the non-metallic area, thereby improving the photoelectric conversion efficiency of the battery.

[0090] The distance h2 between the metal area 21 of the first surface 201 and the non-metal area 22 of the first surface 201 may range from 3 μm to 3.2 μm, 3.2 μm to 3.4 μm, 3.4 μm to 3.6 μm, 3.6 μm to 3.8 μm or 3.8 μm to 4 μm. The distance h2 between the metal area 21 of the first surface 201 and the non-metal area 22 of the first surface 201 may range from 3.1 μm, 3.3 μm, 3.5 μm, 3.7 μm or 3.9 μm.

[0091] In some embodiments, the silicon oxide layer 213 is located in the non-metallic area 22 and at the junction of the non-metallic area 22 and the metal area 21, that is, it is also located on the side of the substrate 200 corresponding to the metal area 21. In this way, the silicon oxide layer 213 can cover the substrate 200 not covered by the intermediate layer 211, that is, the surface of the substrate 200 exposed by the intermediate layer 211, so that each surface of the substrate 200 can be passivated to reduce the recombination rate on the surface of the substrate 200 and improve the photoelectric conversion efficiency of the battery.

[0092] Among them, what is exposed on the substrate is not only the non-metallic area, but also the non-metallic area and the metal area form a groove, the side and bottom of the groove are exposed, and the formed silicon oxide layer is deposited on the bottom and side of the groove, and then formed at the junction of the non-metallic area and the metal area and in the non-metallic area.

[0093] In some embodiments, the pore density of the silicon oxide layer 213 is 5×10 -6 ~5×10 -4 .

[0094] In some embodiments, the thickness of the silicon oxide layer 213 is in the range of 2 nm to 3 nm.

[0095] In some embodiments, the silicon oxide layer 213 includes a first portion 204 and a second portion 205, the first portion 204 is located between the substrate 200 and the second portion 205, the silicon content in the first portion 204 is greater than the silicon content in the second portion 205, and the oxygen content in the first portion 204 is less than the oxygen content in the second portion 205. In this way, the contact performance between the first portion 204 and the substrate 200 is good, and the oxygen atoms can be combined with a large number of silicon dangling bonds, thereby reducing the number of dangling bonds on the surface of the substrate 200, reducing the recombination center of the substrate 200, and thus reducing the carrier recombination rate.

[0096] It should be noted that the silicon oxide layer 213 includes the first part 204 and the second part 205, which is produced by forming a silicon oxide layer on the silicon wafer using a plasma-assisted nitrous oxide (N2O) oxidation treatment method. The plasma-assisted nitrous oxide oxidation treatment method mainly uses N2O as a gas source, and uses the energy of plasma electrons in a plasma enhanced chemical vapor deposition device (Plasma Enhanced Chemical Vaper Deposition, PECVD) to ionize or decompose N2O. The free O ions generated by N2O act on the surface of the silicon wafer, thereby oxidizing the silicon wafer and forming a silicon oxide layer. The plasma-assisted nitrous oxide oxidation treatment method can be regarded as a plasma thermal reaction between a silicon wafer and an oxygen-containing gas at a certain temperature, and its working principle is as follows:

[0097] (1) In the non-equilibrium plasma, electrons react with N2O to decompose N2O to form a mixture of N, O ions and active groups;

[0098] (2) The surface of the substrate made of silicon is exposed to active groups containing O at a certain temperature. These active groups move to the surface of the silicon wafer, causing the surface of the silicon wafer to oxidize and generate SiOx, where 0.3 <x<2。

[0099] In this process, since the oxygen active groups are hindered from moving into the substrate, the oxygen content inside the substrate is less than that outside, thus forming the first part, while the oxygen content on the surface of the substrate is larger, forming the second part. The obstacles include the obstacles formed by the second part that has been formed and the obstacles of the silicon substrate itself.

[0100] Through the combination of the first part and the second part, the second part can have a good passivation effect on the substrate surface, reduce the surface state density and recombination rate of the substrate surface, and the first part can further passivate the substrate, thereby further reducing the recombination rate and improving the passivation effect.

[0101] In some embodiments, the first portion and the second portion have different densities, and the density of the first portion is less than that of the second portion. In other words, the pore density of the first portion is greater than that of the second portion.

[0102] In some embodiments, the intermediate layer 211 is a tunneling layer. The semiconductor doping layer 212 may be a doped polysilicon layer, and a passivation contact structure is formed between the tunneling layer and the doped polysilicon layer. The thickness of the tunneling layer is 0.5 nm to 5 nm. The doped polysilicon layer may be doped with the same type of doping element as the substrate 200, for example, the doping element type of the substrate 200 is N-type. The material of the tunneling layer includes silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon or silicon carbide. The tunneling layer is a tunneling silicon oxide layer, and the density of the tunneling silicon oxide layer is greater than the density of the silicon oxide layer 213.

[0103] In some embodiments, the thickness of the tunneling silicon oxide layer is greater than the thickness of the silicon oxide layer 213 .

[0104] In some embodiments, the silicon oxide layer 213 is located in the non-metal region. In other embodiments (not shown), the silicon oxide layer is not only located in the non-metal region, but also located on the surface of the semiconductor doping layer, that is, between the semiconductor doping layer and the anti-reflection layer.

[0105] The second surface 202 of the solar cell has a doped layer 203 , and the doped layer 203 serves as an emitter of the solar cell.

[0106] The solar cell further includes: a passivation layer 206 , which is located on the surface of the doped layer 203 ; a first anti-reflection layer 207 , which is located on the surface of the passivation layer 206 ; and a first electrode 208 , which is located on the first anti-reflection layer 207 and is in electrical contact with the doped layer 203 .

[0107] It should be noted that the description of the substrate 200, the intermediate layer 211, the semiconductor doping layer 212, the anti-reflection layer 217, the electrode 218, the doping layer 203, the passivation layer 206, the first anti-reflection layer 207 and the first electrode 208 in the second embodiment can refer to the substrate 100, the intermediate layer 111, the semiconductor doping layer 112, the anti-reflection layer 117, the electrode 118, the doping layer 103, the passivation layer 106, the first anti-reflection layer 107 and the first electrode 108 in the first embodiment.

[0108] Correspondingly, the third embodiment of the present application further provides a solar cell, which is different from the solar cell shown in the second embodiment in that the solar cell in the third embodiment further includes a transparent conductive layer, which is located on the non-metallic region and between the anti-reflection layer and the silicon oxide layer. Technical features that are the same or corresponding to the above embodiments will not be described in detail here.

[0109] Figure 4 A schematic structural diagram of a solar cell provided in the third embodiment of the present application.

[0110] refer to Figure 4The solar cell includes a substrate 300, the substrate 300 has a first surface 301 and a second surface 302 arranged opposite to each other, and the first surface 301 has metal areas 31 and non-metal areas 32 arranged alternately. The solar cell includes a silicon oxide layer 313, and the silicon oxide layer 313 is located in the non-metal area 31 of the first surface 301. The solar cell includes an intermediate layer 311, and the intermediate layer 311 is located in the metal area 31 of the first surface 301. The solar cell includes a semiconductor doping layer 312, and the semiconductor doping layer 312 is located on the surface of the intermediate layer 311. The solar cell includes an anti-reflection layer 317, and the anti-reflection layer 317 is located on the semiconductor doping layer 312 and on the surface of the silicon oxide layer 313. The solar cell includes an electrode 318, and the electrode 318 is located on the anti-reflection layer 317 corresponding to the metal area 31, and the electrode 318 is electrically connected to the semiconductor doping layer 312.

[0111] In some embodiments, the metal area of ​​the first surface of the substrate is a polished surface, and the non-metal area of ​​the first surface of the substrate is a polished surface. In other embodiments, the metal area of ​​the first surface of the substrate is a polished surface, and the non-metal area of ​​the first surface of the substrate has a velvet structure. In still other embodiments, the metal area of ​​the substrate has a first tower base structure, and the non-metal area has a second tower base structure, and the first tower base structure and the second tower base structure are different in size, height, and specific surface area.

[0112] In some embodiments, the non-metallic region 32 of the first surface 301 is recessed toward the second surface 302 and forms a groove compared to the metal region 31 of the first surface 301. The distance between the metal region 31 of the first surface 301 and the non-metallic region 32 of the first surface 301 is in the range of 3 μm to 4 μm, that is, the depth of the groove formed on the first surface of the substrate is in the range of 3 μm to 4 μm.

[0113] In some embodiments, the pore density of the silicon oxide layer 313 is 5×10 -6 ~5×10 -4 .

[0114] In some embodiments, the thickness of the silicon oxide layer 313 is in the range of 2 nm to 3 nm.

[0115] In some embodiments, the intermediate layer 311 is a tunneling layer. The semiconductor doping layer 312 may be a doped polysilicon layer, and a passivation contact structure is formed between the tunneling layer and the doped polysilicon layer. The thickness of the tunneling layer is 0.5 nm to 5 nm. The doped polysilicon layer may be doped with the same type of doping element as the substrate 300, for example, the doping element type of the substrate 300 is N-type. The material of the tunneling layer includes silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon or silicon carbide. The tunneling layer is a tunneling silicon oxide layer, and the density of the tunneling silicon oxide layer is greater than the density of the silicon oxide layer 313.

[0116] In some embodiments, the thickness of the tunneling silicon oxide layer is greater than the thickness of the silicon oxide layer 313 .

[0117] In some embodiments, the silicon oxide layer 313 is located in the non-metal region. In other embodiments (not shown), the silicon oxide layer is not only located in the non-metal region, but also located on the surface of the semiconductor doping layer, that is, between the semiconductor doping layer and the anti-reflection layer.

[0118] In some embodiments, reference Figure 4 The solar cell further includes: a transparent conductive layer 314, which is located on the surface of the silicon oxide layer 313; and the transparent conductive layer 314 is in contact with the semiconductor doping layer 312. The transparent conductive layer 314 has a lateral transmission capability, and the transparent conductive layer 314 can transmit the carriers of the non-metallic region 32 to the semiconductor doping layer 312 through the transparent conductive layer 314, and be collected.

[0119] The material of the transparent conductive layer 314 may be at least one of indium tin oxide (or tin-doped indium oxide, Indium Tin Oxide abbreviated as ITO), aluminum-doped zinc oxide (AZO), cerium-doped indium oxide, and tungsten-doped indium oxide.

[0120] It should be noted that although Figure 4 It is further improved on the basis of the second embodiment, but Figure 4 The transparent conductive layer can also be further improved on the basis of the first embodiment. The embodiment of the present application does not provide a detailed description of the solar cell further improved on the basis of the first embodiment. For details, please refer to the description of the transparent conductive layer above.

[0121] The second surface 302 of the solar cell has a doping layer 303 , and the doping layer 303 serves as an emitter of the solar cell.

[0122] The solar cell further includes: a passivation layer 306 , which is located on the surface of the doped layer 303 ; a first anti-reflection layer 307 , which is located on the surface of the passivation layer 306 ; and a first electrode 308 , which is located on the first anti-reflection layer 307 and is in electrical contact with the doped layer 303 .

[0123] It should be noted that, the description of the substrate 300, the doping layer 303, the intermediate layer 311, the semiconductor doping layer 312, the anti-reflection layer 317, the electrode 318, the passivation layer 306, the first anti-reflection layer 307, the first electrode 308 and the silicon oxide layer 313 in the third embodiment can refer to the substrate 200, the doping layer 203, the intermediate layer 211, the semiconductor doping layer 212, the anti-reflection layer 217, the electrode 218, the passivation layer 206, the first anti-reflection layer 207, the first electrode 208 and the silicon oxide layer 213 in the second embodiment.

[0124] Correspondingly, the fourth embodiment of the present application also provides a solar cell, which is different from the solar cell shown in the third embodiment in that the intermediate layer in the solar cell in the fourth embodiment is an intrinsic amorphous silicon layer, the semiconductor doping layer is a doped amorphous silicon layer, and the transparent conductive layer is also located in the metal region, and the transparent conductive layer is located between the anti-reflection layer and the silicon oxide layer and between the semiconductor doping layer and the anti-reflection layer. Technical features that are the same or corresponding to the above embodiments will not be described in detail here.

[0125] Figure 5 A schematic structural diagram of a solar cell provided in the fourth embodiment of the present application.

[0126] refer to Figure 5 The solar cell includes a substrate 400, the substrate 400 has a first surface 401 and a second surface 402 arranged opposite to each other, and the first surface 401 has metal areas 41 and non-metal areas 42 arranged alternately. The solar cell includes a silicon oxide layer 413, and the silicon oxide layer 413 is located in the non-metal area 41 of the first surface 401. The solar cell includes an intermediate layer 421, and the intermediate layer 421 is located in the metal area 41 of the first surface 401. The solar cell includes a semiconductor doping layer 422, and the semiconductor doping layer 422 is located on the surface of the intermediate layer 421. The solar cell includes an anti-reflection layer 417, and the anti-reflection layer 417 is located on the semiconductor doping layer 422 and on the surface of the silicon oxide layer 413. The solar cell includes an electrode 418, and the electrode 418 is located on the anti-reflection layer 417 corresponding to the metal area 41, and the electrode 418 is electrically connected to the semiconductor doping layer 422.

[0127] In some embodiments, the metal area of ​​the first surface of the substrate is a polished surface, and the non-metal area of ​​the first surface of the substrate is a polished surface. In other embodiments, the metal area of ​​the first surface of the substrate is a polished surface, and the non-metal area of ​​the first surface of the substrate has a velvet structure. In still other embodiments, the metal area of ​​the substrate has a first tower base structure, and the non-metal area has a second tower base structure, and the first tower base structure and the second tower base structure are different in size, height, and specific surface area.

[0128] In some embodiments, the non-metallic region 42 of the first surface 401 is recessed toward the second surface 402 and forms a groove compared to the metal region 41 of the first surface 401. The distance between the metal region 41 of the first surface 401 and the non-metallic region 42 of the first surface 401 is in the range of 3 μm to 4 μm, that is, the depth of the groove formed on the first surface of the substrate is in the range of 3 μm to 4 μm.

[0129] The pore density of the silicon oxide layer 413 is 5×10 -6 ~5×10 -4 .

[0130] In some embodiments, the thickness of the silicon oxide layer 413 is in the range of 2 nm to 3 nm.

[0131] In some embodiments, the middle layer 421 is an intrinsic amorphous silicon layer. The semiconductor doping layer 422 is a doped amorphous silicon layer, and a heterojunction structure is formed between the intrinsic amorphous silicon layer and the substrate 400. The intrinsic amorphous silicon layer can have a good passivation effect on the surface of the substrate 400, which can greatly avoid the recombination of carriers and achieve a higher minority carrier lifetime and open circuit voltage.

[0132] In some embodiments, the thickness of the intrinsic amorphous silicon layer may be in a range of greater than or equal to 2 micrometers and less than or equal to 10 micrometers, preferably 5 micrometers.

[0133] In some embodiments, the thickness of the doped amorphous silicon layer ranges from 4 nm to 30 nm. The thickness of the doped amorphous silicon layer can range from 4 nm to 7.2 nm, 7.2 nm to 13 nm, 13 nm to 16.1 nm, 16.1 nm to 21 nm, 21 nm to 25 nm, or 25 nm to 30 nm.

[0134] In other embodiments, the intermediate layer 421 may be an intrinsic microcrystalline silicon layer, an intrinsic silicon oxide layer, an intrinsic nanocrystalline silicon layer or an intrinsic silicon carbide layer. The material of the semiconductor doping layer 422 includes single crystal silicon, nanocrystalline silicon, amorphous silicon or microcrystalline silicon.

[0135] It should be noted that, in some cases, due to the influence of diffusion or doping process conditions of other film layers prepared subsequently, the intrinsic amorphous silicon layer may also include a small amount of doping elements, but the intrinsic amorphous silicon layer with a small amount of doping elements is still regarded as an intrinsic amorphous silicon layer.

[0136] In some embodiments, reference Figure 5 The solar cell further includes a transparent conductive layer 423, which is located on the surface of the silicon oxide layer 413 and the surface of the doped amorphous silicon layer. The transparent conductive layer 423 has a lateral transmission capability, and the transparent conductive layer 423 can collect the carriers of the non-metallic region 42 through the transparent conductive layer 423 by the electrode 418.

[0137] The material of the transparent conductive layer 423 may be at least one of indium tin oxide, aluminum-doped zinc oxide (AZO), cerium-doped indium oxide, and tungsten-doped indium oxide.

[0138] The second surface 402 of the solar cell has a doped layer 403 , and the doped layer 403 serves as an emitter of the solar cell.

[0139] The solar cell further includes: a passivation layer 406 , which is located on the surface of the doped layer 403 ; a first anti-reflection layer 407 , which is located on the surface of the passivation layer 406 ; and a first electrode 408 , which is located on the first anti-reflection layer 407 and is in electrical contact with the doped layer 403 .

[0140] It should be noted that the description of the substrate 400, the doping layer 403, the anti-reflection layer 417, the electrode 418, the passivation layer 406, the first anti-reflection layer 407, the first electrode 408 and the silicon oxide layer 413 in the fourth embodiment can refer to the substrate 300, the doping layer 303, the anti-reflection layer 317, the electrode 318, the passivation layer 306, the first anti-reflection layer 307, the first electrode 308 and the silicon oxide layer 313 in the third embodiment.

[0141] Accordingly, the fifth embodiment of the present application also provides a solar cell, which is different from the solar cell shown in the fourth embodiment in that the transparent conductive layer in the solar cell in the fifth embodiment is only located in the non-metallic region, and the transparent conductive layer is in contact with the semiconductor doping layer. Technical features that are the same as or corresponding to the above embodiments will not be described in detail here.

[0142] refer to Figure 6 The solar cell includes a substrate 500, the substrate 500 has a first surface 501 and a second surface 502 arranged opposite to each other, and the first surface 501 has metal areas 51 and non-metal areas 52 arranged alternately. The solar cell includes a silicon oxide layer 513, and the silicon oxide layer 513 is located in the non-metal area 51 of the first surface 501. The solar cell includes an intermediate layer 521, and the intermediate layer 521 is located in the metal area 51 of the first surface 501. The solar cell includes a semiconductor doping layer 522, and the semiconductor doping layer 522 is located on the surface of the intermediate layer 521. The solar cell includes an anti-reflection layer 517, and the anti-reflection layer 517 is located on the semiconductor doping layer 522 and on the surface of the silicon oxide layer 513. The solar cell includes an electrode 518, and the electrode 518 is located on the anti-reflection layer 517 corresponding to the metal area 51, and the electrode 518 is electrically connected to the semiconductor doping layer 522.

[0143] In some embodiments, the metal area of ​​the first surface of the substrate is a polished surface, and the non-metal area of ​​the first surface of the substrate is a polished surface. In other embodiments, the metal area of ​​the first surface of the substrate is a polished surface, and the non-metal area of ​​the first surface of the substrate has a velvet structure. In still other embodiments, the metal area of ​​the substrate has a first tower base structure, and the non-metal area has a second tower base structure, and the first tower base structure and the second tower base structure are different in size, height, and specific surface area.

[0144] In some embodiments, the non-metallic region 52 of the first surface 501 is recessed toward the second surface 502 and forms a groove compared to the metal region 51 of the first surface 501. The distance between the metal region 51 of the first surface 501 and the non-metallic region 52 of the first surface 501 is in the range of 3 μm to 4 μm, that is, the depth of the groove formed on the first surface of the substrate is in the range of 3 μm to 4 μm.

[0145] The pore density of the silicon oxide layer 513 is 5×10 -6 ~5×10 -4 .

[0146] In some embodiments, the thickness of the silicon oxide layer 513 is in the range of 2 nm to 3 nm.

[0147] In some embodiments, the middle layer 521 is an intrinsic amorphous silicon layer. The semiconductor doping layer 522 is a doped amorphous silicon layer, and a heterojunction structure is formed between the intrinsic amorphous silicon layer and the substrate 500. The thickness of the doped amorphous silicon layer ranges from 4 nm to 30 nm.

[0148] In other embodiments, the intermediate layer 521 may be an intrinsic microcrystalline silicon layer, an intrinsic silicon oxide layer, an intrinsic nanocrystalline silicon layer or an intrinsic silicon carbide layer. The material of the semiconductor doping layer 522 includes single crystal silicon, nanocrystalline silicon, amorphous silicon or microcrystalline silicon.

[0149] In some embodiments, the solar cell further includes: a transparent conductive layer 523, the transparent conductive layer 523 is located on the surface of the silicon oxide layer 513, and the transparent conductive layer 523 is in contact with the semiconductor doping layer 522. The transparent conductive layer 523 has a lateral transmission capability, and the transparent conductive layer 523 can be provided to transmit the carriers of the non-metallic region 52 to the semiconductor doping layer 522 via the transparent conductive layer 523, and be collected.

[0150] The second surface 502 of the solar cell has a doped layer 503 , and the doped layer 503 serves as an emitter of the solar cell.

[0151] The solar cell further includes: a passivation layer 506 , which is located on the surface of the doping layer 503 ; a first anti-reflection layer 507 , which is located on the surface of the passivation layer 506 ; and a first electrode 508 , which is located on the first anti-reflection layer 507 and is in electrical contact with the doping layer 503 .

[0152] It should be noted that, the description of the substrate 500, the doping layer 503, the anti-reflection layer 517, the electrode 518, the passivation layer 506, the first anti-reflection layer 507, the intermediate layer 521, the semiconductor doping layer 522, the transparent conductive layer 523, the first electrode 508 and the silicon oxide layer 513 in the fifth embodiment can refer to the substrate 400, the doping layer 403, the anti-reflection layer 417, the electrode 418, the passivation layer 406, the first anti-reflection layer 407, the intermediate layer 421, the semiconductor doping layer 422, the transparent conductive layer 423, the first electrode 408 and the silicon oxide layer 413 in the fourth embodiment.

[0153] In order to further understand the embodiments of the present application, the passivation layer for passivating solar cells and the solar cell provided by the present application are described below in conjunction with the embodiments. The protection scope of the present application is not limited by the following embodiments.

[0154] Example 1: Using Figure 1 The solar cell shown in the figure adopts an N-type single crystal silicon wafer with a size of 156 mm×156 mm, a resistivity of 1.52 Ω·cm, and a thickness of 180 μm. The second surface of the substrate has a velvet structure. The second surface of the substrate has a doping layer, a passivation layer, and a first anti-reflection layer in sequence, wherein the doping layer is a P-type doping layer, the passivation layer is an aluminum oxide layer, and the first anti-reflection layer is a silicon nitride layer. The first surface of the substrate has a metal region and a non-metal region, the metal region is flush with the non-metal region, a tunneling silicon oxide layer and a doped polysilicon layer are in sequence on the metal region, the non-metal region and the doped polysilicon layer have a silicon oxide layer on the surface, and the silicon oxide layer has an anti-reflection layer on the surface, wherein the anti-reflection layer is a silicon nitride layer, and the pore density of the silicon oxide layer is 1×10 -5 The first surface of the substrate has an electrode, the electrode is in contact with the doped polysilicon layer, and the second surface of the substrate has a first electrode, the first electrode is in contact with the doped layer.

[0155] Embodiment 2: The difference from Embodiment 1 is that the metal area on the first surface is closer to the second surface than the non-metal area on the first surface, and the distance between the metal area on the first surface and the non-metal area on the first surface is 3 μm.

[0156] Embodiment 3: The difference from Embodiment 1 is that a transparent conductive layer is provided between the silicon oxide layer and the anti-reflection layer, and the thickness of the transparent conductive layer is 70 nm.

[0157] Embodiment 4: The difference from Embodiment 1 is that the metal region is not formed by a tunneling silicon oxide layer and a doped polysilicon layer, but by an intrinsic amorphous silicon layer and a doped amorphous silicon layer stacked in sequence.

[0158] Embodiment 5: The difference from Embodiment 4 is that a transparent conductive layer is provided between the silicon oxide layer and the anti-reflection layer, and extends to between the doped amorphous silicon layer and the anti-reflection layer. The thickness of the transparent conductive layer is 70 nm.

[0159] Control group: The difference from Example 1 is that there is no silicon oxide layer on the metal area, and the anti-reflection layer is directly located on the surface of the doped polysilicon layer and the non-metal area.

[0160] The performance of the solar cell was measured, and the results are shown in Table 1. Table 1 is the performance measurement results of the solar cells provided by Examples 1 to 5 of the present application and the control group.

[0161] Table 1

[0162]

[0163] It can be seen from Table 1 that the technical solution of the present application, i.e., forming a silicon oxide layer, can achieve a greater conversion efficiency, thereby improving the battery efficiency of the battery.

[0164] Correspondingly, another aspect of the embodiment of the present application further provides a method for preparing a solar cell, which is used to prepare the solar cell provided by the above embodiment. The technical features that are the same as or corresponding to the above embodiment will not be described in detail here.

[0165] Figure 7 to Figure 12 A schematic diagram of the structure of a solar cell corresponding to each step in a method for preparing a solar cell provided in another embodiment of the present application. Figure 2 A solar cell is shown as an example.

[0166] refer to Figure 7 to Figure 12 The preparation method includes: providing a substrate 200, the substrate 200 has a first surface 201 and a second surface 202 arranged opposite to each other, the first surface 201 has metal areas 21 and non-metal areas 22 arranged alternately; forming a silicon oxide layer 213, the silicon oxide layer 213 is located in the non-metal area 22 of the first surface 201; forming an intermediate layer 211 and a semiconductor doping layer 212, the intermediate layer 211 is located in the metal area 21 of the first surface; the semiconductor doping layer 212 is located on the surface of the intermediate layer 211.

[0167] In some embodiments, the process steps of providing the substrate 200, forming the silicon oxide layer 213, and forming the intermediate layer 211 and the semiconductor doping layer 212 include the following steps:

[0168] refer to Figure 5 and Figure 6 , providing an initial substrate 209, the initial substrate 209 includes a first sub-surface 231 and a second sub-surface 232, the first sub-surface 231 has metal areas 21 and non-metal areas 22 arranged alternately.

[0169] refer to Figure 5 , providing an initial substrate 209.

[0170] refer to Figure 6The second sub-surface 232 is subjected to texturing treatment so that the second sub-surface 232 of the initial substrate 209 forms a velvet structure. The texturing treatment may include conventionally selected methods such as solution texturing, laser texturing, and ion texturing.

[0171] refer to Figure 7 The preparation method includes: forming a doping layer 203, and the doping layer 203 serves as an emitter of a solar cell.

[0172] In some embodiments, the initial substrate 209 may be subjected to a diffusion process so as to convert a portion of the initial substrate 209 into the doped layer 203 .

[0173] refer to Figure 7 , an intermediate film 223 and a semiconductor doped film 224 are formed on the first sub-surface 231 .

[0174] refer to Figure 8 , the intermediate film 223 and the semiconductor doping film 224 corresponding to the non-metallic region 22 are removed, and the first sub-surface 231 of the initial substrate 209 is exposed.

[0175] In other embodiments, reference Fig. 9 After removing the intermediate film 223 and the semiconductor doped film 224 corresponding to the non-metallic area 22, the initial substrate 209 is further etched, and the non-metallic area 22 is concave relative to the metal area 21 toward the second sub-surface 232 (second surface 202), and the depth of the concave is h1.

[0176] refer to Fig.10 , forming a silicon oxide layer 213, which is located on the exposed first sub-surface; wherein the remaining initial substrate 209 serves as the substrate 100, and the surface of the initial substrate 209 in contact with the silicon oxide layer 113 and the surface of the intermediate film 223 in contact with the initial substrate 209 together serve as the first surface 201.

[0177] In some embodiments, the silicon oxide layer 213 is formed by plasma enhanced chemical vapor deposition, wherein the plasma oxidizing gas includes nitrous oxide.

[0178] In some embodiments, the process steps for forming the silicon oxide layer 213 include: the flow rate of nitrous oxide gas is 10000 sccm to 13000 sccm, the process pressure is 2300 Pa to 3150 Pa, the RF power is 10000 W to 14000 W, and the ionization time is 100 s to 150 s.

[0179] Among them, the silicon oxide layer 213 is formed by bombarding the substrate with oxygen source plasma and then reacting with the silicon element of the substrate. The silicon oxide layer 213 can include a first part 204 and a second part 205. The first part 204 is located between the substrate 200 and the second part 205. The silicon element content in the first part 204 is greater than the silicon element content in the second part 205, and the oxygen element content in the first part 204 is less than the oxygen element content in the second part 205.

[0180] It can be understood that, in the solar cell after the silicon oxide layer 213 is formed, the non-metallic region 22 is concave relative to the metal region 21 toward the second sub-surface 232 (second surface 202 ), and the depth of the concave is h2 , which is greater than or equal to h1 .

[0181] refer to Figure 1 The preparation method includes: forming an anti-reflection layer 217, which is located on the semiconductor doping layer 212 and the surface of the silicon oxide layer 213; forming an electrode 218, which is located on the anti-reflection layer 217 corresponding to the metal area 21, and the electrode 218 is electrically connected to the semiconductor doping layer 212.

[0182] In some embodiments, the silicon oxide layer 213 and the anti-reflection layer 217 are formed in the same reaction device.

[0183] refer to Figure 1 The preparation method includes: forming a passivation layer 206, the passivation layer 206 is located on the surface of the doping layer 203; forming a first anti-reflection layer 207, the first anti-reflection layer 207 is located on the surface of the passivation layer 206; forming a first electrode 208, the first electrode 208 is located on the first anti-reflection layer 207, and the first electrode 208 is in electrical contact with the doping layer 203.

[0184] Correspondingly, another embodiment of the present application also provides a stacked battery, including the solar cell of any one of the above embodiments or the solar cell prepared by the solar cell preparation method of any one of the above embodiments, and the technical features that are the same or corresponding to the above embodiments will not be described in detail here.

[0185] Fig.13 A schematic structural diagram of a stacked battery provided in yet another embodiment of the present application.

[0186] refer to Fig.13 The stacked battery includes: a bottom battery 150, which is a solar cell prepared by the preparation method of any one of the above embodiments or a solar cell of any one of the above embodiments; and a top battery 180, which is located on the bottom battery 150.

[0187] In some embodiments, the stacked battery has a first gridline 186 of a first polarity and a second gridline of a second polarity, wherein the first gridline 186 is in electrical contact with the top battery 180 and the second gridline is in electrical contact with the bottom battery 150. The second gridline is the electrode 118 of the bottom battery.

[0188] In some embodiments, an interface layer 181 is provided between the top cell and the bottom cell, and the interface layer 181 also covers the passivation contact structure on the back side, that is, covers the silicon oxide layer 113 and the semiconductor doping layer 112 .

[0189] It is worth noting that the stacked cell in the embodiment of the present application only illustrates two layers of solar cells, and those skilled in the art can set three layers of solar cells or more than three layers of stacked solar cells according to actual needs.

[0190] In some embodiments, the top cell 180 may be a perovskite solar cell, which includes: a stacked first transmission layer 182, a perovskite substrate 183, a second transmission layer 184, a first transparent conductive layer 185, and an anti-reflection layer (not shown). The first transmission layer is directly opposite to the bottom cell.

[0191] In some embodiments, the first transport layer may be one of an electron transport layer and a hole transport layer, and the second transport layer may be the other of the electron transport layer and the hole transport layer.

[0192] Correspondingly, on the other hand, an embodiment of the present application further provides a photovoltaic component, including a solar cell of any one of the above embodiments or a solar cell prepared by the solar cell preparation method of any one of the above embodiments, and technical features that are the same or corresponding to the above embodiments will not be described in detail here.

[0193] Fig.14 A schematic structural diagram of a photovoltaic module provided in yet another embodiment of the present application.

[0194] refer to Fig.14 The photovoltaic module includes: a battery string, which is formed by connecting a plurality of solar cells 10 as in any one of the above embodiments or a plurality of solar cells 10 prepared by the solar cell preparation method as in any one of the above embodiments through a connecting component 220; a packaging film 23, which is used to cover the surface of the battery string; and a cover plate 24, which is used to cover the surface of the packaging film 23 away from the battery string.

[0195] Specifically, in some embodiments, multiple battery cells may be electrically connected through a connecting component 220, and the connecting component 220 is welded to a main grid on the battery cell. The main grid includes a main electrode electrically connected to the first electrode and a main electrode electrically connected to the electrode.

[0196] In some embodiments, no intervals are set between the battery cells, that is, the battery cells overlap each other.

[0197] In some embodiments, the connection component 220 is welded to the auxiliary grid on the battery cell, and the auxiliary grid includes an electrode and a first electrode.

[0198] In some embodiments, the encapsulation film 23 includes a first encapsulation layer and a second encapsulation layer, the first encapsulation layer covers one of the front side or the back side of the solar cell, and the second encapsulation layer covers the other of the front side or the back side of the solar cell. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as a polyvinyl butyral (PVB) film, an ethylene-vinyl acetate copolymer (EVA) film, a polyethylene octene co-elastomer (POE) film or a polyethylene terephthalate (PET) film.

[0199] It is worth noting that there is a boundary line between the first encapsulation layer and the second encapsulation layer before lamination. After lamination, the photovoltaic module is no longer a first encapsulation layer and a second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 23.

[0200] In some embodiments, the cover plate 24 may be a glass cover plate, a plastic cover plate or the like with a light-transmitting function. Specifically, the surface of the cover plate 24 facing the encapsulation film 23 may be a concave-convex surface, thereby increasing the utilization rate of the incident light. The cover plate 24 includes a first cover plate and a second cover plate, the first cover plate is opposite to the first encapsulation layer, and the second cover plate is opposite to the second encapsulation layer; or the first cover plate is opposite to one side of the solar cell, and the second cover plate is opposite to the other side of the solar cell.

[0201] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application, and therefore the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A solar cell, characterized in that: include: A substrate, wherein the substrate has a first surface and a second surface that are oppositely disposed, and the first surface has metal areas and non-metal areas that are alternately arranged; A silicon oxide layer, the silicon oxide layer is located in the non-metallic area of ​​the first surface; the pore density of the silicon oxide layer is 5×10 -6 ~5×10 -4 ; an intermediate layer, the intermediate layer being located in the metal area of ​​the first surface; A semiconductor doping layer, wherein the semiconductor doping layer is located on the surface of the intermediate layer; an anti-reflection layer, the anti-reflection layer being located on the semiconductor doping layer and on the surface of the silicon oxide layer; An electrode is located on the anti-reflection layer corresponding to the metal area, and the electrode is electrically connected to the semiconductor doping layer.

2. The solar cell according to claim 1, characterized in that The non-metallic area is recessed toward the second surface compared to the metal area to form a groove; the depth of the groove ranges from 3 μm to 4 μm.

3. The solar cell according to claim 1, characterized in that The silicon oxide layer includes a first part and a second part, the first part is located between the substrate and the second part, the silicon content in the first part is greater than the silicon content in the second part, and the oxygen content in the first part is less than the oxygen content in the second part.

4. The solar cell according to claim 1, characterized in that The thickness of the silicon oxide layer is 2nm-3nm.

5. The solar cell according to claim 1, characterized in that: The middle layer is a tunneling layer; the tunneling layer is a tunneling silicon oxide layer, and the density of the tunneling silicon oxide layer is greater than the density of the silicon oxide layer.

6. The solar cell according to claim 5, characterized in that: The thickness of the tunneling silicon oxide layer is greater than the thickness of the silicon oxide layer.

7. The solar cell according to claim 1, characterized in that The middle layer is an intrinsic amorphous silicon layer.

8. The solar cell according to any one of claims 1, 5 or 7, characterized in that: Also includes: A transparent conductive layer, wherein the transparent conductive layer is located on the surface of the silicon oxide layer; The transparent conductive layer contacts the semiconductor doping layer.

9. The solar cell according to claim 1, characterized in that: The metal area is a polished surface, and the non-metal area has a suede structure.

10. A method for preparing a solar cell, characterized in that: include: Providing a substrate, wherein the substrate has a first surface and a second surface that are oppositely disposed, and the first surface has metal areas and non-metal areas that are alternately arranged; A silicon oxide layer is formed, wherein the silicon oxide layer is located in the non-metallic region of the first surface; the pore density of the silicon oxide layer is 5×10 -6 ~5×10 -4 ; forming an intermediate layer and a semiconductor doping layer, wherein the intermediate layer is located in the metal region of the first surface; and the semiconductor doping layer is located on the surface of the intermediate layer; forming an anti-reflection layer, wherein the anti-reflection layer is located on the semiconductor doping layer and on the surface of the silicon oxide layer; An electrode is formed, wherein the electrode is located on the anti-reflection layer corresponding to the metal area, and the electrode is electrically connected to the semiconductor doping layer.

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