Aging analysis method and related device

Abstract

Embodiments of the present application provide an aging analysis method and related equipment, wherein the aging analysis method comprises: obtaining a design object to be timing checked, the design object being composed of multiple standard cells; determining a delay aging rate of the standard cell based on an aging cell library, the delay aging rate being used to represent a proportion of an increase in signal transmission delay time of the standard cell caused by aging; wherein the aging cell library comprises multiple sub-aging cell libraries, the sub-aging cell library being used to represent the delay aging rate of the standard cell under a preset aging mechanism, wherein different sub-aging cell libraries correspond to different aging mechanisms; and performing timing analysis on the design object after aging based on the delay aging rate and obtaining a report. Embodiments of the present application can realize accurate evaluation of the aging degree of a chip.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to an aging analysis method and related equipment. Background Technology

[0002] With the rapid development of semiconductor technology and the evolution of Moore's Law, chip integration and complexity have increased unprecedentedly, resulting in significantly enhanced performance. However, this has also exacerbated the chip aging problem. Chip aging leads to transistor performance degradation, such as threshold voltage shift and reduced drive current, which in turn affects circuit timing, threatening the normal function and long-term stability of circuits, and severely impacting the lifespan and reliability of integrated circuits. Although aging phenomena have received widespread attention and close research at the physical / device level, further development and practice are needed to characterize the impact of these aging factors at the design level and apply them to design. Therefore, while pursuing high performance and high integration, how to take the impact of chip aging into account to ensure long-term reliable operation of products has become a key challenge in the field of integrated circuit design.

[0003] Against this backdrop, how to provide an aging analysis method to accurately assess the aging degree of chips has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide an aging analysis method and related equipment to accurately assess the aging degree of a chip.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide an aging analysis method, including:

[0007] Obtain the design object to be time-series checked, the design object consisting of multiple standard units;

[0008] Based on the aging unit library, the delay aging rate of the standard unit is determined. The delay aging rate is used to characterize the proportion of the increase in signal transmission delay time caused by aging of the standard unit. The aging unit library includes multiple sub-aging unit libraries, which are used to characterize the delay aging rate of the standard unit under a preset aging mechanism. Different sub-aging unit libraries correspond to different aging mechanisms.

[0009] Based on the aforementioned delay aging rate, a time-series analysis of the design object after aging is performed and a report is obtained.

[0010] Optionally, the aging unit library includes a first sub-aging unit library and a second sub-aging unit library;

[0011] The first sub-aging cell library is used to characterize the delay aging rate of standard cells under the Negative Bias Temperature Instability (NBTI) mechanism; wherein, the Negative Bias Temperature Instability (NBTI) mechanism is related to the signal probability of the excitation waveform of the standard cell;

[0012] The second sub-aging cell library is used to characterize the delay aging rate of the standard cell under the hot carrier injection (HCI) mechanism; wherein the hot carrier injection (HCI) mechanism is related to the signal switching rate of the excitation waveform of the standard cell.

[0013] Optionally, determining the delay aging rate of the standard cell based on the aging cell library includes:

[0014] Based on the first sub-aging unit library, the first delayed aging rate of the standard unit is determined;

[0015] Based on the second sub-aging unit library, the second delayed aging rate of the standard unit is determined;

[0016] The first delay aging rate is added to the second delay aging rate to obtain the delay aging rate of the standard cell.

[0017] Optionally, before the step of obtaining the design object to be time-series checked, the method further includes: building an aging cell library.

[0018] Optionally, the construction of the aging unit library includes: constructing a first sub-aging unit library;

[0019] Specifically, constructing the first sub-aging unit library involves:

[0020] A negative bias temperature instability (NBTI) aging model is established. The NBTI aging model is used to simulate the delay aging rate of standard cells under the negative bias temperature instability (NBTI) mechanism.

[0021] Under different signal probabilities and preset conditions, simulations were performed based on the negative bias temperature instability (NBTI) aging model to obtain the first sub-aging unit library.

[0022] The signal probability is the percentage of low-level time in the excitation waveform relative to the total signal duration.

[0023] Optionally, the construction of the aging unit library further includes: constructing a second sub-aging unit library;

[0024] Specifically, the construction of the second sub-aging unit library includes:

[0025] A hot carrier injection HCI aging model is established, which is used to simulate the delay aging rate of standard cells under the hot carrier injection HCI mechanism.

[0026] Under different signal switching rates and preset conditions, simulations were performed based on the hot carrier injection HCI aging model to obtain the second sub-aging unit library.

[0027] The signal switching rate is the number of times the signal flips per cycle, or per unit time.

[0028] Optionally, the first sub-aging unit library is a three-dimensional lookup table, where the three dimensions are input transition time, output capacitive load, and signal probability, respectively. The determination of the first delay aging rate of the standard unit based on the first sub-aging unit library specifically involves:

[0029] Determine the input transition time and output capacitive load of the standard unit;

[0030] Determine the signal probability of the excitation waveform of the standard unit;

[0031] The first sub-aging unit library is searched to determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit, and this delay aging rate is used as the first delay aging rate.

[0032] Optionally, the step of searching the first sub-aging unit library and determining the delay aging rate corresponding to the input transition time, output capacitive load, and signal probability of the excitation waveform of the standard unit includes:

[0033] If the first sub-aging unit library does not contain a delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit, then the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit is determined by interpolation.

[0034] Optionally, the second sub-aging unit library is a three-dimensional lookup table, where the three dimensions are input transition time, output capacitance load, and signal switching rate. The determination of the second delay aging rate of the standard unit based on the second sub-aging unit library specifically involves:

[0035] Determine the input transition time and output capacitive load of the standard unit;

[0036] Determine the signal switching rate of the excitation waveform of the standard unit;

[0037] Locate the second sub-aging unit library, determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal switching rate of the excitation waveform of the standard unit, and use this delay aging rate as the second delay aging rate.

[0038] Optionally, the step of searching the second sub-aging unit library and determining the delay aging rate corresponding to the input transition time, output capacitance load, and signal switching rate of the excitation waveform of the standard unit includes:

[0039] If the second sub-aging unit library does not contain a delay aging rate corresponding to the input transition time, output capacitor load, and signal switching rate of the excitation waveform of the standard unit, then the delay aging rate corresponding to the input transition time, output capacitor load, and signal switching rate of the excitation waveform of the standard unit is determined by interpolation.

[0040] Optionally, after the step of obtaining the design object to be time-checked and before the step of determining the delay aging rate of the standard cell based on the aging cell library, the method further includes:

[0041] Determine whether the design object needs to undergo aging timing checks;

[0042] If the determination result is yes, then the step of determining the delay aging rate of the standard cell based on the aging cell library is executed.

[0043] Secondly, embodiments of this application provide an aging analysis apparatus, comprising:

[0044] The acquisition module is used to acquire the design object to be checked for timing, the design object being composed of multiple standard units;

[0045] An aging analysis module is used to determine the delay aging rate of the standard unit based on an aging unit library. The delay aging rate is used to characterize the proportion of the increase in signal transmission delay time caused by aging of the standard unit. The aging unit library includes multiple sub-aging unit libraries, which are used to characterize the delay aging rate of the standard unit under a preset aging mechanism. Different sub-aging unit libraries correspond to different aging mechanisms.

[0046] The timing analysis module is used to perform timing analysis on the design object after aging based on the delay aging rate and generate a report.

[0047] Optional, also includes:

[0048] The building module is used to build the aging unit library.

[0049] Optional, also includes:

[0050] The judgment module is used to determine whether the design object needs to undergo aging timing checks;

[0051] If the judgment result of the judgment module is yes, then the aging analysis module determines the delay aging rate of the standard unit based on the aging unit library.

[0052] Thirdly, embodiments of this application provide an electronic device including at least one memory and at least one processor, wherein the memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the aging analysis method as described in the first aspect above.

[0053] Fourthly, embodiments of this application provide a storage medium that stores one or more computer-executable instructions, which, when executed, implement the aging analysis method as described in the first aspect above.

[0054] Fifthly, embodiments of this application provide a computer program product including one or more computer-executable instructions, which, when executed, implement the aging analysis method as described in the first aspect above.

[0055] This application provides an aging analysis method and related equipment. The aging analysis method includes: acquiring a design object to be time-series checked, the design object being composed of multiple standard units; determining the delay aging rate of the standard units based on an aging unit library, the delay aging rate being used to characterize the proportion of increase in signal transmission delay time caused by aging of the standard units; wherein the aging unit library includes multiple sub-aging unit libraries, the sub-aging unit libraries being used to characterize the delay aging rate of standard units under a preset aging mechanism, wherein different sub-aging unit libraries correspond to different aging mechanisms; and performing a time-series analysis on the design object after aging based on the delay aging rate and obtaining a report.

[0056] As can be seen, the aging analysis method provided in this application determines the delay aging rate of the standard cell based on an aging cell library comprising multiple sub-aging cell libraries. Each sub-aging cell library characterizes the delay aging rate of the standard cell under a preset aging mechanism, with different sub-aging cell libraries corresponding to different aging mechanisms. By considering multiple different aging mechanisms separately and characterizing their respective effects on the delay aging rate of the standard cell, the delay aging rate of the standard cell can be determined accordingly. This enables accurate assessment of the aging degree of the design object, and consequently, accurate assessment of the chip aging degree. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0058] Figure 1 This is a schematic diagram of an optional process for the aging analysis method provided in the embodiments of this application;

[0059] Figure 2 This is a schematic diagram of an optional structure of the aging unit library provided in the embodiments of this application;

[0060] Figure 3 This is an optional flowchart of step S200 provided in the embodiments of this application;

[0061] Figure 4 This is an optional schematic diagram of the first sub-aging unit library provided in the embodiments of this application;

[0062] Figure 5 This is an optional schematic diagram of the second sub-aging unit library provided in the embodiments of this application;

[0063] Figure 6 This is another optional flowchart of the aging analysis method provided in the embodiments of this application;

[0064] Figure 7 This is an optional schematic diagram of excitation waveforms with different signal probabilities provided in the embodiments of this application;

[0065] Figure 8 This is an optional schematic diagram of the excitation waveforms with different signal switching rates provided in the embodiments of this application;

[0066] Figure 9 This is another optional flowchart of the aging analysis method provided in the embodiments of this application;

[0067] Figure 10 This is a schematic diagram of an optional structure of the aging analysis device provided in the embodiments of this application;

[0068] Figure 11 This is an optional block diagram of the electronic device provided in the embodiments of this application. Detailed Implementation

[0069] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0070] As described in the background section, with the rapid development of semiconductor technology and the evolution of Moore's Law, chip integration and complexity have increased unprecedentedly, resulting in significantly enhanced performance. However, this has also exacerbated the chip aging problem. Chip aging leads to transistor performance degradation, such as threshold voltage shift and reduced drive current, which in turn affects circuit timing, threatens the normal function and long-term stability of the circuit, and seriously impacts the lifespan and reliability of integrated circuits. Although aging phenomena have received widespread attention and close research at the physical / device level, how to characterize the impact of these aging factors at the design level and apply them to design still requires further development and practice. Therefore, while pursuing high performance and high integration, how to take into account the impact of chip aging to ensure long-term reliable operation of products has become a key challenge in the field of integrated circuit design.

[0071] To ensure reliable product operation, as an optional implementation, the potential aging effect can be "compensated" by increasing the timing margin. However, this approach has two problems: first, it may underestimate the actual aging level (underestimation), meaning the increased margin is insufficient to cope with actual aging; second, it may overestimate the aging level (overestimation), leading to an overly conservative design that affects chip performance.

[0072] Therefore, it is particularly important to provide an aging analysis method to accurately assess the aging degree of chips.

[0073] In view of this, embodiments of this application provide an aging analysis method and related equipment. The aging analysis method includes: acquiring a design object to be time-series checked, the design object consisting of multiple standard units; determining the delay aging rate of the standard units based on an aging unit library, the delay aging rate being used to characterize the proportion of increase in signal transmission delay time caused by aging of the standard units; wherein the aging unit library includes multiple sub-aging unit libraries, the sub-aging unit libraries being used to characterize the delay aging rate of standard units under a preset aging mechanism, wherein different sub-aging unit libraries correspond to different aging mechanisms; and performing a time-series analysis on the design object after aging based on the delay aging rate and obtaining a report.

[0074] As can be seen, the aging analysis method provided in this application determines the delay aging rate of the standard cell based on an aging cell library comprising multiple sub-aging cell libraries. Each sub-aging cell library characterizes the delay aging rate of the standard cell under a preset aging mechanism, with different sub-aging cell libraries corresponding to different aging mechanisms. By considering multiple different aging mechanisms separately and characterizing their respective effects on the delay aging rate of the standard cell, the delay aging rate of the standard cell can be determined accordingly. This enables accurate assessment of the aging degree of the design object, and consequently, accurate assessment of the chip aging degree.

[0075] To better understand the solutions provided in the embodiments of this application, the specific details of the aging analysis solution will be further explained below.

[0076] In this application embodiment, an aging analysis method is provided, referring to... Figure 1 The illustrated flowchart of an optional aging analysis method may include:

[0077] Step S100: Obtain the design object to be checked for timing, the design object being composed of multiple standard units.

[0078] The design object to be time-checked refers to an integrated circuit design that requires timing verification and evaluation. The design object may include a series of circuit elements (such as transistors, resistors, capacitors, etc.) and their interconnections. The standard cell refers to a pre-designed, functionally defined logic gate or more complex circuit component within the design object.

[0079] Obtaining the design object to be time-series checked can provide a basis for determining the delay aging rate of the standard cell based on the aging cell library.

[0080] Step S200: Determine the delay aging rate of the standard cell based on the aging cell library.

[0081] The delay aging rate is used to characterize the proportion by which the signal transmission delay time of the standard cell increases due to aging. It is understood that the performance of circuit elements in the standard cell deteriorates due to various aging mechanisms, thereby affecting the signal transmission speed in the circuit. The delay aging rate can be used to quantify and characterize the proportion by which the signal transmission time of the standard cell increases relative to its original state after undergoing the aging process.

[0082] In an optional implementation, the aging cell library may include multiple sub-aging cell libraries, which are used to characterize the delay aging rate of a standard cell under a preset aging mechanism. Different sub-aging cell libraries correspond to different aging mechanisms. This application embodiment considers multiple different aging mechanisms separately, characterizing the delay aging rate of the standard cell caused by each, and determines the delay aging rate of the standard cell accordingly. This enables accurate assessment of the aging degree of the design object, and consequently, accurate assessment of the chip aging degree.

[0083] Further reference Figure 2 , Figure 2 This is a schematic diagram of an optional structure of the aging unit library provided in an embodiment of this application. For example... Figure 2 As shown, the aging unit library may include a first sub-aging unit library and a second sub-aging unit library.

[0084] The first sub-aging cell library is used to characterize the delay aging rate of standard cells under the Negative Bias Temperature Instability (NBTI) mechanism; wherein the NBTI mechanism is related to the signal probability of the excitation waveform of the standard cell. In this embodiment, the signal probability is the percentage of low-level time in the excitation waveform relative to the total signal duration. In other embodiments, the signal probability may also be the percentage of high-level time in the excitation waveform relative to the total signal duration.

[0085] Negative bias temperature instability (NBTI) is a reliability problem in PMOSFETs (P-type metal-oxide-semiconductor field-effect transistors) under specific operating conditions. Specifically, when the voltage between the gate and source of a PMOSFET is negative, the transistor is in a strongly inverted state. The silicon-hydrogen bonds (Si-H) at the silicon (Si) to silicon dioxide (SiO2) interface break under the influence of holes and the electric field in the inversion layer, causing H or H2 to diffuse in the gate oxide layer. This generates interface states at the silicon-SiO2 interface, which cause the threshold voltage to shift in the direction of increasing absolute value, making the device more difficult to turn on. In logic circuits, NBTI leads to increased signal delay, causing timing path degradation and ultimately logic circuit malfunction, posing a serious challenge to the long-term reliability of integrated circuits.

[0086] This embodiment combines the Negative Bias Temperature Instability (NBTI) mechanism with the signal probability of the excitation waveform of the standard cell. Since aging caused by NBTI is related to the signal probability of the excitation waveform, different operating modes and signal activity modes will lead to different aging rates. This embodiment, by introducing the concept of the signal probability of the excitation waveform, can more accurately characterize the aging degree of the standard cell under different excitation waveform signal probabilities, ensuring an accurate assessment of the chip's aging degree.

[0087] The second sub-aging cell library is used to characterize the delay aging rate of standard cells under the Hot Carrier Injection (HCI) mechanism; wherein, the Hot Carrier Injection (HCI) mechanism is related to the signal switching rate of the excitation waveform of the standard cell. The signal switching rate is the number of signal flips per cycle, or per unit time.

[0088] Hot carrier injection (HCI) is a critical reliability issue in integrated circuits, particularly in NMOSFETs (N-type metal-oxide-semiconductor field-effect transistors). Electron transport from the source to the drain in an NMOSFET is affected by varying electric fields. Under high source-drain bias, the lateral electric field gradually increases from the source to the drain, peaking near the drain. Due to this high electric field, channel carriers are accelerated, hence the term "hot carriers." These hot carriers collide with crystal atoms near the drain, generating electron-hole pairs through collisional ionization. Electrons from these collisional ionizations may have sufficient energy to inject into the gate oxide region and be trapped by existing oxide traps, creating new oxide interface traps. This can lead to degradation of transistor parameters (such as threshold voltage and saturation current) and even circuit failure, posing a serious challenge to the long-term reliability of integrated circuits.

[0089] This embodiment combines the hot carrier injection (HCI) mechanism with the signal switching rate of the excitation waveform of the standard cell. Since HCI-induced aging is related to the signal switching rate of the excitation waveform, different operating modes and signal activity modes will lead to different aging rates. This embodiment, by introducing the concept of the signal switching rate of the excitation waveform, can more accurately characterize the aging degree of the standard cell under different excitation waveform signal switching rates, ensuring an accurate assessment of the chip aging degree.

[0090] It should be noted that the aforementioned aging cell library, including a first sub-aging cell library for characterizing the delayed aging rate of standard cells under the negative bias temperature instability (NBTI) mechanism and a second sub-aging cell library for characterizing the delayed aging rate of standard cells under the hot carrier injection (HCI) mechanism, is merely an optional example. In other embodiments, the aging cell library may further include a sub-aging cell library for characterizing the delayed aging rate of standard cells under other aging mechanisms (e.g., the positive bias temperature instability (PBTI) mechanism), and this application does not impose limitations on this.

[0091] In the optional implementation, refer to Figure 3 An exemplary schematic diagram of the optional process of step S200 is shown, such as... Figure 3 As shown, determining the delay aging rate of the standard cell based on the aging cell library may include:

[0092] Step S201: Based on the first sub-aging unit library, determine the first delayed aging rate of the standard unit.

[0093] The first sub-aging cell library is used to characterize the delay aging rate of standard cells under the Negative Bias Temperature Instability (NBTI) mechanism; wherein, the NBTI mechanism is related to the signal probability of the excitation waveform of the standard cell. In an optional implementation, the signal probability is the percentage of low-level time in the excitation waveform relative to the total signal duration.

[0094] In a specific implementation, the first sub-aging unit library can be a three-dimensional lookup table. The three dimensions of this three-dimensional lookup table can be, for example, input transition time, output capacitance load, and signal probability. The step of determining the first delay aging rate of the standard unit based on the first sub-aging unit library specifically involves: determining the input transition time and output capacitance load of the standard unit (for example, determining the input transition time and output capacitance load of the standard unit by analyzing the workload of the standard unit); determining the signal probability of the excitation waveform of the standard unit; searching the first sub-aging unit library to determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit, and using this delay aging rate as the first delay aging rate.

[0095] The input transition time refers to the time required for the input signal to change from one stable state to another. In digital circuits, this can be understood as the time required for the input signal to change from a low level to a high level, or from a high level to a low level. The output capacitive load refers to the capacitive load connected to the output pin of the standard unit.

[0096] For details, please refer to Figure 4An exemplary schematic diagram of the first sub-aging cell library is shown. This first sub-aging cell library can be a three-dimensional lookup table. The three dimensions of this lookup table can be, for example, input transition time, output capacitive load, and signal probability α. Figure 4 As can be seen, the first delay aging rate is related to the input transition time, the output capacitance load, and the signal probability. For example, under the same input transition time and output capacitance load, different signal probabilities α correspond to different delay aging rates (e.g., α1 corresponds to the delay aging rate aging_derate). nbti1 α2 corresponds to the delayed aging rate aging_derate nbti2 , ..., α n Corresponding aging rate (aging_derate) nbtin Therefore, by searching the first sub-aging cell library, the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard cell can be determined, and this delay aging rate can be used as the first delay aging rate.

[0097] It should be noted that the aforementioned first sub-aging cell library is a three-dimensional lookup table, which is only one optional example. In other embodiments, the first sub-aging cell library can also take various different forms, such as a parameterized model. The first sub-aging cell library can contain the parameters of these models instead of directly storing a large number of data points. For example, machine learning models (such as neural networks, decision trees, etc.) can be used to predict aging data to obtain a parameterized model: the first delay aging rate aging_derate_1 = aged_delay_1 / fresh_delay_1 = f_1 (input transition time, output capacitive load, signal probability), so aging_derate_1 can be directly calculated. By inputting specific parameters (i.e., input transition time, output capacitive load, and signal probability), the model can calculate the corresponding first delay aging rate. Here, aged_delay_1 refers to the delay after aging of the standard cell under the Negative Bias Temperature Instability (NBTI) mechanism, and fresh_delay_1 refers to the delay before aging of the standard cell under the Negative Bias Temperature Instability (NBTI) mechanism.

[0098] It should be noted that the above-described method for characterizing the aging of the standard unit due to NBTI, i.e., the first delay aging rate, is only one optional example. In other optional implementations, the characterization form of the aging of the standard unit due to NBTI may include, for example, aging_derate_1 = aged_delay_1 - fresh_delay_1, or aging_derate_1 = aged_delay_1 / fresh_delay_1 - 1, etc.

[0099] Furthermore, the step of searching the first sub-aging unit library and determining the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit may include:

[0100] If the first sub-aging unit library does not contain a delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit, then an interpolation method is used to determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit. The interpolation may include, but is not limited to, linear interpolation, polynomial interpolation, Lagrange interpolation, etc.

[0101] Continue to refer to Figure 3 Step S202 is executed to determine the second delayed aging rate of the standard unit based on the second sub-aging unit library.

[0102] The second sub-aging cell library is used to characterize the delay aging rate of standard cells under the hot carrier injection (HCI) mechanism; wherein, the HCI mechanism is related to the signal switching rate of the excitation waveform of the standard cell. The signal switching rate is the number of signal flips per cycle, or per unit time.

[0103] In a specific implementation, the second sub-aging unit library can be a three-dimensional lookup table. The three dimensions of this three-dimensional lookup table can be, for example, input transition time, output capacitance load, and signal switching rate. The step of determining the second delay aging rate of the standard unit based on the second sub-aging unit library specifically involves: determining the input transition time and output capacitance load of the standard unit (for example, determining the input transition time and output capacitance load of the standard unit by analyzing the workload of the standard unit); determining the signal switching rate of the excitation waveform of the standard unit; searching the second sub-aging unit library to determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal switching rate of the excitation waveform of the standard unit, and using this delay aging rate as the second delay aging rate.

[0104] The input transition time refers to the time required for the input signal to change from one stable state to another. In digital circuits, this can be understood as the time required for the input signal to change from a low level to a high level, or from a high level to a low level. The output capacitive load refers to the capacitive load connected to the output pin of the standard unit.

[0105] For details, please refer to Figure 5 An exemplary schematic diagram of an optional second sub-aging cell library is shown. This second sub-aging cell library can be a three-dimensional lookup table. The three dimensions of this lookup table can be, for example, input transition time, output capacitive load, and signal switching rate β. Figure 5 As can be seen, the second delay aging rate is related to the input transition time, the output capacitor load, and the signal switching rate. For example, under the same input transition time and output capacitor load, different signal switching rates β correspond to different delay aging rates (e.g., β1 corresponds to the delay aging rate aging_derate). hci1 β2 corresponds to the aging rate. hci2 , ..., β n Corresponding aging rate (aging_derate) hcin Therefore, by searching the second sub-aging unit library, the delay aging rate corresponding to the input transition time, output capacitance load, and signal switching rate of the excitation waveform of the standard unit can be determined, and this delay aging rate can be used as the second delay aging rate.

[0106] It should be noted that the aforementioned second sub-aging cell library is a three-dimensional lookup table, which is only one optional example. In other embodiments, the second sub-aging cell library can also take various different forms, such as a parameterized model. The second sub-aging cell library can contain the parameters of these models instead of directly storing a large number of data points. For example, machine learning models (such as neural networks, decision trees, etc.) can be used to predict aging data to obtain a parameterized model: the second delay aging rate aging_derate_2 = aged_delay_2 / fresh_delay_2 = f_2 (input transition time, output capacitive load, signal switching rate), so aging_derate_2 can be directly calculated. By inputting specific parameters (i.e., input transition time, output capacitive load, and signal switching rate), the model can calculate the corresponding second delay aging rate. Here, aged_delay_2 refers to the delay after the standard cell ages under the hot carrier injection HCI mechanism, and fresh_delay_2 refers to the delay before the standard cell ages under the hot carrier injection HCI mechanism.

[0107] It should be noted that the above-described method for characterizing the aging of the standard unit due to HCI, i.e., the second delay aging rate, is only one optional example. In other optional implementations, the characterization form of the aging of the standard unit due to HCI may include, for example, aging_derate_2 = aged_delay_2 - fresh_delay_2, or aging_derate_2 = aged_delay_2 / fresh_delay_2 - 1, etc.

[0108] Continue to refer to Figure 3 Then, in step S203, the first delay aging rate and the second delay aging rate are added together to obtain the delay aging rate of the standard unit.

[0109] After determining the first delay aging rate and the second delay aging rate, the first delay aging rate and the second delay aging rate can be added together to obtain the delay aging rate of the standard cell.

[0110] Continue to refer to Figure 1 Step S300 is executed, and based on the time delay aging rate, a time series analysis of the design object after aging is performed and a report is obtained.

[0111] Timing analysis refers to the process of evaluating and verifying the time delay of signal paths within a design object. Post-aging timing analysis of the design object to be time-checked aims to ensure that, after experiencing aging effects, the transmission and interaction of internal signals still meet predetermined timing requirements, thereby guaranteeing the normal function and stability of the circuit or system. Specifically, the timing analysis may include, but is not limited to, path delay calculation, timing constraint checking, and timing violation analysis.

[0112] The path delay calculation refers to calculating the delay of each signal path in the design object, such as the delay of gate circuits (like logic gates) and the transmission delay of interconnects. In the timing analysis after aging, the impact of the delay aging rate on these delay values ​​also needs to be considered; that is, the original delay values ​​are adjusted according to the aging rate.

[0113] The timing constraint check refers to comparing the calculated path delay with the timing constraints set in the design to verify whether the circuit can operate correctly within the predetermined constraints. These timing constraints may include setup and hold time requirements, which define the time conditions that a signal must meet before and after reaching the receiver.

[0114] Timing violation analysis: If timing analysis results show the presence of timing violations, these violations need to be analyzed in detail. Timing violation analysis may include determining the cause of the violation and assessing its impact on circuit function.

[0115] Organize the results of the timing analysis into a report or document. This document should detail the timing analysis process, identified issues, and the final verification results. This will provide a foundation for subsequent design verification, production testing, and troubleshooting.

[0116] As can be seen, the aging analysis method provided in this application determines the delay aging rate of the standard cell based on an aging cell library comprising multiple sub-aging cell libraries. Each sub-aging cell library characterizes the delay aging rate of the standard cell under a preset aging mechanism, with different sub-aging cell libraries corresponding to different aging mechanisms. By considering multiple different aging mechanisms separately and characterizing their respective effects on the delay aging rate of the standard cell, the delay aging rate of the standard cell can be determined accordingly. This enables accurate assessment of the aging degree of the design object, and consequently, accurate assessment of the chip aging degree.

[0117] In an optional example, refer to Figure 6 The diagram illustrates another optional flow of the aging analysis method provided in an embodiment of this application. For example... Figure 6 As shown, before the step of obtaining the design object to be time-checked, the following may also be included:

[0118] Step S001: Construct an aging unit library.

[0119] An aging cell library is constructed to provide a basis for subsequently determining the delay aging rate of the standard cell based on the aging cell library. In an optional implementation, the aging cell library may include multiple sub-aging cell libraries, which are used to characterize the delay aging rate of the standard cell under a preset aging mechanism, wherein different sub-aging cell libraries correspond to different aging mechanisms. The embodiments of this application consider multiple different aging mechanisms separately, characterize the delay aging rate of the standard cell caused by each mechanism, and determine the delay aging rate of the standard cell accordingly, thereby enabling an accurate assessment of the aging degree of the design object, and thus an accurate assessment of the aging degree of the chip.

[0120] In an optional example, the aging cell library may include a first sub-aging cell library and a second sub-aging cell library. The first sub-aging cell library characterizes the delay aging rate of a standard cell under the Negative Bias Temperature Instability (NBTI) mechanism; wherein the NBTI mechanism is related to the signal probability of the excitation waveform of the standard cell. The second sub-aging cell library characterizes the delay aging rate of a standard cell under the Hot Carrier Injection (HCI) mechanism; wherein the HCI mechanism is related to the signal switching rate of the excitation waveform of the standard cell. Accordingly, constructing the aging cell library may include: constructing the first sub-aging cell library and constructing the second sub-aging cell library.

[0121] Specifically, constructing the first sub-aging unit library involves:

[0122] A Negative Bias Temperature Instability (NBTI) aging model is established to simulate the delay aging rate of standard cells under the NBTI mechanism. Simulations are performed based on the NBTI aging model under different signal probabilities and preset conditions to obtain the first sub-aging cell library. In this embodiment, the signal probability can be the percentage of low-level time in the excitation waveform relative to the total signal duration. In other embodiments, the signal probability can also be the percentage of high-level time in the excitation waveform relative to the total signal duration.

[0123] The preset conditions may include, but are not limited to, preset process conditions, preset voltage conditions, preset temperature conditions, preset time conditions, etc.

[0124] In an optional example, refer to Figure 7 The exemplary illustration shows optional schematic diagrams of excitation waveforms with different signal probabilities (e.g., excitation waveforms with different signal probabilities). Figure 7 In α1,...,α n Under the input of (as shown), the standard unit (such as) can be aged based on the negative bias temperature instability NBTI aging model. Figure 7 Simulation was performed using the inverter shown in the figure to obtain the first sub-aging cell library. The first sub-aging cell library can be referred to the corresponding description above, and will not be repeated here.

[0125] This embodiment combines the Negative Bias Temperature Instability (NBTI) mechanism with the signal probability of the excitation waveform of the standard cell. Since aging caused by NBTI is related to the signal probability of the excitation waveform, different operating modes and signal activity modes will lead to different aging rates. This embodiment, by introducing the concept of the signal probability of the excitation waveform, can more accurately characterize the aging degree of the standard cell under different excitation waveform signal probabilities, ensuring an accurate assessment of the chip's aging degree.

[0126] The construction of the second sub-aging unit library specifically involves:

[0127] A hot carrier injection HCI aging model is established to simulate the delay aging rate of standard cells under the hot carrier injection HCI mechanism. Simulations are performed based on the hot carrier injection HCI aging model under different signal switching rates and preset conditions to obtain the second sub-aging cell library. The signal switching rate is the number of signal flips per cycle, or per unit time.

[0128] The preset conditions may include, but are not limited to, preset process conditions, preset voltage conditions, preset temperature conditions, preset time conditions, etc.

[0129] In an optional example, refer to Figure 8 The exemplary diagram shows optional excitation waveforms with different signal switching rates (e.g., excitation waveforms with different signal switching rates). Figure 8 β1, ..., β n Under the input of (as shown), the standard cell (such as) can be aged based on the hot carrier injection HCI aging model. Figure 8 Simulation was performed using the inverter shown in the figure to obtain the second sub-aging cell library. The second sub-aging cell library can be referred to the corresponding description above, and will not be repeated here.

[0130] This embodiment combines the hot carrier injection (HCI) mechanism with the signal switching rate of the excitation waveform of the standard cell. Since HCI-induced aging is related to the signal switching rate of the excitation waveform, different operating modes and signal activity modes will lead to different aging rates. This embodiment, by introducing the concept of the signal switching rate of the excitation waveform, can more accurately characterize the aging degree of the standard cell under different excitation waveform signal switching rates, ensuring an accurate assessment of the chip aging degree.

[0131] In an optional example, refer to Figure 9 The diagram illustrates another optional flow of the aging analysis method provided in this application embodiment. For example... Figure 9As shown, after the step of obtaining the standard cell to be time-tested and before the step of determining the delay aging rate of the standard cell to be time-tested based on the aging cell library, the following may also be included:

[0132] Step S101: Determine whether the design object needs to undergo aging timing checks.

[0133] If the determination result is yes, then the step of determining the delay aging rate of the standard cell based on the aging cell library is executed (i.e., step S200). If the determination result is no, then the step of performing timing analysis on the design object and obtaining a report is executed (i.e., step S400).

[0134] The determination of whether the design object needs to undergo aging sequence checks can be set by the operator according to the actual situation. For example, if the product has specific reliability requirements (such as service life), then the step of determining the delay aging rate of the standard unit based on the aging unit library is executed.

[0135] If the judgment result is yes, the delay aging rate of the standard unit can be determined based on the aging unit library, and then the timing analysis of the design object after aging can be performed based on the delay aging rate and a report can be obtained.

[0136] It should be noted that the above-described determination of whether the design object needs to undergo aging time-series checks is only an optional example. In other embodiments, other judgment conditions can also be set to determine whether the design object needs to undergo aging time-series checks. In practice, the judgment conditions can be flexibly set and adjusted according to the requirements of specific projects and actual conditions, and this application embodiment does not impose any limitations on this.

[0137] The aging analysis apparatus provided in the embodiments of this application will be described below. The aging analysis apparatus described below can be considered as the software or hardware functional modules required to implement the aging analysis method provided in the embodiments of this application. The content of the aging analysis apparatus described below can be referred to in correspondence with the content of the method described above.

[0138] In the optional implementation, Figure 10 An exemplary schematic diagram of an optional structure of the aging analysis apparatus provided in an embodiment of this application is shown. The aging analysis apparatus is used to implement the aging analysis method provided in the embodiment of this application, such as... Figure 10 As shown, the aging analysis device may include:

[0139] Acquisition module 1 is used to acquire the design object to be checked for timing, wherein the design object is composed of multiple standard units;

[0140] Aging analysis module 2 is used to determine the delay aging rate of the standard unit based on the aging unit library. The delay aging rate is used to characterize the proportion of the increase in signal transmission delay time caused by aging of the standard unit. The aging unit library includes multiple sub-aging unit libraries. The sub-aging unit libraries are used to characterize the delay aging rate of the standard unit under a preset aging mechanism. Different sub-aging unit libraries correspond to different aging mechanisms.

[0141] The timing analysis module 3 is used to perform timing analysis on the design object after aging based on the delay aging rate and obtain a report.

[0142] Optionally, the aging unit library includes a first sub-aging unit library and a second sub-aging unit library;

[0143] The first sub-aging cell library is used to characterize the delay aging rate of standard cells under the Negative Bias Temperature Instability (NBTI) mechanism; wherein, the Negative Bias Temperature Instability (NBTI) mechanism is related to the signal probability of the excitation waveform of the standard cell;

[0144] The second sub-aging cell library is used to characterize the delay aging rate of the standard cell under the hot carrier injection (HCI) mechanism; wherein the hot carrier injection (HCI) mechanism is related to the signal switching rate of the excitation waveform of the standard cell.

[0145] Optionally, the aging analysis module 2 is used to determine the time-delay aging rate of the standard unit based on the aging unit library, including:

[0146] Based on the first sub-aging unit library, the first delayed aging rate of the standard unit is determined;

[0147] Based on the second sub-aging unit library, the second delayed aging rate of the standard unit is determined;

[0148] The first delay aging rate is added to the second delay aging rate to obtain the delay aging rate of the standard cell.

[0149] Optionally, the first sub-aging unit library is a three-dimensional lookup table, where the three dimensions are input transition time, output capacitive load, and signal probability, respectively. The determination of the first delay aging rate of the standard unit based on the first sub-aging unit library specifically involves:

[0150] Determine the input transition time and output capacitive load of the standard unit;

[0151] Determine the signal probability of the excitation waveform of the standard unit;

[0152] The first sub-aging unit library is searched to determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit, and this delay aging rate is used as the first delay aging rate.

[0153] Optionally, the step of searching the first sub-aging unit library to determine the delay aging rate corresponding to the input transition time, output capacitive load, and signal probability of the excitation waveform of the standard unit includes:

[0154] If the first sub-aging unit library does not contain a delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit, then the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit is determined by interpolation.

[0155] Optionally, the second sub-aging unit library is a three-dimensional lookup table, where the three dimensions are input transition time, output capacitance load, and signal switching rate. The determination of the second delay aging rate of the standard unit based on the second sub-aging unit library specifically involves:

[0156] Determine the input transition time and output capacitive load of the standard unit;

[0157] Determine the signal switching rate of the excitation waveform of the standard unit;

[0158] Locate the second sub-aging unit library, determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal switching rate of the excitation waveform of the standard unit, and use this delay aging rate as the second delay aging rate.

[0159] Optionally, the step of searching the second sub-aging unit library to determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal switching rate of the excitation waveform of the standard unit includes:

[0160] If the second sub-aging unit library does not contain a delay aging rate corresponding to the input transition time, output capacitor load, and signal switching rate of the excitation waveform of the standard unit, then the delay aging rate corresponding to the input transition time, output capacitor load, and signal switching rate of the excitation waveform of the standard unit is determined by interpolation.

[0161] Optionally, the aging analysis device may also include:

[0162] Module 11 is used to build the aging unit library.

[0163] Optionally, the construction module 11 is used to construct an aging unit library, including: constructing a first sub-aging unit library;

[0164] Specifically, constructing the first sub-aging unit library involves:

[0165] A negative bias temperature instability (NBTI) aging model is established. The NBTI aging model is used to simulate the delay aging rate of standard cells under the negative bias temperature instability (NBTI) mechanism.

[0166] Under different signal probabilities and preset conditions, simulations were performed based on the negative bias temperature instability (NBTI) aging model to obtain the first sub-aging unit library.

[0167] The signal probability is the percentage of low-level time in the excitation waveform relative to the total signal duration.

[0168] Optionally, the construction module 11, used to construct the aging unit library, further includes: constructing a second sub-aging unit library;

[0169] Specifically, the construction of the second sub-aging unit library includes:

[0170] A hot carrier injection HCI aging model is established, which is used to simulate the delay aging rate of standard cells under the hot carrier injection HCI mechanism.

[0171] Under different signal switching rates and preset conditions, simulations were performed based on the hot carrier injection HCI aging model to obtain the second sub-aging unit library.

[0172] The signal switching rate is the number of times the signal flips per cycle, or per unit time.

[0173] Optional, also includes:

[0174] The judgment module 21 is used to determine whether the design object needs to undergo aging timing checks;

[0175] If the judgment result of the judgment module 21 is yes, then the aging analysis module 2 determines the delay aging rate of the standard unit based on the aging unit library.

[0176] As can be seen, the aging analysis method provided in this application determines the delay aging rate of the standard cell based on an aging cell library comprising multiple sub-aging cell libraries. Each sub-aging cell library characterizes the delay aging rate of the standard cell under a preset aging mechanism, with different sub-aging cell libraries corresponding to different aging mechanisms. By considering multiple different aging mechanisms separately and characterizing their respective effects on the delay aging rate of the standard cell, the delay aging rate of the standard cell can be determined accordingly. This enables accurate assessment of the aging degree of the design object, and consequently, accurate assessment of the chip aging degree.

[0177] This application also provides an electronic device that may include at least one memory and at least one processor. The memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the aging analysis method as described above.

[0178] As an optional implementation, refer to Figure 11 , Figure 11 This is an optional block diagram of the electronic device provided in the embodiments of this application. For example... Figure 11 As shown, the electronic device may include: at least one processor 10, at least one communication interface 20, at least one memory 30 and at least one communication bus 40.

[0179] In this embodiment, the number of processor 10, communication interface 20, memory 30 and communication bus 40 is at least one, and processor 10, communication interface 20 and memory 30 communicate with each other through communication bus 40.

[0180] Optionally, the processor 10 may be a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural-network Processing Unit), FPGA (Field Programmable Gate Array), TPU (Tensor Processing Unit), AI chip, ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of this application.

[0181] Optionally, the communication interface 20 can be an interface for a communication module used for network communication.

[0182] The memory 30 may include high-speed RAM, and may also include non-volatile memory, such as at least one disk drive. The memory 30 stores one or more computer-executable instructions, which the processor 10 invokes to perform the aging analysis method as described above.

[0183] This application also provides a storage medium that stores one or more computer-executable instructions, which, when executed, implement the aging analysis method described above.

[0184] This application also provides a computer program product that may include one or more computer-executable instructions, which, when executed, implement the aging analysis method described above.

[0185] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0186] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. An aging analysis method, characterized in that, include: Obtain the design object to be time-series checked, the design object consisting of multiple standard units; Based on the aging unit library, the delay aging rate of the standard unit is determined. The delay aging rate is used to characterize the proportion of the increase in signal transmission delay time caused by aging of the standard unit. The aging unit library includes multiple sub-aging unit libraries, which are used to characterize the delay aging rate of the standard unit under a preset aging mechanism. Different sub-aging unit libraries correspond to different aging mechanisms. Based on the aforementioned delay aging rate, a time-series analysis of the design object after aging is performed and a report is obtained. The aging cell library includes a first sub-aging cell library and a second sub-aging cell library. The first sub-aging cell library is used to characterize the delay aging rate of the standard cell under the Negative Bias Temperature Instability (NBTI) mechanism, wherein the NBTI mechanism is related to the signal probability of the excitation waveform of the standard cell. The second sub-aging cell library is used to characterize the delay aging rate of the standard cell under the Hot Carrier Injection (HCI) mechanism, wherein the HCI mechanism is related to the signal switching rate of the excitation waveform of the standard cell. The determination of the delay aging rate of the standard cell based on the aging cell library includes: Based on the first sub-aging unit library, the first delayed aging rate of the standard unit is determined; Based on the second sub-aging unit library, the second delayed aging rate of the standard unit is determined; The first delay aging rate is added to the second delay aging rate to obtain the delay aging rate of the standard cell.

2. The aging analysis method according to claim 1, characterized in that, Before the step of obtaining the design object to be time-series checked, the method further includes: building an aging cell library.

3. The aging analysis method according to claim 2, characterized in that, The construction of the aging unit library includes: constructing a first sub-aging unit library; Specifically, constructing the first sub-aging unit library involves: A negative bias temperature instability (NBTI) aging model is established. The NBTI aging model is used to simulate the delay aging rate of standard cells under the negative bias temperature instability (NBTI) mechanism. Under different signal probabilities and preset conditions, simulations were performed based on the negative bias temperature instability (NBTI) aging model to obtain the first sub-aging unit library. The signal probability is the percentage of low-level time in the excitation waveform relative to the total signal duration.

4. The aging analysis method according to claim 2, characterized in that, The construction of the aging unit library also includes: constructing a second sub-aging unit library; Specifically, the construction of the second sub-aging unit library includes: A hot carrier injection HCI aging model is established, which is used to simulate the delay aging rate of standard cells under the hot carrier injection HCI mechanism. Under different signal switching rates and preset conditions, simulations were performed based on the hot carrier injection HCI aging model to obtain the second sub-aging unit library. The signal switching rate is the number of times the signal flips per cycle, or per unit time.

5. The aging analysis method according to claim 1, characterized in that, The first sub-aging cell library is a three-dimensional lookup table. The three dimensions of this three-dimensional lookup table are input transition time, output capacitive load, and signal probability, respectively. The determination of the first delay aging rate of the standard cell based on the first sub-aging cell library is specifically as follows: Determine the input transition time and output capacitive load of the standard unit; Determine the signal probability of the excitation waveform of the standard unit; The first sub-aging unit library is searched to determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit, and this delay aging rate is used as the first delay aging rate.

6. The aging analysis method according to claim 5, characterized in that, The step of searching the first sub-aging unit library and determining the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit includes: If the first sub-aging unit library does not contain a delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit, then the delay aging rate corresponding to the input transition time, output capacitance load, and signal probability of the excitation waveform of the standard unit is determined by interpolation.

7. The aging analysis method according to claim 1, characterized in that, The second sub-aging unit library is a three-dimensional lookup table. The three dimensions of this three-dimensional lookup table are input transition time, output capacitance load, and signal switching rate, respectively. The determination of the second delay aging rate of the standard unit based on the second sub-aging unit library is specifically as follows: Determine the input transition time and output capacitive load of the standard unit; Determine the signal switching rate of the excitation waveform of the standard unit; Locate the second sub-aging unit library, determine the delay aging rate corresponding to the input transition time, output capacitance load, and signal switching rate of the excitation waveform of the standard unit, and use this delay aging rate as the second delay aging rate.

8. The aging analysis method according to claim 7, characterized in that, The step of searching the second sub-aging unit library and determining the delay aging rate corresponding to the input transition time, output capacitance load, and signal switching rate of the excitation waveform of the standard unit includes: If the second sub-aging unit library does not contain a delay aging rate corresponding to the input transition time, output capacitor load, and signal switching rate of the excitation waveform of the standard unit, then the delay aging rate corresponding to the input transition time, output capacitor load, and signal switching rate of the excitation waveform of the standard unit is determined by interpolation.

9. The aging analysis method according to claim 1, characterized in that, After the step of obtaining the design object to be time-checked, and before the step of determining the delay aging rate of the standard cell based on the aging cell library, the method further includes: Determine whether the design object needs to undergo aging timing checks; If the determination result is yes, then the step of determining the delay aging rate of the standard cell based on the aging cell library is executed.

10. An aging analysis device, characterized in that, include: The acquisition module is used to acquire the design object to be checked for timing, the design object being composed of multiple standard units; An aging analysis module is used to determine the delay aging rate of the standard unit based on an aging unit library. The delay aging rate is used to characterize the proportion of the increase in signal transmission delay time caused by aging of the standard unit. The aging unit library includes multiple sub-aging unit libraries, which are used to characterize the delay aging rate of the standard unit under a preset aging mechanism. Different sub-aging unit libraries correspond to different aging mechanisms. The timing analysis module is used to perform timing analysis on the design object after aging based on the delay aging rate and obtain a report; The aging cell library includes a first sub-aging cell library and a second sub-aging cell library. The first sub-aging cell library is used to characterize the delay aging rate of the standard cell under the Negative Bias Temperature Instability (NBTI) mechanism, wherein the NBTI mechanism is related to the signal probability of the excitation waveform of the standard cell. The second sub-aging cell library is used to characterize the delay aging rate of the standard cell under the Hot Carrier Injection (HCI) mechanism, wherein the HCI mechanism is related to the signal switching rate of the excitation waveform of the standard cell. The aging analysis module is used to determine the time-delay aging rate of the standard cell based on the aging cell library, including: Based on the first sub-aging unit library, the first delayed aging rate of the standard unit is determined; Based on the second sub-aging unit library, the second delayed aging rate of the standard unit is determined; The first delay aging rate is added to the second delay aging rate to obtain the delay aging rate of the standard cell.

11. The aging analysis apparatus according to claim 10, characterized in that, Also includes: The building module is used to build the aging unit library.

12. The aging analysis apparatus according to claim 10, characterized in that, Also includes: The judgment module is used to determine whether the design object needs to undergo aging timing checks; If the judgment result of the judgment module is yes, then the aging analysis module determines the delay aging rate of the standard unit based on the aging unit library.

13. An electronic device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer-executable instructions, and the processor invoking the one or more computer-executable instructions to perform the aging analysis method as described in any one of claims 1 to 9.

14. A storage medium, characterized in that, The storage medium stores one or more computer-executable instructions, which, when executed, implement the aging analysis method as described in any one of claims 1 to 9.

15. A computer program product, characterized in that, It includes one or more computer-executable instructions, which, when executed, implement the aging analysis method as described in any one of claims 1 to 9.

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