Data recording method, data recording device, system-on-chip and intelligent equipment

Abstract

The invention is suitable for the technical field of data processing, and provides a data recording method, a data recording device, a system-on-chip and intelligent equipment. The data recording method comprises the following steps: determining an updating period of at least one piece of target acquisition data; periodically reading the target acquisition data in the corresponding partitions through a shared memory by taking the updating cycle of each target acquisition data as a cycle; storing the read target acquisition data in a second memory of the first processor; the storage space of the second memory is larger than that of the first memory. According to the invention, long-time recording of a large amount of collected data can be efficiently realized.

Description

Technical Field

[0001] The present application belongs to the field of data processing technology, and in particular relates to a data recording method, a data recording device, a system-level chip and an intelligent device. Background Art

[0002] In order to investigate the cause of an ECU failure, it is necessary to restore the fault scene, including environmental data around the vehicle, the value of the diagnosed content, ECU operating status, etc. These data can greatly improve the efficiency of problem analysis, and the more data that can be collected and the longer the time, the higher the efficiency of locating the problem.

[0003] However, the storage space of the Microcontroller Unit (MCU) is limited and cannot record a large amount of data or cannot record data for a long time. In addition, under some abnormal working conditions, the MCU is prone to lose its data recording ability, and some MCU data is difficult to record by the MCU itself. Therefore, how to efficiently achieve long-term recording of a large amount of collected data is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present application provide a data recording method, a data recording device, a system-level chip and an intelligent device, which can efficiently realize long-term recording of a large amount of collected data.

[0005] In a first aspect, an embodiment of the present application provides a data recording method, the data recording method comprising:

[0006] Determine an update period of at least one target acquisition data; at least one of the target acquisition data is stored in one or more partitions of a first memory of a system-level chip, and the acquisition data in the same partition have the same update period, and the first memory is a memory in a first processor of the system-level chip;

[0007] Taking the update period of each target collection data as a period, periodically reading the target collection data in the corresponding partition through the shared memory;

[0008] The read target acquisition data are saved in a second memory; the storage space of the second memory is larger than the storage space of the first memory, and the second memory is a memory in a second processor of the system-level chip.

[0009] In an embodiment of the present application, by determining an update period of at least one target acquisition data, the target acquisition data in the corresponding partition can be periodically read through the shared memory based on the update period of each target acquisition data, thereby achieving lossless acquisition of each target acquisition data and preventing data loss, thereby improving the reading efficiency of the target acquisition data. On this basis, the read target acquisition data is saved to a second memory with a larger storage space, which can efficiently achieve long-term recording of a large amount of acquisition data.

[0010] In a second aspect, an embodiment of the present application provides a data recording method, the data recording method comprising:

[0011] Obtain one or more collected data;

[0012] Allocate each of the collected data to one or more partitions of a first memory according to an update period of each of the collected data; the update period of the collected data in the same partition is the same, and the first memory is a memory in a first processor of a system-level chip;

[0013] Among them, the update cycle of the collected data is used to trigger the second processor of the system-level chip to periodically read the collected data in the corresponding partition through the shared memory, and save the read collected data to the second memory. The storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor.

[0014] In an embodiment of the present application, by acquiring one or more collected data, each collected data can be allocated to one or more partitions of the first memory according to the update period of each collected data. The update period of the collected data in the same partition is the same. On this basis, the second processor of the system-level chip can be triggered to periodically read the collected data in the corresponding partition through the shared memory, and save the read collected data to the second memory. The storage space of the second memory is larger than the storage space of the first memory, thereby efficiently realizing long-term recording of a large amount of collected data.

[0015] In a third aspect, an embodiment of the present application provides a data recording device, which may be a device applied to a second processor of a system-level chip or the data recording device may serve as a second processor, and the data recording device includes:

[0016] A cycle determination module, used to determine an update cycle of at least one target acquisition data; at least one of the target acquisition data is stored in one or more partitions of a first memory of a system-level chip, and the acquisition data in the same partition have the same update cycle, and the first memory is a memory in a first processor of the system-level chip;

[0017] A data reading module, used for periodically reading the target collection data in the corresponding partition through the shared memory at the update period of each target collection data;

[0018] A storage module is used to save the read target acquisition data into a second memory; the storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor of the system-level chip.

[0019] In a fourth aspect, an embodiment of the present application provides a data recording device, which may be a device applied to a first processor of a system-level chip or the data recording device may serve as the first processor, and the data recording device includes:

[0020] A data acquisition module, used to acquire one or more collected data;

[0021] A data allocation module, used for allocating each of the collected data to one or more partitions of a first memory according to an update period of each of the collected data; the update period of the collected data in the same partition is the same, and the first memory is a memory in a first processor of a system-level chip;

[0022] Among them, the update cycle of the collected data is used to trigger the second processor of the system-level chip to periodically read the collected data in the corresponding partition through the shared memory, and save the read collected data to the second memory. The storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor.

[0023] In a fifth aspect, an embodiment of the present application provides a system-level chip, which includes a first processor and a second processor, wherein the first processor is used to execute the data recording method described in the second aspect, and the second processor is used to execute the data recording method described in the first aspect.

[0024] In a sixth aspect, an embodiment of the present application provides a smart device, which includes the system-level chip as described in the fifth aspect above, or the smart device includes a first processor and a second processor, the first processor is used to execute the data recording method as described in the second aspect above, and the second processor is used to execute the data recording method as described in the first aspect above.

[0025] In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a computer, the data recording method as described in the first aspect or the second aspect is implemented.

[0026] In an eighth aspect, an embodiment of the present application provides a computer program product, including a computer program, and when the computer program is run, the data recording method described in the first aspect or the second aspect above is executed.

[0027] It can be understood that the beneficial effects of the third to eighth aspects mentioned above can be found in the relevant descriptions of the first and second aspects mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is an example diagram of a data recording scenario;

[0030] Figure 2 is a flow chart of a data recording method provided in an embodiment of the present application;

[0031] Figure 3 This is an example diagram of data that needs to be written to the file system provided in an embodiment of the present application;

[0032] Figure 4 is a flow chart of another data recording method provided in an embodiment of the present application;

[0033] Figure 5 is an example diagram of collected data and partitions provided in an embodiment of the present application;

[0034] Figure 6 is an example diagram of the architecture of a data recording system provided in an embodiment of the present application;

[0035] Figure 7 is a structural schematic diagram of a data recording device provided in an embodiment of the present application;

[0036] Figure 8 is a schematic structural diagram of another data recording device provided in an embodiment of the present application;

[0037] Fig. 9 It is a schematic diagram of the structure of the system-level chip provided in the embodiment of the present application. DETAILED DESCRIPTION

[0038] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0039] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0040] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0041] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0042] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0043] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0044] By way of example and not limitation, Figure 1The following is an example of a data recording scenario. The MCU monitors that the camera power supply is less than 9V (normal 9~16V) and reports an undervoltage fault. It is necessary to record multiple system voltages, power supply unit status, and camera power supply voltage before and after the fault to check whether the camera power supply voltage is undervoltage. If only the data of sampling point 3 is recorded, the failure location cannot be determined, because abnormalities in the enable pin of power supply unit 1 or the enable pin of power supply unit 2 will cause abnormal voltage at sampling point 3.

[0045] In the following scenarios, it is difficult for MCU to meet the following requirements:

[0046] 1. A large amount of data needs to be recorded or data needs to be recorded for a long time: For a complex central controller or domain controller, the data to be recorded may reach hundreds or thousands, and the length of time to be recorded may reach several seconds or minutes. The MCU in the system-on-chip (SoC) of the central controller or domain controller is difficult to record a large amount of data or record data for a long time.

[0047] 2. Under some abnormal working conditions, the MCU loses the ability to record data: When an abnormal interrupt or serious scheduling timeout occurs in a core of a multi-core MCU, the MCU itself runs abnormally and loses its normal data recording ability.

[0048] 3. Some MCU data is difficult to collect and save through the MCU itself: Direct access of the MCU to sensitive data such as the stack through business programs may cause system abnormalities, and indirect access will create additional complexity and data consistency risks.

[0049] In order to solve the above technical problems, an embodiment of the present application provides a data recording method. The second processor of the system-level chip determines the update period of at least one target acquisition data, and can periodically read the target acquisition data in the corresponding partition through the shared memory based on the update period of each target acquisition data, thereby achieving lossless acquisition of each target acquisition data and preventing data loss, thereby improving the reading efficiency of the target acquisition data. On this basis, the read target acquisition data are saved to a second memory with a larger storage space, which can efficiently realize long-term recording of a large amount of acquisition data.

[0050] See also Figure 2 , Figure 2A flow chart of a data recording method provided by an embodiment of the present application is shown. As an example but not a limitation, the method is applied to an intelligent device (for example, an intelligent device may include a driving device, an intelligent car, a robot, etc.), or to a system-level chip in an intelligent device. Specifically, it can be applied to a second processor in a system-level chip. The following describes the method using the second processor in the system-level chip as an example. Specifically, the method includes the following steps:

[0051] Step 201: A second processor in the system-on-chip determines an update period of at least one target acquisition data.

[0052] Among them, each target collected data is the collected data that needs to be recorded (that is, the data that the second processor needs to collect or read from the first processor), and each target collected data is stored in one or more partitions of the first memory of the system-level chip, and the update cycle of the collected data in the same partition is the same. The first memory is the memory in the first processor of the system-level chip. The update cycle of the collected data may refer to the update cycle of the collected data in the second processor. The above-mentioned collected data may refer to the data stored in the partition of the first memory, such as the diagnostic data of the vehicle.

[0053] The first memory may be any memory in the first processor, and the present application does not limit the type of the first memory. As an example but not a limitation, the first memory may be a random access memory (RAM) or a static random access memory (SRAM).

[0054] It should be understood that, on the basis that the storage space of the second memory of the second processor is larger than the storage space of the first memory, the present application does not limit the type of the second memory, the type of the second processor, and the type of the second processor. As an example and not a limitation, the second memory may be a double data rate synchronous dynamic random access memory (DDR SDRAM), the second processor may be an advanced reduced instruction set computer (ARM) in a system-on-chip, and the first processor may be an MCU in a system-on-chip.

[0055] A data recording module is deployed on the second processor, and the data recording module can be set to start and run continuously at power-on. Accordingly, step 201 in the embodiment of the present application can be triggered by the second processor in the system-level chip to trigger the data recording module to determine the update period of at least one target acquisition data, and step 202 in the embodiment of the present application described later can be triggered by the second processor to trigger the data recording module to periodically read the target acquisition data in the corresponding partition through the shared memory with the update period of each target acquisition data as the period, and step 203 in the embodiment of the present application described later can be triggered by the second processor to save the read target acquisition data to the second memory.

[0056] As an example but not limitation, the system-level chip is deployed on the vehicle-mounted terminal. After the vehicle-mounted terminal is turned on, the system-level chip is powered on. In this case, the data recording module on the second processor is started and continues to run.

[0057] In one embodiment, the second processor can trigger the data recording module to load a configuration file at startup, and identify the update period of each target acquisition data from the configuration file. Wherein, the above configuration file records the information of each target acquisition data and the information of the partition where each target acquisition data is located. For the information of any target acquisition data, the information of the target acquisition data includes but is not limited to the name of the acquisition data, the address of the acquisition data in the partition of the second processor, the type of acquisition data, the update period of the acquisition data in the second processor, the length of time of the data to be retained before the trigger mark is triggered, the length of time of the data to continue to be recorded after the trigger mark is triggered, the description of the acquisition data, and whether the acquisition data needs to be enabled for acquisition, etc. Whether the acquisition needs to be enabled can refer to whether the first processor is allowed to perform data acquisition from the second processor. For any partition, the information of the partition includes but is not limited to the name of the partition, the starting address of the partition, the ending address of the partition, and the update period of the partition (i.e., the update period of the target acquisition data in the partition), etc.

[0058] As an example but not limitation, the first processor is an MCU in a system-level chip, the first memory is a RAM, and the partition obtained by dividing the MCU in the RAM can be called a RAM partition. In the configuration file, the information of each RAM partition may include the following four attributes: name, that is, the name of the RAM partition; start_address, that is, the starting address of the RAM partition; end_address, that is, the ending address of the RAM partition; period, that is, the update period of the RAM partition. The information of each collected data may include the following nine attributes: variable_name, the name of the collected data; address, the address of the collected data in the RAM partition of the MCU; data_type, the type of collected data, including u8 / int8, u16 / int16, u32 / int32, u64 / int64, float; flag_name, the trigger flag variable corresponding to the collected data. If flag_name is "NA", it means that it is a trigger flag variable; period, the update period of the collected data in the MCU; pre_windows, the length of time that the data should be retained before the trigger flag variable is triggered; post_windows, the length of time that the data should continue to be recorded after the trigger flag variable is triggered; description, the description of the collected data; enabled, whether to enable collection. If it is false, the second processor is not allowed to collect the data from the first processor.

[0059] Step 202: The second processor periodically reads the target collection data in the corresponding partition through the shared memory, taking the update period of each target collection data as a period.

[0060] The second processor can read the target acquisition data in the partition of the first processor through the shared memory technology.

[0061] For any target acquisition data, the second processor uses the update period of the target acquisition data as a period, and periodically reads the target acquisition data in the corresponding partition through the shared memory, so as to ensure that the period in which it reads the target acquisition data from the first processor is the same as the update period of the target acquisition data in the first processor. On this basis, it can be ensured that the target acquisition data read by the second processor from the first processor each time is the latest updated data (i.e., the full reading of the target acquisition data is realized), thereby realizing lossless reading of the target acquisition data by the second processor and ensuring that the data is not lost, thereby improving the reading efficiency of the target acquisition data.

[0062] As an example but not a limitation, the update cycle of the target acquisition data in the first processor is 10 milliseconds. If the target acquisition data is to be fully read, the second processor needs to read the target acquisition data from the corresponding partition of the first processor through the shared memory periodically with a cycle of 10 milliseconds. If the second processor uses a cycle of 100 milliseconds, the target acquisition data in the first processor will be updated 10 times, and the second processor will read the target acquisition data from the first processor once, resulting in 9 updated target acquisition data not being read by the second processor.

[0063] In a possible implementation, the second processor may read the target acquisition data in the following two ways.

[0064] Method 1: The second processor determines the number of update cycles of each target acquisition data; based on the number of update cycles of each target acquisition data, creates a corresponding number of first threads or first processes; controls each first thread or first process to periodically read the target acquisition data in the corresponding partition through the shared memory with the update cycle of the corresponding target acquisition data as the period.

[0065] Among them, the number of update cycles of each target acquisition data mentioned above may refer to the number of different update cycles of each target acquisition data. As an example but not limitation, the number of target acquisition data is four, namely target acquisition data 1, target acquisition data 2, target acquisition data 3 and target acquisition data 4; if the update cycles of these four target acquisition data are different, then it can be determined that the number of update cycles of these four target acquisition data is four; if the update cycles of target acquisition data 1 and target acquisition data 2 are the same, but different from the update cycles of target acquisition data 3 and target acquisition data 4, and the update cycles of target acquisition data 3 and target acquisition data 4 are also different, then it can be determined that the number of update cycles of these four target acquisition devices is three.

[0066] In the above method 1, the second processor creates a corresponding number of first threads or first processes based on the number of update cycles of each target acquisition data, and can read target acquisition data with different update cycles through different threads or processes, thereby improving the reading efficiency of the target acquisition data.

[0067] In one embodiment, when a partition in the first processor is mapped to an address space of the second processor, and the access attribute of the mapped address space is a read-only attribute, the above-mentioned control of each first thread or first process periodically reading the target collection data in the corresponding partition through the shared memory with the update period of the corresponding target collection data as a period includes:

[0068] Each first thread or first process is controlled to use the update period of the corresponding target acquisition data as a period, and to periodically read each target acquisition data from the mapped address space based on the address of the target acquisition data in the corresponding partition.

[0069] The second processor may identify the address of the target acquisition data in the corresponding partition from the configuration file.

[0070] Multiple acquisition data may be allocated in a partition, and each acquisition data has a different address in the partition. Therefore, based on the address of any target acquisition data in the corresponding partition, the mapped address space corresponding to the address of the partition can be accurately found, thereby accurately reading the target acquisition data from the mapped address space.

[0071] Method 2: The second processor can determine the number of partitions where each target acquisition data is located; based on the number of partitions where each target acquisition data is located, create a corresponding number of second threads or second processes; control each second thread or second process to use the update period of the target acquisition data in the corresponding partition as a period, periodically read the acquisition data of the corresponding partition through the shared memory, and determine the target acquisition data from the acquisition data of the corresponding partition based on the address of the target acquisition data in the corresponding partition.

[0072] The number of partitions where the target acquisition data is located may refer to the number of different partitions where the target acquisition data is located. As an example but not a limitation, the number of target acquisition data is four, namely target acquisition data 1, target acquisition data 2, target acquisition data 3 and target acquisition data 4; if the four target acquisition data are located in four different partitions, then the number of partitions where the four target acquisition data are located can be determined to be four; if target acquisition data 1 and target acquisition data 2 are located in the same partition, but are located in different partitions from target acquisition data 3 and target acquisition data 4, and target acquisition data 3 and target acquisition data 4 are also located in different partitions, then the number of partitions where the four target acquisition devices are located can be determined to be three.

[0073] In the above-mentioned method 2, the second processor creates a corresponding number of second threads or second processes based on the number of partitions where each target acquisition data is located, and can read the target acquisition data located in different partitions through different threads or processes, thereby improving the reading efficiency of the target acquisition data.

[0074] In one embodiment, when a partition in a first processor is mapped to an address space of a second processor, and the access attribute of the mapped address space is a read-only attribute, the above-mentioned control of each second thread or second process periodically reading the target collection data in the corresponding partition through the shared memory area with the update period of the target collection data in the corresponding partition as a period includes:

[0075] Each second thread or second process is controlled to use the update period of the target acquisition data in the corresponding partition as a period, and periodically read the acquisition data of the corresponding partition from the mapped address space based on the address of the partition where each target acquisition data is located.

[0076] The second processor may identify the address of the partition where the target acquisition data is located from the configuration file.

[0077] Based on the address of the partition where any target acquisition data is located, the second processor can accurately find the mapped address space corresponding to the address of the partition, thereby accurately reading the acquisition data in the partition from the mapped address space, and the acquisition data in the partition includes the target acquisition data.

[0078] In the above two methods, the second processor can realize shared memory between the first processor and the second processor by mapping the partition in the first processor to the address space of the second processor, that is, the second processor can access the first processor, and the application in the second processor can directly read the data in the partition of the first processor. The second processor can avoid damaging the operation of the first processor by setting the access attribute of the mapped address space to read-only attribute.

[0079] Before the second processor maps the partition in the first processor to the address space, it needs to obtain the partition information in the first processor first, and only on this basis can the partition mapping be realized. Optionally, the partition information can be manually input into the second processor, or sent by the first processor to the second processor, or identified by the second processor from a configuration file. This application does not limit the source of the partition information.

[0080] Step 203: The second processor saves the read target acquisition data into the second memory.

[0081] The storage space of the second memory is larger than the storage space of the first memory. The second memory is a memory in the second processor.

[0082] It should be understood that although the storage space of the second memory is larger than that of the first memory, the storage space of the second memory is also limited. Therefore, in order to ensure that the latest target acquisition data is stored in the second memory, the second processor can save historical acquisition data of a certain time length in real time in the second memory. When the historical acquisition data exceeds the set time, the historical acquisition data is discarded so that the latest read target acquisition data can be saved in the second memory.

[0083] In a possible implementation, after the read target acquisition data is saved in the second memory, the method further includes:

[0084] For any target acquisition data, the state of the trigger flag variable of the target acquisition data is monitored; when it is monitored that the state of the trigger flag variable switches to the trigger state, the target acquisition data that meets the requirements and is stored in the second memory is written to the file system, and the target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within a first time period before the switching moment and a second time period after the switching moment, and the switching moment is the moment when the state of the trigger flag variable is monitored to switch to the trigger state.

[0085] Among them, the state of the trigger flag variable is used to indicate whether to write the corresponding target acquisition data in the second memory to the disk to the file. The trigger state is used to indicate that the corresponding target acquisition data in the second memory is written to the disk to the local file system of the second processor. Relative to the second memory, the file system can be called an external memory. The storage space of the external memory is larger, so saving the target acquisition data to the external memory (i.e. sending the target acquisition data to the outside) can record more acquisition data and can also record acquisition data for a longer time. There is no need to borrow some external devices when sending the target acquisition data to the outside.

[0086] In one embodiment, the configuration file may also record a trigger flag variable of the target acquisition data. The second processor may identify the trigger flag variable of the target acquisition data from the configuration file, and on this basis, monitor the state of the trigger flag variable of the target acquisition data.

[0087] It should be noted that the computing performance and data processing performance of the second processor are higher than those of the first processor (as an example but not a limitation, the first processor is an MCU, which generally runs operating systems such as AUTOSAR CP and FreeRTOS. Unlike Windows and Linux systems, which have such strong connectivity, the development and iteration of these operating systems are very slow, and the computing performance and data processing performance are relatively low. The second processor is a RAM, which generally runs operating systems such as Windows and Linux. These operating systems are relatively easy to develop, and the computing performance and data processing performance are relatively high). The second processor has a file system. On this basis, the second processor can store data on the disk to the file system without the need to specially develop a transmission protocol to send the data in the first processor. When the demand changes, the development and adaptation costs are low. When the first processor sends a large amount of data to the outside, it may affect the real-time performance and performance of the first processor. However, in this embodiment, the real-time performance and performance of the first processor are not affected by sending a large amount of data to the outside through the second processor. When the second processor sends a large amount of data to the outside, it does not depend on the operating system of the first processor, so even if the operating system of the first processor is abnormal, it does not affect the second processor from sending data to the outside.

[0088] Optionally, the first duration and the second duration can be set according to the scene requirements. For example, the first duration is 10 seconds and the second duration is 5 seconds. Figure 3 The following is an example of data that needs to be written to the file system. Figure 3 The historical 10-second data is the target collection data within the first time period before the switching moment, and the future 5-second data is the target collection data within the second time period after the switching moment.

[0089] In actual scenarios, a lot of target acquisition data stored in the second memory may be useless, so when a specific event occurs (in this case, the state of the trigger flag variable of the target acquisition data corresponding to the specific event is switched to the trigger state), the target acquisition data for a period of time before and after the specific event can be written to the disk to the file system, that is, the useful data is written to the disk to the file system, thereby realizing long-term recording of useful data of a large number of different events. When the writing to the disk is completed, the collection and writing of a specific scene data is completed.

[0090] Optionally, when the target collected data is written to the file system, the file formed when the target collected data is written to the disk can be named based on the trigger flag variable and the current time. For example, the trigger flag variable + the current time is used as the file name.

[0091] In one embodiment, the second processor may transmit the files generated by the disk to the cloud for after-sales analysts to perform data analysis.

[0092] In an embodiment of the present application, the second processor of the system-level chip determines the update period of at least one target acquisition data, and can periodically read the target acquisition data in the corresponding partition through the shared memory based on the update period of each target acquisition data, thereby achieving lossless acquisition of each target acquisition data and preventing data loss, thereby improving the reading efficiency of the target acquisition data. On this basis, the read target acquisition data is saved to a second memory with a larger storage space, which can efficiently realize long-term recording of a large amount of acquisition data.

[0093] See also Figure 4 , Figure 4 A flow chart of another data recording method provided by an embodiment of the present application is shown. As an example but not a limitation, the method is applied to an intelligent device (for example, an intelligent device may include a driving device, an intelligent car, a robot, etc.), or to a system-level chip in an intelligent device. Specifically, it can be applied to a first processor in a system-level chip. The following describes the method using the first processor in the system-level chip as an example. Specifically, the method includes the following steps:

[0094] Step 401: A first processor in a system-on-chip obtains one or more collected data.

[0095] It should be understood that the present application does not limit the type of collected data. As an example and not a limitation, the collected data may be environmental data around the vehicle, or may be ECU operating status data, etc.

[0096] Step 402: The first processor distributes each collected data to one or more partitions of the first memory according to the update period of each collected data.

[0097] Among them, the update cycle of the collected data is used to trigger the second processor of the system-level chip to periodically read the collected data in the corresponding partition through the shared memory, and save the read collected data to the second memory. The storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor.

[0098] The first processor can divide the first memory into at least two partitions, and distribute the collected data into these pre-divided partitions, where the collected data with different update cycles are distributed into different partitions, and the update cycle of the collected data in the same partition is the same. Of course, different collected data with the same update cycle can also be distributed into different partitions, which is not limited in this application.

[0099] It should be understood that the partitions are not required to be spatially continuous, but any collected data must be contained in the same partition to ensure that the collected data can be quickly read from the same partition.

[0100] like Figure 5 Shown is an example diagram of collected data and partitions provided in an embodiment of the present application. Figure 5 The first processor divides the RAM into m RAM partitions, each RAM partition is assigned multiple acquisition data, the 10 seconds in RAM partition 1 is the time length of the acquisition data saved in RAM partition 1, that is, RAM partition 1 saves 10 seconds of acquisition data, the 20 seconds in RAM partition 2 and RAM partition n are the time length of the acquisition data saved in RAM partition 2 and RAM partition n, that is, RAM partition 2 and RAM partition n save 20 seconds of acquisition data, 0x1000 0000 is the starting address of RAM partition 1, 0x1100 0000 is the starting address of RAM partition 2, 0x1900 0000 is the starting address of RAM partition n, and 0x2200 0000 is the starting address of RAM partition m.

[0101] In a possible implementation, any collected data has a trigger flag variable;

[0102] When the first processor detects a disk drop event for target collected data among the one or more collected data, the first processor switches the state of the trigger flag variable corresponding to the target collected data to a trigger state;

[0103] Among them, the trigger state is used to trigger the second processor to write the target acquisition data that meets the requirements and is stored in the second memory to the file system. The target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within a first time period before the switching moment and a second time period after the switching moment. The switching moment is the moment when the state of the trigger flag variable is switched to the trigger state.

[0104] On the basis that the first processor divides the partitions and distributes the collected data to different partitions, the information of the collected data to be recorded (i.e., the target collected data) and the information of the corresponding partitions can be saved in the configuration file, and the trigger flag variable of the target collected data is recorded in the configuration file at the same time, and each target collected data corresponds to a trigger flag variable. On this basis, the second processor can realize the recording of the target collected data based on the configuration file. Optionally, the above configuration file can be set manually.

[0105] The first processor notifies the second processor to write data to the disk by updating the state of the trigger flag variable, thereby achieving accurate data capture.

[0106] Optionally, the above-mentioned disk drop event includes but is not limited to specific events such as fault events or entering a scene where data needs to be recorded. As an example but not a limitation, for a scene where you want to record the performance of the chassis system when the user brakes suddenly, you can create a trigger flag variable for this scene, and use the trigger flag variable to monitor the sudden braking of the car. When it is monitored that the user brakes suddenly, the state of the first processor triggers the flag variable to switch to a trigger state. At this time, the second processor records the chassis system's oil cylinder pressure, wheel speed, motor speed and other data.

[0107] like Figure 6 The figure shows an example diagram of the architecture of the data recording system provided in the embodiment of the present application. Figure 6 The first processor in the system-level chip divides the RAM into multiple partitions and allocates the collected data of different update cycles to different partitions. On this basis, the second processor in the system-level chip can trigger the data recording module to periodically read the data in each partition through shared memory technology, and when a specific event occurs, the collected data before and after the specific event is written to the local file system of the second processor, and the files formed by the written disk are transmitted to the cloud for after-sales analysts to perform data analysis.

[0108] In an embodiment of the present application, the first processor in the system-level chip can acquire one or more collected data and store each collected data in one or more partitions of the first memory according to the update period of each collected data. The update period of the collected data in the same partition is the same. On this basis, the second processor of the system-level chip can be triggered to periodically read the collected data in the corresponding partition through the shared memory, and save the read collected data to the second memory. The storage space of the second memory is larger than the storage space of the first memory, thereby efficiently realizing the long-term recording of a large amount of collected data.

[0109] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0110] Corresponding to the data recording method described in the above embodiment, Figure 7 A structural schematic diagram of a data recording device provided in an embodiment of the present application is shown. The data recording device can be a device applied to a second processor of a system-level chip or the data recording device can serve as a second processor. For ease of explanation, only the part related to the embodiment of the present application is shown.

[0111] Reference Figure 7 , the device comprises:

[0112] The cycle determination module 701 is used to determine the update cycle of at least one target acquisition data; at least one of the target acquisition data is stored in one or more partitions of the first memory of the system-level chip, and the acquisition data in the same partition have the same update cycle, and the first memory is a memory in the first processor of the system-level chip;

[0113] The data reading module 702 is used to periodically read the target collection data in the corresponding partition through the shared memory at the update period of each target collection data;

[0114] A storage module is used to save the read target acquisition data to a second memory; the storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor of the system-level chip.

[0115] Optionally, the above device further includes:

[0116] A first determination module is used to determine the number of update cycles of each of the target acquisition data;

[0117] The data reading module 702 includes:

[0118] A first creation unit, configured to create a corresponding number of first threads or first processes based on the number of update cycles of each target collection data;

[0119] The first control unit is used to control each of the first threads or the first process to periodically read the target collection data in the corresponding partition through the shared memory with the update period of the corresponding target collection data as a period.

[0120] Optionally, when the partition in the first processor is mapped to the address space of the second processor, and the access attribute of the mapped address space is a read-only attribute, the first control unit is specifically configured to:

[0121] Each of the first threads or the first process is controlled to periodically read the target acquisition data from the mapped address space based on the address of the target acquisition data in the corresponding partition, with the update period of the corresponding target acquisition data as the period.

[0122] Optionally, the above device further includes:

[0123] A second determination module is used to determine the number of partitions where each target acquisition data is located;

[0124] Optionally, the data reading module 702 includes:

[0125] A second creation unit, configured to create a corresponding number of second threads or second processes based on the number of partitions where the target collection data is located;

[0126] The second control unit is used to control each of the second threads or the second processes to periodically read the collection data of the corresponding partition through the shared memory with the update period of the target collection data in the corresponding partition as the period, and determine the target collection data from the collection data of the corresponding partition based on the address of the target collection data in the corresponding partition.

[0127] Optionally, when the partition in the first processor is mapped to the address space of the second processor, and the access attribute of the mapped address space is a read-only attribute, the second control unit is specifically used to:

[0128] Each of the second threads or the second process is controlled to periodically read the collection data of the corresponding partition from the mapped address space based on the address of the partition where the target collection data is located, with the update period of the target collection data in the corresponding partition as the period.

[0129] Optionally, the above device further includes:

[0130] A state monitoring module, used for monitoring the state of a trigger flag variable of any target acquisition data;

[0131] The disk writing module is used to write the target acquisition data that meets the requirements and is stored in the second memory to the file system when the state of the trigger flag variable is monitored to switch to the trigger state. The target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within a first time period before the switching moment and a second time period after the switching moment. The switching moment is the moment when the state of the trigger flag variable is monitored to switch to the trigger state.

[0132] Corresponding to the data recording method described in the above embodiment, Figure 8 A structural schematic diagram of another data recording device provided in an embodiment of the present application is shown. The data recording device can be a device applied to a first processor of a system-level chip or the data recording device can serve as a first processor. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0133] Reference Figure 8 , the device comprises:

[0134] The data acquisition module 801 is used to acquire one or more collected data;

[0135] The data allocation module 802 is used to allocate each of the collected data to one or more partitions of the first memory according to the update period of each of the collected data; the update period of the collected data in the same partition is the same, and the first memory is the memory in the first processor of the system-level chip;

[0136] Among them, the update cycle of the collected data is used to trigger the second processor of the system-level chip to periodically read the collected data in the corresponding partition through the shared memory, and save the read collected data to the second memory. The storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor.

[0137] Optionally, any of the collected data has a trigger flag variable; the above device also includes:

[0138] A state switching module, configured to switch the state of a trigger flag variable corresponding to one or more target collected data to a trigger state when a disk drop event is detected for the target collected data in the one or more collected data;

[0139] Among them, the trigger state is used to trigger the second processor to write the target acquisition data that meets the requirements and is stored in the second memory to the disk to a file, and the target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within a first time period before the switching moment and a second time period after the switching moment, and the switching moment is the moment when the state of the trigger flag variable is switched to the trigger state.

[0140] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0141] Fig. 9 This is a schematic diagram of the structure of the system-level chip provided in the embodiment of the present application. Fig. 9 As shown, the system-level chip 9 of this embodiment includes: a first processor 901 and a second processor 902, the first processor 901 is used to execute the above Figure 4 In the steps of the method embodiment shown in FIG. 1 , the second processor 902 is configured to execute the following steps: Figure 2 Steps in the illustrated method embodiment.

[0142] The system-on-chip may include, but is not limited to, a first processor 901 and a second processor 902. Those skilled in the art will appreciate that Fig. 9 The system-on-chip is merely an example and does not limit the system-on-chip, which may include more or less components than shown in the figure, or a combination of certain components, or different components.

[0143] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0144] The present application also provides a smart device, which includes the Fig. 9The system-level chip, or the smart device includes a first processor and a second processor, wherein the first processor is used to execute the above Figure 4 The data recording method described above, wherein the second processor is used to execute the above Figure 2 The data recording method.

[0145] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the device / electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0146] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0147] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0148] In the embodiments provided in the present application, it should be understood that the disclosed device / system-level chip and method can be implemented in other ways. For example, the device / system-level chip embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A data recording method, characterized in that: The data recording method comprises: Determine an update period of at least one target acquisition data; at least one of the target acquisition data is stored in one or more partitions of a first memory of a system-level chip, and the acquisition data in the same partition have the same update period, and the first memory is a memory in a first processor of the system-level chip; Taking the update period of each target collection data as a period, periodically reading the target collection data in the corresponding partition through the shared memory; The read target acquisition data are saved in a second memory; the storage space of the second memory is larger than the storage space of the first memory, and the second memory is a memory in a second processor of the system-level chip.

2. The data recording method according to claim 1, characterized in that: Before periodically reading the target acquisition data in the corresponding partition through the shared memory with the update period of each target acquisition data as a period, the method further includes: Determining the number of update cycles for each of the target acquisition data; The step of periodically reading the target acquisition data in the corresponding partition through the shared memory at the update period of each target acquisition data comprises: Based on the number of update cycles of each target acquisition data, create a corresponding number of first threads or first processes; Each of the first threads or the first process is controlled to periodically read the target collection data in the corresponding partition through the shared memory with the update period of the corresponding target collection data as a period.

3. The data recording method according to claim 2, characterized in that: In a case where a partition in the first processor is mapped to an address space of the second processor, and an access attribute of the mapped address space is a read-only attribute, controlling each of the first threads or the first process to periodically read the target acquisition data in the corresponding partition through the shared memory with an update period of the corresponding target acquisition data as a period, including: Each of the first threads or the first process is controlled to periodically read the target acquisition data from the mapped address space based on the address of the target acquisition data in the corresponding partition, with the update period of the corresponding target acquisition data as the period.

4. The data recording method according to claim 1, characterized in that: Before periodically reading the target acquisition data in the corresponding partition through the shared memory with the update period of each target acquisition data as a period, the method further includes: Determine the number of partitions where each target acquisition data is located; The step of periodically reading the target acquisition data in the corresponding partition through the shared memory at the update period of each target acquisition data comprises: Based on the number of partitions where the target collection data is located, create a corresponding number of second threads or second processes; Control each of the second threads or the second processes to periodically read the collection data of the corresponding partition through the shared memory with the update period of the target collection data in the corresponding partition as the period, and determine the target collection data from the collection data of the corresponding partition based on the address of the target collection data in the corresponding partition.

5. The data recording method according to claim 4, characterized in that: In a case where a partition in the first processor is mapped to an address space of the second processor, and an access attribute of the mapped address space is a read-only attribute, controlling each second thread or the second process to periodically read the collected data in the corresponding partition through the shared memory with an update period of the target collected data in the corresponding partition as a period, including: Each of the second threads or the second process is controlled to periodically read the collection data of the corresponding partition from the mapped address space based on the address of the partition where the target collection data is located, with the update period of the target collection data in the corresponding partition as the period.

6. The data recording method according to any one of claims 1 to 4, characterized in that: After the read target acquisition data is saved in the second memory, the method further includes: For any of the target acquisition data, monitoring the state of a trigger flag variable of the target acquisition data; In the case where it is monitored that the state of the trigger flag variable switches to the trigger state, the target acquisition data that meets the requirements and is stored in the second memory is written to the file system, and the target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within a first time period before the switching moment and a second time period after the switching moment. The switching moment is the moment when the state of the trigger flag variable is monitored to switch to the trigger state.

7. A data recording method, characterized in that: The data recording method comprises: Obtain one or more collected data; Allocate each of the collected data to one or more partitions of a first memory according to an update period of each of the collected data; the update period of the collected data in the same partition is the same, and the first memory is a memory in a first processor of a system-level chip; Among them, the update cycle of the collected data is used to trigger the second processor of the system-level chip to periodically read the collected data in the corresponding partition through the shared memory, and save the read collected data to the second memory. The storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor.

8. The data recording method according to claim 7, characterized in that: Any of the collected data has a trigger flag variable; The data recording method further comprises: When a disk drop event for target collected data among one or more collected data is detected, the state of the trigger flag variable corresponding to the target collected data is switched to a triggered state; Among them, the trigger state is used to trigger the second processor to write the target acquisition data that meets the requirements and is stored in the second memory to the file system. The target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within a first time period before the switching moment and a second time period after the switching moment. The switching moment is the moment when the state of the trigger flag variable is switched to the trigger state.

9. A data recording device, characterized in that: The data recording device comprises: A cycle determination module, used to determine an update cycle of at least one target acquisition data; at least one of the target acquisition data is stored in one or more partitions of a first memory of a system-level chip, and the acquisition data in the same partition have the same update cycle, and the first memory is a memory in a first processor of the system-level chip; A data reading module, used for periodically reading the target collection data in the corresponding partition through the shared memory at the update period of each target collection data; A storage module is used to save the read target acquisition data into a second memory; the storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor of the system-level chip.

10. A data recording device, characterized in that: The data recording device comprises: A data acquisition module, used to acquire one or more collected data; A data allocation module, used for allocating each of the collected data to one or more partitions of a first memory according to an update period of each of the collected data; the update period of the collected data in the same partition is the same, and the first memory is a memory in a first processor of a system-level chip; Among them, the update cycle of the collected data is used to trigger the second processor of the system-level chip to periodically read the collected data in the corresponding partition through the shared memory, and save the read collected data to the second memory. The storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor.

11. A system-on-chip, characterized in that: The system-on-chip comprises a first processor and a second processor, wherein the first processor is used to execute the data recording method according to any one of claims 7 to 8, and the second processor is used to execute the data recording method according to any one of claims 1 to 6.

12. A smart device, characterized in that: The smart device includes the system-level chip as claimed in claim 11, or the smart device includes a first processor and a second processor, the first processor is used to execute the data recording method as claimed in any one of claims 7 to 8, and the second processor is used to execute the data recording method as claimed in any one of claims 1 to 6.

Images