Disk pulling and chain dropping method and device based on SAS / SATA protocol, computer device and storage medium

Abstract

The application relates to the technical field of data communication interfaces, and discloses a disk pulling and chain dropping method and device based on a SAS / SATA protocol, computer equipment and a storage medium, the method being used for a target device and comprising the following steps: detecting the device type of the target device; when a physical coding sublayer of the target device is in a physical layer ready state, detecting the receiving state of an indication signal corresponding to the device type of the target device in real time; and when the receiving state of the indication signal corresponding to the device type of the target device meets a chain dropping condition of the device type, triggering the physical coding sublayer to drop from the physical layer ready state. The application realizes the disk pulling and chain dropping function based on the SAS / SATA protocol, solves the problem that the physical coding sublayer does not drop after the disk is pulled, and improves the reliability and stability of serial communication.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data communication interface, and particularly relates to a disk pulling and chain dropping method and device based on a SAS / SATA protocol, a computer device and a storage medium. BACKGROUND

[0002] Serial Attached SCSI (SAS) is a new generation of SCSI technology, which has better transmission speed, longer transmission distance and stronger anti-interference ability compared with the traditional parallel SCSI. SAS hard disk is a mainstream enterprise-level storage method, such as data center, server, etc. Serial ATA (SATA) is also a hard disk interface technology based on serial communication protocol, and SATA hard disk is widely used in personal computers, consumer electronics and other fields. Among them, SAS interface technology is downward compatible with SATA, mainly reflected in the physical layer (Phy layer), that is, SATA can be used in the topology of SAS.

[0003] Hot plug test is an indispensable part of SAS / SATA chip, but when performing hot plug test of SAS disk and SATA disk on FPGA or ASIC, if it is 8b / 10b mode (other speeds except 22.5G adopt 8b10b encoding and decoding), after pulling out the disk, the physical coding sublayer (Pcs) has a high probability of being in the Phyready state, and no chain drop occurs, which not only violates the needs of the test personnel, but also affects the reliability of the chip, resulting in fatal I / O errors in the application layer. Although the existing SPL-5 protocol defines the complete process of building a chain of SAS and SATA interfaces, it does not consider the diversity of SerDes (SERializer (serializer) / DESerializer (deserializer)). In the Phyready state, different SerDeses may have different performances after pulling out the disk, and the SPL-5 protocol only regulates the chain drop condition from the perspective of Pcs, without covering all possible SerDes cases. SUMMARY

[0004] Therefore, the present application provides a disk pulling and chain dropping method and device based on a SAS / SATA protocol, a computer device and a storage medium to solve the problem of no chain drop of the physical coding sublayer after pulling out the disk.

[0005] In a first aspect, the present application provides a method for unplugging and disengaging based on SAS / SATA protocol, the method is used for a target device, and the method comprises the following steps: detecting the device type of the target device; when the physical coding sublayer of the target device is in a physical layer ready state, detecting the receiving state of an indication signal corresponding to the device type of the target device in real time; and triggering the physical coding sublayer to disengage from the physical layer ready state when the receiving state of the indication signal corresponding to the device type of the target device meets the disengagement condition of the device type.

[0006] In an optional implementation, when the indication signal is K code, triggering the physical coding sublayer to disengage from the physical layer ready state when the receiving state of the indication signal corresponding to the device type of the target device meets the disengagement condition of the device type comprises: triggering the physical coding sublayer to disengage from the physical layer ready state when K code cannot be detected after a first preset time when the physical coding sublayer enters the physical layer ready state.

[0007] In an optional implementation, when the indication signal is an electrical indication signal, the electrical indication signal represents whether the SerDes is in an electrical idle state, and triggering the physical coding sublayer to disengage from the physical layer ready state when the receiving state of the indication signal corresponding to the device type of the target device meets the disengagement condition of the device type comprises: triggering the physical coding sublayer to disengage from the physical layer ready state when the SerDes is in the electrical idle state for more than a second preset time.

[0008] In an optional implementation, triggering the physical coding sublayer to disengage from the physical layer ready state when the receiving state of the indication signal corresponding to the device type of the target device meets the disengagement condition of the device type comprises: detecting K code and the electrical indication signal at the same time, and triggering the physical coding sublayer to disengage from the physical layer ready state when K code cannot be detected after a first preset time when the physical coding sublayer enters the physical layer ready state or when the SerDes is in the electrical idle state for more than a second preset time.

[0009] In an optional implementation, the first preset time and the second preset time are configured through a register.

[0010] In an optional implementation, the indication signal is K code, and detecting the receiving state of the indication signal corresponding to the device type of the target device in real time comprises: receiving a data alignment signal every third preset time based on a preset protocol, and detecting K code from the data alignment signal.

[0011] In an optional implementation, when the physical coding sublayer disengages from the physical layer ready state, the physical coding sublayer is reset.

[0012] In a second aspect, the present application provides a disk pulling and chain dropping device based on SAS / SATA protocol, the device comprising: a device detection module, configured to detect a device type of a target device; a signal detection module, configured to detect a receiving state of an indication signal corresponding to the device type of the target device in real time when a physical coding sublayer of the target device is in a physical layer ready state; and a chain dropping trigger module, configured to trigger the physical coding sublayer to drop from the physical layer ready state if the receiving state of the indication signal corresponding to the device type of the target device meets a chain dropping condition of the device type.

[0013] In an optional implementation, the device detection module is further configured to determine that the device type of the target device is FPGA or ASIC.

[0014] In an optional implementation, when the device type is FPGA, the indication signal is K code; and the chain dropping trigger module comprises: an FPGA chain dropping unit, configured to trigger the physical coding sublayer to drop from the physical layer ready state if the K code cannot be detected after a first preset time when the physical coding sublayer enters the physical layer ready state.

[0015] In an optional implementation, when the device type is ASIC, the indication signal is an electrical indication signal; the electrical indication signal represents whether a SerDes is in an electrical idle state; and the chain dropping trigger module further comprises: an ASIC chain dropping unit, configured to trigger the physical coding sublayer to drop from the physical layer ready state if the SerDes is in the electrical idle state for more than a second preset time.

[0016] In an optional implementation, the chain dropping trigger module further comprises: a time configuration unit, configured to configure the first preset time and the second preset time through a register.

[0017] In an optional implementation, the indication signal is K code; and the signal detection module comprises: a first K code acquisition unit, configured to receive a data alignment signal every third preset time based on a preset protocol; and a second K code acquisition unit, configured to detect the K code from the data alignment signal.

[0018] In an optional implementation, the device further comprises: a reset unit, configured to reset the physical coding sublayer after the physical coding sublayer drops from the physical layer ready state.

[0019] In another aspect, the present application provides a computer device, comprising: a memory and a processor, which are communicatively connected to each other, and the memory stores computer instructions; and the processor executes the computer instructions to perform the disk pulling and chain dropping method based on SAS / SATA protocol in the first aspect or any of the corresponding implementations.

[0020] In another aspect, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform a disk disconnection and disconnection method based on the SAS / SATA protocol according to the first aspect or any corresponding embodiment described above.

[0021] In another aspect, the present invention provides a computer program product, including computer instructions, which are used to cause a computer to execute a disk disconnection and disconnection method based on the SAS / SATA protocol according to the first aspect or any corresponding embodiment described above.

[0022] The technical solution provided in this application may include the following beneficial effects:

[0023] The device type of the target device is detected to provide a basis for subsequent steps. When the physical coding sublayer of the target device is in the physical layer ready state, the reception status of the indicator signal corresponding to the device type of the target device is monitored in real time. The indicator signal can reflect the state change of SerDes after disk removal, and determine whether the physical coding sublayer should trigger a disconnection operation. If the reception status of the indicator signal corresponding to the device type of the target device meets the disconnection condition of the device type, the physical coding sublayer is triggered to disconnect from the physical layer ready state. This ensures that the physical coding sublayer can disconnect in a timely manner under various SerDes conditions, thereby avoiding unnecessary I / O errors and improving chip reliability. The above scheme, by detecting whether the reception status of the indicator signal meets the disconnection condition of the device type, realizes the disk removal disconnection function based on the SAS / SATA protocol, solves the problem of the physical coding sublayer not disconnecting after disk removal, and improves the reliability and stability of serial communication. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a flowchart illustrating a disk disconnection and connection loss method based on the SAS / SATA protocol according to an embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of the SAS / SATA disk unplugging operation according to an embodiment of the present invention;

[0027] Figure 3 This is a structural block diagram of a disk disconnection and disconnection device based on the SAS / SATA protocol according to an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] According to an embodiment of the present invention, a method for disconnecting disks and disconnecting the connection based on the SAS / SATA protocol is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0031] This embodiment provides a disk disconnection and connection loss method based on the SAS / SATA protocol. The method is used for the target device. Figure 1 This is a flowchart illustrating a disk disconnection method based on the SAS / SATA protocol according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0032] Step S101: Detect the device type of the target device;

[0033] In the disk disconnection and disconnection method based on the SAS / SATA protocol, the type of the target device must first be detected. As an example of this invention, the target device is FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) to more fully explain the steps of the disk disconnection and disconnection method based on the SAS / SATA protocol provided in the specific embodiments of this invention. However, the method disclosed in this invention is not limited to the two exemplary devices mentioned above; other device types that can be directly conceived by those skilled in the art based on the content of the specific embodiments of this invention are also applicable to this method.

[0034] Specifically, an FPGA is a semiconductor device whose internal logic circuitry can be configured through software programming. It includes a large number of programmable logic blocks (PLBs) and programmable interconnects, allowing users to define the functionality and connection methods of the logic blocks according to their own needs. An ASIC is an integrated circuit customized for a specific application or function and can only perform one or a few specific tasks.

[0035] The reason why the physical coding sublayer of the SerDes of the FPGA and the ASIC does not drop off the chain after the disk is pulled out can be:

[0036] After the disk is pulled out, the SerDes returns to a default value, which is likely to cause no decoding error of the pcs 8b / 10b; for example, when the FPGA is tested, the Xilinx SerDes is used, and the returned default value is 40'haaaaaaaaaa.

[0037] For example, when the ASIC is tested, after the disk is pulled out, the local RX is suspended, but the local TX sends normal 8b / 10b data, which interferes with the RX and causes the Pcs to not drop off the chain.

[0038] Step S102, when the physical coding sublayer of the target device is in a physical layer ready state, the receiving state of an indication signal corresponding to the device type of the target device is detected in real time.

[0039] When the physical coding sublayer of the target device is in a physical layer ready state, the receiving state of an indication signal corresponding to the device type of the target device needs to be detected in real time. The physical coding sublayer is part of the SAS / SATA protocol stack, which is responsible for physically encoding the data from the upper layer for transmission on the physical link, and also responsible for receiving the data on the physical link and decoding it, and then passing it to the upper layer. The physical layer ready state means that the SAS / SATA interface has completed connection and initialization on the physical layer and is ready for data transmission. The indication signal is a signal used to indicate a certain state or condition, and its receiving state represents the reception of the indication signal on the target device, including whether the signal is successfully received. The indication signal can come from the physical layer or a lower hardware interface, and is used to reflect the current connection state or data transmission state of the device. By monitoring these indication signals in real time, abnormal conditions can be detected in a timely manner, such as identifying that the disk has been pulled out.

[0040] Step S103, if the receiving state of the indication signal corresponding to the device type of the target device meets the chain drop-off condition of the device type, triggering the physical coding sublayer to drop off the chain from the physical layer ready state.

[0041] When the physical coding sublayer is in a physical layer ready state, due to various reasons (such as signal interference, device failure, etc.), the connection may be unexpectedly interrupted, which is referred to as a disk pull-out operation in the present application, at which time the chain drop-off operation needs to be triggered.

[0042] When the detection of the reception state of the indication signal corresponding to the target device type meets the chain drop condition, the physical coding sublayer will be triggered to drop from the physical layer ready state. The chain drop operation refers to forcibly exiting the Pcs from the physical layer ready state to prevent data transmission errors or system crashes caused by unstable connections. The chain drop condition is defined according to the device type and protocol standards (such as SPL-5), including signal loss, signal reset, electrical idle state, etc. After triggering the chain drop operation, the resources related to the device are released, and preparation is made for the next connection or data transmission. The setting of the chain drop condition needs to be determined according to the device type and protocol standards to ensure the compatibility and reliability of the system. Optionally, before triggering the chain drop operation, some preprocessing work is performed, such as saving the current data state, notifying relevant modules, etc.

[0043] The SAS / SATA protocol-based disk plugging chain drop method provided by the embodiment can timely trigger the chain drop operation when the device is unplugged by detecting whether the reception state of the indication signal meets the chain drop condition of the device type, thereby reducing the risk of misjudgment and omission, solving the problem of not dropping the physical coding sublayer after plugging the disk, and improving the reliability and stability of serial communication.

[0044] In an optional implementation, when the indication signal is a K code; the step S103 includes the following steps:

[0045] Step S103A, if the K code is not detected after the first preset time when the physical coding sublayer enters the physical layer ready state, the physical coding sublayer is triggered to drop from the physical layer ready state.

[0046] The K code is a special code word used for synchronization, error detection or other specific purposes in serial communication. In SAS / SATA communication, the K code may be used to indicate data alignment, synchronization state or other key information. By detecting the presence or absence of the K code, it can be judged whether the link is stable. If the K code is not detected after the first preset time, it indicates that the link has been disconnected or there are other problems, such as the device being unplugged, so the chain drop is triggered. The first preset time is a configurable parameter for setting the maximum time for waiting to detect the K code.

[0047] Optionally, the K code (K28.5) in the SPL-5 protocol is usually not alone, containing two data formats, dword and primitive, both of which are 4 bytes. The dword and the primitive are different. The first byte of the primitive is the K code, while the dword is pure data. The primitive is in the pcs layer and is usually used for data synchronization. The absence of the primitive does not necessarily mean that the link is problematic or that the synchronization has been lost. The current link may be transmitting and receiving dword. However, if no K code is received after a second preset time (for example, 128 dword corresponding time), the link is disconnected.

[0048] In an optional embodiment, when the indication signal is an electrical indication signal; the electrical indication signal represents whether the SerDes is in an electrical idle state; and the step S103 comprises the following steps:

[0049] Step S103B, if the SerDes is in the electrical idle state for more than a second preset time, triggering the physical coding sublayer to drop from the physical layer ready state.

[0050] In serial communication, such as SAS and SATA, the SerDes is responsible for converting parallel data into serial data for transmission, and converting serial data back into parallel data at the receiving end. When a device communicates with the system through the SerDes, if the device is unplugged, the SerDes may enter an electrical idle state, i.e., a state without data transmission. By detecting the electrical idle state, it can be determined whether the link is in an inactive state. In this embodiment, the SerDes has an electrical indication signal to represent whether it is in an electrical idle state. By monitoring this indication signal, the state of the SerDes can be determined. If the SerDes continues to be in the electrical idle state after a preset time, it means that the device has been unplugged or the link has been interrupted, so the drop is triggered. The second preset time is a configurable parameter for setting the maximum time for the SerDes to wait in the electrical idle state.

[0051] The present embodiment increases an additional detection mechanism to ensure that the physical coding sublayer drops from the physical layer ready state at the appropriate time, thereby improving the reliability and stability of serial communication.

[0052] In an optional embodiment, the step S103 further comprises: simultaneously detecting the K code and the electrical indication signal, and if the K code cannot be detected after a first preset time for the physical coding sublayer to enter the physical layer ready state or the SerDes is in the electrical idle state for more than a second preset time, triggering the physical coding sublayer to drop from the physical layer ready state.

[0053] Two detection processes are started simultaneously: K code detection and electrical idle state detection. In the two detection processes, as long as any one detection condition is met (i.e. K code is not detected after the first preset time when the physical coding sublayer enters the physical layer ready state, or the SerDes is in the electrical idle state for more than the second preset time), the physical coding sublayer is triggered to drop from the physical layer ready state.

[0054] The embodiment ensures that the link state can be quickly responded to, and the reliability and stability of serial communication are improved.

[0055] Further, the first preset time and the second preset time are configured by a register.

[0056] The first preset time and the second preset time are configured by a register. In the scenario of an FPGA device, when the physical coding sublayer enters the physical layer ready state, timing is started. If K code is not detected within the set first preset time, the physical coding sublayer is triggered to drop from the physical layer ready state. In the scenario of an ASIC device, whether the SerDes is in the electrical idle state is monitored. If the SerDes is in the electrical idle state for more than the set second preset time, the physical coding sublayer is triggered to drop from the physical layer ready state.

[0057] Optionally, the first preset time and the second preset time are not fixed, and are flexibly adjusted according to actual application scenarios and requirements. For example, in a scenario requiring quick response, the preset time can be shortened; and in a scenario requiring higher stability, the preset time can be appropriately lengthened.

[0058] The embodiment configures the first preset time and the second preset time by a register, and the first preset time and the second preset time can be flexibly adjusted according to different application scenarios and requirements, thereby improving the flexibility of serial communication.

[0059] In an optional embodiment, the indication signal is a K code; and the step S102 comprises the following steps:

[0060] In step a11, based on a preset protocol, a data alignment signal is received every third preset time.

[0061] The data alignment signal is periodically sent to maintain the correct alignment of data during data transmission. The third preset time refers to the interval time of sending the data alignment signal, which is a configurable parameter configured according to the requirements of the SAS / SATA protocol and related to the period of the data alignment signal. For example, the Align primitive is used to achieve data alignment during data transmission or storage, including specific patterns or identifiers, so that the receiving end can identify and align the data. The SPL-5 protocol specifies that the upper layer inserts an Align primitive once every 128 Dword corresponding time, and the Align primitive contains a K code.

[0062] Step a12, detecting the K code from the data alignment signal.

[0063] After receiving the data alignment signal, it is analyzed and processed to detect whether it contains a K code. The detection process may involve bit-level operations such as bit synchronization, bit counting, pattern matching, etc.

[0064] In this embodiment, by setting the third preset time and detecting the K code, data alignment and synchronization can be effectively performed, ensuring the accuracy and reliability of data transmission.

[0065] Optionally, the first preset time is greater than or equal to the third preset time, indicating that at least one data alignment signal will be received within the time window for detecting the K code, improving the reliability of K code detection.

[0066] Specifically, in the embodiments of the present application, as shown in Figure 2 The SAS disk / SATA disk has a disk removal operation at positions ① and ②, and the present application proposes two solutions to the problem of probabilistic chain drop.

[0067] For the problem on the FPGA: The SPL-5 protocol specifies that the upper layer of SerDes inserts an Align primitive once every 128 Dword corresponding time, and the K code detection mechanism is added in the physical coding sublayer. When the physical layer is ready, after a period of time (register configurable), if no K code is detected, the physical coding sublayer will automatically drop the chain from the physical layer ready state.

[0068] For the problem on the ASIC: SerDes outputs an indication signal to the physical coding sublayer to indicate whether SerDes is in an electrical idle state. When the physical coding sublayer detects that SerDes has been in an electrical idle state for a long time (register configurable), the physical coding sublayer will also automatically drop the chain from the physical layer ready state.

[0069] In an optional embodiment, when the physical coding sublayer drops the chain from the physical layer ready state, the physical coding sublayer is reset.

[0070] After the disconnection, the physical coding sublayer is reset in order to clear any possible error state and prepare for reestablishing the connection. Optionally, the reset operation includes restoring the internal state of the physical coding sublayer to an initial state, clearing any pending errors or interrupts, and reinitializing necessary configuration parameters. When reattempting to establish the connection, the physical coding sublayer will be in a known and stable state, which helps to ensure the reliability of data transmission.

[0071] A SAS / SATA protocol based disc ejection and disconnection device is also provided in the embodiment, which is used to implement the above embodiment and preferred implementation, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiment is preferably implemented in software, hardware, or a combination of software and hardware is also possible and contemplated.

[0072] The embodiment provides a SAS / SATA protocol based disc ejection and disconnection device, as shown in the figure, comprising: Figure 3 A device detection module 301 is configured to detect the device type of a target device.

[0073] A signal detection module 302 is configured to detect the reception state of an indication signal corresponding to the device type of the target device in real time when the physical coding sublayer of the target device is in a physical layer ready state.

[0074] A disconnection triggering module 303 is configured to trigger the physical coding sublayer to disconnect from the physical layer ready state if the reception state of the indication signal corresponding to the device type of the target device meets the disconnection condition of the device type.

[0075] In an optional implementation, when the indication signal is a K code; the disconnection triggering module 303 comprises:

[0076] A K code detection unit is configured to trigger the physical coding sublayer to disconnect from the physical layer ready state if the K code is not detected after a first preset time when the physical coding sublayer enters the physical layer ready state.

[0077] In an optional implementation, when the indication signal is an electrical indication signal; the electrical indication signal represents whether the SerDes is in an electrical idle state; the disconnection triggering module 303 further comprises:

[0078] An electrical detection unit is configured to trigger the physical coding sublayer to disconnect from the physical layer ready state if the SerDes is in the electrical idle state for more than a second preset time.

[0079]

[0080] ​In an alternative embodiment, the drop-off triggering module 303 further comprises:

[0081] a simultaneous detection unit configured to simultaneously detect the K code and the electrical indication signal, and trigger the PCS to drop off from the PHY ready state if the K code cannot be detected or the SerDes is in the electrical idle state for more than a second preset time after a first preset time for the PCS to enter the PHY ready state.

[0082] In an alternative embodiment, the drop-off triggering module 303 further comprises:

[0083] a time configuration unit configured to configure the first preset time and the second preset time through a register.

[0084] In an alternative embodiment, the indication signal is the K code; and the signal detection module 302 comprises:

[0085] a first K code acquisition unit configured to receive a data alignment signal every third preset time based on a preset protocol;

[0086] a second K code acquisition unit configured to detect the K code from the data alignment signal.

[0087] In an alternative embodiment, the device further comprises:

[0088] a reset unit configured to reset the PCS after the PCS drops off from the PHY ready state.

[0089] Further function descriptions of the above-mentioned modules and units are the same as those of the corresponding embodiments, and will not be repeated here.

[0090] The disk pull-off and drop-off device based on the SAS / SATA protocol in the embodiment is presented in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit) circuits, processors and memories executing one or more software or fixed programs, and / or other devices capable of providing the above-mentioned functions.

[0091] The embodiment of the application further provides a computer device having the disk pull-off and drop-off device based on the SAS / SATA protocol. Figure 3 as shown in the above

[0092] Please refer to Figure 4 , Figure 4 is a structural schematic diagram of a computer device provided by an alternative embodiment of the application, as Figure 4As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 4 Take a processor 10 as an example.

[0093] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0094] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0095] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0096] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0097] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means.Figure 4 The bus connection is taken as an example.

[0098] The input device 30 can receive inputted digital or character information, and generate key signal input related to user settings and function control of the computer device, such as touch screen, keypad, mouse, trackpad, touchpad, pointing stick, one or more mouse buttons, trackball, joystick, etc. The output device 40 can include display device, auxiliary lighting device (e.g. LED), and tactile feedback device (e.g. vibration motor), etc. The display device includes but is not limited to liquid crystal display, light emitting diode, display and plasma display. In some alternative embodiments, the display device can be a touch screen.

[0099] The embodiments of the present application also provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, processor, microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, processor or hardware, the method shown in the above embodiments is implemented.

[0100] Part of the embodiments of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, the operation of the computer can call or provide the method and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file, etc., and accordingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0101] While embodiments of the application have been described in connection with the preferred embodiments of the various figures, those of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the application, and that such modifications and changes fall within the scope of the appended claims.

Claims

1. A method for disconnecting a disk based on the SAS or SATA protocol, characterized in that, The method is used for a target device, the target device including an FPGA or ASIC chip with a SAS or SATA interface, and the method includes: The type of equipment used to detect the target device; When the physical coding sublayer of the target device is in the physical layer ready state, the reception status of the indication signal corresponding to the device type of the target device is detected in real time according to the detected device type. If the detected device type is FPGA, the detection indication signal is K code; The real-time detection includes: based on the SPL-5 protocol, receiving a data alignment signal every third preset time interval, and detecting the K code from the data alignment signal; If the K code is not detected within the first preset time after the physical coding sublayer enters the physical layer ready state, it is determined that the link drop condition is met. If the detected device type is ASIC, the detected indication signal is the electrical idle indication signal output by SerDes; The real-time detection includes: monitoring the electrical idle indication signal; if the duration of the SerDes being in an electrical idle state is greater than a second preset time, then it is determined that the link drop condition is met; When the disconnection condition of the device type is met, the physical coding sublayer is triggered to disconnect from the physical layer ready state.

2. The method according to claim 1, characterized in that, The first preset time and the second preset time are configured via registers.

3. The method according to claim 1, characterized in that, When the physical coding sublayer drops from the physical layer ready state, the physical coding sublayer is reset.

4. A disk disconnect / disconnect device based on SAS or SATA protocol, characterized in that, The device includes: The device detection module is used to detect the device type of the target device; wherein, the target device includes an FPGA or ASIC chip with a SAS or SATA interface; The signal detection module is used to detect the reception status of the indication signal corresponding to the device type of the target device in real time, based on the detected device type, when the physical coding sublayer of the target device is in the physical layer ready state. Wherein, if the device detection module detects that the device type is FPGA, the detected indication signal is K code; the signal detection module includes: a first K code acquisition unit, used to receive a data alignment signal every third preset time based on the SPL-5 protocol; and a second K code acquisition unit, used to detect K code from the data alignment signal; The link drop triggering module includes an FPGA link drop unit, which is used to determine that the link drop condition is met if the K code is not detected within a first preset time after the physical coding sublayer enters the physical layer ready state. If the device detection module detects that the device type is ASIC, the detected indication signal is the electrical idle indication signal output by SerDes; the signal detection module is specifically used to monitor the electrical idle indication signal. The chain drop triggering module includes an ASIC chain drop unit, which is used to determine that the chain drop condition is met if the duration of the SerDes being in an electrically idle state is greater than a second preset time. The link drop triggering module is used to trigger the physical coding sublayer to drop from the physical layer ready state when the link drop conditions are met.

5. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method of any one of claims 1 to 3.

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