Discrete Fourier detection implementation method and system based on CUDA (Compute Unified Device Architecture) tensor core

Abstract

The invention belongs to the field of randomness detection, and relates to a discrete Fourier detection implementation method and system based on a CUDA tensor core. The method comprises the following steps: realizing discrete Fourier transform (DFT) with a cardinal number of 10 on a CUDA (Compute Unified Device Architecture) by utilizing the characteristics of a tensor core of an NVIDIA GPU (Graphics Processing Unit); kernel fusion is carried out by using discrete Fourier transform with a cardinal number of 10, a plurality of small kernels are fused into a large kernel, and large-size input data are decomposed and recombined, so that the execution of fast Fourier transform (FFT) operation is optimized. In addition, the execution process is optimized by using the CUDA flow, the advantages of the CUDA architecture can be fully played, and the data processing efficiency and the algorithm execution speed are improved. Compared with the prior art, higher performance can be provided when a large-scale data set is processed.

Description

Technical Field

[0001] The present invention belongs to the field of information technology, relates to a randomness detection method, and specifically to a discrete Fourier detection implementation method and system based on CUDA tensor core. Background Art

[0002] Discrete Fourier detection is a randomness detection method, which is often used for random number detection. It evaluates the randomness of a sequence by calculating the spectrum. The most important step is to perform fast Fourier transform (FFT) on the sequence.

[0003] With the continuous advancement of GPU technology, application programming interfaces (APIs) specifically for GPU computing have provided more options for FFT implementation. The most famous of these is NVIDIA's CUDA (Compute Unified Device Architecture) technology and its affiliated cuFFT library, which utilizes the high floating-point computing power and parallel processing capabilities of NVIDIA GPUs.

[0004] Tensor Cores are special computing units launched by NVIDIA. Durrani et al. proposed a mixed-precision FFT implementation method based on tensor cores. They split the large discrete Fourier transform (DFT) calculation into multiple small, parallelizable baseline discrete Fourier transform calculation sequences, maintaining the inherent low complexity of the FFT algorithm and achieving a speed up to 1.5 times faster than the traditional FFT library cuFFT in a small size. This mixed-precision FFT implementation provides new ideas for the field of high-performance computing.

[0005] The common implementation of existing discrete Fourier detection (such as the NIST detection kit of the National Institute of Standards and Technology of the United States) is 10 8 The time consumption for bit sequence detection (CPU uses AMD Ryzen 7 5800H, main frequency is 3.2GHz) is 32s, and the required memory is about 3GB. However, it is necessary to detect 1,000 sequences to complete a set of detections, which faces obvious efficiency challenges in practical applications.

[0006] As for the fast GPU implementation of discrete Fourier detection, the commonly used implementation methods such as the cuFFT library are not combined with tensor cores due to their universality; the method of introducing tensor cores is limited in the actual application of discrete Fourier detection (whose detection target is a bit sequence with a power length of 10) because of hardware characteristics, as it targets FFTs with a power length of 2 or 16. Summary of the invention

[0007] In view of the above problems, the present invention provides a method and system for realizing discrete Fourier detection based on CUDA tensor core.

[0008] The technical solution adopted by the present invention is as follows:

[0009] A method for implementing discrete Fourier detection based on CUDA tensor cores includes the following steps:

[0010] Using the characteristics of the tensor core of NVIDIA GPU, the discrete Fourier transform DFT with a base of 10 is implemented on the CUDA architecture;

[0011] The discrete Fourier transform with a base of 10 is used for kernel fusion, multiple small kernels are fused into a large kernel, and large-size input data is decomposed and reorganized, thereby optimizing the execution of fast Fourier transform FFT operations.

[0012] Furthermore, the method utilizes the characteristics of the tensor core of the NVIDIA GPU to implement a discrete Fourier transform with a base of 10 on the CUDA architecture, including: for inputs of a specific size, mapping complex operations to the structure of the tensor core for processing, using 10*10 data to fill the tensor core fragments, and filling the remaining space with 0.

[0013] Furthermore, the kernel fusion includes: selecting a set of kernel fusions from a predefined kernel fusion set for calculation according to the dimension and size of the input data, the selected kernel fusions sequentially processing the original input data in multiple iterations, and obtaining the FFT result of the input data after completing all iterations.

[0014] Furthermore, let the scale of kernel fusion be k n , then based on k n The FFT kernel fusion process consists of two radix-10 merge processes accelerated by Tensor Core, and a Radix-k 1 / 100 merging process.

[0015] Preferably, the k n An integer multiple of 100.

[0016] Furthermore, after obtaining the FFT result of the entire input sequence, the GPU is used for parallel processing. Each thread processes the data at different positions and calculates whether the modulus value of each complex point exceeds the threshold. The statistical value is obtained by counting the number of complex numbers that exceed the threshold to determine whether the current sequence is random.

[0017] Furthermore, CUDA streams are used to implement parallel execution of multiple FFT detections.

[0018] A discrete Fourier detection implementation system based on CUDA tensor core, comprising:

[0019] The base 10 DFT module is used to implement the base 10 discrete Fourier transform DFT on the CUDA architecture using the characteristics of the tensor core of the NVIDIA GPU;

[0020] The kernel fusion module is used to perform kernel fusion using discrete Fourier transform with a base of 10, fuse multiple small kernels into a large kernel, decompose and reorganize large-size input data, and thus optimize the execution of fast Fourier transform FFT operations.

[0021] The beneficial effects of the present invention are as follows:

[0022] The present invention makes full use of the characteristics of NVIDIA GPU tensor cores and efficiently implements radix-10 DFT on the CUDA architecture. On this basis, kernel fusion technology is adopted to efficiently decompose and reorganize large-size input data by fusing multiple small kernels into a large kernel, thereby optimizing the execution of FFT operations. The present invention can provide higher performance than the prior art when processing large-scale data sets. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a discrete Fourier detection flow chart of the present invention.

[0024] Figure 2 This is a schematic diagram of CUDA stream execution.

[0025] Figure 3 It is a memory consumption comparison chart, wherein Input Size represents the number of input data points (bit), that is, the length of data to be detected, Memory represents the consumed memory, and our represents the method of the present invention. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below through specific embodiments and drawings.

[0027] 1. DFT based on Tensor Core

[0028] Tensor Cores are a special computing unit introduced in the NVIDIA Tesla Volta microarchitecture. Unlike traditional CUDA cores, they provide computing capabilities for matrices, not just traditional scalar-to-scalar operations. Tensor cores can be implemented by writing specific PTX (Parallel Thread Execution) inline assembly code. In addition, NVIDIA provides the Warp Matrix Multiply Accumulation WMMA API, which is designed to accelerate matrix operations of the form D=A·B+C through tensor cores. Tensor cores are also equipped with their own local storage space, called tensor core fragments, which allow matrices to be loaded and stored in the form of fragments, thereby enabling data to be shared between registers. Compared to traditional fused multiply-add instructions, the use of tensor cores can significantly increase throughput, that is, more floating-point operations can be completed in the same time.

[0029] At present, the standard size supported by the tensor core of the GPU is 16*16. In the present invention, a DFT scheme with a base of 10 is constructed. For inputs of a specific size, complex operations are mapped to the structure of the tensor core for processing, 10*10 data is used to fill the tensor core fragment, and the remaining space is filled with 0. When the CUDA core and the tensor core are used to perform 10*10 matrix multiplication operations respectively, the use of the tensor core can achieve an acceleration effect of about 3 times.

[0030] 2. FFT implementation based on kernel fusion

[0031] In the implementation scheme based on kernel fusion, the present invention adopts a configuration mechanism based on 10-point (Radix-10) DFT to implement FFT.

[0032] Each small-dimensional DFT (i.e., small kernel) can be fused into different large computing units (i.e., large kernels) through different combinations to form a set. This process is called kernel fusion. When the execution function is called, it selects a set of kernel fusions (one or more kernel fusions) from the pre-defined kernel fusion set for calculation based on the dimension and size of the input data (for power lengths of 10, the kernel fusion length is often 100). Subsequently, these selected kernel fusions will process the original input data in turn in multiple iterations. After all iterations are completed, the FFT result of the input data will be obtained. The process is as follows Figure 1 As shown, k 1 , k 2 , k 3 ,…k nIndicates the scale of kernel fusion, preferably an integer multiple of 100, such as 100, 200, 1000, etc.; Intra-Warp means that each Warp matrix can exchange all required elements internally through registers; Inter-Warp means exchanging data through shared memory, which requires block-level synchronization; Radix-k 1 / 100 indicates the adjustment made according to the size of different large kernels. This part is completed using CUDA cores. Data integration means that the sequences are further merged into the final k n Click FFT result.

[0033] The kernel fusion part is an important step of FFT. Taking Algorithm 1 as an example, the algorithm implements an FFT kernel fusion based on 200, that is, Figure 1 k 1 =200. It is based on N 1 Group 200 N 2 The original data of length is taken as input, and finally generates N 1 Group 200×N 2 It consists of three parts: Steps 1)-5) and steps 6)-9) represent two radix-10 (base 10) merging processes accelerated by the Tensor Core; Steps 10-13 implement a radix-2 (base 2, i.e. k 1 / 100=200 / 100=2) merging process.

[0034] In the 200-based FFT kernel fusion process, the radix-10 DFT matrix is ​​first loaded and the rotation factors are calculated. These matrices are split into 10×10 fragments and distributed to each GPU warp. Then, the matrix multiplication is performed using the tensor cores, while the element-wise multiplication is performed using the CUDA cores. Then, all these fragments are combined and N 1 ×200 FFT sequences (the length of each sequence is N 2 ) merged into N 1 ×20 FFT sequences (the length of each sequence is 10N 2 ). During the merging process, if the fragment space allows, the intermediate results will be stored in the Tensor Core fragment. Similar merging operations are continued, and the 10×20 FFT sequences are first merged into sequences of length 200, and then these sequences are further merged into the final 200-point (Radix-200) FFT results.

[0035] Algorithm 1 of the present invention, namely the Radix-200 fusion kernel algorithm, specifically comprises the following steps:

[0036] 1) Data input: N 1 Group 200×N2 The original data of length, in the format of 20N 1 ×10×N 2 The matrix

[0037] 2) Calculate the DFT matrix and rotation factor matrix of radix-10

[0038] 3) Data From 0 to 20N 1 , for the input data Each 10×10 fragment InFrag 10×10 Perform the Hadamard product with the corresponding rotation factor fragment and update the corresponding data.

[0039] 4) The updated point data is multiplied with the DFT matrix using the tensor core.

[0040] 5) Repeat steps 3) and 4) until each 10×10 segment is completed. The data format is now expressed as matrix.

[0041] 6) Calculate the rotation factor matrix

[0042] 7) Data From 0 to 2N 1 , for the input data Each 10×10 fragment InFrag 10×10 Perform the Hadamard product with the corresponding rotation factor fragment and update the corresponding data.

[0043] 8) The updated point data is matrix multiplied with the DFT matrix using the tensor core.

[0044] 9) Repeat steps 7) and 8) until each 10×10 segment is completed. The data format is now expressed as matrix.

[0045] 10) Calculate the radix-2 DFT matrix and rotation factor matrix

[0046] 11) Data From 0 to N 1 , for the input data Each 2×1 fragment of InFrag 2×1 Perform the Hadamard product with the corresponding rotation factor fragment and update the corresponding data.

[0047] 12) The updated point data and the DFT matrix are matrix multiplied using the CUDA core.

[0048] 13) Repeat steps 11) and 12) until each 2×1 segment is calculated. The calculation is now complete.

[0049] 14) Output N 1 Group 200×N 2 Length of FFT.

[0050] After obtaining the FFT results of the entire input sequence, the GPU is also used for parallel processing, with each thread processing data at different positions (e.g. thread 0 is responsible for processing data from 0 to t 1 The FFT result of point t, thread 1 is responsible for 1 -t 2 The FFT result of the complex point is used to calculate whether the modulus value of each complex point exceeds the threshold. The statistical value is obtained by counting the number of complex numbers exceeding the threshold to determine whether the current sequence is random.

[0051] 3. Implementation of multiple detections

[0052] When using TF32 format to construct complex structures for calculation, the processing length is 10 8 The data sequence of 10 ...

[0053] In the CUDA programming model, a stream defines a series of operations that are executed in a specific order on the device. CUDA technology allows us to start multiple streams and enable operations in these streams to run concurrently. Although operations in the same stream will be executed in a set order, operations between different streams can be interleaved or performed concurrently, such as Figure 2 , which can hide the time consumption caused by memory copying and improve resource utilization and processing speed.

[0054] By using multiple CUDA streams simultaneously, where each stream processes an independent batch of data, we are able to process multiple sets of FFT detections simultaneously.

[0055] In summary, the present invention proposes and implements an acceleration solution based on the GPUCUDA architecture to address the computational efficiency issues of discrete Fourier transform detection. According to the characteristics of NVIDIA tensor cores, the present invention implements radix-10DFT on this platform to fully utilize the computational potential of tensor cores. In addition, the present invention uses a kernel fusion method that generates a large kernel by fusing multiple small kernels to efficiently decompose and reorganize large-size inputs. In terms of technical implementation, the present invention uses CUDA streams to optimize the execution process, giving full play to the advantages of the CUDA architecture and improving the efficiency of data processing and the execution speed of the algorithm.

[0056] The targets of the discrete Fourier detection implementation in this invention are the NIST suite (serial) and the discrete Fourier detection using NVIDIAcuFFT, and the comparison includes speed and memory usage. Among them, the FFT using tensor cores by Durrani et al. is not included in the comparison because it cannot be applied to the detection of power-of-10 bit sequences.

[0057] 1) Time:

[0058] Using NIST-STS and different versions of GPU testing, 10 6 Bit length sequence and 10 8 The bit length sequence was tested 1000 times and the average time was recorded. In this experiment, the GPU version detection was implemented using CUDA streams.

[0059] As shown in Table 1, under a large number of inputs, due to the superior computing power of the tensor core, the present invention achieves a 1000-fold acceleration relative to NIST, and slightly exceeds the speed of cuFFT.

[0060] Table 1. Comparison of average time consumption of discrete Fourier detection

[0061]

[0062] 2) Memory usage:

[0063] according to Figure 3 According to the experimental data, the memory usage of the present invention is about 0.6 times that of the traditional DFT (executed on the CPU) and 0.8 times that of cuFFT.

[0064] Specific application scenarios of the present invention:

[0065] The method of the present invention can be used to evaluate the randomness of a sequence, and can be used in specific application scenarios such as the evaluation of a random number generator. For example, when testing the quality of random numbers generated by a random number generator, the method of the present invention can be used to replace the traditional discrete Fourier detection method, thereby achieving rapid detection and solving the problem of low detection efficiency of the traditional implementation method.

[0066] Another embodiment of the present invention provides a discrete Fourier detection implementation system based on CUDA tensor core, which includes:

[0067] The base 10 DFT module is used to implement the base 10 discrete Fourier transform DFT on the CUDA architecture using the characteristics of the tensor core of the NVIDIA GPU;

[0068] The kernel fusion module is used to perform kernel fusion using discrete Fourier transform with a base of 10, fuse multiple small kernels into a large kernel, decompose and reorganize large-size input data, and thus optimize the execution of fast Fourier transform FFT operations.

[0069] The division of the above modules is only an example. In actual applications, the above functions can be assigned to different functional modules as needed to complete all or part of the functions described in the above method. The specific working process of each module can refer to the corresponding process in the above method embodiment, which will not be repeated here.

[0070] The specific embodiments of the present invention disclosed above are intended to help understand the content of the present invention and implement it accordingly. It can be understood by those skilled in the art that various replacements, changes and modifications are possible without departing from the spirit and scope of the present invention. The present invention should not be limited to the contents disclosed in the embodiments of this specification, and the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for implementing discrete Fourier detection based on CUDA tensor cores, characterized in that: The following steps are involved: Using the characteristics of the tensor core of NVIDIA GPU, the discrete Fourier transform DFT with a base of 10 is implemented on the CUDA architecture; The discrete Fourier transform with a base of 10 is used for kernel fusion, multiple small kernels are fused into a large kernel, and large-size input data is decomposed and reorganized, thereby optimizing the execution of fast Fourier transform FFT operations.

2. The method according to claim 1, characterized in that: The method utilizes the characteristics of the tensor core of the NVIDIA GPU to implement a discrete Fourier transform with a base of 10 on the CUDA architecture, including: for inputs of a specific size, mapping complex operations to the structure of the tensor core for processing, using 10*10 data to fill the tensor core fragments, and filling the remaining space with 0.

3. The method according to claim 1, characterized in that The kernel fusion includes: selecting a set of kernel fusions from a predefined kernel fusion set for calculation according to the dimension and size of the input data, the selected kernel fusions sequentially processing the original input data in multiple iterations, and obtaining the FFT result of the input data after completing all iterations.

4. The method according to claim 1, characterized in that: Let the scale of kernel fusion be k n , then based on k n The FFT kernel fusion process includes two radix-10 merging processes accelerated by Tensor Cores, and one Radix-k1 / 100 merging process.

5. The method according to claim 4, characterized in that The k n An integer multiple of 100.

6. The method according to claim 5, characterized in that The k n is 200, taking N1 groups of 200 original data of N2 length as input, and finally generating N1 groups of FFT results of 200×N2 length.

7. The method according to claim 6, characterized in that In the 200-based FFT kernel fusion process, the radix-10 DFT matrix is ​​first loaded and the rotation factors are calculated. The DFT matrix is ​​divided into 10×10 fragments and distributed to the Warps of each GPU; then the tensor core is used for matrix multiplication, and the CUDA core is used to complete the element-level multiplication operation; then all the fragments are collected, and the N1×200 FFT sequences, each of which has a length of N2, are merged into N1×20 FFT sequences, each of which has a length of 10N2; during the merging process, the intermediate results are stored in the tensor core fragments.

8. The method according to claim 1, characterized in that: After obtaining the FFT results of the entire input sequence, the GPU is used for parallel processing. Each thread processes the data at different positions and calculates whether the modulus value of each complex point exceeds the threshold. The statistical value is obtained by counting the number of complex numbers that exceed the threshold to determine whether the current sequence is random.

9. The method according to claim 1, characterized in that: CUDA streams are used to implement parallel execution of multiple FFT detections.

10. A discrete Fourier detection implementation system based on CUDA tensor core, characterized in that: include: The base 10 DFT module is used to implement the base 10 discrete Fourier transform DFT on the CUDA architecture using the characteristics of the tensor core of the NVIDIA GPU; The kernel fusion module is used to perform kernel fusion using discrete Fourier transform with a base of 10, fuse multiple small kernels into a large kernel, decompose and reorganize large-size input data, and thus optimize the execution of fast Fourier transform FFT operations.

Images