Positioning method and device for signal in circuit design file, equipment and medium

Abstract

The invention provides a signal positioning method and device in a circuit design file, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining a signal name of a to-be-debugged signal, and according to a first corresponding relation among a source code module, a compiled code module and the signal name of the signal, obtaining a to-be-debugged signal; determining a target source code module and a target compilation code module matched with the signal name of the to-be-debugged signal, and according to a second corresponding relation between the source code file and the source code module and a third corresponding relation between the compilation code file and the compilation code module, compiling the to-be-debugged signal. Determining a target source code file and a target compilation code file matched with the target source code module, and performing grammar analysis to obtain a first line number corresponding to the to-be-debugged signal in the target source code file and a second line number corresponding to the to-be-debugged signal in the target compilation code file, the signal name, the first line number and the second line number of the to-be-debugged signal are displayed in the display area for waveform debugging of the to-be-debugged signal, and the waveform debugging efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, electronic device and computer-readable storage medium for locating a signal in a circuit design file. Background Art

[0002] Chisel (Constructing Hardware in a Scala Embedded Language) allows designers to use the features and abstractions of high-level programming languages ​​to generate hardware descriptions. For the written Chisel source code files, they need to be compiled into Verilog code files first, and then the Verilog code files are simulated by simulation tools to generate waveforms.

[0003] When debugging a waveform, the related technology can correspond the waveform to the Verilog code, so that according to the Verilog code, the Chisel source code corresponding to the Verilog code can be manually found to adjust the Chisel source code.

[0004] However, it takes a long time and is inefficient to manually search for the Chisel source code corresponding to the Verilog code. Summary of the invention

[0005] The embodiments of the present application provide a method, device, electronic device and computer-readable storage medium for locating a signal in a circuit design file to solve the problems in the related art.

[0006] In a first aspect, an embodiment of the present application provides a method for locating a signal in a circuit design file, the method comprising: Obtaining a signal name of a signal to be debugged in a circuit design file, and determining a target source code module and a target compiled code module that match the signal name of the signal to be debugged according to a first correspondence between a source code module to which the signal belongs, a compiled code module to which the signal belongs, and the signal name of the signal; Determine a target source code file that matches the target source code module according to a second correspondence between source code files and source code modules, and determine a target compiled code file that matches the target compiled code module according to a third correspondence between compiled code files and compiled code modules; Performing syntax analysis on the target source code file and the target compiled code file respectively to obtain a first line number corresponding to the signal to be debugged in the target source code file and a second line number corresponding to the signal to be debugged in the target compiled code file; The signal name, the first line number, and the second line number of the signal to be debugged are displayed in the display area to facilitate waveform debugging of the signal to be debugged.

[0007] In a second aspect, an embodiment of the present application provides a device for locating a signal in a circuit design file, the device comprising: A first determination module is used to obtain a signal name of a signal to be debugged in a circuit design file, and determine a target source code module and a target compiled code module that match the signal name of the signal to be debugged according to a first correspondence between a source code module to which the signal belongs, a compiled code module to which the signal belongs, and the signal name of the signal; a second determining module, configured to determine a target source code file matching the target source code module according to a second correspondence between source code files and source code modules, and to determine a target compiled code file matching the target compiled code module according to a third correspondence between compiled code files and compiled code modules; A first syntax analysis module is used to perform syntax analysis on the target source code file and the target compiled code file respectively to obtain a first line number corresponding to the signal to be debugged in the target source code file and a second line number corresponding to the signal to be debugged in the target compiled code file; The display module is used to display the signal name, the first line number, and the second line number of the signal to be debugged in a display area to facilitate waveform debugging of the signal to be debugged.

[0008] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement the method of the first aspect.

[0009] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0010] In the embodiment of the present application, according to the first correspondence between the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal, the target source code module and the target compiled code module that match the signal name of the signal to be debugged are determined, and according to the second correspondence between the source code file and the source code module, the target source code file that matches the target source code module is determined, and according to the third correspondence between the compiled code file and the compiled code module, the target compiled code file that matches the target compiled code module is obtained, thereby obtaining the target source code file and the target compiled code file to which the signal to be debugged belongs. Then, the target source code file and the target compiled code file are parsed grammatically respectively to obtain the first line number corresponding to the signal to be debugged in the target source code file and the second line number corresponding to the signal to be debugged in the target compiled code file, and the signal name, the first line number, and the second line number of the signal to be debugged are displayed in the display area for waveform debugging of the signal to be debugged. By intuitively displaying the signal to be debugged in the source code file and the signal to be debugged in the compiled code, there is no need to manually search for the source code corresponding to the compiled code, which can greatly improve the efficiency of waveform debugging.

[0011] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 It is a flowchart of the steps of a method for locating a signal in a circuit design file provided in an embodiment of the present application; Figure 2 It is a display interface diagram provided in an embodiment of the present application; Figure 3 It is a flowchart of the specific steps of a method for locating a signal in a circuit design file provided in an embodiment of the present application; Figure 4 It is a flowchart of steps for displaying a signal to be debugged provided by an embodiment of the present application; Figure 5 It is a flowchart of the steps of adding a signal to be debugged into a waveform region provided by an embodiment of the present application; Figure 6It is a block diagram of a signal positioning device in a circuit design file provided in an embodiment of the present application; Figure 7 is a block diagram of an electronic device provided in an embodiment of the present application; Figure 8 It is a block diagram of another electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0015] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0016] Figure 1 is a flowchart of a method for locating a signal in a circuit design file provided by an embodiment of the present application, such as Figure 1 As shown, the method may include: Step 101, obtaining the signal name of the signal to be debugged in the circuit design file, and determining the target source code module and the target compiled code module that match the signal name of the signal to be debugged according to a first correspondence between the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal.

[0017] For example, in digital circuit design and hardware description language, signals are the basic elements used to transfer data between modules. Signals can represent various types of data, including but not limited to bits, vectors, registers, etc. Signals transmit data within and between modules and are the basis for building complex digital systems.

[0018] For example, the source code can be written in Chisel language, which is used to describe hardware construction. Chisel is an open source hardware construction language released by Berkeley University. It is built on the Scala language and is an application of Scala's domain-specific language. It has a highly parameterized generator and can support advanced hardware design. The advantage of using Chisel to write code is that it can more conveniently implement complex hardware design. At the same time, Scala's pattern matching and function combination characteristics enable Chisel to easily reuse code to improve development efficiency. The compiled code can be written in Verilog language. The register transfer level (RTL) written in Chisel is an abstract level in hardware design, between gate-level description and high-level hardware description language (such as Verilog). At the RTL level, designers can define registers, combinational logic, state machines, etc. without going into the specific gate-level implementation details. It is usually necessary to compile files written in Chisel language into Verilog files, so that simulation tools can simulate Verilog files to generate waveforms.

[0019] For example, the first correspondence includes: the correspondence between the source code module to which the signal belongs and the signal name of the signal, and the correspondence between the compiled code module to which the signal belongs and the signal name of the signal. The present application determines the target source code module that matches the signal name of the signal to be debugged based on the correspondence between the source code module to which the signal belongs and the signal name of the signal. According to the correspondence between the compiled code module to which the signal belongs and the signal name of the signal, the target compiled code module that matches the signal name of the signal to be debugged is determined.

[0020] For example, a source code module can be a source code module name, and can also include: a source code module name and a source code instantiation name. A compiled code module can be a compiled code module name, and can also include: a compiled code module name and a compiled code instantiation name. Among them, the module name is the name used when defining a module. It is an identifier used to describe the function and interface of the module. The same module name can be reused in multiple places. The instantiation name is the name assigned to a defined module when instantiating it in the top-level module or other modules. It is an identifier. Different instantiation names can be assigned to the same module in the same design. It is used to distinguish different instances of the same module and uniquely identify each instance of the module during simulation and debugging.

[0021] Step 102, determining a target source code file matching the target source code module according to a second correspondence between source code files and source code modules, and determining a target compiled code file matching the target compiled code module according to a third correspondence between compiled code files and compiled code modules.

[0022] For example, taking the case where the source code module includes: a source code module name and a source code instantiation name, and the source code file is a source code file name, the second correspondence can be a correspondence between the module name and the instantiation name and the source code file name. Specifically, a syntax analysis tool is used to perform syntax analysis on the source code file to obtain all module names and instantiation names in the source code file. After obtaining all module names and instantiation names in the source code file, a second correspondence between the module name and the instantiation name and the source code file name is established. So that after obtaining the module name of the signal to be debugged, the target source code file name is obtained according to the second correspondence between the module name and the instantiation name and the source code file name, thereby finding the target source code file according to the target source code file name.

[0023] For example, after using a syntax analysis tool to perform syntax analysis on the source code file and obtaining all the module names and instantiation names in the source code file, a mapping relationship of the signal hierarchy of the source code file is generated. Among them, the signal hierarchy refers to the organization method of signals in modules and hierarchical designs, and the hierarchical path is used to uniquely identify signals or modules in the hierarchy. The path usually consists of a module instantiation name and a signal name, separated by .. For example, the instantiation name of the top-level module is top, top instantiates counter, and there is a signal clk in counter. Then the hierarchy of the signal clk is top.counter.clk, which is unique in the entire waveform. By using top.counter as the key of the map and the value as the Verilog file name, a mapping relationship between top.counter and Verilog is established, which can be easily analyzed.

[0024] For example, taking the compiled code module including: the compiled code module name and the compiled code instantiation name, and the compiled code file being the compiled code file name as an example, the third correspondence can be the correspondence between the module name and the instantiation name and the compiled code file name. Specifically, a syntax analysis tool is used to perform syntax analysis on the compiled code file to obtain all the module names and instantiation names in the compiled code file. After obtaining all the module names and instantiation names in the compiled code file, a third correspondence between the module name and the instantiation name and the compiled code file name is established. So that after obtaining the module name of the signal to be debugged, the target compiled code file name is obtained according to the third correspondence between the module name and the instantiation name and the compiled code file name, thereby finding the target compiled code file according to the target compiled code file name.

[0025] For example, after using the syntax analysis tool to perform syntax analysis on the compiled code file and obtaining all the module names and instantiation names in the compiled code file, the mapping relationship of the signal hierarchy of the compiled code file is generated. For example, the instantiation name of the top-level module is top, top instantiates counter, and counter has a signal clk, then the hierarchy of the signal clk is top.counter.clk, which is unique in the entire waveform. By using top.counter as the key of the map and the value as the file name of Chisel, a mapping relationship between top.counter and Chisel is established, which can facilitate analysis.

[0026] Step 103, performing syntax analysis on the target source code file and the target compiled code file respectively to obtain a first line number corresponding to the signal to be debugged in the target source code file and a second line number corresponding to the signal to be debugged in the target compiled code file.

[0027] For example, syntax analysis can be to obtain the line number of the signal according to the syntax tree, which usually requires a visitor mode or a listener mode combined with a syntax analysis tool to traverse the syntax tree and extract the required line number information. For example, the syntax analysis tool can be an ANTLR tool.

[0028] For example, the syntax analysis process includes: generating a syntax tree, defining syntax rules, traversing the syntax tree, and extracting variable names and line numbers. In the syntax tree generation step, first, the ANTLR syntax analysis tool is used to generate a lexical analyzer and a syntax analyzer according to the syntax rules of the language.

[0029] Then, the code is input into the generated parser to generate a syntax tree. In defining syntax rules, in a syntax rule file (such as a .g4 file), define the syntax rules for variable declaration. For example, variableDeclaration: typeIDENTIFIER ';';, where type represents the variable type and IDENTIFIER represents the variable name. In traversing the syntax tree, by implementing the visitor interface, traverse the syntax tree and extract variable information. By implementing the listener interface, trigger an event when entering or exiting a specific syntax node. In extracting variable names and line numbers, while traversing the syntax tree, identify the variable declaration node and extract the variable name and line number.

[0030] Step 104: display the signal name, the first line number, and the second line number of the signal to be debugged in a display area to facilitate waveform debugging of the signal to be debugged.

[0031] For example, after obtaining the first line number corresponding to the signal to be debugged in the target source code file and the second line number corresponding to the target compiled code file, the cursor will automatically jump to the first line number and the second line number corresponding to the signal, and the corresponding first line number and the second line number will be highlighted, that is, the signal name of the signal to be debugged will be highlighted at the first line number and the second line number. Figure 2 The highlighted part is represented by a shaded box, and the shaded box part is the signal A to be debugged.

[0032] In summary, in the embodiment of the present application, according to the first correspondence between the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal, the target source code module and the target compiled code module that match the signal name of the signal to be debugged are determined, and according to the second correspondence between the source code file and the source code module, the target source code file that matches the target source code module is determined, and according to the third correspondence between the compiled code file and the compiled code module, the target compiled code file that matches the target compiled code module is obtained, thereby obtaining the target source code file and the target compiled code file to which the signal to be debugged belongs. Then, the target source code file and the target compiled code file are parsed grammatically respectively to obtain the first line number corresponding to the signal to be debugged in the target source code file and the second line number corresponding to the signal to be debugged in the target compiled code file, and the signal name, the first line number, and the second line number of the signal to be debugged are displayed in the display area for waveform debugging of the signal to be debugged. By intuitively displaying the signal to be debugged in the source code file and the signal to be debugged in the compiled code, there is no need to manually search for the source code corresponding to the compiled code, which can greatly improve the efficiency of waveform debugging.

[0033] Figure 3 is a flowchart of the specific steps of a method for locating a signal in a circuit design file provided in an embodiment of the present application, such as Figure 3 As shown, the method may include: Step 201, obtaining the signal name of the signal to be debugged in the circuit design file, and determining the target source code module and the target compiled code module that match the signal name of the signal to be debugged according to a first correspondence between the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal.

[0034] This step may be specifically referred to as the above step 101, and will not be described in detail here.

[0035] Step 202, determining a target source code file matching the target source code module according to a second correspondence between source code files and source code modules, and determining a target compiled code file matching the target compiled code module according to a third correspondence between compiled code files and compiled code modules.

[0036] This step may be specifically referred to as the above step 102, and will not be described in detail here.

[0037] Step 203, perform syntax analysis on the target source code file and the target compiled code file respectively to obtain the first line number corresponding to the signal to be debugged in the target source code file and the second line number corresponding to the signal to be debugged in the target compiled code file.

[0038] This step may be specifically referred to as the above step 103, and will not be described in detail here.

[0039] Step 203 may specifically include: Sub-step 2031, obtaining a first syntax tree corresponding to the first design language of the target source code file and a second syntax tree corresponding to the second design language of the target compiled code file; Sub-step 2032: finding the first position of the node corresponding to the signal to be debugged in the first syntax tree, and determining the first line number according to the first position; Sub-step 2033: finding the second position of the node corresponding to the signal to be debugged in the second syntax tree, and obtaining the second line number according to the second position.

[0040] For sub-step 2031-sub-step 2033, the first design language can be Chisel language, and the second design language can be Verilog language. For the generation process of the second syntax tree, first create a VerilogLexer object, then decompose the input Verilog code into a series of lexical units, and finally parse the lexical unit stream and generate a second syntax tree. The generation of the first syntax tree is similar to the generation of the second syntax tree, and will not be repeated. Specifically, a syntax analysis tool, such as ANTLR, is used to generate a lexical analyzer and a syntax analyzer according to the grammatical rules of the language, and the source code is input into the generated lexical analyzer and syntax analyzer to parse the source code and generate a syntax tree.

[0041] For example, after generating the first syntax tree and the second syntax tree, the first line number and the second line number can be obtained according to the first syntax tree and the second syntax tree. Specifically, taking obtaining the first line number according to the first syntax tree as an example, it is usually necessary to combine the syntax analysis tool and the visitor pattern or the listener pattern to traverse the syntax tree and extract the required information. The visitor interface is implemented through the visitor pattern to traverse the syntax tree and extract variable information. The listener interface is implemented through the listener pattern to trigger an event when entering or exiting a specific syntax node. When traversing the syntax tree, the variable declaration node is identified, and the variable name and line number are extracted.

[0042] Step 204, open the target source code file in the first display area, automatically jump to the position of the first line number, and highlight the signal name of the signal to be debugged at the position of the first line number to facilitate waveform debugging of the signal to be debugged.

[0043] For example, after the server obtains the target source code file and the first line number of the signal to be debugged, it sends the target source code file and the first line number to the client. After the client receives the response from the server, it displays the Chisel code, and the cursor automatically jumps to the position of the first line number corresponding to the signal. The Chisel code will highlight the position of the first line number of the response, that is, the signal name of the signal to be debugged is highlighted at the position of the first line number. Figure 2 , the first display area can be located at Figure 2 The lower left corner is used to display the source code. Figure 2 The shaded box represents the highlighted part, and the shaded box part is the corresponding signal A in the Chisel source code.

[0044] For example, the upper area of ​​the first display area has a search button 21. In response to a click operation on the search button 21 in the upper area of ​​the first display area, after the signal name of the signal to be queried is entered in the search box corresponding to the first display area, the source code file to which the signal to be queried belongs is opened in the first display area, and the file automatically jumps to the location of the signal to be queried, and the signal name of the signal to be debugged and the context content of the signal to be debugged are highlighted at the location of the signal to be queried.

[0045] Step 205, opening the target compiled code file in the second display area, automatically jumping to the second line number position, and highlighting the signal name of the signal to be debugged at the second line number position to facilitate waveform debugging of the signal to be debugged.

[0046] For example, after the server obtains the target source code file and the second line number of the signal to be debugged, it sends the target source code file and the second line number to the client. After the client receives the response from the server, it displays the Verilog code, and the cursor automatically jumps to the position of the second line number corresponding to the signal. The Verilog code will highlight the position of the second line number of the response, that is, the signal name of the signal to be debugged is highlighted at the position of the second line number. Figure 2 , the second display area can be located at Figure 2 The lower right corner of the figure is used to display the compiled code. The highlighted part is represented by a shaded box, and the shaded box part is the corresponding signal A in the Verilog compiled code.

[0047] For example, the upper area of ​​the second display area has a search button 21. In response to a click operation on the search button 21 in the upper area of ​​the second display area, after the signal name of the signal to be queried is entered in the search box corresponding to the second display area, the compiled code file to which the signal to be queried belongs is opened in the second display area, and the position of the signal to be queried is automatically jumped to, and the signal name of the signal to be debugged and the context content of the signal to be debugged are highlighted at the position where the signal to be queried is located.

[0048] Optionally, the method further includes: Step 206, obtaining a source code file and a compiled code file; the compiled code file is generated by compiling the source code in the source code file; Step 207, performing syntax analysis on the source code file and the compiled code file respectively to obtain a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file; Step 208, establishing a first correspondence between the source code module, the compiled code module, and the signal name of the signal; Step 209: establishing a second correspondence between the source code file and the source code module, and a third correspondence between the compiled code file and the compiled code module.

[0049] For step 206-step 209, the source code file can be a Chisel file, and the compiled code file can be a Verilog file. The Verilog file is obtained by converting the code in the Chisel file. There are many tools for syntax analysis, including but not limited to developing your own code for parsing, using tools ANTLR, bison, flex, pyparsing, etc., and ANTLR is used as an example for a simple explanation. Create an ANTLR grammar file, i.e., a g4 file, define the grammatical structure of the language to be parsed, use the ANTLR tool to generate the parser code, which will be used to parse the Scala code and build an abstract syntax tree, write code to traverse the generated syntax tree, extract module information, signal names of signals, instantiation information, etc.

[0050] For example, after generating the source code module and the compiled code module, a first correspondence between the source code module, the compiled code module, and the signal name, a second correspondence between the source code file and the source code module, and a third correspondence between the compiled code file and the compiled code module are established, so that according to the first, second, and third correspondences, the target source code file and the target compiled code file to which the signal to be debugged belongs are obtained.

[0051] Optionally, step 206 may specifically include: Sub-step 2061, obtaining the path of the source code file and the path of the compiled code file; Sub-step 2062, finding the source code file according to the path of the source code file, and finding the compiled code file according to the path of the compiled code file.

[0052] For sub-steps 2061 and 2062, Web applications usually adopt a browser / server (B / S) architecture. In this architecture, users access applications through browsers, and servers handle all business logic and data storage. This architecture makes Web applications have good scalability and maintainability. If a web application is used, the waveform is displayed on the browser side, and the browser can send an http request to the server. The server uses a programming language to perform syntax analysis through a syntax analysis tool based on the parameters carried by the http request to obtain the path of the source code file and the path of the compiled code file.

[0053] Specifically, the HTTP request is used to obtain the source code file and the compiled code file. The HTTP request may include: a request parameter filelist and a request parameter chiselfilelist. Among them, the request parameter filelist includes the path of all compiled code files, and the request parameter chiselfilelist includes the path of all source code files. The HTTP request may also include: the signal name of the signal to be debugged. After obtaining the path of the source code file and the path of the compiled code file, the source code file and the compiled code file are found according to the path of the source code file and the path of the compiled code file.

[0054] Ordinary applications usually adopt the client / server (C / S) architecture. Users run applications directly on local devices. The server mainly handles data storage and some business logic and can run offline. Applications can be developed in languages ​​such as C++ and Rust. The interface and services are completed in one application. When the user selects a signal to be debugged, the corresponding function can be called in the application, and the path of the source code file and the path of the compiled code file can be obtained through syntax analysis tools.

[0055] Optionally, step 207 may specifically include: Sub-step 2071, obtaining a first syntax tree corresponding to the first design language of the target source code file and a second syntax tree corresponding to the second design language of the target compiled code file; Sub-step 2072, finding the module node and the file node to which the node corresponding to the signal to be debugged belongs in the first syntax tree, and using the module corresponding to the module node as the source code module, and using the file corresponding to the file node as the source code file; Sub-step 2073, in the second syntax tree, find the module node and the file node to which the node corresponding to the signal to be debugged belongs, and use the module corresponding to the module node as the compiled code module, and use the file corresponding to the file node as the compiled code file.

[0056] For sub-steps 2071 to 2073, the first design language may be Chisel, and the second design language may be Verilog. For the generation process of the syntax tree, first create a VerilogLexer object, then decompose the input Verilog code into a series of lexical units, and finally parse the lexical unit stream and generate a second syntax tree. Specifically, a syntax analysis tool, such as ANTLR, is used to generate a lexical analyzer and a syntax analyzer according to the grammatical rules of the language, and the source code is input into the generated lexical analyzer and syntax analyzer to parse the source code and generate a syntax tree.

[0057] For example, after generating the first syntax tree and the second syntax tree, the first syntax tree and the second syntax tree are traversed respectively to obtain the modules corresponding to the first syntax tree and the second syntax tree respectively. Specifically, a custom visitor class can be used to traverse the modules corresponding to the first syntax tree and the modules corresponding to the second syntax tree respectively through the ANTLR tool to obtain the module node and file node to which the node corresponding to the signal to be debugged in the first syntax tree belongs, and the module node and file node to which the node corresponding to the signal to be debugged in the second syntax tree belongs. Among them, the module node may include module information and instantiation information. The module information and instantiation information corresponding to the module node in the first syntax tree are used as the source code module, and the file corresponding to the file node is used as the source code file, and the module information and instantiation information corresponding to the module node in the second syntax tree are used as the compiled code module, and the file corresponding to the file node is used as the compiled code file.

[0058] Optionally, step 207 may further include: Sub-step 2074, obtaining a first temporary file corresponding to the source code file and a second temporary file corresponding to the compiled code file; the first temporary file is a file generated by replacing the hyperparameter value of the source code file; the second temporary file is a file generated by replacing the hyperparameter value of the compiled code file; Sub-step 2075, performing syntax analysis on the first temporary file to obtain the source code module; Sub-step 2076, performing syntax analysis on the second temporary file to obtain the compiled code module.

[0059] For sub-steps 2074 to 2076, after obtaining the source code file and the compiled code file, the source code file and the compiled code file are first preprocessed according to the include information and define information to generate a first temporary file and a second temporary file. For example, there are two files, top.v file and defines.vh file. Among them, the defines.vh file defines some macros. The preprocessing is to search in top.v according to the included files and replace the macros with the real values ​​of defines.vh. For example, the macros defined in the defines.vh file can be as follows: / / defines.vh `define CLK_PERIOD 10 `define RESET_HOLD_TIME 10 `define SIMULATION_TIME 100 The contents of the top.v file can include: top.v / / top.v `include "defines.vh" For example, the temporary file is divided into modules, and for each module, all module names, instantiation names, and file names are parsed and cached according to the syntax analysis. According to the chiselfilelist, all Scala files are parsed, each class is parsed, all module names, instantiation names, and file names are parsed, and cached. According to the signal name, it is divided according to the signal hierarchy, and the module to which the signal belongs is found. The .v or .sv file corresponding to the module is searched in the cache, and the syntax analysis is performed to parse the file name and line number corresponding to the signal. According to the signal hierarchy, the corresponding class is found, and the Chisel file is parsed to obtain the file and line number corresponding to the signal name, and the Chisel file and Verilog file are returned to the front end.

[0060] Optionally, the method further includes: Step 210, according to a preset configuration, determining a target signal among all signals as a signal to be debugged; Step 211: in response to a selection operation on a signal except a target signal among all signals, the selected signal is used as a new signal to be debugged, and the new signal to be debugged is displayed in a display area.

[0061] For step 210-step 211, the preset configuration includes the signal that has been displayed in the display area, and the displayed signal is determined as the signal to be debugged. Taking the preset configuration including signal A and signal B as an example, if you want to display signal C, then signal C is used as a new signal to be debugged, and double-clicked to display signal C in the display area. When viewing the source code of Chisel, the present application does not need to manually search for signals in Chisel files or Verilog files to add signals to the display area.

[0062] Optionally, the display area includes a signal name area, a signal value display area and a waveform display area; the signal name area displays the signal names of each existing signal in the circuit design file; step 211 may specifically include: Sub-step 2111, selecting a signal from the signal name area as a new signal to be debugged; Sub-step 2112, displaying the signal name of the new signal to be debugged and the value of the new signal to be debugged in the signal value display area, and displaying the waveform of the new signal to be debugged in the waveform display area.

[0063] For sub-steps 2111 and 2112, Figure 2 As shown, Figure 2 It includes: signal name area, signal value display area and waveform display area. The signal value display area displays the value of the signal, and the waveform display area displays the value of the signal at different times. The graph composed of these values ​​is the waveform of the signal. Select a signal in the signal name area as a new signal to be debugged. You can double-click the new signal to be debugged to add it to the waveform display area. The value of the new signal to be debugged selected at the specified time can be displayed in the signal value display area. When it is necessary to add a signal in the Chisel source code to the waveform, the signal hierarchy corresponding to the signal is obtained through syntax parsing, and then the signal is added to the waveform. At the same time, the file and line number of the Verilog source code corresponding to the hierarchy are searched according to the signal hierarchy. The waveform display area interface will jump to the Verilog source code file and line number and highlight it. When it is necessary to add a signal in the Verilog source file to the waveform, the signal hierarchy corresponding to the signal is obtained through syntax parsing, and then the signal is added to the waveform. The Chisel source code file and line number are searched according to the signal hierarchy. The waveform display area interface will jump to the corresponding Chisel source code file and line number and highlight it.

[0064] For example, the waveform file records the changes of each signal during the simulation process, which needs to be debugged and verified through the waveform. Add the signal of interest to the waveform tool to check whether the signal changes are as expected.

[0065] Optionally, the method further includes: Step 212, if the signal to be debugged is an intermediate variable, find the signal assigned to the signal to be debugged from all signals according to the assignment relationship, determine the signal assigned to the signal to be debugged as the signal to be debugged, and enter the step of obtaining the signal name of the signal to be debugged in the circuit design file.

[0066] For example, when the intermediate variable is generated from Chisel code to Verilog code, the variable name in the Verilog code does not exist in the Chisel code, and it is not a name converted according to a certain rule, but an additional variable generated during the conversion process. If the signal is an intermediate variable generated by Verilog, find the target variable assigned by the variable according to the syntax analysis, and then search for the Chisel file. If it is not found, the process is repeated.

[0067] In summary, in the embodiment of the present application, according to the first correspondence between the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal, the target source code module and the target compiled code module that match the signal name of the signal to be debugged are determined, and according to the second correspondence between the source code file and the source code module, the target source code file that matches the target source code module is determined, and according to the third correspondence between the compiled code file and the compiled code module, the target compiled code file that matches the target compiled code module is obtained, thereby obtaining the target source code file and the target compiled code file to which the signal to be debugged belongs. Then, the target source code file and the target compiled code file are parsed grammatically respectively to obtain the first line number corresponding to the signal to be debugged in the target source code file and the second line number corresponding to the signal to be debugged in the target compiled code file, and the signal name, the first line number, and the second line number of the signal to be debugged are displayed in the display area for waveform debugging of the signal to be debugged. By intuitively displaying the signal to be debugged in the source code file and the signal to be debugged in the compiled code, there is no need to manually search for the source code corresponding to the compiled code, which can greatly improve the efficiency of waveform debugging.

[0068] Figure 4 This is a flowchart of a step of displaying a signal to be debugged provided by an embodiment of the present application, referring to Figure 4 , this step may specifically include: Step S1, loading a waveform file into the display area. The format of the waveform file can be vcd format, fst format, or other formats, which are not limited in this application.

[0069] Step S2: Select the signal to be debugged and obtain the source code file and the compiled code file.

[0070] Step S3: preprocess and grammatically analyze the source code file and the compiled code file to obtain the signal hierarchy structures corresponding to the source code file and the compiled code file respectively.

[0071] Step S4: Obtain the target compiled file code and the second line number corresponding to the signal to be debugged according to the signal hierarchy structure of the compiled code file.

[0072] Step S5, determine whether the signal to be debugged is an intermediate signal, if it is an intermediate signal, jump to step S6, otherwise, jump to step S9.

[0073] Step S6: according to the syntax analysis, find the signal assigned by the signal to be debugged.

[0074] Step S7, determine whether the signal to be debugged is found, if found, jump to step S8, otherwise, jump to step S6.

[0075] Step S8: Determine the signal assigned with the signal to be debugged as the signal to be debugged.

[0076] Step S9: Obtain the target source file code and the first line number corresponding to the signal to be debugged according to the signal hierarchy structure of the source code file.

[0077] Step S10, open the target source code file in the display area, automatically jump to the position of the first line number, highlight the signal name of the signal to be debugged at the position of the first line number, and open the target compiled code file, automatically jump to the position of the second line number, and highlight the signal name of the signal to be debugged at the position of the second line number.

[0078] Figure 5 This is a flowchart of the steps of adding a signal to be debugged to a waveform region provided by an embodiment of the present application, referring to Figure 5 , this step may specifically include: Step M1, obtaining the signal to be debugged in the source code file.

[0079] Step M2: perform syntax analysis on the source code file to obtain the hierarchical structure of the signal to be debugged.

[0080] Step M3: Obtain the compiled code module corresponding to the signal to be debugged according to the hierarchical structure of the signal to be debugged, and perform syntax analysis on the compiled code file to which the compiled code module belongs to obtain the second line number.

[0081] Step M4: add the signal to be debugged to the waveform, jump to the position of the second line number, and display the signal name and the second line number of the signal to be debugged.

[0082] In the embodiment of the present application, according to the first correspondence between the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal, the target source code module and the target compiled code module that match the signal name of the signal to be debugged are determined, and according to the second correspondence between the source code file and the source code module, the target source code file that matches the target source code module is determined, and according to the third correspondence between the compiled code file and the compiled code module, the target compiled code file that matches the target compiled code module is obtained, thereby obtaining the target source code file and the target compiled code file to which the signal to be debugged belongs. Then, the target source code file and the target compiled code file are parsed grammatically respectively to obtain the first line number corresponding to the signal to be debugged in the target source code file and the second line number corresponding to the signal to be debugged in the target compiled code file, and the signal name, the first line number, and the second line number of the signal to be debugged are displayed in the display area for waveform debugging of the signal to be debugged. By intuitively displaying the signal to be debugged in the source code file and the signal to be debugged in the compiled code, there is no need to manually search for the source code corresponding to the compiled code, which can greatly improve the efficiency of waveform debugging.

[0083] Figure 6 is a block diagram of a signal positioning device 30 in a circuit design file provided in an embodiment of the present application, the device comprising: A first determination module 301 is used to obtain a signal name of a signal to be debugged in a circuit design file, and determine a target source code module and a target compiled code module that match the signal name of the signal to be debugged according to a first correspondence between a source code module to which the signal belongs, a compiled code module to which the signal belongs, and the signal name of the signal; A second determining module 302 is used to determine a target source code file that matches the target source code module according to a second correspondence between source code files and source code modules, and to determine a target compiled code file that matches the target compiled code module according to a third correspondence between compiled code files and compiled code modules; A first syntax analysis module 303 is used to perform syntax analysis on the target source code file and the target compiled code file respectively to obtain a first line number corresponding to the signal to be debugged in the target source code file and a second line number corresponding to the signal to be debugged in the target compiled code file; The display module 304 is used to display the signal name, the first line number, and the second line number of the signal to be debugged in the display area, so as to facilitate waveform debugging of the signal to be debugged.

[0084] Optionally, the first syntax analysis module includes: A first acquisition submodule, configured to acquire a first syntax tree corresponding to a first design language of the target source code file and a second syntax tree corresponding to a second design language of the target compiled code file; A first determination submodule is used to find a first position of a node corresponding to the signal to be debugged in the first syntax tree, and determine the first row number according to the first position; The second determining submodule is used to find the second position of the node corresponding to the signal to be debugged in the second syntax tree, and determine the second line number according to the second position.

[0085] Optionally, the display area includes a first display area and a second display area; and the display module includes: A first display submodule, used for opening the target source code file in the first display area, automatically jumping to the position of the first line number, and highlighting the signal name of the signal to be debugged at the position of the first line number; The second display submodule is used to open the target compiled code file in the second display area, automatically jump to the position of the second line number, and highlight the signal name of the signal to be debugged at the position of the second line number.

[0086] Optionally, the device further comprises: An acquisition module, used to acquire a source code file and a compiled code file; the compiled code file is generated by compiling the source code in the source code file; A second syntax analysis module, used to perform syntax analysis on the source code file and the compiled code file respectively, to obtain a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file; A first establishing module, used to establish a first correspondence between the source code module, the compiled code module, and the signal name of the signal; The second establishing module is used to establish a second corresponding relationship between the source code file and the source code module, and a third corresponding relationship between the compiled code file and the compiled code module.

[0087] Optionally, the second syntax analysis module includes: A second acquisition submodule, used to acquire a first syntax tree corresponding to the first design language of the target source code file and a second syntax tree corresponding to the second design language of the target compiled code file; A third determination submodule is used to find, in the first syntax tree, a module node and a file node to which the node corresponding to the signal to be debugged belongs, and use the module corresponding to the module node as the source code module, and use the file corresponding to the file node as the source code file; The fourth determination submodule is used to find the module node and file node to which the node corresponding to the signal to be debugged belongs in the second syntax tree, and use the module corresponding to the module node as the compiled code module and the file corresponding to the file node as the compiled code file.

[0088] Optionally, the device further comprises: A third determination module is used to determine the target signal among all signals as the signal to be debugged according to a preset configuration; The selection module is used for responding to the selection operation of the signal except the target signal among all the signals, taking the selected signal as a new signal to be debugged, and displaying the new signal to be debugged in the display area.

[0089] Optionally, the display area includes a signal name area, a signal value display area and a waveform display area; the signal name area displays the signal names of each existing signal in the circuit design file; the selection module includes: A selection submodule, used for selecting a signal from the signal name area as a new signal to be debugged; The third display submodule is used to display the signal name of the new signal to be debugged and the value of the new signal to be debugged in the signal value display area, and to display the waveform of the new signal to be debugged in the waveform display area.

[0090] Optionally, the acquisition module includes: The third acquisition submodule is used to obtain the path of the source code file and the path of the compiled code file; The fifth determining submodule is used to find the source code file according to the path of the source code file, and to find the compiled code file according to the path of the compiled code file.

[0091] Optionally, the device further comprises: The sixth determination submodule is used to find the signal assigned to the signal to be debugged from all signals according to the assignment relationship if the signal to be debugged is an intermediate variable, determine the signal assigned to the signal to be debugged as the signal to be debugged, and enter the step of obtaining the signal name of the signal to be debugged in the circuit design file.

[0092] Optionally, the second syntax analysis module includes: A fourth acquisition submodule, used to acquire a first temporary file corresponding to the source code file, and a second temporary file corresponding to the compiled code file; the first temporary file is a file generated by replacing the hyperparameter value of the source code file; the second temporary file is a file generated by replacing the hyperparameter value of the compiled code file; A seventh determination submodule, configured to perform syntax analysis on the first temporary file to obtain the source code module; An eighth determination submodule is used to perform syntax analysis on the second temporary file to obtain the compiled code module.

[0093] In summary, in the embodiment of the present application, according to the first correspondence between the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal, the target source code module and the target compiled code module that match the signal name of the signal to be debugged are determined, and according to the second correspondence between the source code file and the source code module, the target source code file that matches the target source code module is determined, and according to the third correspondence between the compiled code file and the compiled code module, the target compiled code file that matches the target compiled code module is obtained, thereby obtaining the target source code file and the target compiled code file to which the signal to be debugged belongs. Then, the target source code file and the target compiled code file are parsed grammatically respectively to obtain the first line number corresponding to the signal to be debugged in the target source code file and the second line number corresponding to the signal to be debugged in the target compiled code file, and the signal name, the first line number, and the second line number of the signal to be debugged are displayed in the display area for waveform debugging of the signal to be debugged. By intuitively displaying the signal to be debugged in the source code file and the signal to be debugged in the compiled code, there is no need to manually search for the source code corresponding to the compiled code, which can greatly improve the efficiency of waveform debugging.

[0094] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0095] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0096] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0097] An embodiment of the present application provides a device for locating signals in a circuit design file, comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to include methods for performing one or more of the methods described in the above-mentioned embodiments.

[0098] Figure 74 is a block diagram of an electronic device 400 provided in an embodiment of the present application. For example, the electronic device 400 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0099] Reference Figure 7 , the electronic device 400 may include one or more of the following components: a processing component 402 , a memory 404 , a power component 406 , a multimedia component 408 , an audio component 410 , an input / output (I / O) interface 412 , a sensor component 414 , and a communication component 416 .

[0100] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 402 may include one or more modules to facilitate the interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate the interaction between the multimedia component 408 and the processing component 402.

[0101] The memory 404 is used to store various types of data to support the operation of the electronic device 400. Examples of such data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, multimedia, etc. The memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0102] The power supply component 406 provides power to the various components of the electronic device 400. The power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 400.

[0103] The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front camera and / or a rear camera. When the electronic device 400 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0104] The audio component 410 is used to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC), and when the electronic device 400 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 404 or sent via the communication component 416. In some embodiments, the audio component 410 also includes a speaker for outputting audio signals.

[0105] The input / output interface 412 provides an interface between the processing component 402 and the peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0106] The sensor assembly 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor assembly 414 can detect the open / closed state of the electronic device 400, the relative positioning of the components, such as the display and keypad of the electronic device 400, and the sensor assembly 414 can also detect the position change of the electronic device 400 or a component of the electronic device 400, the presence or absence of contact between the user and the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and the temperature change of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0107] The communication component 416 is used to facilitate wired or wireless communication between the electronic device 400 and other devices. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 416 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 416 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0108] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of the present application.

[0109] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, and the instructions can be executed by a processor 420 of an electronic device 400 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0110] Figure 8 is a block diagram of another electronic device 500 provided in an embodiment of the present application. For example, the electronic device 500 may be provided as a server. Figure 8 , the electronic device 500 includes a processing component 522, which further includes one or more processors, and a memory resource represented by a memory 532, for storing instructions that can be executed by the processing component 522, such as an application. The application stored in the memory 532 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 522 is configured to execute instructions to perform the method provided in the embodiment of the present application.

[0111] The electronic device 500 may further include a power supply component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input / output interface 558. The electronic device 500 may operate based on an operating system stored in the memory 532, such as Windows Server TM, Mac OS X TM, Unix TM, Linux TM, FreeBSD TM or the like.

[0112] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method described in the above embodiment when executed by a processor.

[0113] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0114] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for locating a signal in a circuit design file, characterized in that: The method comprises: Obtaining a signal name of a signal to be debugged in a circuit design file, and determining a target source code module and a target compiled code module that match the signal name of the signal to be debugged according to a first correspondence between a source code module to which the signal belongs, a compiled code module to which the signal belongs, and the signal name of the signal; Determine a target source code file that matches the target source code module according to a second correspondence between source code files and source code modules, and determine a target compiled code file that matches the target compiled code module according to a third correspondence between compiled code files and compiled code modules; Performing syntax analysis on the target source code file and the target compiled code file respectively to obtain a first line number corresponding to the signal to be debugged in the target source code file and a second line number corresponding to the signal to be debugged in the target compiled code file; The signal name, the first line number, and the second line number of the signal to be debugged are displayed in the display area to facilitate waveform debugging of the signal to be debugged.

2. The method according to claim 1, characterized in that The performing syntax analysis on the target source code file and the target compiled code file respectively to obtain the first line number corresponding to the signal to be debugged in the target source code file and the second line number corresponding to the signal to be debugged in the target compiled code file comprises: Obtaining a first syntax tree corresponding to a first design language of the target source code file and a second syntax tree corresponding to a second design language of the target compiled code file; In the first syntax tree, find a first position where a node corresponding to the signal to be debugged is located, and determine the first line number according to the first position; In the second syntax tree, a second position where the node corresponding to the signal to be debugged is located is found, and the second line number is determined according to the second position.

3. The method according to claim 1, characterized in that The display area includes a first display area and a second display area; The displaying the signal name of the signal to be debugged, the first line number, and the second line number in the display area includes: Open the target source code file in the first display area, automatically jump to the position of the first line number, and highlight the signal name of the signal to be debugged at the position of the first line number; The target compiled code file is opened in the second display area, and the second line number is automatically jumped to the position, and the signal name of the signal to be debugged is highlighted at the position of the second line number.

4. The method according to claim 1, characterized in that: The method further comprises: Obtaining a source code file and a compiled code file; the compiled code file is generated by compiling the source code in the source code file; Performing syntax analysis on the source code file and the compiled code file respectively to obtain a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file; Establishing a first correspondence between the source code module, the compiled code module, and the signal name of the signal; A second corresponding relationship between the source code file and the source code module, and a third corresponding relationship between the compiled code file and the compiled code module are established.

5. The method according to claim 4, characterized in that The grammatical analysis is performed on the source code file and the compiled code file respectively to obtain a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file, including: Obtaining a first syntax tree corresponding to a first design language of the target source code file and a second syntax tree corresponding to a second design language of the target compiled code file; In the first syntax tree, find the module node and the file node to which the node corresponding to the signal to be debugged belongs, and use the module corresponding to the module node as the source code module, and use the file corresponding to the file node as the source code file; In the second syntax tree, find the module node and the file node to which the node corresponding to the signal to be debugged belongs, and use the module corresponding to the module node as the compiled code module, and use the file corresponding to the file node as the compiled code file.

6. The method according to claim 1, characterized in that The method further comprises: According to the preset configuration, a target signal among all signals is determined as a signal to be debugged; In response to a selection operation on a signal except a target signal among all the signals, the selected signal is used as a new signal to be debugged, and the new signal to be debugged is displayed in the display area.

7. The method according to claim 6, characterized in that The display area includes a signal name area, a signal value display area and a waveform display area; the signal name area displays the signal name of each existing signal in the circuit design file; The step of taking the selected signal as a new signal to be debugged and displaying the new signal to be debugged in the display area includes: Select a signal from the signal name area as a new signal to be debugged; The signal name of the new signal to be debugged and the value of the new signal to be debugged are displayed in the signal value display area, and the waveform of the new signal to be debugged is displayed in the waveform display area.

8. The method according to claim 4, characterized in that The obtaining of source code files and compiled code files includes: Get the path of the source code file and the path of the compiled code file; The source code file is found according to the path of the source code file, and the compiled code file is found according to the path of the compiled code file.

9. The method according to claim 1, characterized in that: The method further comprises: If the signal to be debugged is an intermediate variable, the signal assigned to the signal to be debugged is found from all signals according to the assignment relationship, the signal assigned to the signal to be debugged is determined as the signal to be debugged, and the step of obtaining the signal name of the signal to be debugged in the circuit design file is entered.

10. The method according to claim 4, characterized in that The grammatical analysis is performed on the source code file and the compiled code file respectively to obtain a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file, including: Obtain a first temporary file corresponding to the source code file and a second temporary file corresponding to the compiled code file; the first temporary file is a file generated by replacing a hyperparameter value of the source code file; the second temporary file is a file generated by replacing a hyperparameter value of the compiled code file; Performing syntax analysis on the first temporary file to obtain the source code module; Performing syntax analysis on the second temporary file to obtain the compiled code module.

11. A device for locating a signal in a circuit design file, characterized in that: The device comprises: A first determination module is used to obtain a signal name of a signal to be debugged in a circuit design file, and determine a target source code module and a target compiled code module that match the signal name of the signal to be debugged according to a first correspondence between a source code module to which the signal belongs, a compiled code module to which the signal belongs, and the signal name of the signal; a second determining module, configured to determine a target source code file matching the target source code module according to a second correspondence between source code files and source code modules, and to determine a target compiled code file matching the target compiled code module according to a third correspondence between compiled code files and compiled code modules; A first syntax analysis module is used to perform syntax analysis on the target source code file and the target compiled code file respectively to obtain a first line number corresponding to the signal to be debugged in the target source code file and a second line number corresponding to the signal to be debugged in the target compiled code file; The display module is used to display the signal name, the first line number, and the second line number of the signal to be debugged in a display area to facilitate waveform debugging of the signal to be debugged.

12. An electronic device, characterized in that: The invention comprises a processor, a memory and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the signal positioning method in the circuit design file as described in any one of claims 1 to 10.

13. A readable storage medium, characterized in that: The readable storage medium stores a program or an instruction, and when the program or the instruction is executed by a processor, the steps of the method for locating a signal in a circuit design file according to any one of claims 1 to 10 are implemented.

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