A method for automatic layout generation

Abstract

The present invention discloses an automatic layout generation method. First, for a process library PDK specified by an analog circuit or a mixed-analog circuit, a cell library compiler AcellGen is used to generate the minimum analog unit Acell of each circuit component required for automatic layout. Then, each parameterized unit Pcell in a schematic diagram constructed using the parameterized unit Pcell is replaced with the corresponding minimum analog unit Acell. Then, based on the currently obtained schematic diagram, a corresponding circuit netlist is generated, and the Acell used in the schematic diagram is placed in the same schematic to extract a GDS file. Finally, based on the circuit netlist, GDS and the minimum analog unit of each circuit component required for automatic circuit layout, an automatic place and route tool (PNR) is used to perform final layout generation. The method has the advantages that it can be used for the layout design of analog circuits or mixed-analog circuits, the layout area is small, and no manual intervention is required when performing layout design on analog circuits or mixed-analog circuits, so the efficiency is high.

Description

Technical Field

[0001] The present invention relates to a layout generation method, in particular to an automatic layout generation method. Background Art

[0002] In integrated circuit (IC) design, layout is a key step in translating circuit designs into physical layer implementations. With the rapid advancement of semiconductor technology, IC design complexity continues to increase, and traditional manual layout generation methods are no longer sufficient to meet the demands of modern IC design. To meet these demands, automated layout generation methods have been developed to improve design efficiency, shorten design cycles, and achieve the quality of manual layouts.

[0003] There are two main methods for automatic layout generation. The first method is mainly based on Synopsys's ICC2 automatic layout and routing tool of Cadence Virtuoso Layout XL, which is specially used for analog and mixed-signal circuit layout and routing. The second method is based on Innovus, a digital design implementation tool provided by Cadence Design Systems, which is specially used for automatic layout and routing of digital circuit layout.

[0004] The first automatic layout generation method mainly includes the following steps when implementing automatic layout generation: first, according to the target circuit schematic, define the placement target (such as reducing the area, optimizing the wiring space, etc.), and select the automatic placement function to automatically arrange the circuit components according to the design rules, and automatically place each circuit component (cell) on the layout according to the design rules and placement targets. Secondly, set the layout parameters (such as layout length, layout width, etc.) and define the wiring rules (such as line width, line spacing, etc.); finally, according to the set layout parameters and defined wiring rules, use the automatic wiring function to automatically generate the wiring path to connect the circuit components. However, the first automatic layout generation method has the following problems: First, for complex designs, inappropriate routing rule definitions may cause problems in subsequent steps, requiring additional manual inspection and correction; second, the automatic placement of circuit components may not fully meet all design requirements and require further manual adjustment; third, in high-density designs, automatic routing may lead to signal congestion or poor routing paths, failing to meet the accuracy and performance requirements of manual routing, and may require further manual optimization; fourth, it simply implements layout and routing, failing to optimize timing, power consumption, and the energy efficiency of the chip, and failing to automatically optimize the layout area, which also requires further manual optimization. Therefore, in actual use, the first automatic layout generation method often requires designers to perform manual optimization and adjustments to overcome the limitations of the automation function. The workload of manual adjustment and optimization is large and the efficiency is low. In general, using the first automatic layout generation method to complete the design of the mixed-analog circuit layout still requires a lot of manual intervention.

[0005] The second automatic layout generation method mainly includes the following steps when implementing automatic layout generation: first, extract and generate a netlist from the schematic diagram of the target circuit, perform optimization based on the netlist, including area optimization, speed optimization, power optimization, etc., then place the macro cells (such as memory and I / O cells) in the target circuit to predefined locations on the chip, then arrange standard cells (such as logic gates) on the chip according to design requirements, and finally perform global automatic routing to connect the various macro cells and standard cells to ensure signal transmission, thereby achieving automatic layout generation. Although the second automatic layout generation method can provide fast placement and routing capabilities, support efficient processing of complex designs, and achieve performance, power consumption, and area optimization during the generation process, in actual use, it only needs to extract the netlist information from the schematic diagram of the target circuit to achieve automatic layout placement and routing based on the netlist information. The workload of manual adjustment and optimization is small and the efficiency is high. However, it can only be applied to the automatic placement and routing of digital circuits and cannot be used for layout design of analog circuits or mixed analog and digital circuits. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an automatic layout generation method that can be used for the layout design of analog circuits and mixed analog and digital circuits, and does not require manual intervention when performing layout design on analog circuits and mixed analog and digital circuits, and has high efficiency.

[0007] The technical solution adopted by the present invention to solve the above technical problems is: an automatic layout generation method, comprising the following steps:

[0008] Step 1: For the process library PDK specified for the analog circuit or mixed-analog circuit, first use the cell library compiler AcellGen to generate the minimum analog cell Acell of each circuit component required for the automatic layout of the analog circuit or mixed-analog circuit;

[0009] Step 2: First, replace each parameterized unit Pcell in the schematic diagram of the analog circuit or mixed analog circuit constructed using the parameterized unit Pcell with the corresponding minimum analog unit Acell. Then, based on the currently obtained schematic diagram of the analog circuit or mixed analog circuit, generate the corresponding circuit netlist Netlist. The circuit netlist Netlist contains the parameter information of each circuit component in the analog circuit or mixed analog circuit and the connection relationship between each circuit component. In addition, the minimum analog unit Acell used in the analog circuit or mixed analog circuit schematic diagram is placed in the same schematic to extract the GDS file. The GDS file records every detail of the chip layout, including the graphic shapes at different levels and the connection methods of circuit components.

[0010] Step 3: Based on the circuit netlist, GDS file and the minimum analog unit Acell of each circuit component required for the automatic layout of the analog circuit or mixed analog circuit, use the automatic layout and routing tool pnr to generate the layout of the analog circuit or mixed analog circuit.

[0011] Furthermore, the automatic placement and routing tool is a related script and calls Cadence's Innovus digital circuit automatic placement and routing tool.

[0012] Compared with the prior art, the advantage of the present invention is that first, for the process library PDK specified for the analog circuit or the digital-analog mixed circuit, the cell library compiler AcellGen is used to generate the minimum analog unit Acell of the circuit components required for the automatic layout of the analog circuit or the digital-analog mixed circuit, thereby facilitating the subsequent use of automatic layout and routing tools to realize the automatic layout and routing of the analog circuit or the digital-analog mixed circuit. The minimum analog unit Acell is generated according to the process library PDK provided by the chip process manufacturer, fully complying with the design rules of the chip process manufacturer, ensuring that the analog circuit or the digital-analog mixed circuit that is subsequently laid out and routed fully meets the manufacturing requirements of the process manufacturer; then the automatic layout and routing tool is used to generate the minimum analog unit Acell. The parameterized unit Pcell (parameterized unit Pcell is used to represent circuit components with variable parameters, such as transistors, resistors, capacitors, etc.) in the schematic diagram of the analog circuit or mixed analog circuit is replaced with the corresponding minimum analog unit Acell, and the corresponding circuit netlist is generated. The circuit netlist contains the parameter information of each circuit component in the analog circuit or mixed analog circuit and the connection relationship between each circuit component. The minimum analog unit Acell used in the analog circuit or mixed analog circuit schematic is placed in the same schematic to extract the GDS file. At this time, based on The information parameters provided by the circuit netlist are used as input for subsequent automatic layout and routing tools to guide the placement and routing of various circuit components. This can avoid problems in subsequent steps caused by inappropriate routing rule definitions in the automatic layout and routing tools, thereby reducing the manpower required for subsequent adjustments. Finally, based on the circuit netlist, GDS file, and the minimum analog unit Acell of each circuit component required for automatic layout of analog circuits or mixed analog circuits, an automatic layout and routing tool (such as Cadence's Innovus digital circuit automatic layout and routing tool) is used to generate the final layout. Innovus digital circuit automatic layout and routing tool The present invention can only generate automatic layout and routing of digital circuits. By combining it with Acell, it can realize the layout automation of analog circuits and mixed analog and digital circuits. The automatic layout and routing tool integrates an efficient algorithm, which can continuously optimize the layout during the generation process, accelerate the layout and routing process, and achieve the best pipeline layout, line length, utilization and PPA (performance, power consumption, area), so that the ideal analog circuit or mixed analog and digital circuit layout can be obtained without manual intervention. Therefore, the present invention can be used for the layout design of analog circuits or mixed analog and digital circuits, and no manual intervention is required when performing layout design on analog circuits or mixed analog and digital circuits, which is highly efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A flowchart of an automatic layout generation method of the present invention;

[0014] Figure 2Acell: Schematic diagram based on Pcell+ different transistor parameters;

[0015] Figure 3 Schematic diagram of multiple Acell splicing;

[0016] Figure 4 Acell schematic diagram of NMOS;

[0017] Figure 5 This is the schematic diagram of the target secondary op amp;

[0018] Figure 6 This is a schematic diagram of the Acell layout;

[0019] Figure 7 Generate layout for Acell-based automatic layout (secondary op amp circuit). DETAILED DESCRIPTION

[0020] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0021] Example 1: Figure 1 As shown, an automatic layout generation method includes the following steps:

[0022] Step 1: For the process library PDK specified for the analog circuit or mixed-analog circuit, first use the cell library compiler AcellGen to generate the minimum analog cell Acell of each circuit component required for the automatic layout of the analog circuit or mixed-analog circuit;

[0023] Step 2: First, replace each parameterized unit Pcell in the schematic diagram of the analog circuit or mixed analog circuit constructed using parameterized units Pcell for representing circuit components with variable parameters (such as transistors, resistors, capacitors, etc.) with the corresponding minimum analog unit Acell. Then, based on the currently obtained schematic diagram of the analog circuit or mixed analog circuit, generate the corresponding circuit netlist Netlist. The circuit netlist Netlist contains the parameter information of each circuit component in the analog circuit or mixed analog circuit and the connection relationship between each circuit component. In addition, the Acell used in the analog circuit or mixed analog circuit schematic diagram is placed in the same schematic to extract the GDS file. The GDS file records every detail of the chip layout, including the graphic shapes at different levels and the connection methods of circuit components.

[0024] Step 3. Based on the circuit netlist, GDS file, and the minimum analog unit Acell of each circuit component required for the automatic layout of the analog circuit or mixed analog circuit, use the automatic layout and routing tool (pnr) to call the Innovus digital circuit automatic layout and routing tool and related scripts to generate the layout of the analog circuit or mixed analog circuit.

[0025] In this embodiment, first, for the process library PDK specified for the analog circuit or the mixed-analog circuit, the cell library compiler AcellGen is used to generate the minimum analog cell Acell of the circuit components required for the automatic layout of the analog circuit or the mixed-analog circuit, thereby facilitating the subsequent use of automatic layout and routing tools to realize the automatic layout and routing of the analog circuit or the mixed-analog circuit. The minimum analog cell Acell is generated based on the process library PDK provided by the chip process manufacturer and fully complies with the design rules of the chip process manufacturer, ensuring that the analog circuit or the mixed-analog circuit subsequently laid out and routed fully meets the manufacturing requirements of the process manufacturer; then, each parameterized cell Pcell in the schematic diagram of the analog circuit or the mixed-analog circuit constructed using the parameterized cell Pcell (the parameterized cell Pcell is used to represent circuit components with variable parameters, such as transistors, resistors, capacitors, etc.) is replaced with the corresponding minimum analog cell Acell, and a corresponding circuit netlist is generated. The circuit netlist contains the parameter information of each circuit component in the analog circuit or the mixed-analog circuit and the connection relationship between each circuit component. At this time, the information parameters provided by the circuit netlist are used as the parameters for the subsequent automatic layout and routing. The automatic layout and routing tool uses the input of the automatic layout and routing tool to guide the placement and routing of each circuit component. This can avoid problems in subsequent steps caused by inappropriate routing rule definitions in the automatic layout and routing tool, thereby reducing the manpower required for subsequent adjustments. The Acells used in the circuit schematic are placed in the same schematic and the GDS file is extracted. The GDS file records every detail of the chip layout, including the graphic shapes at different levels and the connection methods of circuit components, ensuring the accuracy of the final layout details. Finally, based on the circuit netlist, GDS file, and the minimum analog unit Acells of each circuit component required for automatic layout of analog circuits or mixed-analog circuits, the automatic layout and routing tool (PNR) is used to generate the final layout. This automatic layout and routing tool integrates efficient algorithms and calls the Innovus digital circuit automatic layout and related scripts during operation. It can continuously optimize the layout during the generation process, accelerate the layout and routing process, and achieve the optimal pipeline layout, line length, utilization and PPA (performance, power consumption, area), so that the ideal analog circuit or mixed-analog circuit layout can be obtained without manual intervention.

[0026] Example 2: This example is essentially the same as Example 1, with the following differences: In this example, the automated placement and routing tool is Cadence's Innovus digital circuit automated placement and routing tool. Innovus provides full-process support from early layout planning to final signoff, ensuring that the design meets performance, power, and area requirements. It features high-performance algorithms to accelerate the placement and routing process, supports comprehensive optimization of area, timing, and power, and provides multi-mode and multi-corner analysis. Innovus also employs advanced global and detailed routing strategies and can automatically fix timing violations and other issues during placement and routing.

[0027] In this embodiment, Cadence's Innovus digital circuit automatic layout and routing tool can only automatically layout and route digital circuits. We use Acell generated by AcellGen to enable analog circuits and mixed analog and digital circuits to be laid out and routed using Innovus. The present invention uses the automatic layout and routing tool (pnr) to call Innovus and use it together with related scripts to facilitate multiple runs to successfully verify the IC. Innovus scripts can control steps from initial floor planning (Floorplanning) to detailed layout (Placement), clock tree synthesis (CTS), routing (Routing), timing analysis and optimization (Timing Analysis and Optimization), and power analysis and optimization (Power Analysis and Optimization), which greatly promotes performance improvement, timing consistency, compatibility, DRC results, power optimization, global routing, voltage drop impact, integrated environment, and automation and script support.

[0028] In order to verify the performance of the automatic layout generation method of the present invention, Figure 5 The secondary op amp built with Pcell is used as the target circuit, and the method of the present invention is used to automatically generate the layout of the target circuit. We first use AcellGen to generate the corresponding Acell according to the PDK used by the target circuit and the circuit component parameters (such as MOS tube width and length). Figure 2 The following is a schematic diagram of one of the Acells. Figure 4 This is a schematic diagram of the Acell of NMOS; we will splice it later, the specific form is as follows Figure 3As shown. Then use the generated Acell to replace the Pcell in the circuit schematic, extract the Netlist information and put the Acell used in the circuit schematic in the same schematic to extract the GDS file. Finally, call the minimum analog unit Acell of each circuit component required for the circuit netlist, GDS file and circuit automatic layout based on the circuit netlist, use the automatic layout and routing tool (pnr) to call the Innovus digital circuit automatic layout and routing tool and related scripts to generate the circuit layout. The layout diagram is shown in Figure 6 , and finally generate the layout as Figure 7 As shown, its area is 30% smaller than that of the manual layout based on Pcell.

[0029] In integrated circuit design, manual layout drawing is not only time-consuming but also prone to errors, especially in design rule checking (DRC) and layout and circuit Figure 1Errors in LVS (Low-Level Validation) are avoided. In this invention, since the minimum analog cell (Acell) is generated based on the process library (PDK) provided by the chip foundry, it fully complies with the chip foundry's design rules, ensuring that the analog or mixed-analog circuits subsequently placed and routed fully meet the foundry's manufacturing requirements. Designers can focus more on design innovation and optimization, rather than spending a lot of time on tedious manual drawing and error checking. This not only improves the accuracy and reliability of analog or mixed-analog circuit design, but also shortens the design cycle and accelerates time to market. In this invention, the extracted circuit netlist information ensures that the design adheres to the set rules and optimization goals, offering significant advantages over manual drawing. Automatic place and route tools use high-performance algorithms to quickly complete place and route, optimizing design performance while comprehensively considering area, timing, and power consumption to achieve the best design results. They ensure design reliability across various processes and environments and enhance signal integrity through advanced routing technologies. In contrast, manual drawing can be time-consuming, inefficient, and prone to errors. The automated PNR repair function of automatic place and route tools can resolve complex timing issues, while manual drawing requires designers to constantly check and correct. Furthermore, seamless integration with other Cadence tools further improves design efficiency, a feature lacking in manual drawing. Overall, the system significantly surpasses traditional manual drawing methods in terms of efficiency, accuracy, and optimization capabilities. The present invention introduces Acell, the smallest analog unit of circuit components, to enable automatic layout placement and routing for analog or mixed-analog circuits. This overcomes the limitation of Innovus, a digital design implementation tool provided by Cadence Design Systems, which only performs automatic layout placement and routing for digital circuits, and can now also perform automatic layout placement and routing for analog or mixed-analog circuits. Consequently, through these technical advantages, the present invention improves layout generation accuracy by directly extracting circuit netlist information during layout generation. By utilizing the generated Acell standard cells, Innovus can automatically place and route analog or mixed-analog circuits, overcoming the limitation of Innovus, which only performs automatic layout generation for digital circuits. Furthermore, during the generation process, the automatic place-and-route tool (PNR) uses high-performance algorithms to quickly complete placement and routing, optimize design performance, and comprehensively consider area, timing, and power consumption to achieve the best design results. This significantly reduces the subsequent labor required. The automatic layout generation method of the present invention can realize the automatic and efficient generation of analog circuit and digital-analog mixed circuit layouts, and has broad application prospects in the field of automatic generation of analog circuits and digital-analog mixed circuits.

Claims

1. A method for automatic layout generation, characterized in that The following steps are involved: Step 1: For the process library PDK specified for the analog circuit or mixed-analog circuit, first use the cell library compiler AcellGen to generate the minimum analog cell Acell of each circuit component required for the automatic layout of the mixed-analog circuit; Step 2: First, replace each parameterized unit Pcell in the schematic diagram of the analog circuit or mixed analog circuit constructed using the parameterized unit Pcell with the corresponding minimum analog unit Acell. Then, based on the currently obtained schematic diagram of the analog circuit or mixed analog circuit, generate the corresponding circuit netlist Netlist. The circuit netlist Netlist contains the parameter information of each circuit component in the analog circuit or mixed analog circuit and the connection relationship between each circuit component. In addition, the minimum analog unit Acell used in the analog circuit or mixed analog circuit schematic is placed in the same schematic to extract the GDS file. The GDS file records every detail of the chip layout, including the graphic shapes at different levels and the connection methods of circuit components. Step 3: Based on the circuit netlist, the minimum analog unit Acell of each circuit component required for automatic layout of the analog circuit or mixed analog circuit, and the GDS file, use the automatic layout and routing tool to generate the layout of the analog circuit or mixed analog circuit.

2. An automatic layout generation method according to claim 1, characterized in that The automatic placement and routing tool is a related script and calls Cadence's Innovus digital circuit automatic placement and routing tool.

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