Global wiring method and device based on dynamic tree, electronic equipment and storage medium

Abstract

The invention discloses a global wiring method and device based on a dynamic tree, electronic equipment and a storage medium, and relates to the technical field of integrated circuits, and the method comprises the steps: generating a tree topology with the shortest line length and determined by the shortest line length and congestion reduction weighting for each line network; respectively constructing the two tree topologies of each net into a tree forest; candidate trees are selected from all the tree forests according to the target function, and candidate template paths of the candidate trees are selected; determining a global wiring scheme of the corresponding network according to each candidate tree and the candidate template path; generating a tree topology for reducing congestion for the network with congestion in the global wiring scheme, and replacing unselected tree topologies in the tree forest of the network with congestion; deleting a tree forest corresponding to a non-congested network in the global wiring scheme; and then repeatedly executing the step of global wiring. According to the application, the tree topology of the congested line network is updated, and congestion is reduced; and the tree forest of the non-congestion line network is deleted, so that the calculation amount is reduced, and the efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a global wiring method, device, electronic device and storage medium based on a dynamic tree. Background Art

[0002] Global routing is a key step in the early stage of the automated routing process of integrated circuits (ICs) layout, and is also an important research field of electronic design automation (EDA). After the layout is completed, global routing can find the metal wire connection mode and layer number distribution of all nets in the layout in a coarse-grained manner within a limited time, providing key guidance for the subsequent detailed routing process. However, the global routing solution of the existing technology still has the disadvantages of low efficiency and insufficient congestion handling capability. Summary of the invention

[0003] The main purpose of the embodiments of the present application is to propose a global routing method, device, electronic device and storage medium based on a dynamic tree to improve the efficiency of global routing of integrated circuits and reduce congestion.

[0004] To achieve the above object, an embodiment of the present application provides a global routing method based on a dynamic tree, the method comprising the following steps:

[0005] Generate a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weight for each circuit network;

[0006] constructing the first tree topology and the second tree topology of each circuit network into a corresponding tree forest;

[0007] Select one of the tree topologies from the two tree topologies of each tree forest as a candidate tree for each circuit network according to the objective function of global routing, and select a candidate template path for the candidate tree;

[0008] Determine a global routing scheme corresponding to the circuit network according to each of the candidate trees and each of the candidate template paths;

[0009] Generating a third tree topology that reduces congestion for the circuit net with congestion in the global routing scheme, and replacing the tree topologies that are not selected in the tree forest of the circuit net with congestion with the third tree topology;

[0010] Deleting the tree forest corresponding to the circuit network without congestion in the global routing scheme;

[0011] Return the objective function of global routing, select one of the two tree topologies of each tree forest as a candidate tree for each circuit network and select a candidate template path of the candidate tree until the preset end condition is reached, and use the current global routing scheme as the target global routing scheme for each circuit network.

[0012] In some embodiments, the step of generating a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weight for each circuit network respectively includes the following steps:

[0013] Generating a right-angle Steiner minimum tree with the shortest line length of each circuit network as the first tree topology;

[0014] Performing template routing on the corresponding circuit network according to each of the right-angle Steiner minimum trees, thereby obtaining a congestion distribution diagram of each of the circuit network;

[0015] A winding tree corresponding to each of the circuit nets is generated as the second tree topology according to each of the congestion distribution graphs using an undo rewind algorithm.

[0016] In some embodiments, generating a third tree topology with reduced congestion for the circuit net with congestion in the global routing scheme comprises the following steps:

[0017] A rewinding algorithm is used to generate a wiring tree for the circuit net with congestion in the global routing scheme as the third tree topology.

[0018] In some embodiments, the step of generating a right-angle Steiner minimum tree with the shortest line length of each circuit network as the first tree topology comprises the following steps:

[0019] The FLUTE algorithm is used to generate a rectangular Steiner minimum tree with the shortest line length of each circuit network as the first tree topology.

[0020] In some embodiments, generating the wiring tree of each circuit net using the undo rewinding algorithm comprises the following steps:

[0021] The undo-rewind algorithm of CUGR2 is used to generate the wiring tree of each circuit net.

[0022] In some embodiments, selecting one of the tree topologies from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets and selecting a candidate template path for the candidate tree according to the objective function of the global routing comprises the following steps:

[0023] Initialize first candidate probabilities of two of the tree topologies in each of the tree forests and second candidate probabilities of 2-pin wire nets of the two tree topologies;

[0024] Performing significance calculation on each of the first candidate probabilities and each of the second candidate probabilities;

[0025] Obtaining the minimum value of the objective function according to the result of the significance calculation and the gradient descent method, and then updating each of the first candidate probabilities and each of the second candidate probabilities;

[0026] If the updated first candidate probability and the second candidate probability meet the selection condition, then in each of the tree forests, the tree topology corresponding to the largest first candidate probability is selected as the candidate tree, and the 2-pin wire net corresponding to the largest second candidate probability in the candidate tree is selected as the candidate template path;

[0027] If the updated first candidate probability and the second candidate probability do not meet the selection condition, return to update each of the first candidate probabilities and each of the second candidate probabilities based on the result of the saliency calculation and the gradient descent method until the updated first candidate probability and the second candidate probability meet the selection condition.

[0028] In some embodiments, the method further comprises the following steps:

[0029] Determine whether the updated first candidate probability and the second candidate probability reach 90%;

[0030] The updated probability of the first candidate and the probability of the second candidate reaching 90% are determined as meeting the selection condition;

[0031] If the updated first candidate probability and the second candidate probability do not reach 90%, it is determined that the selection condition is not met.

[0032] To achieve the above object, another aspect of the embodiment of the present application provides a global routing device based on a dynamic tree, the device comprising:

[0033] A tree topology generating unit, used to generate a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weight for each circuit line network;

[0034] A tree forest construction unit, configured to construct the first tree topology and the second tree topology of each circuit network into a corresponding tree forest;

[0035] A tree and path selection unit, configured to select one of the tree topologies from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets and select a candidate template path for the candidate tree according to an objective function of global routing;

[0036] A global routing unit, used for determining a global routing scheme corresponding to the circuit network according to each of the candidate trees and each of the candidate template paths;

[0037] A tree forest updating unit, configured to generate a third tree topology for reducing congestion for the circuit network with congestion in the global routing scheme, and replace the tree topology that is not selected in the tree forest of the circuit network with congestion with the third tree topology;

[0038] A tree forest deletion unit, used for deleting the tree forest corresponding to the circuit network without congestion in the global routing scheme;

[0039] A repeated selection unit is used to return the objective function of global routing and select one of the tree topologies from the two tree topologies of each tree forest as a candidate tree for each circuit network and select a candidate template path of the candidate tree until a preset end condition is reached, and the current global routing scheme is used as the target global routing scheme for each circuit network.

[0040] To achieve the above objective, another aspect of an embodiment of the present application provides an electronic device, the electronic device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the above method when executing the computer program.

[0041] To achieve the above objective, another aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program implements the above method when executed by a processor.

[0042] The embodiments of the present application include at least the following beneficial effects:

[0043] The present application can generate a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and reduced congestion weight for each circuit network; construct the first tree topology and the second tree topology of each circuit network into corresponding tree forests; select one tree topology from the two tree topologies of each tree forest as the candidate tree of each circuit network according to the objective function of global routing and select the candidate template path of the candidate tree; determine the global routing scheme of the corresponding circuit network according to each candidate tree and each candidate template path; generate a third tree topology with reduced congestion for the circuit network with congestion in the global routing scheme, and replace the tree topology that is not selected in the tree forest of the circuit network with congestion with the third tree topology; delete the tree forest corresponding to the circuit network without congestion in the global routing scheme; return to select one tree topology from the two tree topologies of each tree forest as the candidate tree of each circuit network according to the objective function of global routing and select the candidate template path of the candidate tree until the preset end condition is reached, and the current global routing scheme is used as the target global routing scheme for each circuit network. In addition to generating a first tree topology with the shortest line length, the present application also generates a second tree topology that takes into account both the shortest line length and reduced congestion, and then constructs a tree forest based on the two tree topologies. Global routing is then performed based on the tree forest. For circuit lines with congestion, the tree topology is updated to obtain a tree topology with less congestion, thereby reducing congestion; for circuit lines without congestion, the tree forest is deleted, thereby reducing the amount of calculation in the global routing process and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 An example diagram of the tree topology and template path of each network provided in the embodiment of the present application;

[0046] Figure 2 An example flow chart of a global routing method provided in an embodiment of the present application;

[0047] Figure 3 A training flow chart of the tree-forest perspective provided for an embodiment of the present application;

[0048] Figure 4 A schematic diagram of a flow chart of a global routing method based on a dynamic tree provided in an embodiment of the present application;

[0049] Figure 5 An example flow chart of dynamically updating a tree forest provided in an embodiment of the present application;

[0050] Figure 6 An example flow chart of a global routing method based on a dynamic tree provided in an embodiment of the present application;

[0051] Figure 7 An example flow chart of dynamically reducing the size of a tree forest provided in an embodiment of the present application;

[0052] Figure 8 A schematic diagram of the structure of a dynamic tree-based global routing device provided in an embodiment of the present application;

[0053] Fig. 9 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0055] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0056] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0058] Before describing the embodiments of the present application in detail, some terms and related technologies involved in the embodiments of the present application are first described. The terms and related technologies involved in the embodiments of the present application are subject to the following explanations:

[0059] Global routing usually aims to reduce wire length, number of vias, and congestion. Wire length refers to the total length of wires or signal lines connecting circuit elements on all metal layers in the layout; vias refer to the connection channels that establish electrical connections between different metal layers, and the number of vias refers to the cumulative sum of all vias on the layout; congestion refers to the situation where the actual routing on a certain routing unit exceeds the maximum number of routings, causing the routing to violate the design rules, and the congestion refers to the cumulative sum of the excess of all routing units on the layout. With the increase in chip design complexity and design scale, traditional global routing algorithms still do not fully consider the overall routing resources and wire network distribution of the layout, making it difficult to effectively deal with congestion problems in the design in the early stage of routing, which greatly affects the running speed of subsequent EDA algorithms and the quality of the final layout.

[0060] Generally speaking, the global routing process involves the following processes:

[0061] 1. Tree Generation: Use algorithms such as FLUTE to quickly generate a Rectilinear Steiner Minimal Tree (RSMT). FLUTE is a Rectilinear Steiner Minimal Tree construction algorithm that uses a lookup table method. The algorithm is fast and can achieve optimal results on low-degree (i.e., the number of pins in the network) wire networks. The Rectilinear Steiner Minimal Tree refers to the shortest path connecting a group of pins on a two-dimensional plane. The Rectilinear Steiner Minimal Tree can quickly give the wire network a preliminary routing reference.

[0062] 2. Pattern Routing: For the rectangular Steiner minimum tree generated in the first step, the depth first search (DFS) algorithm is used to decompose the rectangular Steiner minimum tree into a two-pin net. The two-pin net refers to the net composed of two points that share an edge in the tree. Since the rectangular Steiner minimum tree is only two-dimensional, it is necessary to use algorithms such as dynamic programming to determine the specific direction of the two-pin net and the layer assignment of the metal wire. That is, a routing template (Pattern) that conforms to certain templates (such as L-type or Z-type) is used to replace each two-pin net of the rectangular Steiner minimum tree and perform layer assignment at the same time to quickly complete the 3D routing.

[0063] 3. Maze Routing: After the above algorithm process, there may still be wire nets that are difficult to route. The maze routing algorithm can better complete the routing of these wire nets.

[0064] Most of the currently commonly used global routing algorithms are based on algorithms running on the CPU (Central Processing Unit), such as CUGR2 and other algorithms. Although they perform well when processing small-scale circuits, in large-scale integrated circuit design, the computing time and memory consumption grow exponentially, resulting in the limited efficiency and scalability of automated design as the scale of modern integrated circuits continues to expand. In order to meet this challenge, acceleration algorithms based on GPUs (Graphics Processing Units) have gradually attracted attention in recent years. The parallel computing capabilities of GPUs can significantly accelerate certain computationally intensive tasks, especially in the automation of routing on a very large scale, where their advantages of high parallelism and large data throughput are brought into play. Compared with algorithms that can only call one or several threads when running on a CPU alone, algorithms that can use GPUs have gained considerable advantages in terms of running time and other aspects in the global routing process of large-scale circuit design.

[0065] Next, the related technologies involved in the present application are explained. It should be pointed out that the related technologies of the present application are only used to more clearly describe the present application, and the related technologies do not necessarily constitute prior art for the present application.

[0066] Related technology (abbreviated as DGR) has proposed a global routing method that can utilize GPU computing resources. DGR first models a tree forest, which corresponds to two levels of selection probability matrices. The first level of the selection probability matrix represents the selection probability of different tree topologies in each wire net (the circuit wire net of this application can be referred to as a wire net, and the 2-pin wire net belongs to a partial structure of the circuit wire net); the second level of the selection probability matrix represents the selection probability of different routing templates in each 2-pin wire net split from all tree topologies. Then the author models the weights of wire length, via, and overflow. Finally, the overhead caused by each routing option in each wire net is accumulated in parallel and multiplied by the selection probability corresponding to the specific routing option, thereby obtaining an objective function expression.

[0067] The relationship between the two levels of selection probability matrices and specific wiring methods comes from the tree forest. The composition structure of the tree forest is as follows: Figure 1 As shown in (a) in the figure, each tree topology and the corresponding candidate path are as follows Figure 1 As shown in (b) in the figure, the tree forest contains an indefinite number of wire mesh structures. Each wire mesh contains two tree topology structures, each of which has a certain selection probability in the optimization, and the sum of the selection probabilities of the two tree topology structures is 1. Each tree topology can be further split into a series of 2-pin wire meshes. If the horizontal and vertical coordinates of the two pins of the 2-pin wire mesh are different (that is, the line connecting the two points is diagonal), then for the 2-pin wire mesh, if the wiring is performed from one pin to another according to the L-shaped template, there will be two wiring possibilities: first horizontal wiring and then vertical wiring, or first vertical wiring and then horizontal wiring. Both wiring methods have a probability of being selected and the sum of the selection probabilities of all wiring templates under the same 2-pin wire mesh is 1.

[0068] After completing the above modeling work, the optimizer is used to optimize the minimum value of the objective function, and the weight parameter with a smaller objective function value corresponds to a better global routing selection. Figure 2 The workflow of the related technology DGR is demonstrated. After reading the wire nets, layout and other information required for wiring, the tree forest is initialized first, so that each wire net has two tree topologies. After the tree forest modeling is completed, the training process begins. In the training process, it is necessary to use gradient descent and other methods to continuously try to obtain the minimum value of the objective function. Until the candidate conditions are met, it can be considered that a better tree topology that meets the expectations and the candidate path of the 2-pin wire net have been obtained, so the training can be stopped. In order to explain the training process in detail, Figure 3The training process from the perspective of the tree forest is shown. First, the unknown probability of each selection is initialized, and then the gradient descent method is used to find the minimum value of the objective function. After several rounds of iterations, the one with the highest probability in the same group of selections is finally selected. Since the parallel computing resources of the GPU can be used, this algorithm can achieve parallel computing. This mechanism of using probability to continuously express the target function reduces the routing time and improves the routing quality. After the training is completed, according to the selected candidate tree topology and the candidate 2-pin wire net candidate path, the dynamic programming algorithm in CUGR2 is used to allocate layers to obtain the 3D routing results of the template routing stage. Then, the maze routing and other common winding algorithms in the routing field are used to perform the most detailed and final trimming of the locations where congestion is difficult to relieve.

[0069] However, through the analysis of the DGR wiring process, the inventors of the present application believe that there is still room for optimization of DGR. First, the spanning tree topology of DGR is not generated from a global perspective. When it is generated, it only calls the FLUTE algorithm, which generates a spanning tree with the shortest line length, but cannot ensure that congestion can be avoided as much as possible under this topology. Secondly, the spanning tree of DGR remains static throughout the entire process. Even if the optimizer performs tree topology selection and template selection from a global perspective, the optimization potential space of the optimizer may be limited due to the inherent topology of the spanning tree.

[0070] Based on this, embodiments of the present application provide a global routing method, device, electronic device and storage medium based on a dynamic tree. The technical solution of the present application includes: generating a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weight for each circuit network; constructing the first tree topology and the second tree topology of each circuit network into corresponding tree forests; selecting one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit network according to the objective function of global routing and selecting a candidate template path of the candidate tree; determining the global routing scheme of the corresponding circuit network according to each candidate tree and each candidate template path; generating a third tree topology for reducing congestion for the circuit network with congestion in the global routing scheme, and replacing the tree topology that is not selected in the tree forest of the circuit network with congestion with the third tree topology; deleting the tree forest corresponding to the circuit network without congestion in the global routing scheme; returning to selecting one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit network according to the objective function of global routing and selecting a candidate template path of the candidate tree until the preset end condition is reached, and the current global routing scheme is used as the target global routing scheme for each circuit network. In addition to generating a first tree topology with the shortest line length, the present application also generates a second tree topology that takes into account both the shortest line length and reduced congestion, and then constructs a tree forest based on the two tree topologies. Global routing is then performed based on the tree forest. For circuit lines with congestion, the tree topology is updated to obtain a tree topology with less congestion, thereby reducing congestion; for circuit lines without congestion, the tree forest is deleted, thereby reducing the amount of calculation in the global routing process and improving efficiency.

[0071] The embodiment of the present application provides a global wiring method based on a dynamic tree, and relates to the field of integrated circuit technology. The global wiring method based on a dynamic tree provided in the embodiment of the present application can be applied to a terminal, can also be applied to a server, and can also be software running in a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and a car terminal, etc., but is not limited to this; the server side can be configured as an independent physical server, or it can be configured as a server cluster or a distributed system composed of multiple physical servers, and can also be configured to provide cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and cloud servers for basic cloud computing services such as big data and artificial intelligence platforms. The server can also be a node server in a blockchain network; the software can be an application that implements a global wiring method based on a dynamic tree, etc., but is not limited to the above forms.

[0072] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0073] Reference Figure 4 , the embodiment of the present application provides a global routing method based on a dynamic tree, the method may include but is not limited to including S400 to S460, specifically as follows:

[0074] S400: Generate, for each circuit network, a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weight.

[0075] Specifically, each wire net generates two tree topologies, one is a first tree topology with the shortest wire length, and the other is a second tree topology that takes into account both the shortest wire length and reduced congestion.

[0076] Further, S400 may include S401 to S403:

[0077] S401: Generate a right-angle Steiner minimum tree with the shortest line length of each circuit network as the first tree topology;

[0078] S402: performing template routing on the corresponding circuit network according to each of the right-angle Steiner minimum trees, thereby obtaining a congestion distribution diagram of each of the circuit networks;

[0079] S403: Generate a winding tree corresponding to each of the circuit nets as the second tree topology according to each of the congestion distribution graphs using an undo rewind algorithm.

[0080] Specifically, in order to create more possibilities for the optimizer to achieve the global optimal routing in the initial stage, a good tree topology needs to be generated as much as possible in the tree generation stage. The advantages and disadvantages of a tree topology are reflected in two aspects: the first is whether it can have the shortest possible line length, and the second is whether it can effectively avoid congestion. Obtaining a tree that is conducive to the global optimal routing requires a balance between the two aspects.

[0081] Considering the actual situation in wiring, the wiring difficulty in different areas varies. Some areas may have a high probability of congestion due to high density of wire nets or complex routing methods. Similarly, the wire nets passing through these areas also have a higher probability of congestion. However, it is difficult to make fast and high-precision predictions in advance about the distribution of such congestion and the probability of congestion in the wire net. Traditional tree generation algorithms such as FLUTE only consider the shortest line length, and do not simultaneously take reducing the line length and avoiding congestion as optimization goals. Even if the congestion distribution is obtained in advance in a coarse-grained manner through algorithms such as RUDY, due to the differences in the degree of congestion between different areas, when generating a tree, it is necessary to be able to dynamically weigh the optimization weights of the two aspects of line length and congestion according to the degree of congestion, which is still very complex and difficult.

[0082] In order to alleviate the above problems, considering that the DGR algorithm can comprehensively weigh the topology advantages and disadvantages of a tree from a global perspective, for congested areas, DGR will give priority to congestion, and vice versa. Therefore, this embodiment introduces two trees with completely different topological characteristics into the tree forest, one is the tree with the shortest line length, and the other is a tree that can avoid congestion to a certain extent. Combined with the characteristic that DGR can measure the advantages and disadvantages of trees from a global perspective, it can indirectly achieve a dynamic trade-off between line length and congestion optimization weights, and select a better tree topology from a global perspective.

[0083] Reference Figure 5 In the process of traversing each network, this embodiment adopts the following method to complete the first construction of the tree forest:

[0084] 1) Using the FLUTE algorithm to quickly generate a rectangular Steiner minimum tree with the shortest or nearly shortest line length; therefore, S401 can be further specifically: using the FLUTE algorithm to generate a rectangular Steiner minimum tree with the shortest line length of each circuit network as the first tree topology;

[0085] 2) Using CUGR2 combined with the rectangular Steiner minimum tree for template routing, a more accurate congestion distribution map can be obtained;

[0086] 3) Using the undo rewinding algorithm to generate a tree that can bypass the current congestion and still keep the line length short. Therefore, S403 can be further specifically: using the undo rewinding algorithm of CUGR2 to generate the winding tree of each circuit network.

[0087] Thus, two trees can be obtained for each line network, and in the subsequent optimization process, the shortest line length and the problem of avoiding congestion can be considered as much as possible. Finally, both obtained trees are added to the tree forest.

[0088] Still refer to Figure 1 (b) in Figure 1 (b) is an example of using the method of this embodiment to construct a tree forest. Under each wire network structure, there are two tree topologies, the first of which is a rectangular Steiner minimum tree structure generated using the FLUTE algorithm, and the second is a winding tree structure generated using the undo rewind algorithm. From this example, it can be seen that the rectangular Steiner minimum tree has a shorter line length, while the winding tree can sacrifice a certain line length to bypass the congested area.

[0089] Beneficial effects of this embodiment:

[0090] Due to the use of dynamic tree generation method, the generation of wiring tree is more flexible and can generate wiring tree in real time according to congestion situation, which significantly reduces the generation of congestion.

[0091] S410: construct the first tree topology and the second tree topology of each of the circuit networks into corresponding tree forests respectively.

[0092] It can be understood that the two tree topologies corresponding to each network constitute a tree forest, that is, each network corresponds to a tree forest.

[0093] S420: selecting one of the tree topologies from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets according to the objective function of the global routing, and selecting a candidate template path of the candidate tree.

[0094] Specifically, the objective function of this embodiment may be aimed at minimizing the wire length of the global wiring.

[0095] A tree topology is selected from each tree forest, and a candidate template path is selected from multiple template paths in the selected tree topology.

[0096] Further, S420 may include S421 to S425:

[0097] S421: Initializing first candidate probabilities of two tree extensions in each of the tree forests and second candidate probabilities of 2-pin wire nets of the two tree extensions;

[0098] S422: Calculate the significance of each of the first candidate probabilities and each of the second candidate probabilities;

[0099] S423: obtaining the minimum value of the objective function according to the result of the saliency calculation and the gradient descent method, and then updating each of the first candidate probabilities and each of the second candidate probabilities;

[0100] S424: If the updated first candidate probability and the second candidate probability meet the selection condition, then select the tree topology corresponding to the largest first candidate probability in each of the tree forests as the candidate tree, and select the 2-pin wire net corresponding to the largest second candidate probability in the candidate tree as the candidate template path;

[0101] S425: If the updated first candidate probability and the second candidate probability do not meet the selection condition, return to update each of the first candidate probabilities and each of the second candidate probabilities based on the result of the saliency calculation and the gradient descent method until the updated first candidate probability and the second candidate probability meet the selection condition.

[0102] S430: Determine a global routing solution corresponding to the circuit network according to each of the candidate trees and each of the candidate template paths.

[0103] Exemplarily, this embodiment may perform global routing according to the candidate tree and the candidate template path through the CUGR2 algorithm.

[0104] S440: Generate a third tree topology that reduces congestion for the circuit mesh with congestion in the global routing scheme, and replace the tree topologies that are not selected in the tree forest of the circuit mesh with congestion with the third tree topology.

[0105] Specifically, for the network that still has congestion, the tree topology is regenerated to reduce the congestion, and then the newly generated tree topology is added to the corresponding tree forest, and the tree topology that has not been selected in the tree forest is deleted.

[0106] Further, the step of generating a third tree topology for reducing congestion for the circuit net with congestion in the global routing scheme in S440 may include:

[0107] A rewinding algorithm is used to generate a wiring tree for the circuit net with congestion in the global routing scheme as the third tree topology.

[0108] Furthermore, the above steps may be specifically as follows: using the undo rewinding algorithm of CUGR2 to generate the winding tree of each circuit net.

[0109] Specifically, the reason why DGR has an advantage over traditional routing algorithms in terms of routing quality is that it can select the tree topology and the routing template of the 2-pin wire net from a more global perspective. However, the tree topology of DGR is not generated from a global perspective. Therefore, the optimization space of DGR is limited by the non-globally optimal tree forest. This results in the global optimization achieved by DGR not taking into account the global optimization of the entire process. Its global environment consideration scope only includes the template routing process but not the tree generation stage before the template routing process.

[0110] In order to alleviate this problem, this embodiment hopes to expand the scope of global environment consideration to the tree generation stage and the template routing stage, that is, it is necessary to generate a tree topology that can maintain a shorter line length and effectively avoid congestion as much as possible, and complete a better routing effect than DGR with a more global consideration scope. On the basis of fully considering the global environment of the layout, specifically in the tree generation scheme, a highly effective tree structure that can avoid congestion can be generated in one go in the early stage through a high-precision global congestion prediction algorithm, or the tree structure can be iterated by feedback of real-time congestion results in the middle of the routing process. However, the former is a long-standing problem in the field of electronic design automation in the routing field. First, before the tree generation stage, it is necessary to make a high-precision prediction of the congestion that will be caused by all wire nets, and then generate a tree topology that can bypass the congestion for all wire nets based on the predicted congested area under the premise of fully considering the global situation; because it is difficult to obtain an accurate congestion distribution map in the tree generation stage, the latter approach adopts a gradual approach, and gradually makes the tree topology structure approach the global optimum through feedback iteration. When routing is in progress, the congestion distribution map is obtained in real time, and the topology is regenerated for the still congested wire nets while canceling their already routed results. Then the DGR process is resumed, thereby bypassing the congestion while still continuing the optimization from a global perspective.

[0111] The steps of dynamically updating the tree forest may include:

[0112] 1) After the optimization curve of the objective function of DGR tends to be flat, the optimal wiring solution has been obtained by using the optimizer in the current state.

[0113] 2) Then, for the still congested network, the undo and rewind algorithm of CUGR2 is used to regenerate its tree topology, and the generated tree topology is added to the tree topology candidate forest of the network, while the tree topology that was not selected last time is eliminated.

[0114] 3) After traversing the still congested network and dynamically updating the tree topology, re-do the DGR training optimization process. Repeat the above process several times until there is no room for optimization.

[0115] The reason for removing tree topologies is that the tree topologies that were not selected last time have been proven by the DGR selection mechanism to be inferior to the selected tree topologies from a global perspective, so they will not be selected by the optimizer again in the subsequent stages, so there is no need to keep them. At the same time, by removing redundant tree topologies, the size of the tree forest can be controlled, computing resources can be saved, and runtime overhead can be reduced.

[0116] By dynamically updating the tree, more global optimal possibilities can be created, which can create more optimization space for DGR optimization, so that the objective function can be further optimized.

[0117] Beneficial effects of this embodiment:

[0118] Only local adjustments are continued for congested nets, reducing unnecessary repeated calculations and improving the overall performance of the routing algorithm.

[0119] S450: Delete the tree forest corresponding to the circuit network without congestion in the global routing scheme.

[0120] Specifically, each time the dynamic tree is updated, since the number of congested nets only accounts for a small part of the total, in order to save computing resources, for most of the nets that are no longer congested, there is no need to continue to optimize their routing. Therefore, when performing the dynamic tree update, this embodiment can remove these nets that are no longer congested from the list that needs to be further optimized, and only retain those nets that are still congested for continued optimization.

[0121] Reference Figure 6 This embodiment provides an example flow chart of a global routing method based on a dynamic tree. In this embodiment, an algorithm for dynamically reducing the size of the tree forest needs to be executed before each training starts. Figure 7 From the perspective of tree forests, a specific implementation method for dynamically reducing the size of tree forests is demonstrated. First, all the wire nets are traversed to check whether they are in a congested state: if there are congested wiring units on the wiring path of the wire net, the wire net is determined to be in a congested state; conversely, if there are no congested wiring locations on the wiring path of the wire net, the wire net is determined to be not congested. If there is no congestion, the tree forest is eliminated and no longer participates in the next training. After adopting the method of dynamically reducing the size of the tree forest, the size of the tree forest participating in the training in each workflow cycle decreases rapidly with the increase in the number of cycles. Since the number of wire nets that may be congested accounts for a relatively low proportion of the total number of wire nets, after adopting the method of dynamically reducing the size of the tree forest, even if the tree is dynamically updated multiple times and then retrained, it will not lead to a linear increase in computing resource consumption. Compared with the one-time training adopted by DGR, this embodiment achieves a better trade-off between computing resource consumption and wiring effect.

[0122] Beneficial effects of this embodiment:

[0123] By introducing a method of dynamically reducing the size of the forest tree, recalculation is avoided and the computational efficiency of global routing is improved.

[0124] S460: Return the objective function of global routing and select one of the tree topologies from the two tree topologies of each tree forest as a candidate tree for each circuit network and select a candidate template path of the candidate tree until a preset end condition is reached, and use the current global routing scheme as the target global routing scheme for each circuit network.

[0125] It can be understood that after replacing the tree topology and deleting the tree forest of the non-congested line network, the tree forest of this embodiment undergoes dynamic update, and then S410 and subsequent steps are repeatedly executed with the current tree forest, realizing iterative selection of tree topology and template path, which can further reduce congestion.

[0126] Next, the solution of the embodiment of the present application will be introduced and explained in detail with reference to specific application examples.

[0127] The purpose of this embodiment is to overcome the shortcomings of low efficiency and insufficient congestion handling capability of traditional global routing algorithms when processing large-scale circuits, while improving the flexibility of the algorithm on the basis of DGR, and providing a global routing dynamic congestion optimization method based on GPU acceleration, which optimizes the congestion problem generated in the global routing process by introducing dynamic tree generation, local update and congestion tree processing mechanisms.

[0128] The purpose of this embodiment is achieved through the following technical solutions:

[0129] This embodiment includes three key steps: Step 1) First, in the pre-training preparation stage, a tree generation method that predicts congestion is used to clarify the construction method of the tree forest, so as to obtain a tree forest that takes into account both line length and congestion perception; Step 2) Second, after each training is completed, for the line network that is still congested, a dynamic tree update method is adopted for the tree topology in the tree forest to expand the possibility of global optimization; Step 3) Third, in response to the problem of computing resource waste that may be caused by repeated training in Step 2), a method for dynamically reducing the size of the candidate tree forest is proposed. By removing those non-congested line networks from the tree forest before training, the size of the tree forest is dynamically reduced, thereby saving computing resources and obtaining faster wiring speeds.

[0130] This embodiment constructs a new complete wiring process based on DGR through the above three steps: Figure 6, after the data such as the wire nets and layouts required for the wiring problem are input, for each wire net, the FLUTE algorithm is first used to obtain the rectangular Steiner minimum tree, and then the winding tree is obtained by using CUGR2, thereby completing the initialization of the tree forest construction. Compared with DGR, this embodiment obtains a clear tree forest initialization construction method. After that, the training process is entered, and the gradient descent method is used for training to obtain the minimum value of the objective function. Finally, the optimal tree topology and 2-pin wire net candidate path are obtained by judging whether the selection condition of the selection probability greater than 90% is met, thereby completing the selection of the tree forest. After the tree forest is selected, a new congestion-aware winding tree is regenerated for the wire nets that are still congested according to the current congestion situation, and then the tree topology that will no longer be selected in the corresponding wire nets in the tree forest is replaced, thereby dynamically updating the composition of the tree forest and obtaining more potential optimization space for a new round of retraining. Before starting a new round of training, for the wire nets that are not congested, they are removed from the tree forest to reduce the size of the tree forest. After completing the work of dynamically updating the tree and reducing the size of the tree forest, a new round of training can be started. By Figure 5 It can be seen that the complete routing process constitutes a loop, and the number of loops can be arbitrarily controlled according to the routing effect and time consumption. In contrast, DGR does not loop, and the coarse-grained tree forest processing method limits its routing effect.

[0131] pass Figure 2 and Figure 6 By comparison, we can see the changes before and after the above three steps are introduced in this embodiment on the basis of DGR. Among the three steps, the tree generation method for predicting congestion plays a role in the initial tree forest construction, and provides a tree forest construction that can take into account the line length and avoid congestion to a certain extent in the initial stage. The dynamic tree update method and the dynamic candidate tree forest size reduction method play a role between two training rounds. The two methods respectively process the congested and non-congested wire nets in the results of the previous round, and work together to cover all the wire nets in the tree forest. Improvement methods are adopted in terms of wiring effect and time consumption, respectively, to achieve a better balance between the contradiction between wiring effect and time consumption.

[0132] Next, a more specific embodiment will be described.

[0133] This embodiment uses the benchmark tests provided by the ISPD18 competition and ISPD19 competition of the International Symposium on Physical Design (ISPD) and the ICCAD19 competition of the International Conference on Computer-Aided Design (ICCAD), inputs the benchmark tests into the global routing results obtained by this patent, and then obtains the detailed routing results of the benchmark tests through relevant technical means. The platform configuration for running the global routing program is shown in Table 1.

[0134] Table 1

[0135]

[0136] The test results of this embodiment are shown in Table 2. The weight standard of ICCAD19 is adopted, and the wiring results are divided into three items: line length, through hole, and overflow.

[0137] Table 2

[0138]

[0139]

[0140] In addition to the implementation methods mentioned in this embodiment, the following changes can also be made: the number of tree updates can be controlled independently; and other tree generation algorithms are fully compatible.

[0141] Reference Figure 8 The embodiment of the present application further provides a global routing device based on a dynamic tree, which can implement the above-mentioned global routing method based on a dynamic tree, and the device includes:

[0142] A tree topology generating unit, used to generate a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weight for each circuit line network;

[0143] A tree forest construction unit, configured to construct the first tree topology and the second tree topology of each circuit network into a corresponding tree forest;

[0144] A tree and path selection unit, configured to select one of the tree topologies from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets and select a candidate template path for the candidate tree according to an objective function of global routing;

[0145] A global routing unit, used for determining a global routing scheme corresponding to the circuit network according to each of the candidate trees and each of the candidate template paths;

[0146] A tree forest updating unit, configured to generate a third tree topology for reducing congestion for the circuit network with congestion in the global routing scheme, and replace the tree topology that is not selected in the tree forest of the circuit network with congestion with the third tree topology;

[0147] A tree forest deletion unit, used for deleting the tree forest corresponding to the circuit network without congestion in the global routing scheme;

[0148] A repeated selection unit is used to return the objective function of global routing and select one of the tree topologies from the two tree topologies of each tree forest as a candidate tree for each circuit network and select a candidate template path of the candidate tree until a preset end condition is reached, and the current global routing scheme is used as the target global routing scheme for each circuit network.

[0149] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0150] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above-mentioned global wiring method based on a dynamic tree when executing the computer program. The electronic device can be any intelligent terminal including a tablet computer, a car computer, etc.

[0151] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0152] See also Fig. 9 , Fig. 9 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes:

[0153] The processor 901 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0154] The memory 902 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 902 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 902, and the processor 901 calls and executes the global routing method based on the dynamic tree in the embodiment of the present application;

[0155] Input / output interface 903, used to implement information input and output;

[0156] Communication interface 904, used to realize communication interaction between the device and other devices, which can be realized by wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.);

[0157] A bus 905 that transmits information between the various components of the device (e.g., the processor 901, the memory 902, the input / output interface 903, and the communication interface 904);

[0158] The processor 901 , the memory 902 , the input / output interface 903 and the communication interface 904 are connected to each other in communication within the device via a bus 905 .

[0159] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned dynamic tree-based global wiring method is implemented.

[0160] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiments, the functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0161] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0162] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0163] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0164] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0165] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0166] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0167] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0168] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0169] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0170] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0171] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0172] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A global routing method based on a dynamic tree, characterized in that: The method comprises the following steps: Generate a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weight for each circuit network; constructing the first tree topology and the second tree topology of each of the circuit networks into corresponding tree forests; Select one of the tree topologies from the two tree topologies of each tree forest as a candidate tree for each circuit network according to the objective function of global routing, and select a candidate template path for the candidate tree; Determine a global routing scheme corresponding to the circuit network according to each of the candidate trees and each of the candidate template paths; Generating a third tree topology that reduces congestion for the circuit net with congestion in the global routing scheme, and replacing the tree topologies that are not selected in the tree forest of the circuit net with congestion with the third tree topology; Deleting the tree forest corresponding to the circuit network without congestion in the global routing scheme; Return the objective function of global routing, select one of the two tree topologies of each tree forest as a candidate tree for each circuit network and select a candidate template path of the candidate tree until the preset end condition is reached, and use the current global routing scheme as the target global routing scheme for each circuit network.

2. The global routing method based on dynamic tree according to claim 1, characterized in that: The method of generating a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weight for each circuit network respectively includes the following steps: Generating a right-angle Steiner minimum tree with the shortest line length of each circuit network as the first tree topology; Performing template routing on the corresponding circuit network according to each of the right-angle Steiner minimum trees, thereby obtaining a congestion distribution diagram of each of the circuit network; A winding tree corresponding to each of the circuit nets is generated as the second tree topology according to each of the congestion distribution graphs using an undo rewind algorithm.

3. The global routing method based on dynamic tree according to claim 1, characterized in that: The generating of a third tree topology for reducing congestion for the circuit net having congestion in the global routing scheme comprises the following steps: A rewinding algorithm is used to generate a wiring tree for the circuit net with congestion in the global routing scheme as the third tree topology.

4. The global routing method based on dynamic tree according to claim 2, characterized in that: The step of generating a right-angle Steiner minimum tree with the shortest line length of each circuit network as the first tree topology comprises the following steps: The FLUTE algorithm is used to generate a rectangular Steiner minimum tree with the shortest line length of each circuit network as the first tree topology.

5. The global routing method based on a dynamic tree according to any one of claims 2 or 3, characterized in that: Generating the winding tree of each circuit net by using the undo rewinding algorithm comprises the following steps: The undo-rewind algorithm of CUGR2 is used to generate the routing tree for each of the circuit nets.

6. The global routing method based on dynamic tree according to claim 1, characterized in that: The step of selecting one of the two tree topologies in each of the tree forests as a candidate tree for each of the circuit nets according to the objective function of the global routing and selecting a candidate template path for the candidate tree comprises the following steps: Initialize first candidate probabilities of two of the tree topologies in each of the tree forests and second candidate probabilities of 2-pin wire nets of the two tree topologies; Performing significance calculation on each of the first candidate probabilities and each of the second candidate probabilities; Obtaining the minimum value of the objective function according to the result of the significance calculation and the gradient descent method, and then updating each of the first candidate probabilities and each of the second candidate probabilities; If the updated first candidate probability and the second candidate probability meet the selection condition, then in each of the tree forests, the tree topology corresponding to the largest first candidate probability is selected as the candidate tree, and the 2-pin wire net corresponding to the largest second candidate probability in the candidate tree is selected as the candidate template path; If the updated first candidate probability and the second candidate probability do not meet the selection condition, return to update each of the first candidate probabilities and each of the second candidate probabilities based on the result of the saliency calculation and the gradient descent method until the updated first candidate probability and the second candidate probability meet the selection condition.

7. The global routing method based on dynamic tree according to claim 6, characterized in that: The method further comprises the following steps: Determine whether the updated first candidate probability and the second candidate probability reach 90%; The updated probability of the first candidate and the probability of the second candidate reaching 90% are determined as meeting the selection condition; If the updated first candidate probability and the second candidate probability do not reach 90%, it is determined that the selection condition is not met.

8. A global routing device based on a dynamic tree, characterized in that: The device comprises: A tree topology generating unit, used to generate a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weight for each circuit line network; A tree forest construction unit, configured to construct the first tree topology and the second tree topology of each circuit network into a corresponding tree forest; A tree and path selection unit, configured to select one of the tree topologies from the two tree topologies of each tree forest as a candidate tree for each circuit network and select a candidate template path for the candidate tree according to an objective function of global routing; A global routing unit, used for determining a global routing scheme corresponding to the circuit network according to each of the candidate trees and each of the candidate template paths; A tree forest updating unit, configured to generate a third tree topology for reducing congestion for the circuit network with congestion in the global routing scheme, and replace the tree topology that is not selected in the tree forest of the circuit network with congestion with the third tree topology; A tree forest deletion unit, configured to delete the tree forest corresponding to the circuit network without congestion in the global routing scheme; A repeated selection unit is used to return the objective function of global routing and select one of the tree topologies from the two tree topologies of each tree forest as a candidate tree for each circuit network and select a candidate template path of the candidate tree until a preset end condition is reached, and the current global routing scheme is used as the target global routing scheme for each circuit network.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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