A display data writing method, a writing circuit and a display device

Abstract

This invention relates to a display data writing method, writing circuit, and display device in the field of data display. The method includes: during the backlight-on time of the current frame of the display, for all pixels of the display device, synchronously initializing and storing intermediate voltages based on a first scan signal; after initialization, for all pixels of the display device, line by line, pre-storing the data signal voltage required for the next frame of the display; after the backlight of the current frame of the display is turned off, resetting the pixel data voltage of the current frame of the display to a common electrode voltage; after resetting, for all pixels of the display device, synchronously reading the pre-stored data signal voltage for display in the next frame. This method reduces the overall display data writing time, which is beneficial for realizing display products with higher refresh rates and higher resolutions.

Description

Technical Field

[0001] This invention relates to the field of data display, and more specifically to a method for writing display data, a writing circuit, and a display device. Background Technology

[0002] In traditional field sequential or color sequential display data writing, the backlight can only be turned on after all screen data has been written and the liquid crystal has deflected to a stable state. Otherwise, screen chaos will occur. Therefore, the data writing and liquid crystal deflection time greatly compress the backlight turn-on time, making it difficult to improve the brightness of display devices, as well as difficult to improve refresh rate and resolution, increase power consumption, and increase the cost of backlight materials.

[0003] An improved display data writing process utilizes a signal storage capacitor Cs1 to pre-store the pixel data voltage of the next frame during backlight illumination. When switching frames, all pixels synchronously read the corresponding pixel data voltage from Cs1. This pixel data voltage register design saves pixel writing time and correspondingly increases backlight illumination time. However, this pixel circuit design faces charge sharing issues, which are detrimental to achieving high refresh rates and high resolutions in display devices. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a display data writing method, writing circuit and display device, which has the characteristics of achieving higher refresh rate and resolution of the display device.

[0005] In a first aspect, one embodiment provides a method for writing display data, including:

[0006] Intermediate voltage initialization storage: During the backlight-on time of the current frame's display, the intermediate voltage of all pixels on the display device is synchronously initialized and stored. Among them, the intermediate voltage of pixels with the same polarity of the data signal voltage in the next frame is configured to be the same.

[0007] Data signal voltage pre-storage: After the intermediate voltage initialization is completed, during the backlight on time of the current frame, for all pixels of the display device, the data signal voltage required for the next frame display is pre-stored line by line based on the intermediate voltage stored in the initialization.

[0008] Pixel data voltage reset: After the backlight of the current frame is turned off, the pixel data voltage of the current frame is reset to the common electrode voltage.

[0009] The data signal voltage is read by resetting the pixel data voltage of the current frame to the common electrode voltage. Then, for all pixels of the display device, the pre-stored data signal voltage is read synchronously for display of the next frame.

[0010] In a second aspect, one embodiment provides a display data writing circuit, including a first control circuit, a second control circuit, a third control circuit, a first signal storage capacitor Cs1, and a pixel capacitor Clc.

[0011] Based on the first control circuit, during the backlight-on time of the current frame display, in the initialization writing phase, the first signal storage capacitor Cs1 corresponding to each pixel is synchronously controlled to initialize and store the intermediate voltage. Among them, the intermediate voltage of pixels with the same polarity of the data signal voltage in the next frame is configured to be the same. In the data writing phase after the initialization writing phase, the first signal storage capacitor Cs1 corresponding to each pixel of the display device is controlled to pre-store the data signal voltage required for the next frame display line by line based on the initialized and stored intermediate voltage.

[0012] Based on the second control circuit, after the backlight of the current frame is turned off, the pixel data voltage of the current frame in the pixel capacitor Clc corresponding to each pixel is reset to the common electrode voltage.

[0013] Based on the third control circuit, for all pixels of the display device, the data signal voltage pre-stored in the first signal storage capacitor Cs1 corresponding to each pixel is synchronously read into the pixel capacitor Clc for display in the next frame.

[0014] Thirdly, one embodiment provides a display device including a display data writing circuit of any of the above embodiments.

[0015] Fourthly, in one embodiment, a computer-readable storage medium is provided, the medium storing a program that can be loaded by a processor and executed as the display data writing method described in any of the above embodiments.

[0016] The beneficial effects of this invention are:

[0017] Before pre-storing the data signal voltage required for the next frame, the intermediate storage voltage is initialized. The intermediate voltages of pixels with the same polarity as the data signal voltage for the next frame are configured to be the same. This reduces the charge required to write the data signal voltage separately for pre-storing the data signal voltage required for the next frame, thus reducing the time for pixels to pre-store the data signal voltage required for the next frame. This reduces the overall display data writing time, which is beneficial for achieving higher refresh rates and higher resolution display products. Moreover, the method is simple and easy to implement. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a display data writing circuit structure according to an embodiment of the prior art;

[0019] Figure 2 yes Figure 1 A schematic diagram of the display data writing timing based on the circuit structure shown;

[0020] Figure 3 This is a schematic diagram of a display data writing circuit structure according to another embodiment of the prior art;

[0021] Figure 4 yes Figure 3 A schematic diagram of the display data writing timing based on the circuit structure shown;

[0022] Figure 5 This is a schematic diagram of the display data writing method of this application;

[0023] Figure 6 Based on Figure 5 The control timing diagram of the method shown is as follows;

[0024] Figure 7 This is a schematic diagram of the pixel region structure of a specific embodiment of the data writing circuit shown in this application;

[0025] Figure 8 yes Figure 7 A schematic diagram of the peripheral circuit structure of the embodiment shown;

[0026] Figure 9 Based on Figure 7 and Figure 8 The control timing diagram of the embodiment shown is as follows;

[0027] Figure 10 This is a schematic diagram of a specific embodiment two of the data writing circuit shown in this application;

[0028] Figure 11 Based on Figure 10 The control timing diagram of the embodiment shown is as follows;

[0029] Figure 12 This is a schematic diagram of the structure of a specific embodiment three of the application for display data writing circuit;

[0030] Figure 13 Based on Figure 12 The control timing diagram of the embodiment shown is illustrated. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0032] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0033] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0034] To facilitate the explanation of the inventive concept of this application, the display data writing technology will be briefly described below.

[0035] In traditional field-sequential or color-sequential display driving technologies, please refer to... Figure 1 The display driver circuit shown is a writing circuit for one pixel of a display device. It includes a MOSFET and a pixel capacitor Clc. The connection node between the MOSFET and the pixel capacitor Clc is the pixel electrode node. The gate of the MOSFET is connected to the scan signal line Scan, and one of its source and drain terminals is connected to the data signal voltage line Data. Please refer to the following for the driving timing. Figure 2 The backlight can only be turned on to display data after all rows of screen data have been written and the liquid crystal deflection has stabilized. Otherwise, screen chaos will occur. Therefore, the data writing and liquid crystal deflection time will greatly compress the backlight turn-on time, making it difficult to improve the brightness of the display device, as well as the refresh rate and resolution, increase power consumption and increase the cost of backlight materials.

[0036] To reduce LCD driving time and increase backlight start time, an improved scheme involves pre-storing the data signal voltage required for the next frame during backlighting. When switching frames, the residual charge on the pixel capacitors is first eliminated, and then the pre-stored data signal voltage is synchronously read. This saves pixel data writing time and correspondingly increases backlight illumination time. A display driving circuit designed based on this control method can be found here. Figure 3 For display driver timings, please refer to [reference]. Figure 4 . Figure 3 Improved drive circuit and Figure 1 The traditional 1T2C pixel design differs in that it includes a pixel data signal write switch TFT T1, a first signal storage capacitor Cs1, a signal transfer switch TFT T2, a pixel capacitor Clc, and a reset switch TFT T3. The first signal storage capacitor Cs1 is used to pre-store the data signal voltage required for the next frame. The signal transfer switch TFT T2 transfers the pre-stored data signal voltage to the corresponding pixel capacitor Clc. The reset switch TFT T3 removes any residual charge on the pixel capacitor Clc to prevent color shift and brightness differences caused by residual charge. This circuit design allows the first signal storage capacitor Cs1 to pre-store the data signal voltage for the next frame during backlight illumination, and all pixels synchronously read the data signal voltage from the corresponding Cs1 during frame switching. This pixel data voltage register design reduces pixel write time and correspondingly increases backlight illumination time.

[0037] However, the applicant discovered in their research that the above pixel circuit design faces the problem of charge sharing, thus requiring a large first data storage capacitor Cs1. This results in a longer charging time for each row of Cs1 during the pre-charging stage, which is detrimental to achieving high refresh rates and high resolutions in the display device. Simultaneously, due to the need for polarity reversal in the liquid crystal drive, the voltage difference between the data signal voltages of two frames is large (e.g., the data signal voltage of the previous frame is greater than the common electrode voltage Vcom, while the voltage of the next frame must be less than Vcom, otherwise it will cause liquid crystal polarization, leading to problems such as DC ghosting). This makes the required charging voltage difference for the first signal storage capacitor Cs1 large, further increasing the charging difficulty. This charging limitation also restricts the increase in Cs1 voltage. Therefore, during charge sharing, a higher pre-charge voltage is required for Cs1, necessitating an increased data signal voltage supply range to meet the operating voltage range of the liquid crystal, placing higher demands on the output voltage range of the data signal IC.

[0038] Based on this, this application provides a display data writing method. Before pre-storing the data signal voltage required for the next frame, an intermediate storage voltage is initialized. This intermediate voltage is between the data signal voltage with the largest difference from the common electrode voltage Vcom under the corresponding polarity and Vcom. This reduces the charge required for the separate pre-storage of the subsequent maximum data signal voltage, thus reducing the maximum time required for the separate pre-storage of each subsequent line of data signal voltage. This reduces the overall pixel data writing time of the display device, which is beneficial for achieving higher refresh rates and higher resolution display devices. Please refer to [reference needed]. Figure 5 The display data writing method includes:

[0039] Step S10: Initialize and store intermediate voltage. During the backlight-on time of the current frame, the intermediate voltage is synchronously initialized and stored for all pixels of the display device. Among them, the intermediate voltage of pixels with the same polarity of the data signal voltage in the next frame is configured to be the same.

[0040] Because of the intermediate voltage during initial storage, the storage time for the data voltage required for each row of pixels in the next frame under the corresponding polarity can be reduced. This reduces the overall time required for the data voltage of the next frame, thereby reducing the overall data writing time and facilitating the realization of higher refresh rates and higher resolution display products.

[0041] In one embodiment, synchronously initializing the storage intermediate voltage includes: synchronously starting to load a first scan signal and an intermediate voltage initialization storage signal. The loading time of the intermediate voltage initialization storage signal is longer than the loading time of the first scan signal, thereby ensuring that the pre-storage node or the first storage capacitor Cs1 is charged to the required potential. In another embodiment, the intermediate voltage is the average of the data signal voltage and Vcom that differs most from the common electrode voltage Vcom under the corresponding polarity of each pixel in the next frame, in order to minimize the overall display data write time.

[0042] Step S20: Data signal voltage pre-storage. After the intermediate voltage initialization is completed, during the backlight-on time of the current frame, for all pixels of the display device, the data signal voltage required for the next frame is pre-stored line by line based on the initialized and stored intermediate voltage.

[0043] After the intermediate voltage initialization is completed, scan signals are loaded line by line for all pixels of the display device. Based on the initialized and stored intermediate voltage, the data signal voltage required for the next frame is pre-stored to the required potential. Because the storage time for the data voltage required for each row of pixels is reduced, the overall storage time for the data voltage required for the next frame is reduced.

[0044] Step S30: Pixel data voltage reset. After the backlight of the current frame is turned off, the pixel data voltage of the current frame is reset to the common electrode voltage.

[0045] Step S40, Data signal voltage reading. After resetting the pixel data voltage of the current frame to the common electrode voltage, the pre-stored data signal voltage is synchronously read for all pixels of the display device for display of the next frame.

[0046] Before pre-storing the data signal voltage required for the next frame, this display data writing method initializes an intermediate storage voltage. This intermediate voltage is between the data signal voltage that differs most from the common electrode voltage Vcom under the corresponding polarity and Vcom. This reduces the charge required to write the data signal voltage required for pre-storing the next frame separately, thus reducing the time for each pixel to pre-store the data signal voltage required for the next frame. This reduces the overall display data writing time, which is beneficial for achieving higher refresh rates and higher resolution display products. Moreover, the method is simple and easy to implement.

[0047] One embodiment of this application provides a display data writing circuit for implementing a display data writing method. The circuit includes a first control circuit, a second control circuit, a third control circuit, a first signal storage capacitor Cs1, and a pixel capacitor Clc. Each pixel of the display device corresponds to a first signal storage capacitor Cs1 and a pixel capacitor Clc.

[0048] The first signal storage capacitor Cs1 is used to initialize and store an intermediate voltage during the backlight-on time of the current frame display. This intermediate voltage is between the data signal voltage that differs most from the common electrode voltage Vcom under the corresponding polarity of the next frame display and Vcom. After a buffer time, the first signal storage capacitor Cs1 is pre-stored based on this intermediate voltage, so that the data voltage stored in the first signal storage capacitor Cs1 reaches the data signal voltage required for the next frame display.

[0049] The display device uses column reversal or row reversal to achieve polarity reversal in its pixel areas. Please refer to [reference needed]. Figure 6The following explanation uses column reversal as an example. In a given frame, odd-numbered pixel electrodes have a positive voltage, while even-numbered pixel electrodes have a negative voltage. In the next frame, the odd-numbered pixel electrodes have a negative voltage, and the even-numbered pixel electrodes have a positive voltage, and so on. Using the Vcom voltage as a reference, and taking odd-numbered columns as an example, assuming that in frame N (where N is a natural number), the odd-numbered pixel voltage is negative, then in frame N+1, the odd-numbered pixel voltage is positive. According to the pre-storage principle, during the light emission time of frame N, the data signal voltage of frame N+1 is written to the first signal storage capacitor Cs1 corresponding to the odd-numbered columns. Therefore, a positive voltage, i.e., a voltage greater than or equal to Vcom, needs to be written. For even-numbered columns, assuming that the pixel voltage of the even-numbered column is positive in the Nth frame, then the pixel voltage of the even-numbered column is negative in the N+1th frame. According to the working principle of pre-storage, the data signal voltage of the N+1th frame is written to the first signal storage capacitor Cs1 corresponding to the even-numbered column during the light emission time of the Nth frame. Therefore, a negative polarity voltage, that is, a voltage less than or equal to Vcom, needs to be written.

[0050] For the first signal storage capacitor Cs1 of a certain odd-numbered pixel column 'a', assuming the data signal voltage to be written is at its maximum (Vdata_max) in the Nth frame, then the charge Q1 = C * V = C required to write the data signal voltage needed to display the image with positive polarity. Cs1 *(Vdata_max-Vcom), where C Cs1 Let Cs1 be the capacitance value of the first signal storage capacitor. If, during the initial charging phase, the first signal storage capacitor Cs1 has been pre-charged to the average of the data signal voltage Vdata_max and Vcom, which have the largest difference between the positive polarity and the common electrode voltage Vcom, then...

[0051] Vcom + (Vdata_max - Vcom) / 2 = (Vdata_max + Vcom) / 2, then when writing data signal voltage to this pixel, the charge to be written is Q2 = C * V = C. Cs1 *(Vdata_max-(Vdata_max+Vcom) / 2)=C Cs1 *(Vdata_max-Vcom) / 2 means that only half of the charge needs to be added to complete the data signal writing.

[0052] For a given odd-numbered pixel b, with a first signal storage capacitor Cs1, in the Nth frame, assuming the required data signal voltage is minimum, i.e., Vcom, then to satisfy the data signal voltage required for displaying the image with positive polarity, the charge Q3 = C * V = C needs to be written. Cs1*(Vcom-Vcom), meaning no charge needs to be written. If, during the initial charging phase, the first signal storage capacitor Cs1 has already been pre-charged to the average of the data signal voltage Vdata_max and Vcom, which have the largest difference between the positive polarity and the common electrode voltage Vcom, i.e., (Vdata_max+Vcom) / 2, then when writing the data signal voltage to this pixel, the charge to be written is Q4=C*V=C. Cs1 *(Vcom-(Vdata_max+Vcom) / 2)=C Cs1 *(Vcom-Vdata_max) / 2. This gives the required write charge amount and the required write charge C for pixel a. Cs1 *(Vdata_max-Vcom) / 2 are equal in size but opposite in direction. Therefore, it can be concluded that, using the driving method proposed in this paper, the maximum charging charge required for the first signal storage capacitor Cs1 of all pixels is reduced by half during the row-by-row data signal voltage writing stage.

[0053] Similarly, for even-numbered columns of pixels, the first signal storage capacitor Cs1 of these pixels needs to be pre-charged with a negative polarity data signal voltage (i.e., ≤Vcom) in the Nth frame. Therefore, during the initial charging phase, the even-numbered columns of pixels are initialized with the intermediate value between the minimum data voltage signal Vdata_min and the Vcom voltage, for example, Vcom - (Vcom - Vdata_min) / 2 = (Vcom - Vdata_min) / 2. This also achieves the effect of halving the maximum charging charge required by the first signal storage capacitor Cs1 during the data signal voltage writing phase.

[0054] In frame N+1, due to the polarity reversal requirement, the odd-numbered columns are pre-charged with negative voltage, and the even-numbered columns are pre-charged with positive voltage. The initial charging method is similar to the process described above, except that the initial intermediate voltage value of the odd-numbered columns becomes the midpoint between the minimum data signal voltage and Vcom, and the initial intermediate voltage value of the even-numbered columns becomes the midpoint between the maximum data signal voltage and Vcom.

[0055] This process is repeated, with two odd-even frames as a cycle. While completing the polarity reversal, the initialization writing and data signal voltage writing corresponding to all frames can be achieved, thus achieving the effect described in this proposal.

[0056] Based on the above analysis, in one embodiment, the intermediate voltage is the average of the data signal voltage and Vcom that differs most from the common electrode voltage Vcom under the corresponding polarity of each pixel in the next frame, so as to minimize the overall display data writing time.

[0057] After the backlight of the current frame (the Nth frame) is turned off, before the backlight of the next frame is turned on, the pixel capacitor Clc is first reset to eliminate the charge that was originally left inside, and then the data signal voltage pre-stored in the corresponding first signal storage capacitor Cs1 is transferred to the pixel capacitor Clc to prepare for the display of the next frame.

[0058] To control the operation of the first signal storage capacitor Cs1 and the pixel capacitor Clc, please refer to... Figure 6 The first control circuit, the second control circuit, and the third control circuit are described below.

[0059] Based on the first control circuit, during the backlight-on time of the current frame display (the display time of the current frame), in the initialization writing phase, the first signal storage capacitor Cs1 corresponding to each pixel of the display device is synchronously controlled to initialize and store the intermediate voltage. Among them, the intermediate voltage of pixels with the same polarity of the data signal voltage in the next frame is configured to be the same.

[0060] During the backlight-on time of the current frame display, in the initialization writing phase, based on the first control circuit, the first signal storage capacitor Cs1 corresponding to each pixel of the display device is initialized to store the intermediate voltage. This intermediate voltage is between the data signal voltage with the largest difference from the common electrode voltage Vcom under the corresponding polarity of each pixel in the next frame and Vcom. Moreover, the intermediate voltage of pixels with the same polarity of the data signal voltage in the next frame is configured to be the same. This can reduce the charge required for the individual pre-storage of the subsequent maximum data signal voltage, and thus reduce the maximum time required for the individual pre-storage of each line of data signal voltage. This reduces the overall pixel data writing time of the display device, which is beneficial for the realization of higher refresh rate and higher resolution display devices. At the same time, it can make the increase of the first signal storage capacitor Cs1 less restricted. Therefore, when charging the pixel electrode, under the same data signal voltage, it can be charged to a higher potential (and to a lower potential in the case of negative polarity). In this way, the voltage range requirement of the data signal IC output is also reduced.

[0061] In one embodiment, the intermediate voltage is the average of the data signal voltage and Vcom that differs most from the common electrode voltage Vcom under the corresponding polarity of each pixel in the next frame.

[0062] In the data writing stage following the initialization writing stage, based on the first control circuit controlling the first signal storage capacitor Cs1 corresponding to each pixel of the display device, the data signal voltage required for the next frame of the display is pre-stored line by line on the basis of the intermediate voltage of the initial storage.

[0063] Based on the initialization write phase, the maximum time required for separate pre-storage of each line of data signal voltage is reduced during the data write phase, and the voltage range requirement for the data signal IC output is also reduced.

[0064] Based on the second control circuit, after the backlight of the current frame is turned off, the pixel data voltage of the current frame displayed in the pixel capacitor Clc corresponding to each pixel is reset to the common electrode voltage (Reset signal). In this way, the charge that was originally left on the pixel capacitor is eliminated, so as to prevent color change and brightness difference effects caused by residual charge.

[0065] Based on the third control circuit, for all pixels of the display device, the pre-stored data signal voltage in the first signal storage capacitor Cs1 corresponding to each pixel is synchronously read into the pixel capacitor Clc (Tran signal) for display in the next frame. Thus, when switching display frames, all pixels synchronously read the pre-stored pixel data voltage, saving pixel data voltage writing time.

[0066] The following detailed description uses specific embodiments of the three write circuits as examples. Specific Implementation Example 1

[0068] Please refer to Figure 7 and Figure 8 The writing circuit includes a pixel data voltage writing array, which comprises multiple pixel data voltage writing units, each corresponding to one pixel. For clarity, the accompanying drawings are provided. Figure 7 The diagram shows a 2×2 pixel data voltage writing array, but is not limited to 2×2.

[0069] Each write unit includes a scan signal input terminal, a data signal voltage input terminal, a reset signal terminal, a reference potential connection terminal, a pre-stored data signal voltage transfer control terminal, a signal write switch T1, a signal transfer switch T2, a reset switch T3, a first signal storage capacitor Cs1, and a pixel capacitor Clc.

[0070] Please refer to Figure 7 The scan signal input terminal is used to connect to the scan signal line Scan, and the scan signal input terminals of different row writing units are connected to different scan signal lines. Figure 7Since this is a 2×2 pixel data voltage writing array, only two rows are shown here. Therefore, only the first scan signal line Scan1 corresponding to the first row of writing units and the second scan signal line Scan2 corresponding to the second row of writing units are shown. The data signal voltage input terminal is used to connect to the data signal voltage line Data, and the data signal voltage input terminals of different columns of writing units are connected to different data signal voltage lines Data. Only two columns are shown here, therefore, only the first data signal voltage line Data1 corresponding to the first column of writing units and the second data signal voltage line Data2 corresponding to the second column of writing units are shown. The reset signal terminal is used to connect to the reset signal line Reset. The reference voltage connection terminal is used to connect to the reference electrode Com, which provides the reference voltage Vcom. The pre-stored data signal voltage transfer control terminal is used to connect to the data signal voltage transfer control signal line Tran. The signal writing switch T1, signal transfer switch T2, and reset switch T3 are all MOSFETs. The MOSFET here can be either an NMOS or a PMOS transistor. An NMOS transistor turns on based on a high-level signal, while a PMOS transistor turns on based on a low-level signal. Therefore, the choice between using an NMOS or PMOS transistor can be based on a control signal. In the specific embodiments of this application, NMOS transistors are used, but this does not limit the scope of protection of this application. Those skilled in the art can adapt the control principle to replace all or part of the switches with PMOS transistors.

[0071] For the specific internal connection structure, the gate of the signal write switch T1 is connected to the scan signal input terminal, and one source / drain is connected to the data signal voltage input terminal. The other source / drain of the signal write switch T1 is connected to one source / drain of the signal transfer switch T2. The connection node between them serves as a pre-charge node. One end of the first signal storage capacitor Cs1 is connected to this pre-charge node, and the other end is connected to a fixed potential. This fixed potential can be any one of the scan signal input terminal, the reference voltage connection terminal, or the pre-stored data signal voltage transfer control terminal. The other end of the first signal storage capacitor Cs1 is connected to a fixed potential, which can be connected to the corresponding scan signal line Scan, the reference electrode Com, or the data signal voltage transfer control signal line Tran.

[0072] In one embodiment, to stabilize the pixel node voltage and reduce flicker caused by voltage changes, the writing unit further includes a second signal storage capacitor Cs2. One end of the second signal storage capacitor Cs2 is connected to the pixel node, and similarly to the first signal storage capacitor Cs1, the other end of the second signal storage capacitor Cs2 is connected to a fixed potential. Here, it can be connected to the corresponding scan signal line Scan, reference electrode Com, or data signal voltage transfer control signal line Tran.

[0073] The gate of signal transfer switch T2 is connected to the pre-stored data signal voltage transfer control terminal. The other source / drain terminal of signal transfer switch T2 is connected to one source / drain terminal of reset switch T3; the connection point serves as a pixel node. One end of pixel capacitor Clc is connected to this pixel node, and the other end is connected to the reference voltage connection terminal.

[0074] The gate of reset switch T3 is connected to the reset signal input terminal, and the other source-drain terminal is connected to the reference voltage connection terminal.

[0075] The second control circuit includes a reset switch T3, and the third control circuit includes a signal transfer switch T2.

[0076] Please refer to Figure 8 Based on the above circuit, after the backlight of the current frame is turned off, a high-level signal is first sent to the reset switch T3 via the reset signal line Reset to eliminate the charge remaining on the pixel capacitor, thus preventing color shift and brightness differences caused by residual charge. After this high-level signal ends, a high-level signal is sent to the signal transfer switch T2 via the data signal voltage transfer control signal line Tran, so that all pixels of the display device synchronously read the data signal voltage pre-stored in the first signal storage capacitor Cs1 corresponding to each pixel and transfer it to the pixel capacitor Clc. In this way, preparation is made for the display of the next frame when switching frames.

[0077] Please refer to Figure 7 and Figure 8 In a specific embodiment, in addition to the writing unit described above, it also includes peripheral circuitry, such as... Figure 8 As shown, Figure 8 The interior of the dashed box is Figure 7 The pixel data voltage is written to the array (pixel area).

[0078] from Figure 7 and Figure 8 As can be seen, there are multiple Scan signal lines, each connected to a row of the pixel data voltage writing array; there are also multiple Data signal voltage lines, each connected to a column of the pixel data voltage writing array.

[0079] In one embodiment, based on Figure 8 The first control circuit includes a write switch T1, multiple scan signal switches (T11, T12) and multiple data voltage switches (T21, T22).

[0080] There is a one-to-one correspondence between multiple scan signal switches, multiple scan signal enable inputs, and multiple scan signal enable outputs. The multiple scan signal enable inputs are used to connect to the scan signal enable line En_Scan, and the multiple scan signal enable outputs are used to connect to their respective scan signal lines Scan. Each scan signal switch is a MOSFET. The gate of this MOSFET is connected to its corresponding scan signal enable input, one source / drain is connected to its corresponding scan signal enable output, and the other source / drain is connected to the high-level signal line VGH. This high-level signal line VGH provides a high potential for the scan signal line Scan to operate normally, thus enabling the write switch T1.

[0081] In one embodiment, the multiple scan signal switches (T11, T12) and the multiple data voltage switches (T21, T22) are all NMOS transistors.

[0082] Multiple data voltage switches correspond one-to-one with multiple input voltage enable inputs and multiple input voltage enable outputs. The multiple input voltage enable inputs are used to connect to the data voltage signal enable line En_Data, and the multiple input voltage enable outputs are used to connect to their respective data signal voltage lines Data. Each data voltage switch is a MOSFET, with its gate connected to its corresponding voltage enable input, one source / drain connected to its corresponding voltage enable output, and the other source / drain connected to its corresponding reference voltage VREF. Odd-numbered data voltage switches are connected to the first reference voltage VREF1, and even-numbered data voltage switches are connected to the second reference voltage VREF2.

[0083] In one embodiment, EN_Scan, EN_Data, VREF1, and VREF2 are all global power signals, provided by a T-con IC or other signal generation unit, and are positioned around the pixel display area using a thin-film process.

[0084] Based on the specific circuit described above, polarity reversal is achieved using a column reversal method. Please refer to [reference needed]. Figure 9In the current frame (frame N), the odd-numbered pixel electrodes have a negative voltage, requiring a positive voltage to be applied to their pre-charge nodes; the even-numbered pixel electrodes have a positive voltage, requiring a negative voltage to be applied to their pre-charge nodes. The next frame (frame N+1) follows the opposite pattern. During the initialization write phase of frame N, the scan signal enable line En_Scan switches to a high level, and multiple scan signal switches (T11, T12) are opened, connecting the scan signal lines Scan of all rows to the high-level signal line VGH. This allows the write switch T1 of each write unit to be turned on. Simultaneously with the scan signal enable line En_Scan switching to high, the data voltage signal enable line En_Data also switches to high. Multiple data voltage switches (T21, T22) open, connecting the odd-numbered column data signal voltage lines Data (Data1) to the first reference voltage VREF1. Therefore, the odd-numbered column data signal voltage lines Data are charged to the positive intermediate voltage Vcom + (Vdata_max - Vcom) / 2. The even-numbered column data signal voltage lines Data (Data2) are connected to the second reference voltage VREF2, thus charging to the negative intermediate voltage Vcom - (Vcom - Vdata_min) / 2. Subsequently, the scan signal enable line En_Scan and the data voltage signal enable line En_Data are switched to low, ensuring that multiple scan signal switches (T11, T12) and multiple data voltage switches (T21, T22) are closed. This allows the scan signal lines Scan for each row and the data signal voltage lines Data for each column to achieve the required charge and timing, completing the initialization write phase.

[0085] In one embodiment, to ensure that the data signal voltage lines Data of each column are charged to the required potential, the high-level time of the data voltage signal enable line En_Data is longer than the high-level time of the scan signal enable line En_Scan.

[0086] Taking odd-numbered columns as an example, assuming that in the Nth frame, the voltage of the first column of pixels is a negative voltage (Vpixel-Vcom≤0, where Vpixel is the pixel pole node voltage), then the pixel voltage corresponding to the N+1th frame should be a positive voltage (Vpixel-Vcom≥0). According to the working principle of the pre-storage method, the light emission time in the Nth frame corresponds to the data signal voltage of the N+1th frame written to the storage capacitor Cs1, so a positive voltage needs to be written.

[0087] Before writing data to the first signal storage capacitor Cs1 of each row and before the voltage is absorbed, all row Scan control lines are simultaneously set to high voltage square wave pulses. Write switch T1 is turned on, and the signal of the data signal voltage line Data is initialized to the intermediate potential of the first signal storage capacitor Cs1 through write switch T1. This can be the average value of the data signal voltage and the common electrode voltage Vcom that differs the most from the voltage of the common electrode under the corresponding polarity of each pixel in the next frame.

[0088] Because the display screen switches constantly during the display process, and a single pixel can display all gray levels from the lowest to the highest, the charging time for each row of Cs1 is generally set to the same width, and charging must be completed even at the gray level with the maximum voltage difference. Therefore, based on the circuit structure of Specific Embodiment 1, the maximum charging charge required by Cs1 during the data signal voltage writing stage is halved, thus significantly reducing the writing time for each row. This reduces the total time required for the data writing stage, which is beneficial for driving higher refresh rate and higher resolution display products.

[0089] The same applies to even-numbered sequences, and will not be elaborated further here.

[0090] During this process, the corresponding outputs of the scan signal IC and data signal IC connected to the Scan and Data lines are set to a high-impedance state (Hi-Z) to ensure that the output signal of the scan signal IC is not short-circuited with VGH. The output of the data signal IC is not short-circuited with VREF1 and VREF2. After ensuring that multiple scan signal switches (T11, T12) and multiple data voltage switches (T21, T22) are closed, the scan signal IC and data signal IC will output normally, completing the subsequent data writing process.

[0091] In the N+1th frame, the operation is similar; according to the polarity reversal requirement, the voltages of VREF1 and VREF2 will switch between each other. This process repeats, with two odd and even frames forming a cycle, to achieve the above function.

[0092] The gate control unit and data signal unit that this control circuit works with are not limited to scan signal ICs and data signal ICs, but can also be other similar signal output units, such as GOA (Gate IC on array) and SOA (Source IC on array) fabricated on the periphery of the display area using thin film technology.

[0093] If the scan signal IC and data signal IC can directly implement the voltage and timing of the data signal in the required initialization phase, it is also feasible, and it is no longer necessary to... Figure 7 and Figure 8 Required peripheral control circuits and corresponding power signals. Specific Implementation Example 2

[0095] Please refer to Figure 10 Unlike the specific circuit structure of Embodiment 1, the write unit further includes a first pre-charge control switch T4. A reference voltage connection terminal is used to connect to a reference electrode. Specifically, the reference voltage connection terminal of the odd-numbered row write units is connected to the first reference electrode Com_Odd, and the reference voltage connection terminal of the even-numbered row write units is connected to the second reference electrode Com_Even. The first pre-charge control switch T4 is a MOSFET, with its gate connected to the scan signal input terminal, one source / drain connected to the pre-charge node, and the other source / drain connected to the reference voltage connection terminal. The first control circuit includes a signal write switch T1 and the first pre-charge control switch T4.

[0096] In this specific embodiment, the initialization write signal is not provided by sharing the Vdata signal, but is instead provided by the first reference signal Vcom_Odd and the second reference signal Vcom_Even, thereby enabling the initialization process of the first signal storage capacitor Cs1 under row inversion drive. For the above structure, please refer to... Figure 11 This method can achieve similar technical effects to Specific Embodiment 1, but compared to Specific Embodiment 1, it has the advantage of simplifying the peripheral control circuit and reducing the number of additional required signals VREF1 / VREF2. Similarly, Vcom_Odd and Vcom_Even can also be routed in odd and even columns, which can also realize the initialization process of the first signal storage capacitor Cs1 in column reversal mode, which will not be described in detail here. Specific Implementation Example 3

[0098] Please refer to Figure 12 Unlike the specific circuit structure of Embodiment 1, the writing unit further includes a second precharge control switch T5 and a precharge signal control terminal. The precharge control signal input terminal is used to connect to the precharge control signal line. Specifically, the precharge control signal input terminal of the odd-numbered column writing unit is used to connect to the first control signal line VREF_Odd, and the precharge control signal input terminal of the even-numbered column writing unit is used to connect to the second control signal line VREF_Even. The second precharge control switch T5 is a MOSFET, with its gate connected to the scan signal input terminal, one source and drain connected to the precharge node, and the other source and drain connected to the precharge control signal input terminal. The first control circuit includes a signal writing switch T1 and a second precharge control switch T5.

[0099] In this specific embodiment, the initialization write signal is not provided by sharing the Vdata signal. Instead, additional global signals (the first control signal line VREF_Odd and the second control signal line VREF_Even) are used as the signal source, thereby enabling the initialization process of the first signal storage capacitor Cs1 under column inversion drive. For the above structure, please refer to... Figure 13This method can achieve similar technical effects to Specific Embodiment 1, but compared to Specific Embodiment 1, it has the advantage of simplifying the peripheral control circuit and reducing the number of additional required signals VREF1 / VREF2. Similarly, the first control signal line VREF_Odd and the second control signal line VREF_Even can also be routed in odd and even rows, which can also realize the initialization process of the first signal storage capacitor Cs1 in row inversion mode, which will not be described in detail here.

[0100] One embodiment of this application provides a display device that includes the display data writing circuit of any of the above embodiments. Based on the display data writing circuit in the above embodiments, the display device can achieve a higher refresh rate and resolution.

[0101] One embodiment of this application provides a computer-readable storage medium storing a program, the stored program including a display data writing method that can be loaded by a processor and processed in any of the above embodiments.

[0102] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0103] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A display data writing circuit, characterized in that, It includes a first control circuit, a second control circuit, a third control circuit, a first signal storage capacitor Cs1, and a pixel capacitor Clc; Based on the first control circuit, during the backlight-on time of the current frame display, in the initialization writing phase, the first signal storage capacitor Cs1 corresponding to each pixel is synchronously controlled to initialize and store the intermediate voltage. Among them, the intermediate voltage of pixels with the same polarity of the data signal voltage in the next frame is configured to be the same. In the data writing phase after the initialization writing phase, the first signal storage capacitor Cs1 corresponding to each pixel of the display device is controlled to pre-store the data signal voltage required for the next frame display line by line based on the initialized and stored intermediate voltage. The intermediate voltage is between the data signal voltage with the largest difference from the common electrode voltage Vcom under the corresponding polarity and Vcom. Based on the second control circuit, after the backlight of the current frame is turned off, the pixel data voltage of the current frame in the pixel capacitor Clc corresponding to each pixel is reset to the common electrode voltage. Based on the third control circuit, for all pixels of the display device, the data signal voltage pre-stored in the first signal storage capacitor Cs1 corresponding to each pixel is synchronously read into the pixel capacitor Clc for display in the next frame; The writing circuit includes a pixel data voltage writing array, which includes multiple pixel data voltage writing units, each writing unit corresponding to a pixel. For each write unit, there are scan signal input terminal, data signal voltage input terminal, reset signal terminal, reference potential connection terminal, pre-stored data signal voltage transfer control terminal, signal write switch T1, signal transfer switch T2, reset switch T3, first signal storage capacitor Cs1 and pixel capacitor Clc; The scan signal input terminal is used to connect to the scan signal line Scan, and the scan signal input terminals of different row write units are connected to different scan signal lines; the data signal voltage input terminal is used to connect to the data signal voltage line Data, and the data signal voltage input terminals of different column write units are connected to different data signal voltage lines; the reset signal terminal is used to connect to the reset signal line Reset, the reference voltage connection terminal is used to connect to the reference electrode Com, and the pre-stored data signal voltage transfer control terminal is used to connect to the data signal voltage transfer control signal line Tran; the signal write switch T1, the signal transfer switch T2, and the reset switch T3 are all MOSFETs; The gate of the signal write switch T1 is connected to the scan signal input terminal, and one source and drain are connected to the data signal voltage input terminal; the other source and drain of the signal write switch T1 is connected to one source and drain of the signal transfer switch T2, and the connection node between them serves as a pre-charge node; one end of the first signal storage capacitor Cs1 is connected to the pre-charge node, and the other end is connected to a fixed potential, which includes any one of the scan signal input terminal, the reference voltage connection terminal, and the pre-stored data signal voltage transfer control terminal; The gate of signal transfer switch T2 is connected to the pre-stored data signal voltage transfer control terminal; the other source and drain of signal transfer switch T2 are connected to one source and drain of reset switch T3, and the connection point between them serves as a pixel pole node; the gate of reset switch T3 is connected to the reset signal input terminal, and the other source and drain are connected to the reference voltage connection terminal; one end of pixel capacitor Clc is connected to the pixel pole node, and the other end is connected to the reference voltage connection terminal; The second control circuit includes a reset switch T3, and the third control circuit includes a signal transfer switch T2; There are multiple Scan signal lines, each Scan line is connected to a row of the pixel data voltage writing array; there are multiple Data signal voltage lines, each Data line is connected to a column of the pixel data voltage writing array. The first control circuit includes a write switch T1, multiple scan signal switches, and multiple data voltage switches; The plurality of scan signal switches correspond one-to-one with the plurality of scan signal enable input terminals and the plurality of scan signal enable output terminals. The plurality of scan signal enable input terminals are used to connect to the scan signal enable line En_Scan, and the plurality of scan signal enable output terminals are used to connect to their respective scan signal lines Scan. For any scan signal switch, it is a MOS transistor. The gate of the MOS transistor is connected to its corresponding scan signal enable input terminal, one source and drain are connected to its corresponding scan signal enable output terminal, and the other source and drain are connected to the high-level signal line VGH. The high-level signal line VGH is used to provide a high potential for the scan signal line Scan to work normally, so as to open the write switch T1. The plurality of data voltage switches correspond one-to-one with a plurality of input voltage enable input terminals and a plurality of input voltage enable output terminals. The plurality of input voltage enable input terminals are used to connect to the data voltage signal enable line En_Data, and the plurality of input voltage enable output terminals are used to connect to their respective data signal voltage lines Data. Each data voltage switch is a MOSFET, with its gate connected to its corresponding voltage enable input terminal, one source and drain connected to its corresponding voltage enable output terminal, and the other source and drain connected to its corresponding reference voltage VREF. Among them, the odd-numbered data voltage switches are connected to the first reference voltage VREF1, and the even-numbered data voltage switches are connected to the second reference voltage VREF2.

2. A display data writing circuit, characterized in that, It includes a first control circuit, a second control circuit, a third control circuit, a first signal storage capacitor Cs1, and a pixel capacitor Clc; Based on the first control circuit, during the backlight-on time of the current frame display, in the initialization writing phase, the first signal storage capacitor Cs1 corresponding to each pixel is synchronously controlled to initialize and store the intermediate voltage. Among them, the intermediate voltage of pixels with the same polarity of the data signal voltage in the next frame is configured to be the same. In the data writing phase after the initialization writing phase, the first signal storage capacitor Cs1 corresponding to each pixel of the display device is controlled to pre-store the data signal voltage required for the next frame display line by line based on the initialized and stored intermediate voltage. The intermediate voltage is between the data signal voltage with the largest difference from the common electrode voltage Vcom under the corresponding polarity and Vcom. Based on the second control circuit, after the backlight of the current frame is turned off, the pixel data voltage of the current frame in the pixel capacitor Clc corresponding to each pixel is reset to the common electrode voltage. Based on the third control circuit, for all pixels of the display device, the data signal voltage pre-stored in the first signal storage capacitor Cs1 corresponding to each pixel is synchronously read into the pixel capacitor Clc for display in the next frame; The writing circuit includes a pixel data voltage writing array, which includes multiple pixel data voltage writing units, each writing unit corresponding to one pixel. For each write unit, there are scan signal input terminal, data signal voltage input terminal, reset signal terminal, reference potential connection terminal, pre-stored data signal voltage transfer control terminal, signal write switch T1, signal transfer switch T2, reset switch T3, first pre-charge control switch T4, first signal storage capacitor Cs1 and pixel capacitor Clc; The scan signal input terminal is used to connect to the scan signal line Scan, and the scan signal input terminals of different row write units are connected to different scan signal lines; the data signal voltage input terminal is used to connect to the data signal voltage line Data, and the data signal voltage input terminals of different column write units are connected to different data signal voltage lines; the reset signal terminal is used to connect to the reset signal line Reset, and the pre-stored data signal voltage transfer control terminal is used to connect to the data signal voltage transfer control signal line Tran; the reference voltage connection terminal is used to connect to the reference electrode, wherein the reference voltage connection terminal of the odd-numbered row write unit is connected to the first reference electrode Com_Odd, and the reference voltage connection terminal of the even-numbered row write unit is connected to the second reference electrode Com_Even; the signal write switch T1, signal transfer switch T2, reset switch T3, and first pre-charge control switch T4 are all MOSFETs; The gate of the signal write switch T1 is connected to the scan signal input terminal, and one source and drain are connected to the data signal voltage input terminal; the other source and drain of the signal write switch T1 is connected to one source and drain of the signal transfer switch T2, and the connection node between them serves as a pre-charge node; one end of the first signal storage capacitor Cs1 is connected to the pre-charge node, and the other end is connected to a fixed potential, which includes any one of the scan signal input terminal, the reference voltage connection terminal, and the pre-stored data signal voltage transfer control terminal; The gate of signal transfer switch T2 is connected to the pre-stored data signal voltage transfer control terminal; the other source and drain of signal transfer switch T2 are connected to one source and drain of reset switch T3, and the connection point between them serves as a pixel pole node; the gate of reset switch T3 is connected to the reset signal input terminal, and the other source and drain are connected to the reference voltage connection terminal; one end of pixel capacitor Clc is connected to the pixel pole node, and the other end is connected to the reference voltage connection terminal; The gate of the first precharge control switch T4 is connected to the scan signal input terminal, one source and drain are connected to the precharge node, and the other source and drain are connected to the reference voltage connection terminal. The first control circuit includes a signal writing switch T1 and a first precharge control switch T4, the second control circuit includes a reset switch T3, and the third control circuit includes a signal transfer switch T2.

3. A display data writing circuit, characterized in that, It includes a first control circuit, a second control circuit, a third control circuit, a first signal storage capacitor Cs1, and a pixel capacitor Clc; Based on the first control circuit, during the backlight-on time of the current frame display, in the initialization writing phase, the first signal storage capacitor Cs1 corresponding to each pixel is synchronously controlled to initialize and store the intermediate voltage. Among them, the intermediate voltage of pixels with the same polarity of the data signal voltage in the next frame is configured to be the same. In the data writing phase after the initialization writing phase, the first signal storage capacitor Cs1 corresponding to each pixel of the display device is controlled to pre-store the data signal voltage required for the next frame display line by line based on the initialized and stored intermediate voltage. The intermediate voltage is between the data signal voltage with the largest difference from the common electrode voltage Vcom under the corresponding polarity and Vcom. Based on the second control circuit, after the backlight of the current frame is turned off, the pixel data voltage of the current frame in the pixel capacitor Clc corresponding to each pixel is reset to the common electrode voltage. Based on the third control circuit, for all pixels of the display device, the data signal voltage pre-stored in the first signal storage capacitor Cs1 corresponding to each pixel is synchronously read into the pixel capacitor Clc for display in the next frame; The writing circuit includes a pixel data voltage writing array, which includes multiple pixel data voltage writing units, each writing unit corresponding to one pixel. For each write unit, there are scan signal input terminal, data signal voltage input terminal, reset signal terminal, reference potential connection terminal, pre-stored data signal voltage transfer control terminal, pre-charge control signal input terminal, signal write switch T1, signal transfer switch T2, reset switch T3, second pre-charge control switch T5, first signal storage capacitor Cs1 and pixel capacitor Clc; The scan signal input terminal is used to connect to the scan signal line Scan, and the scan signal input terminals of different row write units are connected to different scan signal lines; the data signal voltage input terminal is used to connect to the data signal voltage line Data, and the data signal voltage input terminals of different column write units are connected to different data signal voltage lines; the reset signal terminal is used to connect to the reset signal line Reset, and the pre-stored data signal voltage transfer control terminal is used to connect to the data signal voltage transfer control signal line Tran; the reference voltage connection terminal is used to connect to the reference electrode Com; the pre-charge control signal input terminal is used to connect to the pre-charge control signal line, wherein the pre-charge control signal input terminal of the odd-numbered column write units is used to connect to the first control signal line VREF_Odd, and the pre-charge control signal input terminal of the even-numbered column write units is used to connect to the second control signal line VREF_Even; the signal write switch T1, the signal transfer switch T2, the reset switch T3, and the second pre-charge control switch T5 are all MOSFETs; The gate of the signal write switch T1 is connected to the scan signal input terminal, and one source and drain are connected to the data signal voltage input terminal; the other source and drain of the signal write switch T1 is connected to one source and drain of the signal transfer switch T2, and the connection node between them serves as a pre-charge node; one end of the first signal storage capacitor Cs1 is connected to the pre-charge node, and the other end is connected to a fixed potential, which includes any one of the scan signal input terminal, the reference voltage connection terminal, and the pre-stored data signal voltage transfer control terminal; The gate of signal transfer switch T2 is connected to the pre-stored data signal voltage transfer control terminal; the other source and drain of signal transfer switch T2 are connected to one source and drain of reset switch T3, and the connection point between them serves as a pixel pole node; the gate of reset switch T3 is connected to the reset signal input terminal, and the other source and drain are connected to the reference voltage connection terminal; one end of pixel capacitor Clc is connected to the pixel pole node, and the other end is connected to the reference voltage connection terminal; The gate of the second precharge control switch T5 is connected to the scan signal input terminal, one source and drain are connected to the precharge node, and the other source and drain are connected to the precharge control signal input terminal. The first control circuit includes a signal writing switch T1 and a second precharge control switch T5, the second control circuit includes a reset switch T3, and the third control circuit includes a signal transfer switch T2.

4. The display data writing circuit as described in any one of claims 1-3, characterized in that, The writing unit also includes a second signal storage capacitor Cs2, one end of which is connected to a pixel-level node and the other end is connected to a fixed potential.

5. The display data writing circuit as described in any one of claims 1-3, characterized in that, The intermediate voltage is the average of the data signal voltage and Vcom that differs most from the common electrode voltage Vcom under the corresponding polarity of each pixel in the next frame.

6. The display data writing circuit as described in any one of claims 1-3, characterized in that, The signal writing switch T1, signal transfer switch T2, and reset switch T3 are all NMOS transistors.

7. A display device, characterized in that, Includes the display data writing circuit as described in any one of claims 1-3.

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