High-side switching circuit and radio frequency front-end system

Abstract

The embodiment of the invention provides a high-side switching circuit and a radio frequency front-end system, and the high-side switching circuit comprises a first frequency modulation circuit, a first charge pump circuit, and a first switching transistor. The first end of the first frequency modulation circuit receives a first initial adjustment signal, the second end of the first frequency modulation circuit is connected with the control end of the first charge pump circuit, and the first end of the first charge pump circuit is connected with the gate end of the first switch transistor. The second end of the first charge pump circuit and the second end of the first switch transistor are both connected with the input end of the load circuit, and the first end of the first switch transistor is connected with a first power supply; the first frequency modulation circuit is used for generating a first oscillation clock signal under the control of the first initial adjustment signal; the oscillation frequency of the first oscillation clock signal in the initial charging state of the first charge pump circuit is greater than that in other states; and the first charge pump circuit is used for conducting the first switch transistor under the control of the first oscillation clock signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of switching power supplies, and relates to but is not limited to a high-side switch circuit and a radio frequency front-end system. Background Art

[0002] Metal Oxide Semiconductor (MOS) high-side switches are currently widely used in many fields such as automobiles, industry, and mobile devices due to their low loss, easy driving, high reliability, and near-ideal switching characteristics.

[0003] In the related art, the switching on of the switching transistor is controlled by controlling the charging and discharging of the capacitor in the charge pump circuit; however, it takes a certain amount of time to charge the capacitor in the charge pump circuit, which makes the switching on time of the switching transistor longer, reducing the response speed of the switching transistor. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a high-side switch circuit.

[0005] In a first aspect, an embodiment of the present disclosure provides a high-side switch circuit, the high-side switch circuit comprising:

[0006] A first frequency modulation circuit, a first charge pump circuit and a first switch transistor; a first end of the first frequency modulation circuit receives a first initial adjustment signal, a second end of the first frequency modulation circuit is connected to a control end of the first charge pump circuit, a first end of the first charge pump circuit is connected to a gate end of the first switch transistor, a second end of the first charge pump circuit and a second end of the first switch transistor are both connected to an input end of a load circuit, and a first end of the first switch transistor is connected to a first power supply; wherein:

[0007] The first frequency modulation circuit is used to generate a first oscillation clock signal under the control of the first initial adjustment signal; the oscillation frequency of the first oscillation clock signal in the initial state of charging of the first charge pump circuit is greater than the oscillation frequency in other states;

[0008] The first charge pump circuit is used to adjust its gate terminal voltage according to the voltage feedback of the second end of the first switching transistor under the control of the first oscillation clock signal, so that the difference between the gate terminal voltage of the first switching transistor and the voltage of the second end of the first switching transistor is a preset difference, so as to turn on the first switching transistor.

[0009] In some embodiments, the first frequency modulation circuit includes: a first control circuit and a first oscillator; a first end of the first control circuit receives the first initial adjustment signal, a second end of the first control circuit is connected to a first end of the first oscillator, and a second end of the first oscillator is connected to a control end of the first charge pump circuit; wherein:

[0010] The first control circuit is used to perform a first preprocessing on the first initial adjustment signal to generate a first adjustment signal; the first preprocessing is to convert the first adjustment signal from the second level state to the first level state and last for a first preset time when the first initial adjustment signal is converted from the second level state to the first level state;

[0011] The first oscillator is used to generate the first oscillation clock signal under the control of the first adjustment signal; the oscillation frequency of the first oscillation clock signal when the first adjustment signal is in the first level state is greater than the oscillation frequency when the first adjustment signal is in the second level state.

[0012] In some embodiments, the high-side switch circuit further includes a second frequency modulation circuit, a second charge pump circuit and a second switch transistor; a first end of the second frequency modulation circuit receives a second initial adjustment signal, a second end of the second frequency modulation circuit is connected to a control end of the second charge pump circuit, a first end of the second charge pump circuit is connected to a gate end of the second switch transistor, a second end of the second charge pump circuit and a second end of the second switch transistor are both connected to an input end of the load circuit, and a first end of the second switch transistor is connected to a second power supply; wherein:

[0013] The second frequency modulation circuit is used to generate a second oscillation clock signal under the control of the second initial adjustment signal; the oscillation frequency of the second oscillation clock signal in the initial state of charging of the second charge pump circuit is greater than the oscillation frequency in other states;

[0014] The second charge pump circuit is used to adjust its gate terminal voltage according to the voltage feedback of the second end of the second switching transistor under the control of the second oscillation clock signal, so that the difference between the gate terminal voltage of the second switching transistor and the voltage of the second end of the second switching transistor is a preset difference, so as to turn on the second switching transistor.

[0015] In some embodiments, the second frequency modulation circuit includes: a second control circuit and a second oscillator; a first end of the second control circuit receives the second initial adjustment signal, and a second end of the second control circuit is connected to a first end of the second oscillator; a second end of the second oscillator is connected to a control end of the second charge pump circuit; wherein:

[0016] The second control circuit is used to perform a second preprocessing on the second initial adjustment signal to generate a second adjustment signal; the second preprocessing is to convert the second adjustment signal from the second level state to the first level state and last for a second preset time when the second initial adjustment signal is converted from the second level state to the first level state;

[0017] The second oscillator is used to generate the second oscillation clock signal under the control of the second adjustment signal; the oscillation frequency of the second oscillation clock signal when the second adjustment signal is in the first level state is greater than the oscillation frequency when the second adjustment signal is in the second level state.

[0018] In some embodiments, the high-side switch circuit further includes: a logic control circuit; a first output end of the logic control circuit is connected to a first end of the first control circuit, and a second output end of the logic control circuit is connected to a first end of the second control circuit; wherein:

[0019] A logic control circuit is used to receive a first adjustment control signal and a second adjustment control signal, and perform logic processing on the first adjustment control signal and the second adjustment control signal to generate the first initial adjustment signal and the second initial adjustment signal; wherein, if the first adjustment control signal and the second adjustment control signal are both in the first level state, then the first initial adjustment signal and the second initial adjustment signal are both in the second level state; otherwise, the first initial adjustment signal is the same as the first adjustment control signal, and the second initial adjustment signal is the same as the second adjustment control signal.

[0020] In some embodiments, the first output terminal of the logic control circuit is further coupled to the third terminal of the first charge pump circuit, and the second output terminal of the logic control circuit is further coupled to the third terminal of the second charge pump circuit; wherein:

[0021] The first initial adjustment signal is also used to control the opening and closing of the first charge pump circuit;

[0022] The second initial adjustment signal is also used to control the opening and closing of the second charge pump circuit.

[0023] In some embodiments, the high-side switch circuit further includes: a dead time control circuit, the dead time control circuit including a first delay processing circuit and a second delay processing circuit; a first end of the first delay processing circuit is connected to a first output end of the logic control circuit, a second end of the first delay processing circuit is connected to a third end of the first charge pump circuit, a first end of the second delay processing circuit is connected to a second output end of the logic control circuit, and a second end of the second delay processing circuit is connected to a third end of the second charge pump circuit; wherein:

[0024] The first delay processing circuit is used to receive the first initial adjustment signal, and perform delay logic processing on the first initial adjustment signal to generate a first control signal;

[0025] The second delay processing circuit is used to receive the second initial adjustment signal, and perform delay logic processing on the second initial adjustment signal to generate a second control signal;

[0026] Wherein, when the first control signal is in an enabled state, the first charge pump circuit is turned on and the first switching transistor is turned on; when the second control signal is in an enabled state, the second charge pump circuit is turned on and the second switching transistor is turned on; when one of the first initial adjustment signal and the second initial adjustment signal changes from the second level state to the first level state, after an interval dead time, one of the first control signal and the second control signal changes from the second level state to the first level state.

[0027] In some embodiments, the logic control circuit includes: a first NOT gate, a second NOT gate, a first AND gate, and a second AND gate;

[0028] The first input end of the first AND gate is used to receive the first adjustment control signal, the second input end of the first AND gate is connected to the output end of the first NOT gate, and the output end of the first AND gate outputs the first initial adjustment signal; the input end of the first NOT gate is used to receive the second adjustment control signal;

[0029] The first input end of the second AND gate is connected to the output end of the second NOT gate, the second input end of the second AND gate is used to receive the second adjustment control signal, and the output end of the second AND gate outputs the second initial adjustment signal; the input end of the second NOT gate is used to receive the first adjustment control signal.

[0030] In some embodiments, the first delay processing circuit includes: a first delay unit and a third AND gate, and the second delay processing circuit includes: a second delay unit and a fourth AND gate;

[0031] The input end of the first delay unit is used to receive the first initial adjustment signal, the output end of the first delay unit is connected to the first input end of the third AND gate, the second input end of the third AND gate is used to receive the first initial adjustment signal, and the output end of the third AND gate outputs the first control signal;

[0032] The input end of the second delay unit is used to receive the second initial adjustment signal, the output end of the second delay unit is connected to the second input end of the fourth AND gate, the first input end of the fourth AND gate is used to receive the second initial adjustment signal, and the output end of the fourth AND gate outputs the second control signal.

[0033] In some embodiments, both the first switch transistor and the second switch transistor are NMOS transistors;

[0034] The working mode of the first power supply includes an ET mode or an APT mode; the working mode of the second power supply includes an ET mode or an APT mode; wherein the working modes of the first power supply and the second power supply are different.

[0035] In a second aspect, an embodiment of the present disclosure provides a radio frequency front-end system, comprising a high-side switch circuit as described in any one of the above embodiments.

[0036] The embodiment of the present disclosure provides a high-side switch circuit and a radio frequency front-end system, wherein the high-side switch circuit includes: a first frequency modulation circuit, a first charge pump circuit and a first switch transistor; the first end of the first frequency modulation circuit receives a first initial adjustment signal, the second end of the first frequency modulation circuit is connected to the control end of the first charge pump circuit, the first end of the first charge pump circuit is connected to the gate end of the first switch transistor, the second end of the first charge pump circuit and the second end of the first switch transistor are both connected to the input end of the load circuit, and the first end of the first switch transistor is connected to the first power supply; wherein: the first frequency modulation circuit is used to generate a first oscillation clock signal under the control of the first initial adjustment signal; the oscillation frequency of the first oscillation clock signal in the initial state of charging of the first charge pump circuit is greater than the oscillation frequency in other states; the first charge pump circuit is used to adjust the gate terminal voltage of the first switch transistor according to the voltage feedback of the second end of the first switch transistor under the control of the first oscillation clock signal, so that the difference between the gate terminal voltage of the first switch transistor and the voltage of the second end of the first switch transistor is a preset difference, so as to turn on the first switch transistor. In this way, since the first oscillation clock signal has a higher frequency when the charge pump circuit is initially charged, the charging speed of the charge pump circuit can be accelerated, and the first switch transistor can be quickly turned on, so that the response speed of the first switch transistor is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1A schematic diagram of the structure of the high-side switch circuit provided in the embodiment of the present disclosure Figure 1 ;

[0038] Figure 2 A schematic diagram of the waveform of the first voltage under the ET mode and APT provided in an embodiment of the present disclosure;

[0039] Figure 3 A schematic diagram of the structure of a load circuit provided in an embodiment of the present disclosure;

[0040] Figure 4 A schematic diagram of the structure of the high-side switch circuit provided in the embodiment of the present disclosure Figure 2 ;

[0041] Figure 5 A timing diagram of a first frequency modulation circuit provided in an embodiment of the present disclosure;

[0042] Figure 6 A schematic diagram of the structure of the high-side switch circuit provided in the embodiment of the present disclosure Figure 3 ;

[0043] Figure 7 A schematic diagram of the structure of a logic control circuit and a dead time control circuit provided in an embodiment of the present disclosure;

[0044] Figure 8 A timing diagram of a logic control circuit and a dead time control circuit provided in an embodiment of the present disclosure;

[0045] Fig. 9 A schematic diagram of the structure of a radio frequency front-end system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0047] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0048] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0049] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0050] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] At present, MOS high-side switches are widely used in many fields such as automobiles, industry, and mobile devices due to their low loss, easy driving, high reliability, and near-ideal switching characteristics, and cover control and protection of currents within tens of amperes.

[0052] Furthermore, when an N-type MOS tube (NMOS tube) is used as a high-side switch device, it has the advantages of small size and stable switch resistance. Since the source of the NMOS tube is connected to the load when the NMOS tube is used for the high-side switch, there are two problems: the source is suspended and the gate voltage is higher than the drain supply voltage; in the related art, in order to overcome these two problems, it is usually necessary to control the voltage at the gate end of the NMOS tube through a voltage regulator circuit and a charge pump circuit; however, since the voltage regulator circuit requires a certain startup time, and the capacitor in the charge pump circuit also requires a certain charging time, the switch transistor is turned on for a long time, which reduces the response speed of the switch transistor.

[0053] Based on this, an embodiment of the present disclosure provides a high-side switch circuit and a radio frequency front-end system, wherein the high-side switch circuit includes: a first frequency modulation circuit, a first charge pump circuit and a first switch transistor; the first end of the first frequency modulation circuit receives a first initial adjustment signal, the second end of the first frequency modulation circuit is connected to the control end of the first charge pump circuit, the first end of the first charge pump circuit is connected to the gate end of the first switch transistor, the second end of the first charge pump circuit and the second end of the first switch transistor are both connected to the input end of the load circuit, and the first end of the first switch transistor is connected to the first power supply; wherein: the first frequency modulation circuit is used to generate a first oscillation clock signal under the control of the first initial adjustment signal; the oscillation frequency of the first oscillation clock signal in the initial state of charging of the first charge pump circuit is greater than the oscillation frequency in other states; the first charge pump circuit is used to adjust the gate terminal voltage of the first switch transistor according to the voltage feedback of the second end of the first switch transistor under the control of the first oscillation clock signal, so that the difference between the gate terminal voltage of the first switch transistor and the voltage of the second end of the first switch transistor is a preset difference, so as to turn on the first switch transistor. In this way, since the first oscillation clock signal has a higher frequency when the charge pump circuit is initially charged, the charging speed of the charge pump circuit can be accelerated, and the first switch transistor can be quickly turned on, so that the response speed of the first switch transistor is higher.

[0054] The high side switch circuit in the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0055] Figure 1 A schematic diagram of the structure of a high-side switch circuit 100 provided in an embodiment of the present disclosure is shown in FIG. Figure 1As shown, the high-side switch circuit 100 includes: a first frequency modulation circuit 110, a first charge pump circuit 120 and a first switch transistor 130; the first end of the first frequency modulation circuit 110 receives the first initial adjustment signal, the second end of the first frequency modulation circuit 110 is connected to the control end of the first charge pump circuit 120, the first end of the first charge pump circuit 120 is connected to the gate end of the first switch transistor 130, the second end of the first charge pump circuit 120 and the second end of the first switch transistor 130 are both connected to the input end of the load circuit 150, and the first end of the first switch transistor 130 is connected to the first power supply 140; wherein:

[0056] The first frequency modulation circuit 110 is used to generate a first oscillation clock signal under the control of a first initial adjustment signal; the oscillation frequency of the first oscillation clock signal in the initial state of charging of the first charge pump circuit 120 is greater than the oscillation frequency in other states.

[0057] The first charge pump circuit 120 is used to adjust its gate terminal voltage according to the voltage feedback of the second end of the first switch transistor 130 under the control of the first oscillation clock signal, so that the difference between the gate terminal voltage of the first switch transistor 130 and the second end voltage of the first switch transistor 130 is a preset difference, so as to turn on the first switch transistor 130.

[0058] Here, the first initial adjustment signal can be expressed as EN Fre ctrl <0> Indicates that the first oscillation clock signal can be CLK <0> In other embodiments, the first power supply 140 is used to output a first voltage, which may be a voltage for supplying power to the load circuit 150 and may be represented by VCC_PS1 (not shown). In other embodiments, the first voltage may also be other voltages or provided by other power supply circuits.

[0059] Furthermore, the first voltage can be a fixed voltage or a variable voltage. The first power supply 140 supplies power and operates in either of two modes: envelope tracking mode (ET mode) and average power tracking mode (Average Power Tracking mode, APT mode); the voltage waveform diagram of the first voltage in the ET mode and the APT mode is shown in FIG. Figure 2 shown.

[0060] In addition, the structural diagram of the load circuit 150 is as follows Figure 3As shown, the load circuit 150 may include a power amplifier 151 (Power Amplifier, PA). The first end of the power amplifier 151 is connected to the second end of the first switch transistor 130 through a port 152; the second end of the power amplifier 151 is grounded; the input end of the power amplifier 151 is used to receive a radio frequency input signal RF_in; and the output end of the power amplifier 151 is used to output a radio frequency output signal RF_out. It should be noted that Figure 3 The load circuit 150 in FIG. 1 is a simplified structural diagram. In fact, the load circuit 150 can be any achievable circuit structure.

[0061] In the embodiment of the present disclosure, the oscillation frequency of the first oscillation clock signal in the initial state of charging of the first charge pump circuit 120 is greater than the oscillation frequency in other states, which means: the frequency of the first oscillation clock signal is increased when the capacitor in the first charge pump circuit 120 starts to charge, and the first oscillation clock signal is restored to the original frequency when the capacitor in the first charge pump circuit 120 is about to be fully charged or fully charged. In this way, the charging speed of the capacitor in the first charge pump circuit 120 can be faster, so that the first switch transistor 130 can be turned on quickly.

[0062] In some embodiments, the first switch transistor 130 is an NMOS transistor. The first switch transistor 130 may also be other N-type field effect transistors, which is not limited here.

[0063] In the disclosed embodiment, the first charge pump circuit 120 also receives the voltage of a preset power supply (not shown), and the voltage value output by the preset power supply is equal to the preset difference value; the first charge pump circuit 120 may be a QPUMP (gate drive charge pump), which is used to raise the voltage of the received preset power supply according to the voltage of the second end of the first switch transistor 130, and then input it to the gate end of the first switch transistor 130, so that the voltage difference between the voltage of the second end of the first switch transistor 130 and the voltage of its gate end is the preset difference value. The preset difference value may be, for example, 5V. In actual implementation, the preset difference value may also be other values ​​that can realize the conduction of the first switch transistor 130, such as 6V, 6.5V, 7V, etc.

[0064] It should be noted that, since the voltage stabilizing circuit (e.g., a low voltage drop linear regulator) requires a certain startup time, the embodiment of the present disclosure removes the voltage stabilizing circuit connected between the preset power supply and the first switch transistor 130, thereby accelerating the time for the first switch transistor 130 to turn on; accordingly, only the first charge pump circuit 120 is provided between the preset power supply and the first switch transistor 130 for turning on the first switch transistor 130, that is, the voltage boost requirement for turning on the first switch transistor 130 can be achieved only by the first charge pump circuit 120. Further, in order to compensate for the voltage fluctuation caused by reducing the voltage stabilizing circuit, on the one hand, compensation can be made by increasing the power (i.e., current) of the preset power supply, so that the first charge pump circuit 120 is fully charged faster and reaches a stable state; on the other hand, the capacitance in the first charge pump circuit 120 can also be increased, thereby stabilizing the voltage in the first charge pump circuit 120.

[0065] In the embodiment of the present disclosure, since the voltage of the preset power supply is raised by the first charge pump circuit 120, the voltage at the gate terminal of the first switching transistor is relatively high. Therefore, the first switching transistor 130 in the high-side switching circuit 100 can adopt a smaller NMOS tube with stable switching resistance as a high-side switch, thereby reducing the area of ​​the high-side switching circuit 100.

[0066] In addition, since the first oscillation clock signal has a higher frequency when the first charge pump circuit 120 is initially charged, the charging speed of the first charge pump circuit 120 is faster, so the first switch transistor 130 can be turned on quickly, so that the response speed of the first switch transistor 130 is higher.

[0067] Next, please refer to Figures 4 to 8 , the high-side switch circuit 100 provided in the embodiment of the present disclosure is further described.

[0068] In some embodiments, please refer to Figure 4 and Figure 5The first frequency modulation circuit 110 includes: a first control circuit 111 and a first oscillator 112; a first end of the first control circuit 111 receives a first initial adjustment signal EN Fre ctrl <0> The second end of the first control circuit 111 is connected to the first end of the first oscillator 112, and the second end of the first oscillator 112 is connected to the control end of the first charge pump circuit 120, wherein: the first control circuit 111 is used to adjust the first initial adjustment signal EN Frectrl <0> Perform the first preprocessing to generate the first adjustment signal Fast <0> ; The first preprocessing is to adjust the signal EN Fre ctrl in the first initial <0> When the second level state is converted into the first level state, the first adjustment signal Fast <0> The second level state is converted into the first level state and lasts for a first preset time; the first oscillator 112 is used to generate a first oscillation clock signal CLK under the control of the first adjustment signal <0> ; The first oscillation clock signal CLK <0> In the first regulation signal Fast <0> The oscillation frequency when the first adjustment signal is in the first level state is greater than the oscillation frequency when the first adjustment signal is in the second level state.

[0069] Here, the first adjustment signal can be Fast <0> The first control circuit 111 may be an oscillator frequency control module Fre_Ctrl, and the first oscillator 112 may be an oscillator (OSC). The first preset time may be set according to actual needs, and the present disclosure does not limit this.

[0070] In this disclosure, please continue to refer to Figure 4 and Figure 5 When the first control circuit 111 receives the first initial adjustment signal EN Fre ctrl <0> When the second level state is converted into the first level state, it means that the first switch transistor 130 is turned on, and the first control circuit 111 outputs the first adjustment signal Fast <0> The first adjustment signal Fast <0> The first oscillator 112 is input to control the frequency response of the first oscillator 112 so that the first adjustment signal Fast <0> When the first level state is reached, the first oscillator 112 outputs the first oscillation clock signal CLK <0> The oscillation frequency is higher, thereby driving the first charge pump circuit 120 to start faster; and in the first adjustment signal Fast <0> When the first oscillator 112 is in the second level state, the first oscillator 112 outputs the first oscillation clock signal CLK <0> The oscillation frequency is restored to a lower frequency, thereby reducing the noise and electromagnetic interference caused by the clock frequency.

[0071] It should be noted that Figure 5 Only the first initial adjustment signal EN Fre ctrl is shown in <0> Take a pulse signal in the example as an example, the first initial adjustment signal EN Fre ctrl <0> Please refer to the timing Figure 8 .

[0072] It should also be noted that the first level state is 1 (logic high level), and the second level state is 0 (logic low level); the first initial adjustment signal EN Fre ctrl <0> The first level state is the first initial adjustment signal EN Frectrl <0> In the enabled state, the first initial adjustment signal EN Fre ctrl <0> The second level state is the first initial adjustment signal EN Fre ctrl <0> In the non-enabled state, the “first level state” and “second level state” that appear in the subsequent specification can be understood with reference to the above explanation.

[0073] In some embodiments, please refer to Figure 4 The high-side switch circuit 100 further includes a first body-end switch circuit 160, wherein a first terminal and a second terminal of the first body-end switch circuit 160 are respectively connected to a gate terminal and a second terminal of the first switch transistor 130, so as to ensure that the first switch transistor 130 is reliably turned on and off.

[0074] It should also be noted that in Figure 4 In the embodiment, the first power supply supplies power to the first switch transistor 130 through the port 141, and the load circuit is connected to the first switch transistor 130 through the port 152. In addition, the high-side switch circuit 100 further includes a port GND and a port VBAT, and some devices in the high-side switch circuit 100 are grounded through the port GND, and are connected to a preset power supply through the port VBAT.

[0075] In some embodiments, please refer to Figure 6The high-side switch circuit 100 further includes a second frequency modulation circuit 170, a second charge pump circuit 180 and a second switch transistor 190; a first end of the second frequency modulation circuit 170 receives a second initial adjustment signal, a second end of the second frequency modulation circuit 170 is connected to a control end of the second charge pump circuit 180, a first end of the second charge pump circuit 180 is connected to a gate end of the second switch transistor 190, a second end of the second charge pump circuit 180 and a second end of the second switch transistor 190 are both connected to an input end of a load circuit (not shown) through a port 152, and a first end of the second switch transistor 190 is connected to an input end of a load circuit (not shown) through a port 200. Connected to a second power supply (not shown); wherein: a second frequency modulation circuit 170 is used to generate a second oscillation clock signal under the control of a second initial adjustment signal; the oscillation frequency of the second oscillation clock signal in the initial state of charging of the second charge pump circuit is greater than the oscillation frequency in other states; a second charge pump circuit 180 is used to adjust the gate terminal voltage of the second switch transistor 190 according to the voltage feedback of the second end of the second switch transistor 190 under the control of the second oscillation clock signal, so that the difference between the gate terminal voltage of the second switch transistor 190 and the second end voltage of the second switch transistor 190 is a preset difference, so as to turn on the second switch transistor 190.

[0076] Here, the second initial adjustment signal can be expressed as EN Fre ctrl <1> Indicates that the second oscillation clock signal can be used with CLK <1> express.

[0077] It should be noted that the load circuit, the first power supply, the second power supply, the first frequency modulation circuit, the second frequency modulation circuit and the high-side switch circuit can also be set on one IC, or part of them and the high-side switch circuit can be set on one IC. In this case, no external interface is required for connection and they can be directly connected.

[0078] In some embodiments, the second switch transistor 190 is an NMOS transistor; since the NMOS transistor has a higher carrier mobility characteristic. This allows the high-side switch circuit to have a stronger driving current capability, thereby improving current density and efficiency. In addition, the operating mode of the second power supply includes an ET mode or an APT mode; wherein the operating modes of the first power supply 140 and the second power supply are different. In this way, the power supply mode of the load circuit can be switched by the first switch transistor 130 and the second switch transistor 190, thereby broadening the application scenario of the high-side switch circuit 100.

[0079] In some embodiments, the second switch transistor 190 has a similar structure and function to the first switch transistor 130 , and the first charge pump circuit 120 has a similar structure and function to the second charge pump circuit 180 , which will not be described in detail here.

[0080] In some embodiments, the second frequency modulation circuit 170 includes: a second control circuit 171 and a second oscillator 172; a first terminal of the second control circuit 171 receives a second initial adjustment signal EN Fre ctrl <1> The second end of the second control circuit 171 is connected to the first end of the second oscillator 172; the second end of the second oscillator 172 is connected to the first end of the second charge pump circuit 180; wherein: the second control circuit 171 is used to adjust the second initial adjustment signal EN Fre ctrl <1> Perform the second preprocessing to generate the second adjustment signal Fast <1> The second preprocessing is to adjust the second initial signal EN Fre ctrl <1> When the second level state is converted into the first level state, the second adjustment signal Fast <1> The second level state is converted into the first level state and lasts for a second preset time; the second oscillator 172 is used to adjust the signal Fast <1> Under the control of <1> ; The second oscillation clock signal CLK <1> In the second regulation signal Fast <1> The oscillation frequency when it is in the first level state is greater than that in the second adjustment signal Fast <1> The oscillation frequency when it is in the second level state.

[0081] Here, the second adjustment signal can be Fast <1> The second preset time can be set according to actual needs, and the present disclosure does not limit this.

[0082] It should be noted that the first control circuit 111 and the second control circuit 171 have similar structures and functions, and the second oscillator 172 and the first oscillator 112 have similar structures and functions, which will not be described in detail here.

[0083] In some embodiments, please refer to Figure 6 and Figure 8 The high-side switch circuit 100 further includes: a logic control circuit 210; a first output end of the logic control circuit 210 is connected to a first end of the first control circuit 111, and a second output end of the logic control circuit 210 is connected to a first end of the second control circuit 171; wherein: the logic control circuit 210 is used to receive the first adjustment control signal and the second adjustment control signal, and perform logic processing on the first adjustment control signal and the second adjustment control signal to generate a first initial adjustment signal EN Fre ctrl <0> and the second initial adjustment signal EN Fre ctrl <1> Wherein, if the first adjustment control signal and the second adjustment control signal are both in the first level state, the first initial adjustment signal EN Frectrl <0> and the second initial adjustment signal EN Fre ctrl <1> Otherwise, the first initial adjustment signal EN Fre ctrl <0> The second initial adjustment signal EN Fre ctrl is the same as the first adjustment control signal. <1> Same as the second adjustment control signal.

[0084] Here, the input signal of the logic control circuit 210 can be represented by CTRL_IN<1:0>, which includes the first adjustment control signal CTRL_IN <0> and the second regulation control signal CTRL_IN <1> .

[0085] In some embodiments, please refer to Figure 6 The first output terminal of the logic control circuit 210 is also coupled to the third terminal of the first charge pump circuit 120, and the second output terminal of the logic control circuit 210 is also coupled to the third terminal of the second charge pump circuit 180; wherein: the first initial adjustment signal EN Fre ctrl <0> It is also used to control the first charge pump circuit 120 to be turned on or off, thereby controlling the first switch transistor 130 to be turned on or off; the second initial adjustment signal EN Fre ctrl <1> It is also used to control the on or off of the second charge pump circuit 180 , thereby controlling the on or off of the second switch transistor 190 .

[0086] It should be noted that the first output terminal of the logic control circuit 210 is coupled to the first charge pump circuit 120: it means that the first output terminal of the logic control circuit 210 and the first charge pump circuit 120 can be directly connected or indirectly connected, that is, "coupling" includes two ways of direct connection or indirect connection. The "coupling" that appears in the subsequent description can be understood with reference to the above explanation.

[0087] Furthermore, the first control signal CTRL_IN is controlled by the logic control circuit 210. <0> and the second control signal CTRL_IN <1> Performing logic processing, generating a first initial adjustment signal EN Fre ctrl in an enabled state when indicating to turn on the first switch transistor 130 <0> and the second initial adjustment signal EN Fre ctrl in the non-enabled state <1> In the case of indicating that the second switching transistor 190 is turned on, a second initial adjustment signal EN Frectrl is generated in an enabled state <1> and the first initial adjustment signal EN Fre ctrl in the non-enabled state <0> It should be noted that, when the high-side switch circuit does not have the second switch transistor 190 , the control signal related thereto is omitted.

[0088] In some embodiments, please refer to Figure 7The logic control circuit 210 includes: a first NOT gate 10, a second NOT gate 12, a first AND gate 11 and a second AND gate 13; the first input terminal of the first AND gate 11 is used to receive the first adjustment control signal CTRL_IN <0> The second input terminal of the first AND gate 11 is connected to the output terminal of the first NOT gate 10, and the output terminal of the first AND gate 11 outputs the first initial adjustment signal EN Fre ctrl <0> The input terminal of the first NOT gate 10 is used to receive the second adjustment control signal CTRL_IN <1> The first input terminal of the second AND gate 13 is connected to the output terminal of the second NOT gate 12, and the second input terminal of the second AND gate 13 is used to receive the second adjustment control signal CTRL_IN <1> The output terminal of the second AND gate 13 outputs the second initial adjustment signal EN Frectrl <1> The input terminal of the second NOT gate 12 is used to receive the first adjustment control signal CTRL_IN <0> .

[0089] In the embodiment of the present disclosure, in order to avoid the problem that the first switch transistor 130 and the second switch transistor 190 are turned on at the same time during the operation of the high-side switch circuit 100, resulting in excessive transient current and burning the load circuit. In some embodiments, please continue to refer to Figure 6The high-side switch circuit 100 further includes: a dead time control circuit 220, the dead time control circuit 220 includes a first delay processing circuit 221 and a second delay processing circuit 222; a first end of the first delay processing circuit 221 is connected to a first output end of the logic control circuit 210, a second end of the first delay processing circuit 221 is connected to a third end of the first charge pump circuit 120, a first end of the second delay processing circuit 222 is connected to a second output end of the logic control circuit 210, and a second end of the second delay processing circuit is connected to a third end of the second charge pump circuit 180; wherein: the first delay processing circuit 221 is used to receive a first initial adjustment signal EN Fre ctrl <0> , and the first initial adjustment signal EN Frectrl <0> Perform delay logic processing to generate the first control signal CTRL_OUT <0> A second delay processing circuit 222 for receiving a second initial adjustment signal EN Fre ctrl <1> , and the second initial adjustment signal EN Fre ctrl <1> Perform delay logic processing to generate the second control signal CTRL_OUT <1> ; Wherein, in the first control signal CTRL_OUT <0> When in the enabled state, the first charge pump circuit 120 is turned on, and the first switch transistor 130 is turned on; <1> When in the enabled state, the second charge pump circuit 180 is turned on, and the second switch transistor 190 is turned on; when the first initial adjustment signal EN Fre ctrl <0> and the second initial adjustment signal EN Fre ctrl <1> When one of the first control signals changes from the second level state to the first level state, after the dead time (DT), the first control signal CTRL_OUT <0> and the second control signal CTRL_OUT <1> One of the state changes from the second level to the first level.

[0090] In some embodiments, please refer to Figure 7The first delay processing circuit 221 includes: a first delay unit 14, a third AND gate 15, and the second delay processing circuit 222 includes: a second delay unit 16 and a fourth AND gate 17; the input end of the first delay unit 14 is used to receive the first initial adjustment signal EN Fre ctrl <0> The output end of the first delay unit 14 is connected to the first input end of the third AND gate 15, and the second input end of the third AND gate 15 is used to receive the first initial adjustment signal EN Frectrl <0> , the output terminal of the third AND gate 15 outputs the first control signal CTRL_OUT <0> The input end of the second delay unit 16 is used to receive the second initial adjustment signal EN Fre ctrl <1> The output end of the second delay unit 16 is connected to the second input end of the fourth AND gate 17, and the first input end of the fourth AND gate 17 is used to receive the second initial adjustment signal EN Fre ctrl <1> The output terminal of the fourth AND gate 17 outputs the second control signal CTRL_OUT <1> .

[0091] In the embodiment of the present disclosure, since the high-side switch circuit 100 includes a first switch transistor 130 and a second switch transistor 190, during the operation of the high-side switch circuit 100, the first switch transistor 130 and the second switch transistor 190 are turned on at the same time, which may cause the transient current of the input load circuit 150 to be too large and burn the chip. Therefore, by setting the dead time control circuit 220, the first initial adjustment signal EN Fre ctrl <0> and / or the second initial adjustment signal EN Fre ctrl <1> After delay processing, the signals are transmitted to the first charge pump circuit 120 and the second charge pump circuit 190 respectively, thereby preventing the first switch transistor 130 and the second switch transistor 190 from being turned on at the same time, thereby increasing the reliability of the high-side switch circuit 100 .

[0092] In some embodiments, please refer to Figure 6 The high-side switch circuit 100 further includes a second body-end switch circuit 161, a first end and a second end of the second body-end switch circuit 161 are respectively connected to the gate end and the second end of the second switch transistor 190. The body end of the second switch transistor 190 is used to control the body end of the second switch transistor 190 to ensure that the second switch transistor 190 is reliably turned on and off.

[0093] It should be noted that the first switch transistor 130 in the embodiment of the present disclosure can be a depletion-type NMOS tube or an enhancement-type NMOS tube, and the second switch transistor 190 can be a depletion-type NMOS tube or an enhancement-type NMOS tube; among them, the manufacturing process of the depletion-type NMOS tube is simple; the enhancement-type NMOS tube has a fast switching speed and a stronger driving capability, and can be selected as needed during implementation.

[0094] The embodiments of the present disclosure provide Figure 6 The high-side switch circuit shown is similar to the above Figure 4 The high-side switch circuit in the embodiment is similar. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0095] In addition, the present disclosure also provides a radio frequency front-end system 300, please refer to Fig. 9 The RF front-end system 300 includes: a high-side switch circuit 100, a power amplifier 151, an output matching circuit 310, a first filter 320, an antenna switch (ASM, Antenna Switch Module) 330, a receiving component (RX component) 350 and a second filter 360.

[0096] Please continue to refer to Fig. 9 The first end of the power amplifier 151 is connected to the high-side switch circuit 100, and the working mode of the power supply of the power amplifier 151 is controlled to be ET mode or APT mode through the high-side switch circuit 100; the input end of the power amplifier 151 is used to receive the radio frequency input signal RF_in; the output end of the power amplifier 151 is connected to the input end of the output matching circuit 310.

[0097] The output end of the output matching circuit 310 is connected to the input end of the first filter 320 , and the output end of the first filter 320 is connected to the first input end of the antenna switch 330 .

[0098] The input end of the receiving component 350 receives the signal LNA_OUT output by the low noise amplifier LAN, the output end of the receiving component 350 is connected to the second filter 360, the output end of the second filter 360 is connected to the second input end of the antenna switch 330, and the output end of the antenna switch 330 is output to the antenna (ANT) through the port 360.

[0099] It should be noted that Fig. 9 The RF front-end system 300 is a simplified structural diagram. In fact, the RF front-end system 300 can be any achievable circuit structure.

[0100] In the embodiment of the present disclosure, since the RF front-end system 300 includes the high-side switch circuit 100 in the above-mentioned embodiment, the operating mode of the power supply of the RF front-end system 300 can be switched to ET mode or APT mode through the high-side switch circuit 100. At the same time, since the switching or starting speed of the switching transistor (i.e., the first switching transistor 130 and / or the second switching transistor 190) is fast, the response speed of the RF front-end system 300 is higher.

[0101] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0102] The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0103] The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A high side switch circuit, characterized in that: The high-side switch circuit includes: a first frequency modulation circuit, a first charge pump circuit and a first switch transistor; the first end of the first frequency modulation circuit receives a first initial adjustment signal, the second end of the first frequency modulation circuit is connected to the control end of the first charge pump circuit, the first end of the first charge pump circuit is connected to the gate end of the first switch transistor, the second end of the first charge pump circuit and the second end of the first switch transistor are both connected to the input end of the load circuit, and the first end of the first switch transistor is connected to the first power supply; wherein: The first frequency modulation circuit is used to generate a first oscillation clock signal under the control of the first initial adjustment signal; the oscillation frequency of the first oscillation clock signal in the initial state of charging of the first charge pump circuit is greater than the oscillation frequency in other states; The first charge pump circuit is used to adjust its gate terminal voltage according to the voltage feedback of the second end of the first switching transistor under the control of the first oscillation clock signal, so that the difference between the gate terminal voltage of the first switching transistor and the voltage of the second end of the first switching transistor is a preset difference, so as to turn on the first switching transistor.

2. The circuit according to claim 1, characterized in that The first frequency modulation circuit includes: a first control circuit and a first oscillator; the first end of the first control circuit receives the first initial adjustment signal, the second end of the first control circuit is connected to the first end of the first oscillator, and the second end of the first oscillator is connected to the control end of the first charge pump circuit; wherein: The first control circuit is used to perform a first preprocessing on the first initial adjustment signal to generate a first adjustment signal; the first preprocessing is to convert the first adjustment signal from the second level state to the first level state and last for a first preset time when the first initial adjustment signal is converted from the second level state to the first level state; The first oscillator is used to generate the first oscillation clock signal under the control of the first adjustment signal; the oscillation frequency of the first oscillation clock signal when the first adjustment signal is in the first level state is greater than the oscillation frequency when the first adjustment signal is in the second level state.

3. The circuit according to claim 2, characterized in that The high-side switch circuit further includes a second frequency modulation circuit, a second charge pump circuit and a second switch transistor; a first end of the second frequency modulation circuit receives a second initial adjustment signal, a second end of the second frequency modulation circuit is connected to a control end of the second charge pump circuit, a first end of the second charge pump circuit is connected to a gate end of the second switch transistor, a second end of the second charge pump circuit and a second end of the second switch transistor are both connected to an input end of the load circuit, and a first end of the second switch transistor is connected to a second power supply; wherein: The second frequency modulation circuit is used to generate a second oscillation clock signal under the control of the second initial adjustment signal; the oscillation frequency of the second oscillation clock signal in the initial state of charging of the second charge pump circuit is greater than the oscillation frequency in other states; The second charge pump circuit is used to adjust its gate terminal voltage according to the voltage feedback of the second end of the second switching transistor under the control of the second oscillation clock signal, so that the difference between the gate terminal voltage of the second switching transistor and the second end voltage of the second switching transistor is a preset difference, so as to turn on the second switching transistor.

4. The circuit according to claim 3, characterized in that The second frequency modulation circuit includes: a second control circuit and a second oscillator; the first end of the second control circuit receives the second initial adjustment signal, the second end of the second control circuit is connected to the first end of the second oscillator; the second end of the second oscillator is connected to the control end of the second charge pump circuit; wherein: The second control circuit is used to perform a second preprocessing on the second initial adjustment signal to generate a second adjustment signal; the second preprocessing is to convert the second adjustment signal from the second level state to the first level state and last for a second preset time when the second initial adjustment signal is converted from the second level state to the first level state; The second oscillator is used to generate the second oscillation clock signal under the control of the second adjustment signal; the oscillation frequency of the second oscillation clock signal when the second adjustment signal is in the first level state is greater than the oscillation frequency when the second adjustment signal is in the second level state.

5. The circuit according to claim 4, characterized in that The high-side switch circuit further comprises: a logic control circuit; a first output end of the logic control circuit is connected to a first end of the first control circuit, and a second output end of the logic control circuit is connected to a first end of the second control circuit; wherein: A logic control circuit is used to receive a first adjustment control signal and a second adjustment control signal, and perform logic processing on the first adjustment control signal and the second adjustment control signal to generate the first initial adjustment signal and the second initial adjustment signal; wherein, if the first adjustment control signal and the second adjustment control signal are both in the first level state, then the first initial adjustment signal and the second initial adjustment signal are both in the second level state; otherwise, the first initial adjustment signal is the same as the first adjustment control signal, and the second initial adjustment signal is the same as the second adjustment control signal.

6. The circuit according to claim 5, characterized in that The first output terminal of the logic control circuit is also coupled to the third terminal of the first charge pump circuit, and the second output terminal of the logic control circuit is also coupled to the third terminal of the second charge pump circuit; wherein: The first initial adjustment signal is also used to control the opening and closing of the first charge pump circuit; The second initial adjustment signal is also used to control the opening and closing of the second charge pump circuit.

7. The circuit according to claim 6, characterized in that The high-side switch circuit further includes: a dead time control circuit, the dead time control circuit includes a first delay processing circuit and a second delay processing circuit; a first end of the first delay processing circuit is connected to a first output end of the logic control circuit, a second end of the first delay processing circuit is connected to a third end of the first charge pump circuit, a first end of the second delay processing circuit is connected to a second output end of the logic control circuit, and a second end of the second delay processing circuit is connected to a third end of the second charge pump circuit; wherein: The first delay processing circuit is used to receive the first initial adjustment signal, and perform delay logic processing on the first initial adjustment signal to generate a first control signal; The second delay processing circuit is used to receive the second initial adjustment signal, and perform delay logic processing on the second initial adjustment signal to generate a second control signal; Wherein, when the first control signal is in an enabled state, the first charge pump circuit is turned on and the first switching transistor is turned on; when the second control signal is in an enabled state, the second charge pump circuit is turned on and the second switching transistor is turned on; when one of the first initial adjustment signal and the second initial adjustment signal changes from the second level state to the first level state, after an interval dead time, one of the first control signal and the second control signal changes from the second level state to the first level state.

8. The circuit according to claim 7, characterized in that The logic control circuit comprises: a first NOT gate, a second NOT gate, a first AND gate and a second AND gate; The first input end of the first AND gate is used to receive the first adjustment control signal, the second input end of the first AND gate is connected to the output end of the first NOT gate, and the output end of the first AND gate outputs the first initial adjustment signal; the input end of the first NOT gate is used to receive the second adjustment control signal; The first input end of the second AND gate is connected to the output end of the second NOT gate, the second input end of the second AND gate is used to receive the second adjustment control signal, and the output end of the second AND gate outputs the second initial adjustment signal; the input end of the second NOT gate is used to receive the first adjustment control signal.

9. The circuit according to claim 8, characterized in that The first delay processing circuit includes: a first delay unit and a third AND gate, and the second delay processing circuit includes: a second delay unit and a fourth AND gate; The input end of the first delay unit is used to receive the first initial adjustment signal, the output end of the first delay unit is connected to the first input end of the third AND gate, the second input end of the third AND gate is used to receive the first initial adjustment signal, and the output end of the third AND gate outputs the first control signal; The input end of the second delay unit is used to receive the second initial adjustment signal, the output end of the second delay unit is connected to the second input end of the fourth AND gate, the first input end of the fourth AND gate is used to receive the second initial adjustment signal, and the output end of the fourth AND gate outputs the second control signal.

10. The circuit according to any one of claims 3 to 9, characterized in that: The first switch transistor and the second switch transistor are both NMOS transistors; The working mode of the first power supply includes an ET mode or an APT mode; the working mode of the second power supply includes an ET mode or an APT mode; wherein the working modes of the first power supply and the second power supply are different.

11. A radio frequency front-end system, characterized in that: The invention comprises the high side switch circuit as claimed in any one of claims 1 to 10.

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