Double-clock cooperative synchronization method in wireless communication based on single photon counting detection

Abstract

The invention discloses a double-clock cooperative synchronization method in wireless communication based on single photon counting detection, which comprises the following steps: a receiving end sets N paths of gating clocks which are operated in parallel and a path of high-frequency clock, and each path of gating clock is provided with an independent counter; a counter Cni (i belongs to [1, N]) counts under the control of a gating clock Clki (i belongs to [1, N]), an electric pulse output by the single-photon detector and a high-frequency clock Clkh; when the counter Cnt passes through the counting of M (M is greater than or equal to 1) counting cycles, the counter Cnt stops counting and outputs a counting value Counnt; and comparing the relative values of the N count values output by the N counters, and taking the gated clock corresponding to the maximum count value as the synchronous clock. According to the method, rapid and high-precision clock synchronization can be realized, and the synchronization precision is improved along with the increase of the number N of the gated clocks.

Description

Technical Field

[0001] The present invention relates to the field of single-photon wireless communication and detection, and to the field of high-precision clock synchronization with single-photon time resolution, and in particular to a dual-clock cooperative synchronization method in wireless communication based on single-photon counting detection. Background Art

[0002] Single photon counting detection is a light intensity detection technology with single photon limited sensitivity. Its principle is that when a weak light wave signal is incident on a single photon detector, the detector outputs a discrete pulse sequence. Each pulse indicates that a photon is detected, and then the intensity of the signal incident on the detector is represented by the density (i.e., count rate) of the detector output pulse signal, rather than the amplitude. Single photon counting detection is one of the key technologies for wireless optical communication in large attenuation scenarios such as deep space and underwater. Studies have shown that due to the influence of post-pulse, dead time, dark count effect, etc., the pulse output waveform of the single photon detector and the output waveform based on photodiode (PD) and avalanche photodiode (APD) have significant differences and typical characteristics, which bring new challenges to the design of wireless optical communication systems based on single photon detectors. In particular, single photon detection relies on accurate single photon counting, and its time resolution can reach the picosecond level, which means that compared with traditional optical communication systems based on PD or APD, wireless communication based on single photon detection requires higher-precision clock synchronization to achieve data demodulation. At the same time, since single-photon detection outputs discrete electrical pulses and the photon detection process is strongly affected by shot noise, in order to ensure reliable communication on extremely weak optical links, the key is how to extract clock synchronization signals from these discrete electrical pulses.

[0003] The traditional single-photon clock synchronization method counts the number of electrical pulses output by the detector during the high-level time slot of the gated clock, but this counting method may cause the counting results of two adjacent gated clocks to be the same, resulting in synchronization clock extraction errors and affecting system performance. Therefore, designing a high-precision clock synchronization method that can meet the needs of wireless communication based on single-photon detection and fully tapping the potential of single-photon detection technology is the premise and foundation for realizing highly robust single-photon counting communication. Summary of the invention

[0004] In response to the above problems, the present invention innovatively proposes a dual-clock collaborative synchronization method in wireless communication based on single-photon counting detection. When a weak light wave signal irradiates a single-photon detector, the detector will output a discrete electrical pulse signal. By processing these discrete electrical pulse signals using the dual-clock collaborative synchronization method of the present invention, high-precision clock synchronization of a single-photon counter can be achieved.

[0005] The technical solution for achieving the purpose of the present invention is as follows:

[0006] A dual clock cooperative synchronization method in wireless communication based on single photon counting detection, comprising:

[0007] At the receiving end, set N (N ≥ 2) parallel gated clocks Clk1, Clk2, ..., Clk N And a high frequency clock Clk h , the frequency of each gated clock is the same as the transmitter clock frequency f1, and the phase difference between two adjacent gated clocks is Each gated clock is equipped with an independent counter Cnt1, Cnt2, ..., Cnt N ;

[0008] When the gated clock Clk i When (i∈[1,N]) is at a high level, the electrical pulse output by the single-photon detector in response to the weak light signal is used as the counter Cnt i The enable signal, at the same time, the high-frequency clock Clk h As counter Cnt i The counting signal, that is, when there is an enable signal, the counter Cnt is turned on i , and every time the high frequency clock Clk h When the pulse rising edge arrives, the counter Cnt is triggered i Counts once; when the gated clock Clk i When it is low, the counter Cnt is paused. i Counts until the next gated clock Clk i When the high level comes, the counter Cnt i Keep counting;

[0009] The gated clock Clk i One clock cycle of (i∈[1,N]) is used as the counter Cnt i (i∈[1,N]) a counting cycle, when the counter Cnt i After M (M ≥ 1) counting cycles, the counter Cnt i Output a count value Count i (i∈[1,N]); compare Count1, Count2, ..., Count N The relative size of the count value is selected, and the gated clock corresponding to the maximum count value is used as the synchronization clock.

[0010] Through this method, the clock synchronization accuracy of the receiving end can reach

[0011] The specific technical solutions of the present invention are as follows:

[0012] A dual clock cooperative synchronization method in wireless communication based on single photon counting detection comprises the following steps:

[0013] S1, set N independent and parallel gated clocks at the receiving end. The frequency of each gated clock is the same as the clock frequency of the transmitting end, which is f1. The phase difference between two adjacent gated clocks is Δθ. and N ≥ 2;

[0014] S2, set a corresponding counter Cnt1, Cnt2, ..., Cnt for each of the N gated clocks. N ;

[0015] S3, set a high-frequency clock Clk h , its clock period is T1, the time slot width of the minimum electrical pulse output by the single-photon detector is T2, nT1<T2, n is an integer greater than or equal to 2;

[0016] S4, when the gated clock Clk i When (i∈[1,N]) is at a high level, the electrical pulse output by the single-photon detector in response to the weak light signal is used as the counter Cnt i The enable signal; at the same time, the high-frequency clock Clk h As counter Cnt i The counting signal, that is, when there is an enable signal, the counter Cnt is turned on i , and every time the high frequency clock Clk h Trigger counter Cnt i When the counter Cnt i It counts once, and when the gate clock Cnt i When the counter Cnt is low, i Pause counting until the gated clock Clk i is high level, and the single photon detector has an electrical pulse output, and the counter Cnt i Keep counting;

[0017] S5, gate the clock Clk i One clock cycle of (i∈[1,N]) is used as the counter Cnt i (i∈[1,N]) a counting cycle, when the counter Cnt i After M (M ≥ 1) counting cycles, the counter Cnt i Output a count value Count i , compare N count values ​​Count1, Count2, ..., Count NThe relative size of the count value is selected, and the gated clock corresponding to the maximum count value is used as the synchronization clock. At this point, the clock synchronization is completed.

[0018] The technical features and significant effects of the present invention are as follows:

[0019] (1) High-precision clock synchronization: Through the multi-channel gated clock and counter mechanism, the present invention can achieve high-precision clock synchronization, and the synchronization accuracy is proportional to the number of gated clocks N. The larger N is, the higher the clock synchronization accuracy is;

[0020] (2) Fast clock synchronization: The present invention sets multiple counters in parallel and uses a comparator to quickly select the best synchronization clock, thereby ensuring that the clock synchronization process is fast and efficient, reducing the delay problem existing in traditional synchronization methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a system block diagram of an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a single-photon detector according to an embodiment of the present invention outputting discrete electrical pulses in response to a weak light signal;

[0023] Figure 3 is a schematic diagram of clock synchronization using a gated clock and a high-frequency counting clock in an embodiment of the present invention;

[0024] Figure 4 About Figure 3 Medium counter Cnt i In the gated clock Clk i A detailed enlarged view of counting under the control of the electrical pulse signal;

[0025] Figure 5 is the counter Cnt in the embodiment of the present invention i Schematic diagram of the (i∈[1,N]) counting method.

[0026] In the figure, 1. first computer 2. transmitter 2-1. coding modulator 2-2. framer 3. laser driving module 4. laser 5. collimator 6. channel 7. convex lens 8. narrow band filter 9. single photon detector 10. receiver 10-1. gated clock generator 10-2. counter 10-3. comparator 11. second computer. DETAILED DESCRIPTION

[0027] The content of the present invention is further described below in conjunction with the embodiments and drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Example:

[0029] like Figure 1 As shown, an operable embodiment of a dual clock cooperative synchronization method in wireless communication based on single photon counting detection includes two parts: a transmitting end and a receiving end;

[0030] The transmitting end includes a first computer 1, a transmitter 2, a laser driving module 3, a laser 4 and a collimating lens 5;

[0031] The first computer 1, the transmitter 2, the laser driving module 3 and the laser 4 are connected in sequence, the collimator 5 is arranged in front of the laser 4, and the laser emitted by the laser 4 passes through the collimator 5 to reach the channel 6;

[0032] The transmitter 2 includes a coding modulator 2-1 and a framer 2-2, the coding modulator 2-1 is connected to the framer 2-2; the coding modulator 2-1 is connected to the first computer 1, and the framer 2-2 is connected to the laser driving module 3;

[0033] The receiving end includes a convex lens 7, a narrow-band filter 8, a single-photon detector 9, a receiver 10 and a second computer 11;

[0034] The single photon detector 9, the receiver 10 and the second computer 11 are connected in sequence, the narrow band filter 8 is arranged in front of the single photon detector 9, the convex lens 7 is arranged in front of the narrow band filter 8, and the convex lens 7 corresponds to the channel 6;

[0035] The receiver 10 includes a gated clock generator 10 - 1 , N (N ≥ 2) counters 10 - 2 and N (N ≥ 2) comparators 10 - 3 connected in sequence; the single photon detector 9 is connected to the gated clock generator 10 - 1 , and the comparator 10 - 3 is connected to the second computer 11 .

[0036] The weak optical signal arriving through the channel 6 is focused by the convex lens 7, and then reaches the single-photon detector 9 after passing through the narrow-band filter 8. The single-photon detector 9 outputs a discrete pulse signal and sends it to the receiver 10 for processing.

[0037] The specific steps of the receiving end in the embodiment are as follows:

[0038] like Figure 1 Figure 2 As shown, photon counting detection is a light intensity detection technology with single-photon limited sensitivity. Its principle is that the light signal sent by the laser 4 will become a weak light signal after passing through the channel 6 and irradiate the single-photon detector 9. After receiving the weak light signal, the single-photon detector 9 outputs a discrete electrical pulse.

[0039] A dual clock cooperative synchronization method in wireless communication based on single photon counting detection comprises the following steps:

[0040] S1), such as Figure 3 Figure 4 As shown, N independent and parallel gated clocks are set at the receiving end. The frequency of each gated clock is the same as the clock frequency of the transmitting end, which is f1. The phase difference between two adjacent gated clocks is Δθ. In the figure, N=30, and the 30 gated clocks operating in parallel use Clk1, Clk2, ..., Clk 30 express;

[0041] S2), a corresponding counter Cnt1, Cnt2, ..., Cnt is set for each of the 30 gated clocks. 30 ;

[0042] S3), set a high frequency clock Clk h , its clock period is T1, T1 = 4ns, and the time slot width of the minimum electrical pulse output by the single-photon detector is T2, T2 = 10ns;

[0043] S4), such as Figure 5 As shown, the gated clock Clk is shown in detail i (i∈[1,30]) corresponds to the counter Cnt i (i∈[1,30]) counting method: when the gated clock Clk i When (i∈[1,30]) is at a high level, the electrical pulse output by the single-photon detector in response to the weak light signal is used as the counter Cnt i The enable signal, at the same time, the high-frequency clock Clk h As counter Cnt i The counting signal, that is, when the enable signal exists, turns on the counter Cnt i , and every time the high-frequency clock triggers the counter Cnt i When the counter Cnt i It counts once, when the gated clock Clk i When the counter Cnt is low, i Pause counting until the gated clock Clk i is high level, and the single photon detector has an electrical pulse output, and the counter Cnt i Keep counting;

[0044] S5), such as Figure 3-Figure 5 As shown, the counter Cnt is shown in detail i (i∈[1,30]) Output count value: Gate clock Clk iOne clock cycle of (i∈[1,30]) is used as the counter Cnt i One counting cycle of the counter Cnt i After M counting cycles, the counter Cnt i Output a count value Count i (i∈[1,30]), Figure 2 M = 4, Figure 3 Medium counter Cnt i m counting cycles have been counted;

[0045] like Figure 3-Figure 4 As shown, the counter Cnt i The four counting cycles of (i∈[1,30]) use Cnt i _1, Cnt i _2, ..., Cnt i _4 indicates that counters Cnt1, Cnt2, ..., Cnt 30 The output count values ​​are Count1=33, Count2=21, Count3=15..., Count 30 =26;

[0046] like Figure 3-Figure 4 As shown, a comparator is used to compare Count1, Count2, ..., Count 30 The relative size of the maximum count value is selected, and the gated clock corresponding to the maximum count value is used as the synchronization clock.

[0047] At this point, clock synchronization is completed.

[0048] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A dual clock cooperative synchronization method in wireless communication based on single photon counting detection, characterized in that: The steps include: S1, set N independent and parallel gated clocks at the receiving end. The frequency of each gated clock is the same as the clock frequency of the transmitting end, which is f1. The phase difference between two adjacent gated clocks is Δθ. and N ≥ 2; S2, a corresponding counter unit Cnt1, Cnt2, ..., Cnt is set for each of the N gated clocks. N ; S3, set a high-frequency clock Clk h , its clock period is T1, the time slot width of the minimum electrical pulse output by the single-photon detector is T2, nT1<T2, n is an integer greater than or equal to 2; S4, when the gated clock Clk i When (i∈[1,N]) is at a high level, the electrical pulse output by the single-photon detector in response to the weak light signal is used as the counter Cnt i The enable signal; at the same time, the high-frequency clock Clk h As counter Cnt i The counting signal, that is, when there is an enable signal, the counter Cnt is turned on i , and every time the high frequency clock Clk h Trigger counter Cnt i When the counter Cnt i It counts once, and when the gated clock Clk i When the counter Cnt is low, i Pause counting until the gated clock Clk i is high level, and the single photon detector has an electrical pulse output, and the counter Cnt i Keep counting; S5, gate the clock Clk i One clock cycle of (i∈[1,N]) is used as the counter Cnt i (i∈[1,N]) a counting cycle, when the counter Cnt i After M (M ≥ 1) counting cycles, the counter Cnt i Output a count value Count i , compare N count values ​​Count1, Count2, ..., Count N The relative size of the count value is selected, and the gated clock corresponding to the maximum count value is used as the synchronization clock.

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