Data coding method and related device

Abstract

The embodiment of the invention provides a data coding method and a related device. The coding complexity is reduced while the code word length and the redundancy cost of an inner code are not changed. Specifically, for a first data stream subjected to outer code coding, every continuous k bits in the first data stream need to be subjected to inner code coding, and k is an odd number greater than 1. The other bits except one target bit in the k bits are subjected to XOR pairwise to obtain (k-1) / 2 bits in total. Further, a bit sequence including (k-1) / 2 bits and a target bit is subjected to second FEC coding to obtain p check bits. Wherein the n bits in the code word of the inner code after the inner code is coded comprise continuous k bits and p check bits. It can be seen that the embodiment of the invention adopts a mode of first exclusive OR and then encoding, for example, code word processing of (128, 119) can be realized through an encoder of (69, 60), and the encoding complexity is reduced while the code word length of an inner code and the redundancy cost are not changed.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of optical communications, and in particular, to a data encoding method and related devices. Background Art

[0002] Driven by 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTN) are developing towards large capacity and ultra-high speed. Using forward error correction (FEC) to correct the transmitted data can solve transmission errors and recover the original data sent by the sender from the received data.

[0003] In the 400GZR scenario, CFEC is used as the error correction coding scheme in the optical module, where the outer code uses staircase code and the inner code uses double-bit extended Hamming code. In the future 1.6TZR scenario, due to the significant increase in transmission rate, the power consumption problem faced by the existing CFEC (Concatenated-FEC) solution will become more severe, and a coding scheme with lower power consumption is urgently needed. Summary of the invention

[0004] The embodiments of the present application provide a data encoding method and related devices, which reduce the complexity of encoding while not changing the length of the inner code word and the redundancy cost.

[0005] In the first aspect, an embodiment of the present application provides a data encoding method. Specifically, first obtain k consecutive bits in a first data stream that has been encoded by a first forward error correction (FEC), and the first FEC encoding can be regarded as an outer code encoding. Wherein, k is an odd number greater than 1, and the consecutive k bits include a bit set and a target bit, and the bit set includes (k-1) / 2 bit subsets, and each bit subset includes 2 bits. Next, the consecutive k bits are inner-coded to obtain a codeword, and the specific operation of the inner-code encoding is as follows: first, XOR the 2 bits in each bit subset to obtain 1 bit to obtain a total of (k-1) / 2 bits, and then perform a second FEC encoding on the bit sequence including (k-1) / 2 bits and the target bit to obtain p check bits. Wherein, the codeword after inner-code encoding includes consecutive k bits and p check bits, and p is an integer greater than or equal to 1.

[0006] In this embodiment, for the first data stream that has been encoded by the outer code, every consecutive k bits in the first data stream need to be encoded by the inner code, where k is an odd number greater than 1. Specifically, the remaining bits of the k bits except for one target bit are XORed in pairs to obtain a total of (k-1) / 2 bits. Furthermore, a second FEC encoding is performed on the bit sequence including the (k-1) / 2 bits and the target bit to obtain p check bits. After the inner code encoding, the n bits in the inner code codeword include consecutive k bits and p check bits. It can be seen that the embodiment of the present application adopts a method of first XORing and then encoding. For example, the codeword processing of (128,119) can be realized by a (69,60) encoder, which reduces the complexity of encoding while not changing the inner code codeword length and redundancy cost.

[0007] In some possible implementations, the two bits in each bit subset are two adjacent bits in the continuous k bits. The method of selecting two adjacent bits for XOR is easier to implement and is conducive to standardization.

[0008] In some possible implementations, the p check bits are located after the consecutive k bits in the codeword, and the target bit is the last bit of the consecutive k bits. Alternatively, the p check bits are located before the consecutive k bits in the codeword, and the target bit is the first bit of the consecutive k bits. In other words, selecting the first bit or the last bit in the k-bit information sequence as the target bit, and arranging the check sequence of the p check bits next to the target bit is more conducive to achieving the distribution of the information sequence and the check sequence in the inner codeword.

[0009] In some possible implementations, after performing inner code encoding on continuous k bits to obtain a codeword, the method further includes: performing symbol mapping and polarization division on 8 bits from 4 bit subsets in a second data stream including at least one codeword to obtain a dual-polarization (DP)-16QAM symbol. Among them, the 4 bit subsets are respectively mapped to the I-path component in the X polarization direction, the Q-path component in the X polarization direction, the I-path component in the Y polarization direction, and the Q-path component in the Y polarization direction of the DP-16QAM symbol through Gray. In other words, any component of the DP-16QAM symbol is obtained by Gray mapping from 2 bits of a bit subset participating in XOR, so usually only one error bit will appear in the two bits mapped to the same PAM4 symbol, reducing the possibility of error bits.

[0010] In some possible implementations, the second FEC code uses a finite field GF(2 m ) BCH coding or extended BCH coding with t bits of error correction, enriching the coding methods that can be used for inner code coding. Among them, mt≤p, and That is, GF(2 m ) is not unique. For example, if the value of m is reduced by 1, the number of check bits can be reduced by t, thereby increasing the code rate and reducing the code overhead when the length of the information remains unchanged.

[0011] In some possible implementations, k=119, and the second FEC encoding uses GF(2 m ) is GF(2 8 ) or GF(2 7 ), which improves the feasibility of inner code encoding in the scenario where k=119.

[0012] In some possible implementations, the length of the codeword is n, and the second FEC encoding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following items:

[0013] n=133,k=119,GF(2 m )=GF(2 7 ), t=2, p=14;

[0014] n=135,k=119,GF(2 m )=GF(2 8 ), t=2, p=16.

[0015] In some possible implementations, the length of the codeword is n, and the second FEC encoding uses a finite field GF(2 m ) extended BCH code with t error correction bits, p check bits including q bits of cyclic redundancy check (CRC) extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following:

[0016] n=128,k=119,GF(2 m )=GF(2 7 ), t=1, p=9, q=2;

[0017] n=134,k=119,GF(2 m )=GF(2 7 ), t=2, p=15, q=1;

[0018] n=135,k=119,GF(2 m )=GF(2 7), t=2, p=16, q=2;

[0019] n=136,k=119,GF(2 m )=GF(2 8 ), t=2, p=17, q=1;

[0020] n=137,k=119,GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

[0021] In the second aspect, an embodiment of the present application provides a data encoding method. Specifically, first obtain k consecutive bits in a first data stream that has been encoded by a first FEC, and the first FEC encoding can be regarded as an outer code encoding. Wherein, k is an integer greater than or equal to 3, the consecutive k bits include v bit subsets, each bit subset includes 3 bits, and v is an integer greater than or equal to 1. Next, the consecutive k bits are encoded by inner code to obtain a codeword, and the specific operation of the inner code encoding is as follows: first, XOR the 3 bits in each bit subset to obtain 1 bit to obtain a total of v bits, and then perform a second FEC encoding on the bit sequence including v bits to obtain p check bits. The codeword after inner code encoding includes k consecutive bits and p check bits, and p is an integer greater than or equal to 1.

[0022] In this embodiment, for the first data stream that has been encoded by the outer code, every consecutive k bits in the first data stream need to be encoded by the inner code, where k is an odd number greater than 1. Specifically, a total of v bits can be obtained by performing XOR on every 3 bits of the k bits. Furthermore, the v bits are subjected to a second FEC encoding to obtain p check bits, and after the inner code encoding, the n bits in the inner code codeword include consecutive k bits and p check bits. It can be seen that the embodiment of the present application adopts a method of first XORing and then encoding. For example, the codeword processing of (128, 119) can be achieved by using a (50, 41) encoder, which reduces the complexity of encoding while not changing the inner code codeword length and redundancy cost.

[0023] In some possible implementations, the 3 bits in each bit subset are 3 consecutive bits among k consecutive bits. The method of selecting every 3 consecutive bits for XOR is easier to implement and is conducive to standardization.

[0024] In some possible implementations, k=v×3, that is, among the k bits, it is possible to perform XOR on every 3 bits, which has good practicality.

[0025] In some possible implementations, the continuous k bits also include r target bits, k=v×3+r, r=1 or 2. Performing a second FEC encoding on a bit sequence including v bits to obtain p check bits includes: performing a second FEC encoding on a bit sequence including v bits and r target bits to obtain p check bits. That is, the present solution can also be applied to a scenario where k is not divisible by 3, which expands the application scenario of the present solution.

[0026] In some possible implementations, the p check bits are located after the consecutive k bits in the codeword, and the target bits are the last r bits of the consecutive k bits. Alternatively, the p check bits are located before the consecutive k bits in the codeword, and the target bits are the first r bits of the consecutive k bits. In other words, the first r bits or the last r bits of the k-bit information sequence are selected as the target bits, and the check sequence of the p check bits is arranged adjacent to the target bit, which is more conducive to the distribution of the information sequence and the check sequence in the inner codeword.

[0027] In some possible implementations, after performing inner code encoding on continuous k bits to obtain a codeword, the method further includes: performing symbol mapping and polarization division on 12 bits from 4 bit subsets in a second data stream including at least one codeword to obtain a DP-64QAM symbol, wherein the 4 bit subsets are respectively mapped to the I-path component in the X polarization direction, the Q-path component in the X polarization direction, the I-path component in the Y polarization direction, and the Q-path component in the Y polarization direction of the DP-64QAM symbol through Gray mapping, and the X polarization direction is orthogonal to the Y polarization direction. In other words, any component of the DP-64QAM symbol is obtained by Gray mapping from 3 bits of a bit subset participating in XOR, so usually only one error bit will appear in the 3 bits mapped to the same PAM8 symbol, reducing the possibility of error bits.

[0028] In some possible implementations, the second FEC code uses a finite field GF(2 m ) BCH coding or extended BCH coding with t bits of error correction, enriching the coding methods that can be used for inner code coding. Among them, mt≤p, and v+r≤2 m -1-p, that is, GF(2 m ) is not unique. For example, if the value of m is reduced by 1, the number of check bits can be reduced by t, thereby increasing the code rate and reducing the code overhead when the length of the information remains unchanged.

[0029] In some possible implementations, k=119, and the second FEC encoding uses GF(2 m ) is GF(28 )、GF(2 7 ) or GF(2 6 ), which improves the feasibility of inner code encoding in the scenario where k=119.

[0030] In some possible implementations, the length of the codeword is n, and the second FEC encoding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following items:

[0031] n=131,k=119,GF(2 m )=GF(2 6 ), t=2, p=12;

[0032] n=133,k=119,GF(2 m )=GF(2 7 ), t=2, p=14;

[0033] n=135,k=119,GF(2 m )=GF(2 8 ), t=2, p=16.

[0034] In some possible implementations, the length of the codeword is n, and the second FEC encoding uses a finite field GF(2 m ) extended BCH code with t error correction bits, p check bits including q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following:

[0035] n=127,k=119,GF(2 m )=GF(2 6 ), t=1, p=8, q=2;

[0036] n=128,k=119,GF(2 m )=GF(2 7 ), t=1, p=9, q=2;

[0037] n=132,k=119,GF(2 m )=GF(2 6 ), t=2, p=13, q=1;

[0038] n=133,k=119,GF(2 m )=GF(2 6 ), t=2, p=14, q=2;

[0039] n=134,k=119,GF(2 m )=GF(2 7 ), t=2, p=15, q=1;

[0040] n=135,k=119,GF(2 m )=GF(2 7 ), t=2, p=16, q=2;

[0041] n=136,k=119,GF(2 m )=GF(2 8 ), t=2, p=17, q=1;

[0042] n=137,k=119,GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

[0043] In a third aspect, an embodiment of the present application provides a data encoding device, which includes: an acquisition unit and an encoding unit. The acquisition unit is used to: acquire k consecutive bits in a first data stream that has been encoded by a first FEC, k is an odd number greater than 1, the k consecutive bits include a bit set and a target bit, the bit set includes (k-1) / 2 bit subsets, and each bit subset includes 2 bits. The encoding unit is used to: perform inner code encoding on the consecutive k bits to obtain a codeword. The encoding unit is specifically used to: perform XOR on 2 bits in each bit subset to obtain 1 bit, so as to obtain a total of (k-1) / 2 bits; perform a second FEC encoding on a bit sequence including (k-1) / 2 bits and the target bit to obtain p check bits. The codeword after inner code encoding includes k consecutive bits and p check bits, and p is an integer greater than or equal to 1.

[0044] In some possible implementations, the two bits in each bit subset are two adjacent bits in the continuous k bits.

[0045] In some possible implementations, the p check bits are located after k consecutive bits in the codeword, and the target bit is the last bit of the k consecutive bits. Alternatively, the p check bits are located before k consecutive bits in the codeword, and the target bit is the first bit of the k consecutive bits.

[0046] In some possible embodiments, the data encoding device also includes a mapping unit, which is used to: perform symbol mapping and polarization division on 8 bits from 4 bit subsets in a second data stream including at least one codeword to obtain 1 DP-16QAM symbol, wherein the 4 bit subsets are respectively mapped to the I component in the X polarization direction, the Q component in the X polarization direction, the I component in the Y polarization direction, and the Q component in the Y polarization direction of the DP-16QAM symbol, and the X polarization direction and the Y polarization direction are orthogonal to each other.

[0047] In some possible implementations, the second FEC encoding uses GF(2 m ) BCH code or extended BCH code with t bits of error correction, m and t are both integers greater than or equal to 1, mt≤p, and

[0048] In some possible implementations, k=119, and the second FEC encoding uses GF(2 m ) is GF(2 8 ) or GF(2 7 ).

[0049] In some possible implementations, the length of the codeword is n, and the second FEC encoding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following items:

[0050] n=133,k=119,GF(2 m )=GF(2 7 ), t=2, p=14;

[0051] n=135,k=119,GF(2 m )=GF(2 8 ), t=2, p=16.

[0052] In some possible implementations, the length of the codeword is n, and the second FEC encoding uses a finite field GF(2 m ) extended BCH code with t error correction bits, p check bits including q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following:

[0053] n=128,k=119,GF(2 m )=GF(2 7 ), t=1, p=9, q=2;

[0054] n=134,k=119,GF(2m )=GF(2 7 ), t=2, p=15, q=1;

[0055] n=135,k=119,GF(2 m )=GF(2 7 ), t=2, p=16, q=2;

[0056] n=136,k=119,GF(2 m )=GF(2 8 ), t=2, p=17, q=1;

[0057] n=137,k=119,GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

[0058] In a fourth aspect, an embodiment of the present application provides a data encoding device, which includes: an acquisition unit and an encoding unit. The acquisition unit is used to: acquire k consecutive bits in a first data stream that has been encoded by a first FEC, k is an integer greater than or equal to 3, the k consecutive bits include v bit subsets, each bit subset includes 3 bits, and v is an integer greater than or equal to 1. The encoding unit is used to: perform inner code encoding on the k consecutive bits to obtain a codeword. The encoding unit is specifically used to: perform XOR on the three bits in each bit subset to obtain 1 bit, so as to obtain a total of v bits; perform a second FEC encoding on the bit sequence including v bits to obtain p check bits. The codeword after inner code encoding includes k consecutive bits and p check bits, and p is an integer greater than or equal to 1.

[0059] In some possible implementations, the 3 bits in each bit subset are 3 consecutive bits among the consecutive k bits.

[0060] In some possible implementations, k=v×3.

[0061] In some possible implementations, the consecutive k bits also include r target bits, k=v×3+r, r=1 or 2, and the encoding unit is specifically used to: perform a second FEC encoding on the bit sequence including v bits and r target bits to obtain p check bits.

[0062] In some possible implementations, the p check bits are located after the consecutive k bits in the codeword, and the target bits are the last r bits of the consecutive k bits. Alternatively, the p check bits are located before the consecutive k bits in the codeword, and the target bits are the first r bits of the consecutive k bits.

[0063] In some possible embodiments, the data encoding device also includes a mapping unit, which is used to: perform symbol mapping and polarization division on 12 bits from 4 bit subsets in a second data stream including at least one codeword to obtain 1 DP-64QAM symbol, wherein the 4 bit subsets are respectively mapped to the I component in the X polarization direction, the Q component in the X polarization direction, the I component in the Y polarization direction, and the Q component in the Y polarization direction of the DP-64QAM symbol, and the X polarization direction and the Y polarization direction are orthogonal to each other.

[0064] In some possible implementations, the second FEC encoding uses GF(2 m ) BCH code or extended BCH code with error correction of t bits, where m and t are integers greater than or equal to 1, mt≤p, and v+r≤2 m -1-p.

[0065] In some possible implementations, k=119, and the second FEC encoding uses GF(2 m ) is GF(2 8 )、GF(2 7 ) or GF(2 6 ).

[0066] In some possible implementations, the length of the codeword is n, and the second FEC encoding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following items:

[0067] n=131,k=119,GF(2 m )=GF(2 6 ), t=2, p=12;

[0068] n=133,k=119,GF(2 m )=GF(2 7 ), t=2, p=14;

[0069] n=135,k=119,GF(2 m )=GF(2 8 ), t=2, p=16.

[0070] In some possible implementations, the length of the codeword is n, and the second FEC encoding uses a finite field GF(2 m ) extended BCH code with t error correction bits, p check bits including q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following:

[0071] n=127,k=119,GF(2 m )=GF(2 6 ), t=1, p=8, q=2;

[0072] n=128,k=119,GF(2 m )=GF(2 7 ), t=1, p=9, q=2;

[0073] n=132,k=119,GF(2 m )=GF(2 6 ), t=2, p=13, q=1;

[0074] n=133,k=119,GF(2 m )=GF(2 6 ), t=2, p=14, q=2;

[0075] n=134,k=119,GF(2 m )=GF(2 7 ), t=2, p=15, q=1;

[0076] n=135,k=119,GF(2 m )=GF(2 7 ), t=2, p=16, q=2;

[0077] n=136,k=119,GF(2 m )=GF(2 8 ), t=2, p=17, q=1;

[0078] n=137,k=119,GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

[0079] In a fifth aspect, an embodiment of the present application provides a chip, which includes a processor and a memory, the memory and the processor are interconnected through lines, instructions are stored in the memory, and the processor is used to execute the method described in any implementation method of the first aspect and the second aspect.

[0080] In a sixth aspect, an embodiment of the present application provides a data transmission system, which includes a data sending device and a data receiving device, wherein the data sending device is used to execute the method described in any implementation mode of the first aspect and the second aspect and send data to the data receiving device, and the data receiving device is used to perform operations such as decoding the received data.

[0081] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a computer, the method described in any embodiment of the first aspect and the second aspect is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] Figure 1 A schematic diagram of a communication system used in an embodiment of the present application;

[0083] Figure 2 A schematic diagram of another communication system used in an embodiment of the present application;

[0084] Figure 3 A schematic diagram of a flow chart of a data encoding method provided in an embodiment of the present application;

[0085] FIG4( a ) is a schematic diagram of an implementation method of performing an XOR operation on every two bits in an embodiment of the present application;

[0086] FIG4( b ) is a schematic diagram of another implementation method of performing an XOR operation on every two bits in an embodiment of the present application;

[0087] FIG4( c ) is a schematic diagram of an implementation method of performing an XOR operation on every 3 bits in an embodiment of the present application;

[0088] Figure 5 This is a schematic diagram of an implementation method of internal code encoding in an embodiment of the present application;

[0089] Figure 6 This is a schematic diagram of the first application scenario of the internal code encoding in the embodiment of the present application;

[0090] Figure 7 This is a schematic diagram of a second application scenario of internal code encoding in an embodiment of the present application;

[0091] Figure 8 This is a schematic diagram of a third application scenario of internal code encoding in an embodiment of the present application;

[0092] Fig. 9 This is a schematic diagram of a fourth application scenario of internal code encoding in an embodiment of the present application;

[0093] Fig.10 This is a schematic diagram of a fifth application scenario of internal code encoding in an embodiment of the present application;

[0094] Fig.11 This is a schematic diagram of a sixth application scenario of internal code encoding in an embodiment of the present application;

[0095] Fig.12 This is a schematic diagram of the seventh application scenario of the internal code encoding in the embodiment of the present application;

[0096] Fig.13 A schematic diagram of the structure of a data encoding device in an embodiment of the present application;

[0097] Fig.14 Another structural schematic diagram of the data encoding device in the embodiment of the present application. DETAILED DESCRIPTION

[0098] The present application embodiment provides a data encoding method and related devices, which reduces the complexity of encoding without changing the inner code word length and redundancy cost. It should be noted that the terms "first", "second", etc. in the present application specification and claims and the above-mentioned drawings are used to distinguish similar objects, rather than to limit a specific order or sequence. It should be understood that the above-mentioned terms can be interchangeable under appropriate circumstances, so that the embodiments described in the present application can be implemented in a sequence other than the content described in the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, the process, method, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0099] Figure 1 Schematic diagram of a communication system used in the embodiment of the present application. Figure 1 As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04 and a receiving device 05. Taking the communication system as a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers, and the transmitting device 01 is also called a client-side chip (host chip) located at the transmitting end, and the receiving device 05 is also called a client-side chip located at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side chip is sometimes also called a client-side device (host device). Among them, the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the receiving device 05 and the receiving processing module 04 can be connected through the AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules (optical modules), electrical modules, connectors (connectors) or other modules that process data during data transmission. For example, the processing module can be an 800ZR module (800ZR module, a coherent optical module). Furthermore, the transmitting device 01, the transmitting processing module 02, the channel transmission medium 03, the receiving processing module 04 and the receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not specifically limited here.

[0100] Figure 2 FIG. 1 is a schematic diagram of another communication system used in the embodiment of the present application. Figure 2 As shown, at the transmitting end, the information source provides the data stream to be sent; the transmitting end data processor receives the data stream, and performs data processing including coding, interleaving, and modulation on it to obtain a symbol data stream, which is sent to the transmitting end signal processor for framing, transmitted through the channel, and reaches the receiving device. After the receiving device receives the distorted signal caused by noise or other damage in the channel, it is sent to the receiving end signal processor for dispersion compensation, synchronization, phase recovery and other operations, and then sent to the receiving end data processor for demodulation, deinterleaving, decoding, and recovery of the original data, which is sent to the destination. Among them, Figure 2 The transmitting data processing and transmitting signal processing shown in can be applied to Figure 1 In the sending end processing module 02 shown, Figure 2 The receiving end data processing and receiving end signal processing shown in can be applied to Figure 1 In the receiving end processing module 04 shown.

[0101] It should be understood that the "inner" in the inner code and the "outer" in the outer code are distinguished only based on the distance of the execution subject operating the data relative to the channel transmission medium. The execution subject operating the inner code is closer to the channel transmission medium, and the execution subject operating the outer code is farther away from the channel transmission medium. Figure 1 For example, since the transmitting end processing module 02 encodes the data twice before sending it to the channel transmission medium. The data encoded by the transmitting end processing module 02 first is far away from the channel transmission medium, and the data encoded by the transmitting end processing module 02 later is closer to the channel transmission medium. Therefore, the data encoded by the transmitting end processing module 02 first is called data encoded by the outer code, and the data encoded by the transmitting end processing module 02 later is called data encoded by the inner code. Correspondingly, the data decoded by the receiving end processing module 04 first is called data decoded by the inner code, and the data decoded by the receiving end processing module 04 later is called data decoded by the outer code. In a possible implementation, the above-mentioned inner code encoding and outer code encoding are both FEC encoding methods, thereby forming a cascade FEC transmission scheme. For example, the transmitting end processing module 02 can use staircase code for outer code encoding, use Hamming code for inner code encoding, or use Bose-Chaudhuri-Hocquenghem (BCH) code for inner code encoding.

[0102] It should be noted that the above content is an exemplary description of the application scenario of the data encoding method provided in the embodiment of the present application, and does not constitute a limitation on the application scenario of the data encoding method. It is known to those skilled in the art that as business needs change, its application scenario can be adjusted according to application needs, and the embodiment of the present application does not list them one by one. The following mainly introduces the data encoding method applied to the data sending end, and the data decoding method applied to the receiving end can be understood as the inverse operation of the data encoding method. On the basis of the determination of the data encoding method, the data decoding method is also clear, and this application will no longer introduce the data decoding method in detail.

[0103] Figure 3 A flow chart of a data encoding method provided in an embodiment of the present application. The data encoding method includes the following steps, which are described in detail below. It should be understood that for ease of explanation, the first FEC encoding in the following is equivalent to the outer code encoding described above, and the inner code encoding provided in the embodiment of the present application includes two operations, group XOR and second FEC encoding, which can be understood based on this in the following.

[0104] 101. Obtain k consecutive bits from a first data stream that has undergone first FEC encoding.

[0105] In the embodiment of the present application, the k consecutive bits in the first data stream are the k information bits to be encoded by the inner code. It should be understood that, for the inner code, the k information bits to be encoded by the inner code may include information bits and check bits in the outer code codeword. Considering that the embodiment of the present application mainly introduces the inner code encoding, the information bits appearing below can be understood as the information bits of the inner code encoding. It should also be understood that the present application does not limit the specific implementation method of the outer code encoding. As an example, the outer code encoding can specifically adopt staircase (512, 510) encoding.

[0106] 102. Perform an XOR operation on every s bits of k consecutive bits of the first data stream to obtain a sequence to be encoded.

[0107] It should be understood that, since the inner code codeword after the inner code encoding, the continuous s bits will be mapped into a symbol through Gray mapping and sent to the channel for transmission, under non-extremely harsh channel conditions, only one bit error will occur in these continuous s bits. The symbol mapping method includes but is not limited to quadrature phase shift keying (Quadrature PhaseShift Keying, QPSK) and quadrature amplitude modulation (Quadrature Amplitude Modulation, QAM), and further polarization symbol division is performed to obtain dual-polarization (Dual-polarization, DP) symbols, for example, DP-QPSK, DP-8QAM, DP-16QAM, DP-32QAM and DP-64QAM. As an example, when DP-16QAM is used, 2 consecutive bits in the inner codeword will be mapped to the same PAM4 symbol. As another example, when DP-64QAM is used, three consecutive bits in the inner codeword will be mapped to the same PAM8 symbol. Therefore, the embodiment of the present application considers performing an XOR operation on every 2 or 3 bits of the k consecutive bits of the first data stream before encoding. The following takes k=119 as an example to introduce several possible XOR operation methods.

[0108] FIG4(a) is a schematic diagram of an implementation method of performing an XOR operation on every two bits in an embodiment of the present application. As shown in FIG4(a), in a possible implementation method, since 119 is an odd number, there is one bit in the information sequence of 119 bits that cannot be XORed with each other. This bit is referred to as the target bit. It should be understood that the target bit can be any bit in the information sequence. Usually, the target bit is the first bit or the last bit in the information sequence. For example, as shown in FIG4(a), the target bit is the last bit in the information sequence. 118 For the sake of convenience, the remaining 118 bits in the information sequence except the target bit are referred to as a bit set. The bit set includes 59 bit subsets, each of which includes 2 bits. Then, the 2 bits in each bit subset are XORed to obtain 1 bit, so that a total of 59 bits can be obtained, as shown in b0-b0 in Figure 4(a). 58 In this embodiment, the two bits in each bit subset are two adjacent bits in the 119-bit information sequence. As shown in FIG4(a), a0 and a1 are XORed to obtain b0, a2 and a3 are XORed to obtain b1, ..., a 116 and a 117 XOR to get b 58 . Then, the target bit a in the information sequence 118 As one of the bits b in the sequence to be encoded 59, the sequence to be encoded includes b0-b obtained by XOR 58 and b 59 .

[0109] FIG4(b) is a schematic diagram of another implementation method of performing an XOR operation on every two bits in an embodiment of the present application. Different from the implementation method shown in FIG4(a), in another possible implementation method, the two bits in each bit subset can also be any two non-adjacent bits in the 119-bit information sequence, and the specific method is not limited here. For example, as shown in FIG4(b), a0 and a 59 XOR to get b0, a2 and a 60 XOR to get b1, ..., a 58 and a 117 XOR to get b 58 . Then, the target bit a in the information sequence 118 As one of the bits b in the sequence to be encoded 59 , the sequence to be encoded includes b0-b obtained by XOR 58 and b 59 .

[0110] It should be noted that based on the implementation of the 2-bit XOR shown in FIG. 4(a) and FIG. 4(b), the present application does not limit the specific value of k. If k is an odd number greater than 1, then there must be a target bit in the information sequence including k bits that does not participate in the XOR. If k is an even number, then all k bits in the information sequence can be XORed in pairs.

[0111] FIG4(c) is a schematic diagram of an implementation method of performing an XOR operation on every 3 bits in an embodiment of the present application. As shown in FIG4(c), in another possible implementation method, since the remainder when 119 is divided by 3 is 2, there are 2 bits in the information sequence including 119 bits that cannot perform a 3-bit XOR operation. These 2 bits are referred to as target bits here. It should be understood that these 2 target bits can be any 2 bits in the information sequence. Usually, these 2 target bits are the first 2 bits or the last 2 bits in the information sequence. For example, as shown in FIG4(c), these 2 target bits are the last 2 bits in the information sequence. 117 and a 118 For the sake of convenience, the remaining 117 bits in the information sequence except the target bit are referred to as a bit set. The bit set includes 39 bit subsets, each of which includes 3 bits. Then, the 3 bits in each bit subset are XORed to obtain 1 bit, so that a total of 39 bits can be obtained, as shown in Figure 4(c) b0-b 38 In this embodiment, the three bits in each bit subset are three consecutive bits in the 119-bit information sequence, as shown in FIG4(c).0、 XOR a1 and a2 to get b0, ..., a 114、 a 115 and a 116 XOR to get b 38 . Then, the target bit a in the information sequence 117 and a 118 As two bits b in the sequence to be encoded 39 and b 40 , the sequence to be encoded includes b0-b obtained by XOR 38、 b 39 and b 40 .

[0112] It should be noted that, based on the implementation of the 3-bit XOR shown in FIG4(c), the present application does not limit the specific value of k. For example, k may also be an integer multiple of 3, then all k bits in the information sequence can be subjected to 3-bit XOR. For another example, k may also be divided by 3 with a remainder of 1, then one of the k bits of the information sequence is the target bit that does not participate in the XOR, and all other bits can be subjected to 3-bit XOR.

[0113] 103. Perform a second FEC encoding on the sequence to be encoded.

[0114] Figure 5 Schematic diagram of an implementation method of internal code encoding in the embodiment of the present application. Figure 5As shown, the sequence to be encoded refers to a bit sequence to be subjected to the second FEC encoding. Among them, the sequence to be encoded includes the bits obtained by the XOR operation in step 102. On this basis, the sequence to be encoded may also include target bits that do not participate in the XOR. The specific situation depends on the value of k. Please refer to the relevant introduction of step 102. Here, k=119 is taken as an example. The sequence to be encoded is subjected to the second FEC encoding to obtain a check sequence including p check bits. For the inner code codeword obtained by the inner code encoding, the inner code codeword includes a k-bit information sequence and p check bits, that is, the length of the inner code codeword is n=k+p, and p is an integer greater than or equal to 1. In other words, the second FEC encoding of the sequence to be encoded is only used to generate the check sequence, and the inner code codeword obtained by encoding still includes a k-bit information sequence. For example, if the target bit is the last bit in the sequence to be encoded, the check sequence in the inner code codeword is located after the information sequence. For another example, if the target bit is the first bit in the sequence to be encoded, the check sequence in the inner code codeword is located before the information sequence. It should be noted that the above-mentioned second FEC coding can adopt BCH coding or extended BCH coding, wherein the p check bits in the inner code codeword using BCH coding do not include cyclic redundancy check (CRC) extended check bits, and the p check bits in the inner code codeword using extended BCH coding include 1-bit or 2-bit CRC extended check bits.

[0115] In a possible implementation manner, for a coding scheme using 2-bit XOR and 3-bit XOR, the second FEC coding may specifically use GF(2 m ) is a BCH code with t bits of error correction, where m and t are both integers greater than or equal to 1. GF refers to a finite field, also known as a Galois Field, 2 m Indicates the order of the finite field. The error correction capability of the second FEC code is t bits, that is, an inner code word can correct up to t bits. Among them, if the P check bits do not include the CRC extended check bit, then p = m × t; if the P check bits include 1 bit of CRC extended check bit, then p = m × t + 1; if the P check bits include 2 bits of CRC extended check bits, then p = m × t + 2.

[0116] In another possible implementation, for a 2-bit XOR encoding scheme, if Then the second FEC code can also use GF(2 m-1) to further simplify the inner code encoding scheme. Wherein, if the P check bits do not include the CRC extended check bit, then p = (m-1) × t; if the P check bits include 1 bit of CRC extended check bit, then p = (m-1) × t + 1; if the P check bits include 2 bits of CRC extended check bits, then p = (m-1) × t + 2. It should be understood that when the second FEC encoding adopts GF(2 m ) is denoted as n0. When the second FEC encoding uses GF(2 m-1 ) is a BCH codeword, the length of the inner codeword is recorded as n1, n0 = k + (m-1) t = n1-t, and the original (n0, k) codeword is replaced by the (n1, k) codeword. In other words, the number of check bits can be reduced by t by using this encoding method, thereby increasing the codeword rate and reducing the codeword overhead when the information length remains unchanged.

[0117] In another possible implementation, for a coding scheme using 3-bit XOR, k bits are recorded as including v bit subsets, each bit subset includes 3 bits, v is an integer greater than or equal to 1, and the number of CRC extended check bits included in p check bits is recorded as r. If v+r≤2 m-1 -1-p, the second FEC code can also use GF(2 m-1 ) to further simplify the inner code encoding scheme. Among them, if the P check bits do not include the CRC extended check bit, then p = (m-1) × t; if the P check bits include 1 bit of CRC extended check bit, then p = (m-1) × t + 1; if the P check bits include 2 bits of CRC extended check bits, then p = (m-1) × t + 2. If v + r ≤ 2 m-2 -1-p, the second FEC code can also use GF(2 m-2 ) to further simplify the inner code encoding scheme. Among them, if the P check bits do not include the CRC extended check bit, then p = (m-2) × t; if the P check bits include 1 bit of CRC extended check bit, then p = (m-2) × t + 1; if the P check bits include 2 bits of CRC extended check bits, then p = (m-2) × t + 2.

[0118] 104. Perform symbol mapping and polarization division on the second data stream.

[0119] It should be understood that the second data stream includes at least one inner code word encoded by the inner code. As an example, for a coding scheme using 2-bit XOR, symbol mapping and polarization division are performed on every 8 bits in the second data stream to obtain a DP-16QAM symbol. Among them, the 8 bits participating in the symbol mapping and polarization division come from 4 subsets of bits participating in the XOR operation in the information sequence. As another example, for a coding scheme using 3-bit XOR, symbol mapping and polarization division are performed on every 12 bits in the second data stream to obtain a DP-64QAM symbol. Among them, the 12 bits participating in the symbol mapping and polarization division come from 4 subsets of bits participating in the XOR operation in the information sequence. It should be understood that the 4 bit subsets are respectively mapped to the X polarization direction I-way (in-phase) component, the X polarization direction Q-way (quadrature-phase) component, the Y polarization direction I-way (in-phase) component and the Y polarization direction Q-way (quadrature-phase) component of the DP-16QAM symbol or the DP-64QAM symbol. Among them, the X polarization direction and the Y polarization direction are orthogonal to each other. That is, any component of the DP-16QAM symbol is obtained by mapping 2 bits of a bit subset participating in the XOR, and any component of the DP-64QAM symbol is obtained by mapping 3 bits of a bit subset participating in the XOR. It should also be understood that the above-mentioned 4 bit subsets mapped to the DP-16QAM symbol or DP-64QAM symbol can come from the same codeword or from different codewords, which is not specifically limited here.

[0120] It should be noted that, taking the information sequence length of the inner code encoding as 119 bits as an example, on this basis, the embodiment of the present application provides a variety of possible inner code encoding parameters. When the DP-16QAM scheme is adopted, the specific parameters are shown in Table 1 below, and when the DP-64QAM scheme is adopted, the specific parameters are shown in Table 2 below. Wherein, n represents the length of the inner code codeword, k represents the information sequence length of the inner code codeword, w represents the coding length (including the sequence to be encoded and the check sequence), f represents the length of the sequence to be encoded, GF(2 m ) represents a finite field. t represents the error correction capability of the inner code. OH represents the overhead of the inner code codeword, which refers to the ratio of the length of the check sequence to the length of the information sequence in the inner code codeword, that is, OH = (nk) / k. The no extension in the remarks means that there is no CRC extension check bit in the check sequence, the single-bit extension in the remarks means that there is a 1-bit CRC extension check bit in the check sequence, and the double-bit extension in the remarks means that there are 2-bit CRC extension check bits in the check sequence.

[0121] Table 1

[0122]

[0123]

[0124] For the solutions provided in Table 1, Solution 1 is defined in the finite field GF(2 7 ) with error correction capability t = 1, the complexity of encoding and decoding can be reduced by XOR method under the existing technology. The codeword actually encoded in scheme 5-7 is based on the finite field GF(2 8 ) on the t=2 system BCH(255,239), which is shortened by 179 bits to obtain the actual code BCH(76,60) of Scheme 5, which has a stronger coding gain than Scheme 1. On the basis of Scheme 5, by adding single-bit and double-bit CRC extension check bits respectively, the actual code BCH(77,60) of Scheme 6 and the actual code BCH(78,60) of Scheme 7 can be obtained, which can further improve the coding gain on the basis of Scheme 5. The actual code in Schemes 2-4 is based on the finite field GF(2 7 ) on the t=2 system BCH(127,113), the codeword is shortened by 53 bits to obtain the codeword of the actual code BCH(74,60) of Scheme 2. On the basis of Scheme 2, by adding single-bit and double-bit CRC extension check bits respectively, the codewords of the actual code BCH(75,60) of Scheme 3 and the actual code BCH(76,60) of Scheme 4 can be obtained. Compared with Schemes 5-7, Schemes 2-4 satisfy the above mentioned , so the original finite field GF(2 8 ) is replaced by a low-complexity finite field GF(2 7 ).

[0125] Table 2

[0126]

[0127]

[0128] For the schemes provided in Table 2, the actual encodings of schemes 1 and 2 are defined in the finite field GF(2 6 ) and GF(2 7 ) with error correction capability t = 1, the actual encoding of Scheme 3-5 is the finite field GF(2 6 ) with error correction capability t = 2, the actual encoding of Schemes 6-8 is the finite field GF(2 7 ) with error correction capability t = 2, the actual encoding of candidate schemes 9-11 is the finite field GF(2 8 ) on a BCH code with error correction capability t=2.

[0129] It should be noted that in some possible scenarios, the inner code coding scheme under the DP-16QAM modulation mode is compatible with the inner code coding scheme under the DP-64QAM modulation mode. The following Table 3 provides parameters for inner code coding that are compatible with the two modulation modes. In practical applications, the encoders corresponding to the two modulation modes can be integrated together for flexible selection according to actual needs.

[0130] Table 3

[0131]

[0132] Several specific inner code coding embodiments are introduced below in combination with relevant parameters of inner code coding.

[0133] Example 1: In DP-16QAM modulation mode, the inner code is (128,119)+GF(2 7 ) is encoded on (69,60).

[0134] Figure 6 This is a schematic diagram of the first application scenario of the internal code encoding in the embodiment of the present application. Figure 6 As shown, the length of the inner code codeword is 128 bits, the length of the information sequence is 119 bits, and the length of the check sequence is 9 bits. First, select 118 bits from the 119-bit information sequence A to form a sequence A', denoted as A' = [a'0, a'1, ... a' 117 ], A' can be any 118 bits in A. To facilitate subsequent channel interleaving and modulation, the first 118 bits in A can be selected as A', that is, A' = [a0, a1, ... a 117 Then, two adjacent bits in A' are grouped together and XORed to obtain 59 bits [b0, b1, ..., b 58 ]. At the same time, the bits in A that are not selected into A' are recorded as A\A', and A\A' will skip the group XOR operation with b0~b 58 Combined together to form the sequence to be encoded B[0:59] = [b0, b1, ..., b 59 ], which means as follows: Then, the coded sequence is encoded using the extended Hamming code (69,60) to generate a 9-bit check bit [p0, p1, …, p8]. The extended Hamming code (69,60) is constructed on the finite field GF(2 7 ) is obtained by shortening 59 bits. Finally, the generated codeword C[0:127]=[c0,c1,…,c 127 ] can be expressed as It should be understood that in the above process, SD-FEC (128, 119) is still a system code, that is, the (69, 60) code is only used to generate check bits and does not participate in actual transmission.

[0135] Embodiment 2: In DP-16QAM modulation mode, the inner code is (133,119)+GF(2 7 ) is encoded on (74,60).

[0136] Figure 7 Schematic diagram of the second application scenario of the internal code encoding in the embodiment of the present application. Figure 7 As shown, the length of the inner code codeword is 133 bits, the length of the information sequence is 119 bits, and the length of the check sequence is 14 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is encoded by BCH(74,60) to generate a 14-bit check bit [p0,p1,…,p 13 ] Among them, BCH (74,60) is constructed on the finite field GF (2 7 ) on t = 2 BCH (127, 113), obtained by shortening 53 bits. GF ​​(2 7 The generating polynomial of BCH(74,60) on ) can be expressed as:

[0137] g(x)=M1(x)M3(x)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)

[0138] =x 14 +x 9 +x 8 +x 6 +x 5 +x 4 +x 2 +x+1

[0139] Among them, M1(x) and M3(x) correspond to α respectively. 1 With α 3 The minimum polynomial of α is a finite field GF(2 7 ) primitive element. The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 14m(x) is divided by g(x) by modulo 2 division to obtain the remainder polynomial r(x), and the coefficients of each term in r(x) are the check sequence P[0:13]. Finally, the information sequence A and the check sequence P form a complete codeword of the inner code (133,119), denoted as C[0:132] = [c0,c1,…,c 132 ], which can be expressed as

[0140] Example 3: In DP-16QAM modulation mode, the inner code is (134,119)+GF(2 7 ) is encoded at (75,60).

[0141] Figure 8 FIG. 1 is a schematic diagram of the third application scenario of the internal code encoding in the embodiment of the present application. Figure 8 As shown, the length of the inner code codeword is 134 bits, the length of the information sequence is 119 bits, and the length of the check sequence is 15 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is extended by BCH(75,60) encoding to generate 15-bit check bits [p0,p1,…,p 14 ]. The extended BCH (75, 60) is obtained by adding a single-bit parity check on the basis of BCH (74, 60) in Example 2. GF (2 7 The generator polynomial of the extended BCH(75,60) on ) can be expressed as:

[0142] g1(x)=g(x)(x+1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x+1)

[0143] =x 15 +x 14 +x 10 +x 8 +x 7 +x 4 +x 3 +1

[0144] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 15m(x) is divided by g1(x) through modulo 2 division to obtain the remainder polynomial r(x), and the coefficients of each term in r(x) are the check sequence P[0:14]. Finally, the information sequence A and the check sequence P form a complete codeword of the inner code (134,119), denoted as C[0:133] = [c0,c1,…,c 133 ], which can be expressed as

[0145] Example 4: In DP-16QAM modulation mode, the inner code is (135,119)+GF(2 7 ) is encoded on (76,60).

[0146] Fig. 9 Schematic diagram of the fourth application scenario of the internal code encoding in the embodiment of the present application. Fig. 9 As shown, the length of the inner code codeword is 135 bits, the length of the information sequence is 119 bits, and the length of the check sequence is 16 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is extended by BCH (76, 60) encoding to generate 16-bit check bits [p0, p1, ..., p 15 ]. The extended BCH (76, 60) is obtained by adding a double-bit parity check on the basis of BCH (74, 60) in Example 2. GF (2 7 The generator polynomial of the extended BCH(76,60) on ) can be expressed as:

[0147] g2(x)=g(x)(x 2 +1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x 2 +1)

[0148] =x 16 +x 14 +x 11 +x 10 +x 9 +x 7 +x 5 +x 3 +x+1

[0149] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 16m(x) is divided by g2(x) by modulo 2 division to obtain the remainder polynomial r(x), and the coefficients of each term in r(x) are the check sequence P[0:15]. Finally, the information sequence A and the check sequence P form a complete codeword of the inner code (135,119), denoted as C[0:134] = [c0,c1,…,c 134 ], which can be expressed as

[0150] Example 5: In DP-16QAM modulation mode, the inner code is (135,119)+GF(2 8 ) is encoded on (76,60).

[0151] like Fig. 9 As shown, the length of the inner code codeword is 135 bits, the length of the information sequence is 119 bits, and the length of the check sequence is 16 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is encoded by BCH(76,60) to generate a 16-bit check bit [p0,p1,…,p 15 ]. Among them, BCH(76,60) is constructed on the finite field GF(2 8 ) is obtained by shortening GF(2 8 The generating polynomial of BCH(76,60) on ) can be expressed as:

[0152] g3(x)=M1(x)M3(x)=(x 8 +x 4 +x 3 +x 2 +1)(x 8 +x 6 +x 5 +x 4 +x 2 +x+1)

[0153] =x 16 +x 14 +x 13 +x 11 +x 10 +x 9 +x 8 +x 6 +x 5 +x+1

[0154] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 16m(x) is divided by g3(x) through modulo 2 division to obtain the remainder polynomial r(x), and the coefficients of each term in r(x) are the check sequence P[0:15]. Finally, the information sequence A and the check sequence P form a complete codeword of the inner code (135,119), denoted as C[0:134] = [c0,c1,…,c 134 ], which can be expressed as

[0155] Example 6: In DP-16QAM modulation mode, the inner code is (136,119)+GF(2 8 ) is encoded on (77,60).

[0156] Fig.10 Schematic diagram of the fifth application scenario of the internal code encoding in the embodiment of the present application. Fig.10 As shown, the length of the inner code codeword is 136 bits, the length of the information sequence is 119 bits, and the length of the check sequence is 17 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is extended by BCH(77,60) encoding to generate 17-bit check bits [p0,p1,…,p 16 ]. The extended BCH (77, 60) is obtained by adding a single-bit parity check on the basis of BCH (76, 60) in Example 5. GF (2 8 The generator polynomial of the extended BCH(77,60) on ) can be expressed as:

[0157] g4(x)=g3(x)(x+1)

[0158] =(x 8 +x 4 +x 3 +x 2 +1)(x 8 +x 6 +x 5 +x 4 +x 2 +x+1)(x+1)

[0159] =x 17 +x 16 +x 15 +x 13 +x 12 +x 8 +x 7 +x 5 +x 2 +1

[0160] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x).17 m(x) is divided by g4(x) through modulo 2 division to obtain the remainder polynomial r(x), and the coefficients of each term in r(x) are the check sequence P[0:16]. Finally, the information sequence A and the check sequence P form a complete codeword of the inner code (136,119), denoted as C[0:135] = [c0,c1,…,c 135 ], which can be expressed as

[0161] Example 7: In DP-16QAM modulation mode, the inner code is (137,119)+GF(2 8 ) is encoded on (78,60).

[0162] Fig.11 Schematic diagram of the sixth application scenario of the internal code encoding in the embodiment of the present application. Fig.11 As shown, the length of the inner code codeword is 137 bits, the length of the information sequence is 119 bits, and the length of the check sequence is 18 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is extended by BCH(78,60) encoding to generate 18-bit check bits [p0,p1,…,p 17 ]. The extended BCH (78, 60) is obtained by adding a double-bit parity check on the basis of BCH (76, 60) in Example 5. GF (2 8 The generator polynomial of the extended BCH(78,60) on ) can be expressed as:

[0163] g5(x)=g3(x)(x 2 +1)

[0164] =(x 8 +x 4 +x 3 +x 2 +1)(x 8 +x 6 +x 5 +x 4 +x 2 +x+1)(x 2 +1)

[0165] =x 18 +x 15 +x 14 +x 12 +x 9 +x 7 +x 6 +x 5 +x 3 +x 2 +x+1

[0166] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 18 m(x) is divided by g5(x) through modulo 2 division to obtain the remainder polynomial r(x), and the coefficients of each term in r(x) are the check sequence P[0:17]. Finally, the information sequence A and the check sequence P form a complete codeword of the inner code (137,119), denoted as C[0:136] = [c0,c1,…,c 136 ], which can be expressed as

[0167] Example 8: In DP-64QAM modulation mode, the inner code is (128,119)+GF(2 7 ) is encoded on (50,41).

[0168] Fig.12 FIG. 7 is a schematic diagram of the seventh application scenario of the internal code encoding in the embodiment of the present application. Fig.12 As shown, the length of the inner code codeword is 128 bits, the length of the information sequence is 119 bits, and the length of the check sequence is 9 bits. First, select 117 bits from the 119-bit information sequence A to form a sequence A', denoted as A' = [a'0, a'1, ... a' 116 ], A' can be any 117 bits in A. To facilitate subsequent channel interleaving and modulation, the first 117 bits in A can be selected as A', that is, A' = [a0, a1, ... a 116 Then the three consecutive bits in A' are grouped together and XORed to obtain 39 bits [b0, b1, ..., b 38 ]. At the same time, the bits in A that are not selected into A' are recorded as A\A', and A\A' will skip the group XOR operation with b0~b 38 The combined sequence to be encoded is B[0:40]=[b0,b1,…,b 40 ], which means as follows: Then, the coded sequence is encoded using the extended Hamming code (50,41) to generate a 9-bit check bit [p0,p1,…,p8]. The extended Hamming code (50,41) is constructed over the finite field GF(2 7 ) is obtained by shortening 79 bits. Finally, the generated codeword C[0:127]=[c0,c1,…,c 127 ] can be expressed as

[0169] Fig.13 FIG. 1 is a schematic diagram of a structure of a data encoding device in an embodiment of the present application. Fig.13 As shown, the data encoding device includes an acquisition unit 201, an encoding unit 202 and a mapping unit 203. The acquisition unit 201 is used to perform the operation of the above step 101, the encoding unit 202 is used to perform the operations of the above steps 102 and 103, and the mapping unit 203 is used to perform the operation of the above step 104. It should be understood that the data encoding device provided by the present application can also be implemented in other ways. For example, the unit division in the above device is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of the present application can be integrated into a processing unit, or they can be independent physical units, or two or more functional units can be integrated into a processing unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0170] Fig.14 FIG. 2 is another structural diagram of the data encoding device in the embodiment of the present application. Fig.14 As shown, the data encoding device includes a processor 301 and a transceiver 302. The processor 301 and the transceiver 302 are connected to each other through a line. Specifically, the transceiver 302 is used to perform data transmission and reception operations, and the processor 301 is used to perform other operations except data transmission and reception. In a possible implementation, the processor 301 may include the above Fig.13 The encoding unit 202 and mapping unit 203 shown in the figure, the transceiver 302 includes the above Fig.13 The acquisition unit 201 is shown. Optionally, the data encoding device may further include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0171] The embodiment of the present application also provides a chip. The chip integrates a circuit and one or more interfaces for implementing the functions of the above-mentioned processor 301. When the chip integrates a memory, the chip can complete the method steps of any one or more embodiments in the above-mentioned embodiments. When the chip does not integrate a memory, it can be connected to an external memory through an interface. The chip implements the actions performed by the sending end device or the receiving end device in the above-mentioned embodiment according to the program code stored in the external memory.

[0172] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A data encoding method, characterized in that: include: Acquire k consecutive bits in a first data stream that has been encoded by a first forward error correction (FEC), where k is an odd number greater than 1, and the k consecutive bits include a bit set and a target bit, where the bit set includes (k-1) / 2 bit subsets, and each of the bit subsets includes 2 bits; The k consecutive bits are inner-coded to obtain a codeword, wherein the inner-coded encoding includes: XORing two bits in each of the bit subsets to obtain one bit, so as to obtain a total of (k-1) / 2 bits; Performing a second FEC encoding on a bit sequence including the (k-1) / 2 bits and the target bit to obtain p check bits, wherein the codeword includes the consecutive k bits and the p check bits, and p is an integer greater than or equal to 1.

2. The method according to claim 1, characterized in that The two bits in each of the bit subsets are two adjacent bits in the continuous k bits.

3. The method according to claim 1 or 2, characterized in that: The p check bits are located after the consecutive k bits in the codeword, and the target bit is the last bit of the consecutive k bits; or, In the codeword, the p check bits are located before the consecutive k bits, and the target bit is the first bit of the consecutive k bits.

4. The method according to any one of claims 1 to 3, characterized in that After performing inner code encoding on the continuous k bits to obtain a codeword, the method further includes: Symbol mapping and polarization division are performed on 8 bits from 4 bit subsets in a second data stream including at least one of the codewords to obtain a dual-polarization DP-16QAM symbol, wherein the 4 bit subsets are respectively mapped to an I component in an X polarization direction, a Q component in an X polarization direction, an I component in a Y polarization direction, and a Q component in a Y polarization direction of the DP-16QAM symbol, and the X polarization direction is orthogonal to the Y polarization direction.

5. The method according to any one of claims 1 to 4, characterized in that The second FEC code uses a finite field GF(2 m ) BCH code or extended BCH code with t bits of error correction, m and t are both integers greater than or equal to 1, mt≤p, and k 2 +1 +p≤2 m -1.

6. The method according to any one of claims 1 to 5, characterized in that k=119, the second FEC code uses GF(2 m ) is GF(2 8 ) or GF(2 7 ).

7. The method according to any one of claims 1 to 6, characterized in that The length of the codeword is n, and the second FEC coding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following items: n=133,k=119,GF(2 m )=GF(2 7 ),t=2,p=14; n=135,k=119,GF(2 m )=GF(2 8 ),t=2,p=16。 8. The method according to any one of claims 1 to 6, characterized in that The length of the codeword is n, and the second FEC coding adopts the finite field GF(2 m ) extended BCH code with t error correction bits, wherein the p check bits include q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following: n=128,k=119,GF(2 m )=GF(2 7 ),t=1,p=9,q=2; n=134,k=119,GF(2 m )=GF(2 7 ),t=2,p=15,q=1; n=135,k=119,GF(2 m )=GF(2 7 ),t=2,p=16,q=2; n=136,k=119,GF(2 m )=GF(2 8 ),t=2,p=17,q=1; n=137,k=119,GF(2 m )=GF(2 8 ),t=2,p=18,q=2。 9. A data encoding method, characterized in that: include: Obtain k consecutive bits in a first data stream that has been encoded by a first forward error correction (FEC), where k is an integer greater than or equal to 3, the k consecutive bits include v bit subsets, each of the bit subsets includes 3 bits, and v is an integer greater than or equal to 1; The k consecutive bits are inner-coded to obtain a codeword, wherein the inner-coded encoding includes: XORing three bits in each of the bit subsets to obtain one bit, so as to obtain a total of v bits; Performing a second FEC encoding on the bit sequence including the v bits to obtain p check bits, wherein the codeword includes the consecutive k bits and the p check bits, and p is an integer greater than or equal to 1.

10. The method according to claim 9, characterized in that The three bits in each of the bit subsets are three consecutive bits in the consecutive k bits.

11. The method according to claim 9 or 10, characterized in that: k=v×3.

12. The method according to claim 9 or 10, characterized in that: The continuous k bits also include r target bits, k=v×3+r, r=1 or 2, and performing the second FEC encoding on the bit sequence including the v bits to obtain p check bits includes: The second FEC encoding is performed on a bit sequence including the v bits and the r target bits to obtain the p check bits.

13. The method according to claim 12, characterized in that In the codeword, the p check bits are located after the consecutive k bits, and the target bits are the last r bits of the consecutive k bits; or, In the codeword, the p check bits are located before the consecutive k bits, and the target bits are the first r bits of the consecutive k bits.

14. The method according to any one of claims 9 to 13, characterized in that After performing inner code encoding on the continuous k bits to obtain a codeword, the method further includes: Symbol mapping and polarization division are performed on 12 bits from 4 bit subsets in a second data stream including at least one of the codewords to obtain a dual-polarization DP-64QAM symbol, wherein the 4 bit subsets are respectively mapped to an I component in an X polarization direction, a Q component in an X polarization direction, an I component in a Y polarization direction, and a Q component in a Y polarization direction of the DP-64QAM symbol, and the X polarization direction is orthogonal to the Y polarization direction.

15. The method according to any one of claims 9 to 14, characterized in that The second FEC code uses a finite field GF(2 m ) BCH code or extended BCH code with error correction of t bits, where m and t are integers greater than or equal to 1, mt≤p, and v+r≤2 m -1-p.

16. The method according to any one of claims 9 to 15, characterized in that k=119, the second FEC encoding uses GF(2 m ) is GF(2 8 )、GF(2 7 ) or GF(2 6 ).

17. The method according to any one of claims 9 to 16, characterized in that The length of the codeword is n, and the second FEC coding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following items: n=131,k=119,GF(2 m )=GF(2 6 ),t=2,p=12; n=133,k=119,GF(2 m )=GF(2 7 ),t=2,p=14; n=135,k=119,GF(2 m )=GF(2 8 ),t=2,p=16。 18. The method according to any one of claims 9 to 16, characterized in that The length of the codeword is n, and the second FEC coding adopts the finite field GF(2 m ) extended BCH code with t error correction bits, wherein the p check bits include q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following: n=127,k=119,GF(2 m )=GF(2 6 ),t=1,p=8,q=2; n=128,k=119,GF(2 m )=GF(2 7 ),t=1,p=9,q=2; n=132,k=119,GF(2 m )=GF(2 6 ),t=2,p=13,q=1; n=133,k=119,GF(2 m )=GF(2 6 ),t=2,p=14,q=2; n=134,k=119,GF(2 m )=GF(2 7 ),t=2,p=15,q=1; n=135,k=119,GF(2 m )=GF(2 7 ),t=2,p=16,q=2; n=136,k=119,GF(2 m )=GF(2 8 ),t=2,p=17,q=1; n=137,k=119,GF(2 m )=GF(2 8 ),t=2,p=18,q=2。 19. A data encoding device, characterized in that: include: Acquisition unit and encoding unit; The acquisition unit is used to: acquire k consecutive bits in a first data stream that has been encoded by a first forward error correction (FEC), where k is an odd number greater than 1, and the k consecutive bits include a bit set and a target bit, where the bit set includes (k-1) / 2 bit subsets, and each of the bit subsets includes 2 bits; The encoding unit is used to: perform inner code encoding on the continuous k bits to obtain a code word; The encoding unit is specifically used to: perform XOR on 2 bits in each of the bit subsets to obtain 1 bit, so as to obtain a total of (k-1) / 2 bits; Performing a second FEC encoding on a bit sequence including the (k-1) / 2 bits and the target bit to obtain p check bits, wherein the codeword includes the consecutive k bits and the p check bits, and p is an integer greater than or equal to 1.

20. The data encoding device according to claim 19, characterized in that: The two bits in each of the bit subsets are two adjacent bits in the continuous k bits.

21. The data encoding device according to claim 19 or 20, characterized in that: The p check bits are located after the consecutive k bits in the codeword, and the target bit is the last bit of the consecutive k bits; or, In the codeword, the p check bits are located before the consecutive k bits, and the target bit is the first bit of the consecutive k bits.

22. The data encoding device according to any one of claims 19 to 21, characterized in that: The data encoding device further comprises a mapping unit, wherein the mapping unit is used for: Symbol mapping and polarization division are performed on 8 bits from 4 bit subsets in a second data stream including at least one of the codewords to obtain a dual-polarization DP-16QAM symbol, wherein the 4 bit subsets are respectively mapped to an I component in an X polarization direction, a Q component in an X polarization direction, an I component in a Y polarization direction, and a Q component in a Y polarization direction of the DP-16QAM symbol, and the X polarization direction is orthogonal to the Y polarization direction.

23. The data encoding device according to any one of claims 19 to 22, characterized in that: The second FEC code uses a finite field GF(2 m ) BCH code or extended BCH code with t bits of error correction, m and t are both integers greater than or equal to 1, mt≤p, and k 2 +1 +p≤2 m -1.

24. The data encoding device according to any one of claims 19 to 23, characterized in that: k=119, the second FEC encoding uses GF(2 m ) is GF(2 8 ) or GF(2 7 ).

25. The data encoding device according to any one of claims 19 to 24, characterized in that: The length of the codeword is n, and the second FEC coding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following items: n=133,k=119,GF(2 m )=GF(2 7 ),t=2,p=14; n=135,k=119,GF(2 m )=GF(2 8 ),t=2,p=16。 26. The data encoding device according to any one of claims 19 to 24, characterized in that: The length of the codeword is n, and the second FEC coding adopts the finite field GF(2 m ) extended BCH code with t error correction bits, wherein the p check bits include q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following: n=128,k=119,GF(2 m )=GF(2 7 ),t=1,p=9,q=2; n=134,k=119,GF(2 m )=GF(2 7 ),t=2,p=15,q=1; n=135,k=119,GF(2 m )=GF(2 7 ),t=2,p=16,q=2; n=136,k=119,GF(2 m )=GF(2 8 ),t=2,p=17,q=1; n=137,k=119,GF(2 m )=GF(2 8 ),t=2,p=18,q=2。 27. A data encoding device, characterized in that: include: Acquisition unit and encoding unit; The acquisition unit is used to: acquire k consecutive bits in the first data stream after the first forward error correction FEC encoding, where k is an integer greater than or equal to 3, the k consecutive bits include v bit subsets, each of the bit subsets includes 3 bits, and v is an integer greater than or equal to 1; The encoding unit is used to: perform inner code encoding on the continuous k bits to obtain a code word; The encoding unit is specifically used for: performing XOR on three bits in each of the bit subsets to obtain one bit, so as to obtain a total of v bits; Performing a second FEC encoding on the bit sequence including the v bits to obtain p check bits, wherein the codeword includes the consecutive k bits and the p check bits, and p is an integer greater than or equal to 1.

28. The data encoding device according to claim 27, characterized in that: The three bits in each of the bit subsets are three consecutive bits in the consecutive k bits.

29. The data encoding device according to claim 27 or 28, characterized in that: k=v×3.

30. The data encoding device according to claim 27 or 28, characterized in that: The continuous k bits also include r target bits, k=v×3+r, r=1 or 2, and the encoding unit is specifically used for: The second FEC encoding is performed on a bit sequence including the v bits and the r target bits to obtain the p check bits.

31. The data encoding device according to claim 30, characterized in that: In the codeword, the p check bits are located after the consecutive k bits, and the target bits are the last r bits of the consecutive k bits; or, In the codeword, the p check bits are located before the consecutive k bits, and the target bits are the first r bits of the consecutive k bits.

32. The data encoding device according to any one of claims 27 to 31, characterized in that: The data encoding device further comprises a mapping unit, wherein the mapping unit is used for: Symbol mapping and polarization division are performed on 12 bits from 4 bit subsets in a second data stream including at least one of the codewords to obtain a dual-polarization DP-64QAM symbol, wherein the 4 bit subsets are respectively mapped to an I component in an X polarization direction, a Q component in an X polarization direction, an I component in a Y polarization direction, and a Q component in a Y polarization direction of the DP-64QAM symbol, and the X polarization direction is orthogonal to the Y polarization direction.

33. The data encoding device according to any one of claims 27 to 32, characterized in that: The second FEC code uses a finite field GF(2 m ) BCH code or extended BCH code with error correction of t bits, where m and t are both integers greater than or equal to 1, mt≤p, and v+r≤2 m -1-p.

34. The data encoding device according to any one of claims 27 to 33, characterized in that: k=119, the second FEC encoding uses GF(2 m ) is GF(2 8 )、GF(2 7 ) or GF(2 6 ).

35. The data encoding device according to any one of claims 27 to 34, characterized in that: The length of the codeword is n, and the second FEC coding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following items: n=131,k=119,GF(2 m )=GF(2 6 ),t=2,p=12; n=133,k=119,GF(2 m )=GF(2 7 ),t=2,p=14; n=135,k=119,GF(2 m )=GF(2 8 ),t=2,p=16。 36. The data encoding device according to any one of claims 27 to 34, characterized in that: The length of the codeword is n, and the second FEC coding adopts the finite field GF(2 m ) extended BCH code with t error correction bits, wherein the p check bits include q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following: n=127,k=119,GF(2 m )=GF(2 6 ),t=1,p=8,q=2; n=128,k=119,GF(2 m )=GF(2 7 ),t=1,p=9,q=2; n=132,k=119,GF(2 m )=GF(2 6 ),t=2,p=13,q=1; n=133,k=119,GF(2 m )=GF(2 6 ),t=2,p=14,q=2; n=134,k=119,GF(2 m )=GF(2 7 ),t=2,p=15,q=1; n=135,k=119,GF(2 m )=GF(2 7 ),t=2,p=16,q=2; n=136,k=119,GF(2 m )=GF(2 8 ),t=2,p=17,q=1; n=137,k=119,GF(2 m )=GF(2 8 ),t=2,p=18,q=2。 37. A chip, characterized in that: The chip includes a processor and a memory, wherein the memory and the processor are connected to each other via a line, instructions are stored in the memory, and the processor is used to execute the method according to any one of claims 1 to 18.

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