Bit error judgment method for CANFD frame, controller and communication system

Abstract

The application relates to a bit error judgment method for a CANFD frame, a controller and a communication system. After storing to-be-sent data and bit timing parameters into a configuration register, the to-be-sent data and the bit timing parameters are transmitted to a bit stream processor and a bit timing unit through a sending buffer. Sampling points and sending points are generated in the bit timing unit according to the bit timing parameters. Sending bits are generated in the bit stream processor according to the to-be-sent data and the sending points, a CANFD frame is constructed, and the frame is output through a sending port. The generated sending bits are sequentially transmitted to an error management unit. Sampling bits are generated by sampling at a receiving port, and the sampling bits are analyzed. The analysis result is transmitted to the error management unit. In the error management unit, for data bits in a high-speed data bit period, each data bit of the to-be-sent data is directly obtained from the configuration register and compared with the analysis result. If there is a difference, it is judged as a bit error. The method can effectively avoid the difficulty and inaccuracy of calculating SSP in the prior art.

Description

Technical Field

[0001] This application relates to the field of CANFD communication technology, and in particular to a bit error judgment method, controller and communication system for CANFD frames. Background Technology

[0002] CANFD communication is a network standard commonly used in vehicles and other control systems, allowing data transmission at different communication rates. In a CANFD system, the transmitting end needs to check whether the received voltage level matches the transmitted voltage level while sending data to determine if there are any bit errors.

[0003] However, in existing technologies, calculating the location of the second sampling point (SSP) for data bits in high-speed data bit periods is difficult and uncertain, especially in high-speed communication. Summary of the Invention

[0004] Therefore, it is necessary to provide a bit error detection method, controller, and communication system for CANFD frames that can improve the accuracy of bit error detection, in order to address the above-mentioned technical problems.

[0005] A method for determining bit errors in CANFD frames, the method being applied in a CANFD controller, the method comprising:

[0006] Obtain the data to be transmitted and the bit timing parameters, and store the data to be transmitted and the bit timing parameters in the configuration register;

[0007] The data to be transmitted and the bit timing parameters are transferred from the configuration register to the bit stream processor and bit timing unit in the CANFD core through the transmit buffer, respectively.

[0008] Within the bit timing unit of the CANFD core, sampling points and transmission points are generated according to the bit timing parameters, and the sampling points and transmission points are transmitted to the bit stream processor.

[0009] In the bit stream processor, a transmission bit is generated based on the data to be transmitted and the transmission point, thereby constructing a CANFD frame. The CANFD frame is then output through the transmission port, and the generated transmission bits are sequentially transmitted to the error management unit.

[0010] The receiving port samples the CANFD frame and transmits it to the bit timing unit. Based on the sampling point, a sampling bit is generated. Then, the bit stream processor parses the CANFD frame based on the sampling bit and transmits the parsing result to the error management unit in sequence.

[0011] In the error management unit, for data bits in the high-speed data bit period, the data to be transmitted is directly obtained from the configuration register, and each data bit in the data to be transmitted is compared with the parsing result of the CANFD frame in sequence. If there is a difference, it is judged as a bit error.

[0012] In one embodiment, the bit timing parameters are configured via the configuration register;

[0013] Configure the bit timing of the synchronization segment, Seg1 segment, and Seg2 segment in each data bit of the data to be transmitted according to the bit timing parameters;

[0014] Simultaneously, the bit timing of the received sample is configured according to the bit timing parameters, and the intersection of the Seg1 segment and the Seg2 segment is taken as the sampling point.

[0015] In one embodiment, in the bit timing unit, the sampled CANFD frame is resampled, and sample bits are generated based on the sampling points, including:

[0016] For data bits in a high-speed data bit period, the level value of each received data bit at the sampling point is taken as the sampling bit of that data bit.

[0017] In one embodiment, when performing bit error detection in the error management unit:

[0018] For data bits in a normal bit period, bit errors are determined by comparing the transmitted bits and sampled bits at the sampling point.

[0019] In one embodiment, the error management unit further determines whether the received data has format errors, ACK errors, padding errors, or CRC errors.

[0020] In one embodiment, in the bit stream processor:

[0021] The ID value obtained from the parsed received data is transmitted to the filtering unit;

[0022] In the filtering unit, ID filtering is performed against the configured ID value and mask information to determine whether the received data needs to be received.

[0023] If the filtering is successful, the received data is stored in the corresponding register via the receive buffer.

[0024] This application also provides a controller, which includes a register module, a transmit buffer module, and a CANFD core including a bit timing unit, a bit stream processor, and an error management unit;

[0025] The register module is used to acquire the data to be transmitted and the bit timing parameters, and to store the data to be transmitted and the bit timing parameters in the configuration register in the register module.

[0026] The data to be transmitted and the bit timing parameters are transferred from the configuration register to the bit stream processor and bit timing unit in the CANFD core through the transmit buffer module.

[0027] The bit timing unit is used to generate sampling points and transmission points according to the bit timing parameters, and transmit the sampling points and transmission points to the bit stream processor;

[0028] The bit stream processor is used to generate transmission bits according to the data to be transmitted and the transmission point, thereby constructing a CANFD frame, and outputting the CANFD frame through the transmission port, while transmitting the generated transmission bits sequentially to the error management unit.

[0029] The receiving port samples the CANFD frame and transmits it to the bit timing unit. Based on the sampling point, a sampling bit is generated. Then, the bit stream processor parses the CANFD frame based on the sampling bit and transmits the parsing result to the error management unit in sequence.

[0030] In the error management unit, for data bits in the high-speed data bit period, the data to be transmitted is directly obtained from the configuration register, and each data bit in the data to be transmitted is compared with the parsing result of the CANFD frame in sequence. If there is a difference, it is judged as a bit error.

[0031] In one embodiment, the controller further includes a receive filtering module and a receive buffer module;

[0032] The bitstream processor transmits the ID value obtained from the parsed received data to the filtering unit;

[0033] The filtering unit is used to perform ID filtering on the ID value in the received data and the configured ID value and mask information to determine whether the received data needs to be received.

[0034] If the filtering is successful, the received data is stored in the corresponding register in the register module via the receive buffer module.

[0035] This application also provides a communication system, which is a CANFD communication system, including multiple communication nodes. Each communication node transmits information through a CAN bus. Each communication node includes a CANFD controller and a CANFD transceiver, wherein the CANFD controller of each communication node is the aforementioned controller.

[0036] A computer-readable storage medium having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0037] Obtain the data to be transmitted and the bit timing parameters, and store the data to be transmitted and the bit timing parameters in the configuration register;

[0038] The data to be transmitted and the bit timing parameters are transferred from the configuration register to the bit stream processor and bit timing unit in the CANFD core through the transmit buffer, respectively.

[0039] Within the bit timing unit of the CANFD core, sampling points and transmission points are generated according to the bit timing parameters, and the sampling points and transmission points are transmitted to the bit stream processor.

[0040] In the bit stream processor, a transmission bit is generated based on the data to be transmitted and the transmission point, thereby constructing a CANFD frame. The CANFD frame is then output through the transmission port, and the generated transmission bits are sequentially transmitted to the error management unit.

[0041] The receiving port samples the CANFD frame and transmits it to the bit timing unit. Based on the sampling point, a sampling bit is generated. Then, the bit stream processor parses the CANFD frame based on the sampling bit and transmits the parsing result to the error management unit in sequence.

[0042] In the error management unit, for data bits in the high-speed data bit period, the data to be transmitted is directly obtained from the configuration register, and each data bit in the data to be transmitted is compared with the parsing result of the CANFD frame in sequence. If there is a difference, it is judged as a bit error.

[0043] The aforementioned bit error judgment method, controller, and communication system for CANFD frames involves storing the data to be transmitted and bit timing parameters in a configuration register, then transmitting them through a transmit buffer to the bit stream processor and bit timing unit in the CANFD core. Within the bit timing unit, sampling points and transmission points are generated based on the bit timing parameters and transmitted to the bit stream processor. The bit stream processor then generates transmission bits based on the data to be transmitted and the transmission points, thus constructing a CANFD frame. The CANFD frame is output through the transmit port, and the generated transmission bits are sequentially transmitted to the error management unit. The CANFD frame is then sampled back at the receive port and transmitted to the bit timing unit. Sampling bits are generated based on the sampling points, and the bit stream processor parses the CANFD frame based on the sampling bits. The parsing results are sequentially transmitted to the error management unit. In the error management unit, for data bits in the high-speed data bit period, the data to be transmitted is directly retrieved from the configuration register. Each data bit in the data to be transmitted is sequentially compared with the parsing results of the CANFD frame. If a difference exists, a bit error is determined. This method effectively avoids the difficulty and inaccuracy of calculating SSPs in existing technologies. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the CAN bus network structure in one embodiment;

[0045] Figure 2 This is a schematic diagram of a data transmitting node in a CAN bus network in one embodiment;

[0046] Figure 3 This is a schematic diagram of the frame format of CANFD in one embodiment;

[0047] Figure 4 This is a schematic diagram illustrating bit error detection based on transmitted data TX and retrieved data RX in one embodiment.

[0048] Figure 5 This is a schematic diagram illustrating the time delay between transmitted data TX and retrieved data RX in one embodiment.

[0049] Figure 6 This is a schematic diagram of the second sampling point in one embodiment;

[0050] Figure 7 This is a schematic diagram illustrating the inaccuracy of bit error detection using the second sampling point in one embodiment.

[0051] Figure 8 This is a flowchart illustrating a bit error detection method for a CANFD frame in one embodiment.

[0052] Figure 9 This is a block diagram of the controller in one embodiment;

[0053] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0055] like Figure 1 and 2 As shown, in a CAN (Controller Area Network) communication system, the CANFD transceiver is an important component connecting the CANFD controller and the CAN bus. The CANFD transceiver and the CANFD controller form a communication node, which then communicates with other communication nodes through the CAN bus.

[0056] During CANFD communication, the signal is output from the CANFD controller's transmit pin (CAN_TX). The transmitter in the CANFD transceiver converts the 0 and 1 digital level sequence into a differential level and sends it to the CAN bus via CANH and CANL. Simultaneously, the receiver in the CANFD transceiver reads back the differential level from the CAN bus, converts it back into 0 and 1 digital levels, and transmits it to the CANFD controller's receiver pin (CAN_RX), completing the message retrieval for one transmitted frame. This data transmission and retrieval process involves multiple stages, including the propagation delay from the controller to the transceiver, the loop delay within the transceiver, and the delay incurred during the signal return from the transceiver to the controller. Particularly during retrieval, the CANFD transceiver undergoes two conversions: the transmitter converts the 0 and 1 digital level sequence into a differential level; and the receiver converts the differential level back into a 0 and 1 digital level sequence. Because conversion takes time, there is inevitably a physical delay. Therefore, when CANFD sends a message frame, the digital level change on the Rx pin is delayed compared to the Tx pin.

[0057] To ensure the reliability and consistency of transmitted data, the CAN (CANFD) protocol specifies that the sender determines whether a bit error has occurred by checking whether the received level matches the transmitted level when transmitting a signal. When a CANFD node is used as a transmitting node, the CAN_TX pin transmits a signal to the bus while the CAN_RX pin receives and detects the bus level. A bit error occurs when the output level and the detected bus level are different.

[0058] like Figure 3The image shows the CANFD frame format. The rate of the normal bit time is less than 1 Mbps, and the rate is adjusted at the BRS bit. The bit rate of the high-speed data bit time can reach up to 15 Mbps. This results in wider data bits in the normal bit time and narrower data bits in the high-speed data bit time.

[0059] like Figure 4 As shown, when the transmitted data (i.e., the data output from the transmitting end CAN_TX) is compared with the data retrieved by the receiving end CAN_RX, for example, at sampling point A of the res bit in the normal bit phase of CANFD, RX samples a low level, while TX is still in the transmission phase A' of the res bit, also transmitting a low level. Therefore, the transmitted level and the detected received level are consistent, and there is no bit error.

[0060] However, due to the internal loop delay of the CANFD transceiver, the protocol specifies a maximum delay of 255ns. If the bit rate of the high-speed data segment is 10Mbps, meaning one bit is 100ns, the waveform of the receiver's RX may be delayed beyond the duration of one bit of the high-speed data segment. At sampling point B of the ESI bit in the CANFD high-speed data segment, RX samples a low level. Because the rate of the high-speed data segment after speed adjustment is higher than that of the normal bit segment, TX is already in the DLC bit and is transmitting a high level. Therefore, the high level transmitted at points B and B' is detected as a low level, resulting in a bit error. This bit error is incorrectly determined by an incorrect sampling point, which is caused by the delay and the high data rate.

[0061] To address this issue, the CANFD protocol introduces Transmit Delay Compensation (TDC) technology. By adjusting the transceiver's delay compensation offset, the sampling point can be shifted from the edge to the midpoint of the bit time, thus moving it away from the edge and improving sampling accuracy.

[0062] TDC (Time Difference Control) technology involves delaying the transmission of data bits during a high-speed data bit period and sampling the received bits at the Secondary Sample Point (SSP) to correctly sample the received bit corresponding to the transmitted bit. Each bit in the high-speed data bit period needs to be sampled at the SSP for bit error detection. The protocol states: "The transmitter should ignore bit errors detected at the sampling point (SP). At the SSP, the received bit value should be compared with the delayed transmitted bit value. If a bit error is detected at the SSP, the transmitter will respond to this bit error at subsequent sampling points."

[0063] When performing SSP testing, the transmission delay must first be measured. According to the CANFD protocol, the CANFD controller will automatically measure the delay time between the falling edge of the FDF bit to the res bit on the TX signal line and the falling edge of the FDF bit to the res bit on the RX signal line. Figure 5 As shown, TDCV represents the delay time. That is:

[0064] SSP location = Measurement Delay TDCV + Transmission Delay Compensation Offset TDCO

[0065] Furthermore, after calculating the position of the second sampling point (SSP), the transmitter buffers the transmitted level TX and delays it until the SSP of that bit. The transmitted level is then compared with the sampled RX level to determine if a bit error has occurred. Figure 6 As shown.

[0066] However, the above methods have certain difficulties and uncertainties. For example, the bit rate of high-speed data segments is high, at 10Mbps, meaning one bit takes 100ns. The maximum transceiver loop delay could be 255ns. Figure 7 As shown, when the transmitting end TX sends the ESI bit, the SSP position is delayed until point A. However, by this time, DLC0, DLC1, and DLC2 bits have already been sent. This means that before the ESI SSP arrives, the next three DLC0, DLC1, and DLC2 bits must be delayed, and their SSP positions must be calculated, which increases the design complexity. If the loop delay is small, say 100ns, then delaying the next DLC0 bit might be sufficient. Therefore, the above method, even the existing technology, has uncertainties.

[0067] To address the aforementioned issues, this application, such as Figure 8 As shown, a method for determining bit errors in CANFD frames is provided. This method is applied in a CANFD controller and specifically includes the following steps:

[0068] Step S100: Obtain the data to be sent and the bit timing parameters, and store the data to be sent and the bit timing parameters in the configuration register.

[0069] In step S110, the data to be transmitted and the bit timing parameters are transferred from the configuration register to the bit stream processor and bit timing unit in the CANFD core through the transmit buffer.

[0070] Step S120: In the bit timing unit of the CANFD core, sampling points and transmission points are generated according to the bit timing parameters, and the sampling points and transmission points are sent to the bit stream processor.

[0071] In step S130, in the bit stream processor, a transmission bit is generated based on the data to be transmitted and the transmission point, thereby constructing a CANFD frame. The CANFD frame is then output through the transmission port, and the generated transmission bits are sequentially transmitted to the error management unit.

[0072] Step S140: The CANFD frame is sampled back at the receiving port and transmitted to the bit timing unit. Sample bits are generated according to the sampling points. The bit stream processor then parses the CANFD frame according to the sample bits and transmits the parsing results to the error management unit in sequence.

[0073] In step S150, in the error management unit, for the data bits of the high-speed data bit period, the data to be transmitted is directly obtained from the configuration register, and each data bit in the data to be transmitted is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

[0074] Considering that the value of each data bit transmitted is stored in a different configuration register before transmission, the receiving end samples the RX and compares the level of a specific data bit in the received data with the transmitted level of that bit in the configuration register at the sampling point SP to directly determine a bit error. This simplifies the calculation of the SSP point and avoids the difficulty and uncertainty of the calculation. Therefore, this application proposes a bit error detection method for high-speed data bit segments of CANFD frames. This method stores each bit of data to be transmitted in the configuration register at the transmitting end. While transmitting each bit, the receiving end samples the received level. At the sampling point (SP), the received level is compared with the data of that bit in the configuration register. If the comparison result is inconsistent, a bit error can be quickly determined. This method can directly detect bit errors at the transmitting end without calculating complex SSP positions, thus simplifying the bit error detection process and improving the reliability and efficiency of the system. This method reduces the reliance on Transmit Delay Compensation (TDC) technology, thereby simplifying hardware design and software algorithms.

[0075] In step S100, the bit time of the synchronization segment (Sync_Seg), the Seg1 segment (Prop_Seg+Phase_Seg1), and the Seg2 segment (Phase_Seg2) in each data bit of the data to be transmitted is configured according to the bit timing parameters. At the same time, the bit timing of the received sample is configured according to the bit timing parameters, and the boundary between the Seg1 segment and the Seg2 segment is taken as the sampling point.

[0076] In this embodiment, the number of sampling points is determined by the relationship between the transmission rate, the number of time quantizers, and the number of sampling points. The selection of the number of sampling points needs to balance factors such as data sampling accuracy, anti-interference capability, bus load, and transmission delay.

[0077] Preferably, the sampling points are located at 75% to 90% of the data bits.

[0078] In step S120, in the bit timing unit, a sampling bit is generated based on the received data and the sampling point, including: taking the level value of each data bit in the received data at the sampling point as the sampling bit of that data bit.

[0079] Specifically, at the receiving end, CANFD frames are sampled and sent to the bit timing unit. Sampling points are generated based on the bit timing unit, and the input CANFD frame is sampled at these sampling points to obtain sampled bits. Furthermore, the bit stream processor parses the sampled bits to determine that the received data is a specific bit in the CANFD frame format.

[0080] In step S130, the CANFD frame is output through the transmit port and transmitted to other destination communication nodes via the CAN bus.

[0081] In step S150, when performing bit error judgment in the error management unit, bit error judgment is performed on the high-speed data bit period of the received data by comparing each data bit in the data to be transmitted with the sampled bits of the received data. This effectively improves both the judgment speed and the accuracy of the judgment.

[0082] In this embodiment, the bit stream processor also transmits the transmit bits and CRC sequence value to the error bit management unit. The error management unit further determines whether the received data contains format errors, ACK errors, padding errors, or CRC errors based on the received transmit bits and CRC sequence value.

[0083] Specifically, a format error refers to the bitstream processor detecting an invalid bit at a bit with a fixed format. For example, the ACK delimiter is always a high level; if the bitstream processor detects a low level, the error management unit will generate a format error.

[0084] Specifically, an ACK error occurs when the CANFD controller acts as a transmitting node. When the bit stream processor detects a high level in the ACK bit of its own CANFD message, it assumes that no other node has received the message, and the error management unit generates an ACK error.

[0085] Specifically, a stuffing error occurs when the bit stream processor detects six consecutive identical voltage levels on the bus during CANFD message transmission; in this case, the error management unit generates a stuffing error.

[0086] Specifically, a CRC error occurs when the CANFD controller, acting as a receiving node, receives a CRC sequence that differs from the calculated CRC sequence value, causing the error management unit to generate a CRC error.

[0087] Furthermore, a bit error refers to the situation where, when a bit stream processor sends data, it outputs a transmit bit at the transmit point and simultaneously acquires the bus level at the sampling point to obtain a sample bit. When the transmit bit and the sample bit are detected to be different, the error management unit issues a bit error.

[0088] The bit error detection method for CANFD frames described above simplifies the process by directly detecting bit errors at the sender point (SP), eliminating the need to calculate complex sender point (SSP) locations and thus improving system reliability and efficiency. This method reduces reliance on transmit delay compensation (TDC) techniques, thereby simplifying hardware design and software algorithms. This method simplifies the bit error detection process, improves system reliability, and avoids the difficulty and uncertainty of calculating SSPs, especially in high-speed communication. It is applicable to various CANFD communication systems without requiring extensive modifications to existing hardware.

[0089] This method can be applied to high-speed communication systems between automotive electronic control units (ECUs) to improve the accuracy and reliability of data transmission and reduce communication failures caused by bit errors.

[0090] It should be understood that, although Figure 8 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 8 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0091] like Figure 9As shown, this application also proposes a controller based on the above-mentioned bit error judgment method for CANFD frames, including a register module, a transmit buffer module, and a CANFD kernel including a bit timing unit, a bit stream processor, and an error management unit. The register module is used to acquire the data to be transmitted and the bit timing parameters, and store the data and bit timing parameters in the configuration register of the register module. The data to be transmitted and the bit timing parameters are then transmitted from the configuration register to the bit stream processor and bit timing unit in the CANFD core through the transmit buffer module. The bit timing unit is used to generate sampling points and transmission points according to the bit timing parameters, and transmit the sampling points and transmission points to the bit stream processor. The bit stream processor is used to generate transmission bits according to the data to be transmitted and the transmission points, thereby constructing a CANFD frame, and outputting the CANFD frame through the transmit port. At the same time, the generated transmission bits are transmitted sequentially to the error management unit. The CANFD frame is sampled back at the receive port and transmitted to the bit timing unit. Sampling bits are generated according to the sampling points. The bit stream processor then parses the CANFD frame according to the sampling bits and transmits the parsing results sequentially to the error management unit. The generated sampling bits are also transmitted sequentially to the error management unit. In the error management unit, for the data bits of the high-speed data bit period, the data to be transmitted is directly obtained from the configuration register, and each data bit in the data to be transmitted is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

[0092] In this embodiment, the bit timing parameters are configured through the configuration register. The bit timing of the synchronization segment, Seg1 segment, and Seg2 segment in each data bit of the data to be transmitted is configured according to the bit timing parameters. At the same time, the bit timing of the received sampling is configured according to the bit timing parameters, and the boundary between the Seg1 segment and the Seg2 segment is used as the sampling point.

[0093] In this embodiment, the number of sampling points is determined by the relationship between the transmission rate, the number of time quantizers, and the number of sampling points. The selection of the number of sampling points needs to balance factors such as data sampling accuracy, anti-interference capability, bus load, and transmission delay.

[0094] Preferably, the sampling points are located at 75% to 90% of the data bits.

[0095] In this embodiment, the generation of sampling bits in the bit timing unit based on the received data and sampling points includes: taking the level value of each data bit in the received data at the sampling point as the sampling bit of that data bit.

[0096] In this embodiment, when performing bit error judgment in the error management unit, bit error judgment is performed on the high-speed data segment of the received data by comparing each data bit in the data to be transmitted with the sampled bits of the received data. This effectively improves both the judgment speed and the accuracy of the judgment.

[0097] In this embodiment, the bitstream processor also sends the transmit bits and CRC sequence value to the error management unit. The error management unit further determines whether the received data contains format errors, ACK errors, padding errors, or CRC errors based on the received transmit bits and CRC sequence value.

[0098] Furthermore, the controller also includes a receive filtering module and a receive buffer module. The bit stream processor transmits the ID value in the parsed received data to the filtering unit. The filtering unit is used to perform ID filtering on the ID value in the received data and the configured ID value and mask information to determine whether the received data needs to be received. If the filtering is successful, the received data is stored in the corresponding register in the register module via the receive buffer module.

[0099] Specifically, the CANFD controller's transmission workflow includes: configuring the parameter register via the CPU and sending timing parameters to the bit timing unit of the CANFD core to generate the bit timing sequence for CANFD transmission. The CPU configures the data to be transmitted, ID values, and other information (i.e., the transmission data) into the configuration register and stores it in the transmit buffer module, then sends this information to the bit stream processor. Next, the bit timing unit generates the necessary transmission points based on the timing parameters and sends them to the bit stream processor. Simultaneously, the bit stream processor constructs CANFD frames from the data, ID values, and other information, and outputs them to the CAN bus via the transmit port CANTX at each transmission point. This completes the controller's data transmission process.

[0100] Specifically, the CANFD controller's receiving workflow includes: configuring the parameter register through the CPU and sending the timing parameters to the bit timing unit of the CANFD core to generate the bit timing for CANFD transmission; configuring the ID value, mask, and other information required for reception into the configuration register and sending it to the receive filtering module for ID filtering; the bit timing unit generating the sampling points required for reception sampling based on the timing parameters and sending them to the bit stream processor; the receiving port CANRX receiving and re-sampled CANFD frames and sending them to the bit stream processor to parse them into data, ID values, and other information; sending the received ID value to the receive filtering module for ID filtering against the configured ID value and mask information to determine whether the CANFD frame needs to be received; if the filtering is successful, sending the data, ID value, and other information into the receive buffer; storing the data, ID value, and other information in the receive buffer into the corresponding registers; and finally, the CPU reading the received information.

[0101] For specific limitations regarding the controller, please refer to the limitations on the bit error detection method for CANFD frames mentioned above, which will not be repeated here. Each module in the aforementioned controller can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the corresponding operations of each module.

[0102] This application also provides a communication system, which is a CAN communication system, the structure of which can be referred to. Figure 1 It includes multiple communication nodes, each of which transmits information via a CANFD bus. Each communication node includes a CANFD controller and a CANFD transceiver, wherein the CANFD controller of each communication node is the aforementioned controller.

[0103] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 10 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When executed by the processor, the computer program implements a bit error detection method for CANFD frames. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0104] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0105] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0106] Obtain the data to be transmitted and the bit timing parameters, and store the data to be transmitted and the bit timing parameters in the configuration register;

[0107] The data to be transmitted and the bit timing parameters are transferred from the configuration register to the bit stream processor and bit timing unit in the CANFD core through the transmit buffer, respectively.

[0108] Within the bit timing unit of the CANFD core, sampling points and transmission points are generated according to the bit timing parameters, and the sampling points and transmission points are transmitted to the bit stream processor.

[0109] In the bit stream processor, a transmission bit is generated based on the data to be transmitted and the transmission point, thereby constructing a CANFD frame. The CANFD frame is then output through the transmission port, and the generated transmission bits are sequentially transmitted to the error management unit.

[0110] The receiving port samples the CANFD frame and transmits it to the bit timing unit. Based on the sampling point, a sampling bit is generated. Then, the bit stream processor parses the CANFD frame based on the sampling bit and transmits the parsing result to the error management unit in sequence.

[0111] In the error management unit, for data bits in the high-speed data bit period, the data to be transmitted is directly obtained from the configuration register, and each data bit in the data to be transmitted is compared with the parsing result of the CANFD frame in sequence. If there is a difference, it is judged as a bit error.

[0112] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0113] Obtain the data to be transmitted and the bit timing parameters, and store the data to be transmitted and the bit timing parameters in the configuration register;

[0114] The data to be transmitted and the bit timing parameters are transferred from the configuration register to the bit stream processor and bit timing unit in the CANFD core through the transmit buffer, respectively.

[0115] Within the bit timing unit of the CANFD core, sampling points and transmission points are generated according to the bit timing parameters, and the sampling points and transmission points are transmitted to the bit stream processor.

[0116] In the bit stream processor, a transmission bit is generated based on the data to be transmitted and the transmission point, thereby constructing a CANFD frame. The CANFD frame is then output through the transmission port, and the generated transmission bits are sequentially transmitted to the error management unit.

[0117] The receiving port samples the CANFD frame and transmits it to the bit timing unit. Based on the sampling point, a sampling bit is generated. Then, the bit stream processor parses the CANFD frame based on the sampling bit and transmits the parsing result to the error management unit in sequence.

[0118] In the error management unit, for data bits in the high-speed data bit period, the data to be transmitted is directly obtained from the configuration register, and each data bit in the data to be transmitted is compared with the parsing result of the CANFD frame in sequence. If there is a difference, it is judged as a bit error.

[0119] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0120] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for determining bit errors in CANFD frames, characterized in that, The method is applied in a CANFD controller, and the method includes: Obtain the data to be transmitted and the bit timing parameters, and store the data to be transmitted and the bit timing parameters in the configuration register; The data to be transmitted and the bit timing parameters are transferred from the configuration register to the bit stream processor and bit timing unit in the CANFD core through the transmit buffer, respectively. Within the bit timing unit of the CANFD core, sampling points and transmission points are generated according to the bit timing parameters, and the sampling points and transmission points are transmitted to the bit stream processor. In the bit stream processor, a transmission bit is generated based on the data to be transmitted and the transmission point, thereby constructing a CANFD frame. The CANFD frame is then output through the transmission port, and the generated transmission bits are sequentially transmitted to the error management unit. The receiving port samples the CANFD frame and transmits it to the bit timing unit. Based on the sampling point, a sampling bit is generated. Then, the bit stream processor parses the CANFD frame based on the sampling bit and transmits the parsing result to the error management unit in sequence. In the error management unit, for data bits in the high-speed data bit period, the data to be transmitted is directly obtained from the configuration register, and each data bit in the data to be transmitted is compared with the parsing result of the CANFD frame in sequence. If there is a difference, it is judged as a bit error.

2. The bit error judgment method according to claim 1, characterized in that, The bit timing parameters are configured through the configuration register; Configure the bit timing of the synchronization segment, Seg1 segment, and Seg2 segment in each data bit of the data to be transmitted according to the bit timing parameters; Simultaneously, the bit timing of the received sample is configured according to the bit timing parameters, and the intersection of the Seg1 segment and the Seg2 segment is taken as the sampling point.

3. The bit error judgment method according to claim 2, characterized in that, In the bit timing unit, the sampled CANFD frame is resampled, and sample bits are generated based on the sampling points, including: For data bits in a high-speed data bit period, the level value of each received data bit at the sampling point is used as the sampling bit of that data bit.

4. The bit error judgment method according to any one of claims 1-3, characterized in that, When performing bit error detection in the error management unit: For data bits in a normal bit period, bit errors are determined by comparing the transmitted bits and sampled bits at the sampling point.

5. The bit error judgment method according to claim 4, characterized in that, The error management unit also determines whether the received data has format errors, ACK errors, padding errors, or CRC errors.

6. The bit error judgment method according to claim 5, characterized in that, In the bit stream processor: The ID value obtained from the parsed received data is transmitted to the filtering unit; In the filtering unit, ID filtering is performed against the configured ID value and mask information to determine whether the received data needs to be received. If the filtering is successful, the received data is stored in the corresponding register via the receive buffer.

7. A controller, characterized in that, The controller includes a register module, a transmit buffer module, and a CANFD core including a bit timing unit, a bit stream processor, and an error management unit; The register module is used to acquire the data to be transmitted and the bit timing parameters, and to store the data to be transmitted and the bit timing parameters in the configuration register in the register module. The data to be transmitted and the bit timing parameters are transferred from the configuration register to the bit stream processor and bit timing unit in the CANFD core through the transmit buffer module. The bit timing unit is used to generate sampling points and transmission points according to the bit timing parameters, and transmit the sampling points and transmission points to the bit stream processor; The bit stream processor is used to generate transmission bits according to the data to be transmitted and the transmission point, thereby constructing a CANFD frame, and outputting the CANFD frame through the transmission port, while transmitting the generated transmission bits sequentially to the error management unit. The receiving port samples the CANFD frame and transmits it to the bit timing unit. Based on the sampling point, a sampling bit is generated. Then, the bit stream processor parses the CANFD frame based on the sampling bit and transmits the parsing result to the error management unit in sequence. In the error management unit, for data bits in the high-speed data bit period, the data to be transmitted is directly obtained from the configuration register, and each data bit in the data to be transmitted is compared with the parsing result of the CANFD frame in sequence. If there is a difference, it is judged as a bit error.

8. The controller according to claim 7, characterized in that, The controller also includes a filtering unit and a receiving buffer module; The bitstream processor transmits the ID value from the parsed received data to the filtering unit; The filtering unit is used to perform ID filtering on the ID value in the received data and the configured ID value and mask information to determine whether the received data needs to be received. If the filtering is successful, the received data is stored in the corresponding register in the register module via the receive buffer module.

9. A communication system, wherein the communication system is a CANFD communication system, comprising multiple communication nodes, each of the communication nodes transmitting information via a CAN bus, characterized in that, Each of the communication nodes includes a CANFD controller and a CANFD transceiver, wherein the CANFD controller of each of the communication nodes is the controller described in claim 8.

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