A DDR interface arbitration control method suitable for video processing

Abstract

The present invention provides a DDR interface arbitration control method suitable for video processing, relating to the field of embedded computer video processing technology, comprising: setting a fixed data length for each of multiple independent video storage control channels; performing arbitration control of the current state via a DDR interface arbitration controller, and determining whether the current buffer size to be written to the video storage control channel has reached the fixed data length for the channel if a write operation is in progress; and determining whether the current buffer size to be read from the video storage control channel has reached the fixed data length for the channel if a read operation is in progress. The DDR interface arbitration control method of the present invention can avoid the abnormal situation of reading an empty data FIFO, and has high reliability; reduces channel switching frequency, improves data access efficiency; avoids frequent changes in multiple addresses, and has high stability, better meeting the stability and reliability requirements of multi-channel image data processing and image display in embedded computers.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded computer video processing, and in particular to a DDR interface arbitration control method suitable for video processing. Background Art

[0002] With the development of embedded computer and video imaging technologies, integrated display technology has become increasingly complex, and the requirements for display integration are also increasing. Integrated computer display systems need to capture and display video images sent by multiple external visual acquisition devices. Currently, embedded computers with integrated display capabilities use FPGA (Field Programmable Gate Array) logic processing to implement functions such as video switching and overlay display. For video switching and overlay display, the FPGA logic in the computer typically controls the video and enters DDR memory to splice the complete image. The images from different data sources are read from the DDR memory and then controlled for display based on the final display requirements.

[0003] The DDR controller in an FPGA consists of two components: the FPGA's official IP core, the Memory Interface Solutions (MIS), and the DDR interface arbitration controller. The MIS utilizes internal FPGA resources to implement the physical layer for the DDR memory interface, directly interfacing with external DDR memory chips and providing a user-friendly application program interface (MIS-APP interface).

[0004] The DDR interface arbitration controller has developed a multi-channel memory controller based on a dual FIFO interface for the MIS-APP interface. Figure 1 As shown in the figure, the arbiter provides multiple independent storage control channels to the upper layer. Each channel contains two FIFO interfaces: an instruction FIFO interface and a data FIFO interface. The arbiter prioritizes read and write requests from each channel and selects a channel to exclusively use the MIS-APP interface for DDR read and write operations. The glue logic completes the interaction between the dual FIFO interfaces and the MIS-APP interface. During write operations, the instruction FIFO and data FIFO are read and written to the MIS-APP interface (i.e., the DDR). During read operations, the instruction FIFO is read and the data read from the MIS-APP interface is written to the data FIFO.

[0005] All logic circuits within the DDR interface arbitration controller in the FPGA operate within the same clock domain. Signals introduced into non-clock domains exist only at the interface with the glue logic. The DDR interface arbitration controller uses asynchronous FIFOs (command FIFO and data FIFO) to isolate the clock domains of the application layer and the MIS-APP interface. These asynchronous FIFOs are the source of cross-clock domain signals. The data and control signals in the asynchronous FIFOs of the DDR controller are cross-clock domain signals, which are affected by the frequencies of the previous and next clock domains and the internal processing mechanisms, resulting in a certain delay. The state machine jump mode of the DDR interface arbitration controller must fully consider the elimination of abnormal reading when the asynchronous FIFO is empty. Otherwise, data written to the DDR memory may be erroneous, which will appear as a chaotic display.

[0006] If only the command FIFO is checked for "non-empty" status without also checking the data FIFO for "non-empty," the command FIFO may be non-empty while the data FIFO is empty (the command FIFO is valid before the data FIFO). Because the asynchronous FIFO switches clock domains internally, data written to the "empty" FIFO is not complete when it is read, ultimately causing data errors in the DDR3 memory. Therefore, only when the data FIFO is checked for "non-empty" status can the internally stored data be reliably read. Summary of the Invention

[0007] In view of this, in order to fully solve the abnormal error of reading when the asynchronous FIFO in the DDR controller is empty during video data processing, the embodiment of the present application provides a DDR interface arbitration control method suitable for video processing to ensure that there is no abnormal operation caused by the data FIFO being "empty" during the read / write operation, thereby meeting the stability and reliability requirements of multi-channel image data processing and image display of embedded computers.

[0008] The present application provides the following technical solution: a DDR interface arbitration control method suitable for video processing, comprising:

[0009] Setting a fixed data length for each of the multiple independent video storage control channels; wherein the video storage control channel is a storage control channel based on a dual FIFO interface, and the dual FIFO interface includes an instruction FIFO interface and a data FIFO interface;

[0010] Perform arbitration control of the current state through the DDR interface arbitration controller. If the write operation state is running, determine whether the current cache amount to be written of the video storage control channel reaches the data amount fixed length of the channel. If so, issue a write request through the instruction FIFO interface, read the image data through the data FIFO interface and write it to the MIS-APP interface, determine whether the image data amount written to the MIS-APP interface reaches the data amount fixed length of the channel, and if so, jump to the waiting arbitration control state;

[0011] If the read operation state is in progress, determine whether the current cache amount to be read of the video storage control channel reaches the data length of the channel. If so, issue a read request through the instruction FIFO interface, read the image data through the MIS-APP interface and write it to the data FIFO interface, determine whether the image data amount read from the MIS-APP interface reaches the data length of the channel, and if so, jump to the waiting arbitration control state.

[0012] According to an embodiment of the present application, the data volume fixed length of the channel is calculated based on the image resolution of the video storage control channel.

[0013] According to an embodiment of the present application, calculating the fixed length of the data volume of the channel according to the image resolution of the video storage control channel includes:

[0014] According to the image resolution of the video storage control channel, the maximum pixel value and the pixel value transmitted per unit time of the channel are determined, and the ratio of the maximum pixel value and the pixel value transmitted per unit time is used as the data length of the channel.

[0015] According to one embodiment of the present application, the MIS-APP interface is connected to an external DDR memory to write and read image data to the DDR memory.

[0016] According to an embodiment of the present application, the DDR memory stitches the written image data into a complete picture, and reads different data source pictures from the DDR memory and controls the display according to display requirements.

[0017] According to an embodiment of the present application, the instruction FIFO interface caches instruction types and memory addresses, and the data FIFO interface caches image data.

[0018] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least the following: the embodiments of the present invention add a fixed-length burst jump mechanism, which can be specifically configured according to actual conditions and is flexible to control; it avoids the abnormal situation of reading an empty data FIFO and has high reliability; it reduces the channel switching frequency and improves data access efficiency; it avoids frequent changes in multiple addresses and has high stability, which better meets the stability and reliability requirements of multi-channel image data processing and image display of embedded computers. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is a schematic diagram of the upper and lower functional blocks of the DDR3 controller;

[0021] Figure 2 1 is a schematic diagram of the internal state machine of the DDR interface arbitration controller of the burst mechanism with fixed data length according to an embodiment of the present invention;

[0022] Figure 3 This is a functional block diagram of a DDR3 controller in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0024] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0025] like Figure 2-Figure 3 As shown, an embodiment of the present invention provides a DDR interface arbitration control method suitable for video processing, including:

[0026] Setting a fixed data length for each of the multiple independent video storage control channels; wherein the video storage control channel is a storage control channel based on a dual FIFO interface, wherein the dual FIFO interface includes an instruction FIFO interface and a data FIFO interface; wherein the instruction FIFO interface caches instruction types and memory addresses, and the data FIFO interface caches image data;

[0027] The arbitration control of the current state is performed through the DDR interface arbitration controller. If the write operation state is running, it is determined whether the current cache amount to be written of the video storage control channel reaches the data amount fixed length of the channel. If so, a write request is issued through the instruction FIFO interface, the image data is read through the data FIFO interface and written to the MIS-APP interface, and it is determined whether the image data amount written to the MIS-APP interface reaches the data amount fixed length of the channel. If so, it jumps to the waiting arbitration control state; if the read operation state is running, it is determined whether the current cache amount to be read of the video storage control channel reaches the data amount fixed length of the channel. If so, a read request is issued through the instruction FIFO interface, the image data is read through the MIS-APP interface and written to the data FIFO interface, and it is determined whether the image data amount read from the MIS-APP interface reaches the data amount fixed length of the channel. If so, it jumps to the waiting arbitration control state.

[0028] The MIS-APP interface is connected to an external DDR memory to write and read image data to the DDR memory. The DDR memory stitches the written image data into a complete picture and reads different data source pictures from the DDR memory for control display according to display requirements.

[0029] The method of an embodiment of the present invention provides an improved state machine jump mode for a DDR interface arbitration controller. In this mode, the state machine jump mode adopts a fixed-length burst mode, where the burst length is calculated based on the resolution of the image in each channel. In this mode, the channel data caching and jump strategy changes from a random jump mode that processes data as soon as it is available to a burst jump mode that continuously processes fixed-length values ​​after caching a certain amount of data. This ensures that read / write operations are free of abnormal operations caused by an empty data FIFO.

[0030] In a specific implementation of the embodiment of the present invention, the fixed length of the data volume of the channel is calculated according to the image resolution of the video storage control channel.

[0031] Specifically, the data volume fixed length of the channel is calculated according to the image resolution of the video storage control channel, including: determining the maximum pixel value and the pixel value transmitted per unit time of the channel according to the image resolution of the video storage control channel, and taking the ratio of the maximum pixel value and the pixel value transmitted per unit time as the data volume fixed length of the channel.

[0032] like Figure 2 As shown, in the internal state machine of the embodiment of the present invention, read and write operations are not performed in the IDLE state, write operations are performed in the WRITE state, and read operations are performed in the READ state. The data length determination mechanism of the embodiment of the present invention, compared with the traditional simple instruction FIFO "not empty" determination mechanism, has a comparative change as shown in Table 1.

[0033] Table 1 Change comparison table

[0034]

[0035] For example, an embedded computer needs to complete various overlay display functions of 1 channel analog PAL video and 2 channels digital DVI video. The internal working principle of the product is to decode the analog PAL format video and DVI format digital video and convert them into RGB signals. The signal data is controlled by the FPGA and enters the DDR3 memory to splice into a complete picture. According to the final display requirements, the pictures of different data sources are read from the DDR3 memory and controlled for display. The specific functional block diagram is as follows Figure 3 shown.

[0036] The embedded computer has the following video interfaces:

[0037] a. 1-channel analog differential PAL video interface, denoted as PAL;

[0038] b. 2-way digital DVI video input interface; one from external video equipment, denoted as EDVI; the other from internal graphics rendering interface, denoted as GDVI;

[0039] c. 3-way digital DVI video output interface, marked as DISDVI1, DISDVI2, DISDVI3.

[0040] One of the complex video switching overlay display function modes is: PAL, EDVI and GDVI overlay display;

[0041] The three-channel videos of PAL, EDVI and GDVI corresponding to the display mode are buffered in DDR after format conversion. The video switching and overlay function block takes out the required video data from the buffer of DDR according to the bus instruction to perform video overlay processing.

[0042] In this display mode, the DDR controller usage is as follows:

[0043] a. Write channel 1: PAL amplified before buffering;

[0044] b. Write channel 2: PAL is amplified and stored in the buffer for superposition reading;

[0045] c. Write channel 3: EDVI is put into cache and is to be read by overlay;

[0046] d. Write channel 4: GDVI is put into the cache and is ready to be read by overlay;

[0047] e. Read channel 1: read PAL before amplification and do amplification;

[0048] f. Read channel 2: read and amplify the PAL and do superposition;

[0049] g. Read channel 3: read EDVI for superposition;

[0050] h. Read channel 4: read GDVI for overlay;

[0051] The specific implementation method of the method of the embodiment of the present invention is as follows:

[0052] 1. In the example embodiment of the present invention, the video channel resolutions are: 720x576 before PAL amplification, 800x600 after PAL amplification, and 1600x1200 for the other three DVI channels. The video data transmission architecture in this example utilizes four channels of DDR3 memory, each with 16 bits, using 8-burst mode (i.e., continuously transmitting 8 bits of data per unit time). The total bit width transmitted per unit time is calculated to be 4*16*8=512 bits. If each pixel is set to 16 bits (for higher image quality scenarios), the number of pixels transmitted per unit time is 32 (512 ÷ 16 = 32).

[0053] 2. Calculate the burst length based on the resolution of the images in different channels: the maximum pixel value ÷ the number of pixels transmitted per unit time = the fixed length. For PAL video with a resolution of 720x576, the burst depth is calculated based on a row pixel value of 720, and the fixed length burst depth is 720 ÷ 32 = 20. For PAL video with a resolution of 800x600, the burst depth is calculated based on a row pixel value of 800, and the fixed length burst depth is 800 ÷ 32 = 25. For DVI video with a resolution of 1600x1200, the burst depth is calculated based on a row pixel value of 1600, and the fixed length burst depth is 1600 ÷ 32 = 50. For a single channel of PAL video at 720x576 or 800x600, the burst lengths of the three DVI video channels at 1600x1200 are set to 20, 25, 50, 50, and 50, respectively.

[0054] 3. During a read operation, when the channel's buffered capacity reaches the fixed-length burst depth, the instruction FIFO interface issues a read request, waiting for data to be read from the MIS-APP interface (i.e., DDR3 memory) and written to the data FIFO. After the data read from the MIS-APP interface reaches the fixed-length burst depth, the system jumps to wait for the next arbitration.

[0055] 4. During a write operation, when the amount of buffer to be written to the channel reaches the fixed-length burst depth, the instruction FIFO interface issues a write request, waiting to read data from the data FIFO interface and write it to the MIS-APP interface. After the data written to the MIS-APP interface reaches the fixed-length burst depth, the system jumps to wait for the next arbitration.

[0056] Since the minimum data volume is 20-burst, even if the command and data FIFOs are written to at different times, the asynchronous FIFOs will always contain at least 19 data points and will not be empty. This completely eliminates the possibility of reading an empty FIFO and ensures stable image display.

[0057] The data fixed-length jump mechanism of the embodiment of the present invention can be specifically configured according to actual conditions and has flexible control; it can avoid the abnormal situation of reading an empty data FIFO and has high reliability; it reduces the channel switching frequency and improves data access efficiency; it avoids frequent changes in multiple addresses and has high stability, which better meets the stability and reliability requirements of multi-channel image data processing and image display of embedded computers.

[0058] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A DDR interface arbitration control method suitable for video processing, characterized in that: include: Setting a fixed data length for each of the multiple independent video storage control channels; wherein the video storage control channel is a storage control channel based on a dual FIFO interface, and the dual FIFO interface includes an instruction FIFO interface and a data FIFO interface; Perform arbitration control of the current state through the DDR interface arbitration controller. If the write operation state is running, determine whether the current cache amount to be written of the video storage control channel reaches the data amount fixed length of the channel. If so, issue a write request through the instruction FIFO interface, read the image data through the data FIFO interface and write it to the MIS-APP interface, determine whether the image data amount written to the MIS-APP interface reaches the data amount fixed length of the channel, and if so, jump to the waiting arbitration control state; If the read operation state is in progress, determine whether the current cache amount to be read of the video storage control channel reaches the data length of the channel. If so, issue a read request through the instruction FIFO interface, read the image data through the MIS-APP interface and write it to the data FIFO interface, determine whether the image data amount read from the MIS-APP interface reaches the data length of the channel, and if so, jump to the waiting arbitration control state.

2. The DDR interface arbitration control method suitable for video processing according to claim 1, characterized in that: The data volume fixed length of the channel is calculated according to the image resolution of the video storage control channel.

3. The DDR interface arbitration control method suitable for video processing according to claim 2, characterized in that: Calculating the fixed length of the data volume of the channel according to the image resolution of the video storage control channel respectively includes: According to the image resolution of the video storage control channel, the maximum pixel value and the pixel value transmitted per unit time of the channel are determined, and the ratio of the maximum pixel value and the pixel value transmitted per unit time is used as the data length of the channel.

4. The DDR interface arbitration control method suitable for video processing according to claim 1, characterized in that: The MIS-APP interface is connected to an external DDR memory to write and read image data into and from the DDR memory.

5. The DDR interface arbitration control method suitable for video processing according to claim 4, characterized in that: The DDR memory stitches the written image data into a complete picture, and reads pictures of different data sources from the DDR memory according to display requirements and controls the display.

6. The DDR interface arbitration control method suitable for video processing according to claim 1, characterized in that: The instruction FIFO interface caches instruction types and memory addresses, and the data FIFO interface caches image data.

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