Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel includes: a plurality of pixels (PX), each of the plurality of pixels (PX) including a plurality of sub-pixels (SP), in the same pixel (PX), at least one of the plurality of sub-pixels (SP) being a top-emitting sub-pixel (SPT) and at least one of the plurality of sub-pixels (SP) being a bottom-emitting sub-pixel (SPB), the top-emission sub-pixels (SPT) and the bottom-emission sub-pixels (SPB) emit light toward the same side of the display panel. According to the display panel, maximization of the openings of the sub-pixels is facilitated.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display panel and a display device. Background Art

[0002] In the display field, organic light-emitting diode (OLED) display panels have the characteristics of self-luminescence, high contrast, low energy consumption, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, and simple manufacturing, and have broad development prospects. Summary of the invention

[0003] Embodiments of the present disclosure provide a display panel and a display device.

[0004] An embodiment of the present disclosure provides a display panel, comprising: a plurality of pixels, wherein each pixel of the plurality of pixels comprises a plurality of sub-pixels, and in the same pixel, at least one sub-pixel of the plurality of sub-pixels is a top-emitting sub-pixel, and at least one sub-pixel of the plurality of sub-pixels is a bottom-emitting sub-pixel, and the top-emitting sub-pixel and the bottom-emitting sub-pixel emit light toward the same side of the display panel.

[0005] For example, a light emitting area of ​​at least one top-emitting sub-pixel is smaller than a light emitting area of ​​at least one bottom-emitting sub-pixel.

[0006] For example, the pixel includes an even number of sub-pixels, and in the same pixel, the top-emitting sub-pixel and the bottom-emitting sub-pixel are arranged in a mirror-image manner.

[0007] For example, the plurality of sub-pixels are four sub-pixels, two of the four sub-pixels are top-emitting sub-pixels, and the other two of the four sub-pixels are bottom-emitting sub-pixels.

[0008] For example, the bottom-emitting sub-pixels are sub-pixels that emit blue light and sub-pixels that emit white light, and the top-emitting sub-pixels are sub-pixels that emit red light and sub-pixels that emit green light.

[0009] For example, the pixel includes an odd number of sub-pixels, and in the same pixel, the light-emitting area of ​​at least one sub-pixel is greater than or equal to the sum of the light-emitting areas of each sub-pixel in the other two sub-pixels.

[0010] For example, the plurality of sub-pixels are three sub-pixels, two of the three sub-pixels are top-emitting sub-pixels, and the other sub-pixel of the three sub-pixels is a bottom-emitting sub-pixel.

[0011] For example, the bottom-emitting sub-pixel is a sub-pixel emitting blue light, and the top-emitting sub-pixel is a sub-pixel emitting red light and a sub-pixel emitting green light.

[0012] For example, the light emitting area of ​​the sub-pixel emitting blue light is larger than the light emitting area of ​​the sub-pixel emitting red light, and larger than the light emitting area of ​​the sub-pixel emitting green light.

[0013] For example, the display panel has a base substrate, and the top-emitting sub-pixels and the bottom-emitting sub-pixels are respectively arranged on two opposite sides of the base substrate.

[0014] For example, the display panel includes a first side and a second side relative to each other, the first side is a light-emitting side, the top-emitting sub-pixel is located on the first side, and the bottom-emitting sub-pixel is located on the second side, and the display panel has a transparent area on the first side, and the orthographic projection of the transparent area on the substrate overlaps with the orthographic projection of the light-emitting area of ​​the bottom-emitting sub-pixel on the substrate.

[0015] For example, the area of ​​the orthographic projection of the transparent region on the base substrate is greater than or equal to the area of ​​the orthographic projection of the light emitting region of the bottom-emitting sub-pixel on the base substrate.

[0016] For example, the sub-pixel includes a pixel circuit and a light-emitting element, and an orthographic projection of the pixel circuit of the top-emitting sub-pixel on the substrate overlaps with an orthographic projection of the pixel circuit of the bottom-emitting sub-pixel on the substrate.

[0017] For example, the orthographic projection of the light emitting element of the top-emitting sub-pixel on the base substrate overlaps with the orthographic projection of the pixel circuit of the bottom-emitting sub-pixel on the base substrate.

[0018] For example, the pixel circuit of the top-emitting sub-pixel is closer to the substrate than the light-emitting element of the top-emitting sub-pixel, and the pixel circuit of the bottom-emitting sub-pixel is closer to the substrate than the light-emitting element of the bottom-emitting sub-pixel.

[0019] For example, the pixel circuit includes a first transistor, a second transistor, a third transistor, and a storage capacitor, and the display panel also includes a gate line, wherein the gate line is connected to the gate of the second transistor and the gate of the third transistor, and the first transistor is located on a side of the storage capacitor away from the gate line.

[0020] For example, the second transistor and the third transistor are located on a side of the storage capacitor close to the gate line.

[0021] For example, the display panel also includes a data line, a sensing line and a first power line, the data line is connected to the second transistor, the first power line is connected to the first transistor, the sensing line is connected to the third transistor, and the data line, the sensing line, and the first power line are located on the same layer.

[0022] For example, the display panel also includes an auxiliary electrode, the light-emitting element includes a first electrode connected to the pixel circuit, a light-emitting functional layer located on a side of the first electrode away from the base substrate, and a second electrode located on a side of the light-emitting functional layer away from the first electrode, the second electrode is connected to the auxiliary electrode, and the auxiliary electrode is located on the same layer as the data line, the sensing line, and the first power line.

[0023] For example, the display panel further includes a shading layer, which is located on a side of the pixel circuit close to the base substrate, the first electrode of the first transistor is connected to the first electrode of the light-emitting element, and the shading layer is connected to the first electrode of the first transistor.

[0024] For example, the display panel also includes a first pixel defining layer, which is located on a first side of the display panel, and the first pixel defining layer has a first opening and a second opening, the first opening is configured to define the light-emitting area of ​​the top-emitting sub-pixel, and the orthographic projection of the second opening on the base substrate overlaps with the orthographic projection of the transparent area on the base substrate.

[0025] For example, an area of ​​the first opening is smaller than an area of ​​the second opening.

[0026] For example, the display panel also includes a second pixel defining layer, the second pixel defining layer is located on the second side of the display panel, the second pixel defining layer has a third opening, the third opening is configured to limit the light-emitting area of ​​the bottom-emitting sub-pixel, and the area of ​​the third opening is less than or equal to the area of ​​the second opening.

[0027] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0029] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0030] Figure 2 is a schematic diagram of another display panel provided by an embodiment of the present disclosure.

[0031] Figure 3 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.

[0032] Figure 4 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure.

[0033] Figure 5 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure.

[0034] Figure 6 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure.

[0035] Fig. 7A A schematic diagram of a 3T1C pixel circuit in a display panel provided in an embodiment of the present disclosure.

[0036] Figure 7B for Fig. 7A The signal timing diagram of the pixel circuit during the display process is shown.

[0037] Figure 7C and Fig.7D for Fig. 7A The signal timing diagram of the pixel circuit during the detection process is shown.

[0038] Figures 8 to 15 A plan view of a single film layer in a display panel provided in an embodiment of the present disclosure.

[0039] Figures 16 to 23 A plan view of a stack of multiple film layers in a display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0042] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 2 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. Figure 3 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure. Figure 4 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure. Figure 5 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure. Figure 6 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure.

[0043] like Figure 1 and Figure 2 As shown, an embodiment of the present disclosure provides a display panel, which includes a plurality of pixels PX, and each of the plurality of pixels PX includes a plurality of sub-pixels SP.

[0044] like Figure 1 As shown, the pixel PX includes four sub-pixels SP, that is, the pixel PX includes a sub-pixel SP1, a sub-pixel SP2, a sub-pixel SP3, and a sub-pixel SP4. Figure 1 As shown, sub-pixels SP1 and SP2 are arranged along direction Y, sub-pixels SP3 and SP4 are arranged along direction Y, sub-pixels SP1 and SP3 are arranged along direction X, and sub-pixels SP2 and SP4 are arranged along direction X. That is, the four sub-pixels SP are arranged in two rows and two columns. Figure 1 In the display panel shown, in two adjacent columns of sub-pixels, in one column of sub-pixels, a plurality of sub-pixels SP1 and a plurality of sub-pixels SP2 are alternately arranged along direction Y, and in the other column of sub-pixels, a plurality of sub-pixels SP3 and a plurality of sub-pixels SP4 are alternately arranged along direction Y. For example, Figure 1 In the display panel shown, in two adjacent rows of sub-pixels, in one row of sub-pixels, multiple sub-pixels SP1 and multiple sub-pixels SP3 are alternately arranged along direction X, and in the other row of sub-pixels, multiple sub-pixels SP2 and multiple sub-pixels SP4 are alternately arranged along direction X.

[0045] Figure 1 The sub-pixel SP1 is a red sub-pixel, the sub-pixel SP2 is a green sub-pixel, the sub-pixel SP3 is a blue sub-pixel, and the sub-pixel SP4 is a white sub-pixel. However, the luminous colors of the sub-pixels SP are not limited to the above description, and they can emit other colors of light, or they can be arranged in other ways instead of two rows and two columns. The embodiments of the present disclosure do not specifically limit the luminous colors of the sub-pixels SP1, SP2, SP3, and SP4, and they can be determined according to needs.

[0046] like Figure 2 As shown, the pixel PX includes three sub-pixels SP, that is, the pixel PX includes a sub-pixel SP1, a sub-pixel SP2, and a sub-pixel SP3. Figure 2 As shown, the sub-pixel SP1 and the sub-pixel SP2 are arranged along the direction Y and are both located in the same side row of the sub-pixel SP3. Figure 2 As shown, the center line of the sub-pixel SP1, the sub-pixel SP2, and the sub-pixel SP3 forms a triangle. For example, the triangle can be an acute triangle to facilitate the arrangement of the sub-pixels. Figure 2 As shown, in two adjacent columns of sub-pixels, a plurality of sub-pixels SP1 and a plurality of sub-pixels SP2 in one column of sub-pixels are arranged alternately, and the sub-pixels in the other column are sub-pixels of the same color.

[0047] Figure 2 The following description is made by taking the sub-pixel SP1 as a red sub-pixel, the sub-pixel SP2 as a green sub-pixel, and the sub-pixel SP3 as a blue sub-pixel. However, the luminous color of the sub-pixel SP is not limited to the above description, and may emit light of other colors, or may not emit light of other colors. Figure 2 The arrangement shown in the figure is different from that in the embodiment of the present disclosure. The embodiment of the present disclosure does not specifically limit the luminous colors of the sub-pixel SP1, the sub-pixel SP2, and the sub-pixel SP3, which can be determined according to needs.

[0048] Figure 1 and Figure 2 A base substrate BS is shown. A plurality of pixels PX are located on the base substrate BS.

[0049] like Figures 3 to 6 As shown, in the same pixel PX, at least one sub-pixel SP among the multiple sub-pixels SP is a top-emitting sub-pixel SPT, and at least one sub-pixel SP among the multiple sub-pixels SP is a bottom-emitting sub-pixel SPB, and the top-emitting sub-pixel SPT and the bottom-emitting sub-pixel SPB emit light toward the same side of the display panel.

[0050] The display panel provided by the embodiment of the present disclosure is configured such that in the same pixel PX, at least one sub-pixel SP among the multiple sub-pixels SP is set as a top-emitting sub-pixel SPT, and at least one sub-pixel SP among the multiple sub-pixels SP is set as a bottom-emitting sub-pixel SPB, that is, the multiple sub-pixels of the same pixel PX are layered, so that the opening of the sub-pixel is not limited by the minimum distance of the pixel defining layer in the case of the same-layer design (the multiple sub-pixels in the same pixel are all top-emitting sub-pixels, or all bottom-emitting sub-pixels), which is conducive to maximizing the opening of the sub-pixel, especially maximizing the opening of the sub-pixel in the case of high resolution. Generally speaking, the minimum distance of the pixel defining layer is more than 10 microns.

[0051] The display panel provided by the embodiments of the present disclosure designs different sub-pixels of a pixel in layers. The two parts are basically designed in a mirror image, namely the top-emitting sub-pixel and the bottom-emitting sub-pixel. The light-emitting area of ​​the bottom-emitting sub-pixel after left-right inversion can correspond to the transparent area on the side where the top-emitting sub-pixel is located. The pixel circuits of the two parts are stacked or the two parts are made on two substrates respectively, which can maximize the sub-pixel opening under high resolution.

[0052] Figures 3 to 6 A top-emitting sub-pixel SPT and a bottom-emitting sub-pixel SPB are shown. For example, the light-emitting area of ​​at least one top-emitting sub-pixel SPT is smaller than the light-emitting area of ​​at least one bottom-emitting sub-pixel SPB. By setting the area of ​​the bottom-emitting sub-pixel SPB to be larger, a significant reduction in the brightness of the bottom-emitting sub-pixel SPB is avoided, which is beneficial to improving the display quality.

[0053] For example, Figure 1 As shown, the pixel PX includes an even number of sub-pixels SP, and in the same pixel PX, the top-emitting sub-pixel SPT and the bottom-emitting sub-pixel SPB are mirror-imaged. The number of the top-emitting sub-pixels SPT and the bottom-emitting sub-pixels SPB is the same, and the structure is mirror-imaged. That is, half of the even number of sub-pixels SP are top-emitting sub-pixels SPT, and the other half are bottom-emitting sub-pixels SPB. The mirror-image setting is conducive to space utilization and helps improve display quality.

[0054] For example, Figure 1 As shown, the plurality of sub-pixels SP are four sub-pixels SP, two of which are top-emitting sub-pixels SPT, and the other two of which are bottom-emitting sub-pixels SPB. Figure 1 As shown, the sub-pixel SP1 and the sub-pixel SP2 are top-emitting sub-pixels SPT, and the sub-pixel SP3 and the sub-pixel SP4 are bottom-emitting sub-pixels SPB.

[0055] For example, the bottom-emitting sub-pixel SPB is a sub-pixel SP emitting blue light (sub-pixel SP3, B) and a sub-pixel SP emitting white light (sub-pixel SP4, W), and the top-emitting sub-pixel SPT is a sub-pixel SP emitting red light (sub-pixel SP1, R) and a sub-pixel SP emitting green light (sub-pixel SP2, G). The way in which the pixel PX includes four sub-pixels of RGBW can reduce the power consumption of the display panel. According to the different lifespans of the light-emitting elements of the sub-pixels of different colors, the top-emitting sub-pixel can be RG, while the bottom-emitting sub-pixel can be BW.

[0056] For example, Figure 2As shown, the pixel PX includes an odd number of sub-pixels SP. To facilitate the arrangement of the sub-pixels, in the same pixel PX, the light-emitting area of ​​at least one sub-pixel SP is greater than or equal to the sum of the light-emitting areas of each sub-pixel SP in the other two sub-pixels SP. Figure 2 As shown, the light emitting area of ​​sub-pixel SP3 is greater than the sum of the light emitting areas of sub-pixel SP1 and sub-pixel SP2. Of course, in other embodiments, the light emitting area of ​​sub-pixel SP3 may be equal to the sum of the light emitting areas of sub-pixel SP1 and sub-pixel SP2.

[0057] For example, Figure 2 As shown, the plurality of sub-pixels SP are three sub-pixels SP, two of the three sub-pixels SP are top-emitting sub-pixels SPT, and the other sub-pixel SP of the three sub-pixels SP is a bottom-emitting sub-pixel SPB.

[0058] For example, Figure 2 As shown, the bottom-emitting sub-pixel SPB is a sub-pixel SP emitting blue light (sub-pixel SP3 ), and the top-emitting sub-pixel SPT is a sub-pixel SP emitting red light (sub-pixel SP1 ) and a sub-pixel SP emitting green light (sub-pixel SP2 ).

[0059] like Figure 2 As shown, the top-emitting sub-pixel SPT is sub-pixel SP1 and sub-pixel SP2 (RG), and the bottom-emitting sub-pixel SPB is sub-pixel SP3 (B). According to the different life spans of the light-emitting elements of sub-pixels of different colors, the top-emitting sub-pixel can be RG, and the bottom-emitting sub-pixel can be B.

[0060] For example, Figure 2 As shown, the light emitting area of ​​the sub-pixel SP emitting blue light (sub-pixel SP3) is larger than the light emitting area of ​​the sub-pixel SP emitting red light (sub-pixel SP1) and larger than the light emitting area of ​​the sub-pixel SP emitting green light (sub-pixel SP2).

[0061] A sub-pixel with a larger light-emitting area may be used as a bottom-emitting sub-pixel SPB.

[0062] like Figure 5 and Figure 6 As shown, in the display panel, the sub-pixel SP has a light-emitting element EM, which includes a first electrode E1, a light-emitting functional layer FL located on a side of the first electrode E1 away from the substrate BS, and a second electrode E2 located on a side of the light-emitting functional layer FL away from the first electrode E1. The first electrode E1 is connected to the pixel circuit.

[0063] For example, Figures 1 to 6 As shown, the display panel has a base substrate BS, and a top-emitting sub-pixel SPT and a bottom-emitting sub-pixel SPB are respectively arranged on two opposite sides of the base substrate BS. Figure 4 and Figure 6 A substrate base plate BS is shown. Figure 3 and Figure 5 It is shown that the base substrate BS includes a base substrate BS1 and a base substrate BS2. In the case where the base substrate BS includes the base substrate BS1 and the base substrate BS2, they can be manufactured separately first, and then the base substrate BS1 and the base substrate BS2 can be bonded together.

[0064] For example, Figures 3 to 6 As shown, the base substrate BS of the display panel includes a first side S1 and a second side S2 relative to each other, the first side S1 is the light-emitting side, the top-emitting sub-pixel SPT is located on the first side S1, and the bottom-emitting sub-pixel SPB is located on the second side S2, and the display panel has a transparent area A0 on the first side S1, and the orthographic projection of the transparent area A0 on the base substrate BS overlaps with the orthographic projection of the light-emitting area EMR of the bottom-emitting sub-pixel SPB on the base substrate BS.

[0065] In the embodiment of the present disclosure, the top-emitting subpixel SPT emits light from the side where its second electrode E2 is located to the side away from the substrate, and the bottom-emitting subpixel SPB emits light from the side where its first electrode E1 is located to the side toward the substrate.

[0066] In the embodiment of the present disclosure, the light emitting region EMR of the sub-pixel SP refers to an actual light emitting region of the sub-pixel, and may correspond to an opening of the pixel defining layer.

[0067] In the embodiment of the present disclosure, the transparent area A0 refers to an area without a light-blocking component. The light-blocking component includes, for example, a metal component. An insulating layer may be provided in the transparent area A0, or a transparent or semi-transparent metal layer may be provided. Figure 5 and Figure 6 As shown, an insulating layer and a second electrode E2 may be disposed in the transparent area A0.

[0068] For example, to improve the brightness of the bottom-emitting subpixel SPB, the orthographic projection area of ​​the transparent region A0 on the base substrate BS is greater than or equal to the orthographic projection area of ​​the light emitting region EMR of the bottom-emitting subpixel SPB on the base substrate BS.

[0069] Figure 3 and Figure 4 The light emitting functional layer FL and the second electrode E2 are omitted. Figure 5 and Figure 6 The light emitting functional layer FL and the second electrode E2 are shown.

[0070] like Figures 3 to 6As shown, the display panel further includes a light shielding layer SL, a buffer layer BF located on the side of the light shielding layer SL away from the substrate BS, an active layer AT located on the side of the buffer layer BF away from the substrate BS, an insulating layer GI located on the side of the active layer AT away from the substrate BS, a gate GT located on the side of the insulating layer GI away from the substrate BS, an insulating layer ILD located on the side of the gate GT away from the substrate BS, a first electrode Ea and a second electrode Eb of the transistor located on the side of the insulating layer ILD away from the substrate BS, and a passivation layer PVX and a planarization layer PLN located on the side of the first electrode Ea and the second electrode Eb away from the substrate BS. Figures 3 to 6 As shown, the first electrode E1 of the light emitting element EM is connected to the first electrode Ea of the transistor through a via hole penetrating the passivation layer PVX and the planarization layer PLN. Figures 3 to 6 As shown, the first electrode Ea of the transistor is connected to the active layer AT through a via hole penetrating the insulating layer ILD, and the second electrode Eb of the transistor is connected to the active layer AT through a via hole penetrating the insulating layer ILD. Figures 3 to 6 As shown, the first electrode Ea of the transistor is also connected to the light shielding layer SL through a via hole penetrating the insulating layer ILD and the buffer layer BF to prevent the light shielding layer SL from floating.

[0071] like Figures 3 to 6 As shown, the pixel defining layer PDL has an opening PN configured to expose a portion of the first electrode E1 to form a sub-pixel or a light emitting region of the light emitting element. Figures 3 to 6 A pixel defining layer PDL1 and a pixel defining layer PDL2 are shown. The pixel defining layer PDL1 is located at a first side S1, and the pixel defining layer PDL2 is located at a second side S2.

[0072] Figure 3 A passivation layer PVX and a planarization layer PLN are shown. The passivation layer PVX is closer to the substrate BS than the planarization layer PLN. Figures 4 to 6 The passivation layer PVX and the planarization layer PLN are briefly shown, which can be referred to Figure 3 shown.

[0073] Fig. 7A A schematic diagram of a 3T1C pixel circuit in a display panel provided in an embodiment of the present disclosure. The pixel circuit of the display panel provided in the embodiment of the present disclosure is also not limited to the 3T1C pixel circuit. This embodiment takes the pixel circuit of the display panel as a 3T1C pixel circuit as an example to illustrate the structure of the display panel. As required, the pixel circuit may further include a compensation circuit, a reset circuit, etc., which is not limited in the embodiment of the present disclosure.

[0074] Reference Fig. 7A, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst. The first transistor T1 is a driving transistor, and the second transistor T2 is a data writing transistor. The first electrode of the second transistor T2 is electrically connected to the first electrode plate Ca of the storage capacitor Cst and the gate of the first transistor T1, the second electrode of the second transistor T2 is connected to the data line DT, and is configured to receive the data signal Vdt, the gate of the second transistor T2 is connected to the gate line G1, the gate line G1 is configured to provide a first control signal Vg1, and the second transistor T2 is configured to write the data signal Vdt into the gate of the first transistor T1 and the storage capacitor Cst in response to the first control signal Vg1; the first electrode of the first transistor T1 is electrically connected to the second electrode plate Cb of the storage capacitor Cst, and is configured to be electrically connected to the first electrode E1 of the light emitting element, the second electrode of the first transistor T1 is connected to the first power line PL1, and is configured to receive a first power supply voltage (for example, a high power supply voltage VDD), and the first power line PL1 is configured to provide a first power supply voltage. The first transistor T1 is configured to control the current for driving the light-emitting element under the control of the voltage of the gate of the first transistor T1; the first electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1 and the second electrode plate Cb of the storage capacitor Cst, the second electrode of the third transistor T3 is configured to be connected to the sensing line SS to be connected to the external detection circuit, the gate of the third transistor T3 is connected to the gate line G2, the gate line G2 is configured to provide the second control signal Vg2, and the third transistor T3 is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the second control signal Vg2 to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage and driving current of the light-emitting element. The external detection circuit is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), etc., and the embodiments of the present disclosure are not described in detail. Fig. 7A A gate g, a first electrode a, and a second electrode b of the transistor are shown.

[0075] like Fig. 7A As shown, the first electrode of the second transistor T2, the first electrode Ca of the storage capacitor Cst, and the gate of the first transistor T1 are all connected to the node G.

[0076] like Fig. 7A As shown, the second electrode plate Cb, the third electrode plate Cc, the first electrode of the first transistor T1, the first electrode of the third transistor T3, and the first electrode E1 of the light emitting element are all connected to the node S.

[0077] like Fig. 7A As shown, the second electrode E2 of the light emitting element EM is connected to the second power line PL2 to receive a second power voltage (eg, a low power voltage VSS). The second power line PL2 is configured to provide a second power voltage.

[0078] For example, Fig. 7A The storage capacitor Cst shown also includes a third plate Cc, which is located on a side of the first plate Ca away from the second plate Cb and is electrically connected to the second plate Cb to form a parallel capacitor structure, thereby increasing the capacitance value of the storage capacitor Cst. For example, in a direction perpendicular to the substrate BS, the third plate Cc, the second plate Cb, and the first plate Ca all overlap with each other.

[0079] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are all described by taking thin film transistors as examples. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of the transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). It should be noted that in the following description, Fig. 7A The transistor in the figure is an N-type transistor for illustration, but it is not intended to limit the present disclosure.

[0080] Combine the following FIG. 7B to FIG. 7D The signal timing diagram shown is Fig. 7A The working principle of the pixel circuit shown is explained, Figure 7B shows the signal timing diagram of the pixel circuit during the display process, Figure 7C and Fig.7D The signal timing diagram of the pixel circuit during the detection process is shown.

[0081] For example, Figure 7B As shown, the display process of each frame of image includes a data writing and resetting phase 1 and a light emitting phase 2. Figure 7BThe timing waveforms of each signal in each stage are shown. A working process of the 3T1C pixel circuit includes: in the data writing and resetting stage 1, the first control signal Vg1 and the second control signal Vg2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, the data signal Vdt is transmitted to the gate of the first transistor T1 through the second transistor T2, the analog-to-digital converter writes a reset signal to the first electrode E1 (for example, the anode of the OLED) of the light-emitting element through the sensing line SS and the third transistor T3, the first transistor T1 is turned on and generates a driving current to charge the first electrode E1 of the light-emitting element EM to the working voltage; in the light-emitting stage 2, the first control signal Vg1 and the second control signal Vg2 are both off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 works in a saturated state and the current remains unchanged, and drives the light-emitting element to emit light.

[0082] For example, Figure 7C The signal timing diagram of the pixel circuit when detecting the threshold voltage is shown. A working process of the 3T1C pixel circuit includes: the first control signal Vg1 and the second control signal Vg2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal Vdt is transmitted to the gate of the first transistor T1 through the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode E1 (node ​​S) of the light-emitting element EM through the sensing line SS and the third transistor T3, the first transistor T1 is turned on and charges the node S until the first transistor T1 is turned off, and the digital-to-analog converter samples the voltage on the sensing line SS to obtain the threshold voltage of the first transistor T1. This process can be performed, for example, when the display device is turned off. Figure 7C Vs in represents the voltage at the node S.

[0083] For example, Fig.7DThe signal timing diagram of the pixel circuit when detecting the carrier mobility is shown. A working process of the 3T1C pixel circuit includes: in the first stage, the first control signal Vg1 and the second control signal Vg2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal Vdt is transmitted to the gate of the first transistor T1 through the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode E1 (node ​​S) of the light-emitting element EM through the sensing line SS and the third transistor T3; in the second stage, the first control signal Vg1 is a closing signal, the second control signal Vg2 is an on signal, the second transistor T2 is turned off, the third transistor T3 is turned on, and the sensing line SS is floated; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 works in a saturated state and the current remains unchanged and drives the light-emitting element to emit light, and then the digital-to-analog converter samples the voltage on the sensing line SS, and the carrier mobility in the first transistor T1 can be calculated in combination with the magnitude and duration of the light-emitting current. For example, the process can be performed in the blanking stage between the display stages.

[0084] Through the above detection, the electrical characteristics of the first transistor T1 can be obtained and a corresponding compensation algorithm can be implemented.

[0085] For example, the display panel may further include a data driving circuit and a scanning driving circuit (not shown). The data driving circuit is configured to send a data signal, such as the above-mentioned data signal Vdt, as required (e.g., an image signal input to the display device); the pixel circuit of each sub-pixel is also configured to receive the data signal and apply the data signal to the gate of the first transistor. The scanning driving circuit is configured to output various scanning signals, such as the above-mentioned first control signal Vg1 and the second control signal Vg2, which is, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly prepared on the display panel.

[0086] For example, the display panel further includes a control circuit. For example, the control circuit is configured to control the data drive circuit to apply a data signal, and to control the gate drive circuit to apply a scan signal. An example of the control circuit is a timing control circuit (T-con). The control circuit can be in various forms, for example, including a processor and a memory, the memory including an executable code, and the processor runs the executable code to execute the above-mentioned detection method.

[0087] For example, the processor may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0088] For example, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on a computer-readable storage medium, and a processor may run the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium, such as electrical characteristic parameters obtained in the above-mentioned detection method, etc.

[0089] Figures 8 to 15 A plan view of a single film layer in a display panel provided in an embodiment of the present disclosure. Figures 16 to 23 A plan view of a stack of multiple film layers in a display panel provided in an embodiment of the present disclosure.

[0090] Figure 8 A plan view of a light shielding pattern LY0 in a display panel provided in an embodiment of the present disclosure. Fig. 9 A plan view of an active pattern ATL in a display panel provided for an embodiment of the present disclosure. Fig.10 A plan view of a first conductive pattern LY1 in a display panel provided according to an embodiment of the present disclosure. Fig.11 A plan view of a via hole pattern VH1 in a display panel provided in an embodiment of the present disclosure. Fig.12 A plan view of a second conductive pattern LY2 in a display panel provided in an embodiment of the present disclosure. Fig.13 A plan view of a via hole pattern VH2 in a display panel provided in an embodiment of the present disclosure. Fig.14 A plan view of an electrode pattern EL in a display panel provided in an embodiment of the present disclosure. Fig.15 A plan view of a pixel defining layer (PDL) in a display panel provided in an embodiment of the present disclosure.

[0091] Fig.16 A plan view of a light shielding pattern LY0 and an active pattern ATL in a display panel provided according to an embodiment of the present disclosure. Fig.17 A plan view of a light shielding pattern LY0 , an active pattern ATL, and a first conductive pattern LY1 in a display panel according to an embodiment of the present disclosure is provided. Fig.18 A stacked plan view of a light shielding pattern LY0 , an active pattern ATL, a first conductive pattern LY1 , ​​and a via hole pattern VH1 in a display panel provided according to an embodiment of the present disclosure. Fig.19A stacked plan view of a light shielding pattern LY0 , an active pattern ATL, a first conductive pattern LY1 , ​​a via hole pattern VH1 , and a second conductive pattern LY2 in a display panel provided according to an embodiment of the present disclosure. Fig. 20 A stacked plan view of a light shielding pattern LY0 , an active pattern ATL, a first conductive pattern LY1 , ​​a via pattern VH1 , a second conductive pattern LY2 , and a via pattern VH21 in a display panel provided according to an embodiment of the present disclosure. Fig.21 A stacked plan view of a light shielding pattern LY0 , an active pattern ATL, a first conductive pattern LY1 , ​​a via pattern VH1 , a second conductive pattern LY2 , a via pattern VH21 , and a via pattern VH22 in a display panel provided according to an embodiment of the present disclosure. Fig. 22 A stacked plan view of a light shielding pattern LY0 , an active pattern ATL, a first conductive pattern LY1 , ​​a via pattern VH1 , a second conductive pattern LY2 , a via pattern VH2 , and an electrode pattern EL in a display panel provided according to an embodiment of the present disclosure. Fig.23 A stacking plan view of a light shielding pattern LY0 , an active pattern ATL, a first conductive pattern LY1 , ​​a via pattern VH1 , a second conductive pattern LY2 , a via pattern VH2 , an electrode pattern EL, and a pixel defining layer PDL in a display panel provided in an embodiment of the present disclosure.

[0092] like Figure 8 As shown, the light shielding pattern LY0 includes a light shielding layer SL, a connecting electrode CE1, and a connecting electrode CE2. Figure 8 As shown, the light shielding layer SL also serves as the second electrode Cb. The function of the connecting electrode CE1 is to serve as a base pad or a blocking pad to prevent the via hole subsequently set at this position from affecting the base substrate.

[0093] like Fig. 9 As shown, the active pattern ATL includes an active layer A1, an active layer A2, and an active layer A3. In each of the active layer A1, the active layer A2, and the active layer A3, the middle portion is a semiconductor layer, and the portions on both sides are conductor portions, which can be used as the first electrode and the second electrode of the transistor respectively. Fig. 9 As shown, the active layers A3 of the third transistors in two adjacent sub-pixels in direction Y (column direction) are connected to each other and form an integrated structure.

[0094] like Fig.10 As shown, the first conductive pattern LY1 includes a first electrode Ca, a gate line G0, and a connecting electrode CE3. Fig. 7A The gate line G1 and the gate line G2 in the circuit are an integrated structure, and are both gate line G0. A portion of the gate line G0 is the gate of the second transistor T2, and a portion of the gate line G0 is the gate of the third transistor. That is, the gate line G0, the gate of the second transistor T2, and the gate of the third transistor are an integrated structure.

[0095] like Fig.11 As shown, the via hole pattern VH1 includes via holes V1 to V10 and via holes Va to Vk. The via hole pattern VH1 includes via holes penetrating the buffer layer BF and the insulating layer ILD and via holes penetrating the insulating layer ILD.

[0096] like Fig.12 As shown, the second conductive pattern LY2 includes a first power line PL1, a data line DT, a third electrode Cc, a sensing line SS, an auxiliary electrode AE, a connecting electrode CEa, a connecting electrode CEb, and a connecting electrode CEc. Fig.12 As shown in the figure, the auxiliary electrode AE ​​is disposed on the left side of the figure, and the auxiliary electrode AE ​​is not disposed on the right side of the figure. That is, the auxiliary electrode AE ​​is disposed on the side where the top-emitting sub-pixel is located, while the auxiliary electrode AE ​​is not disposed on the side where the bottom-emitting sub-pixel is located. Of course, in other embodiments, the auxiliary electrode AE ​​may also be disposed on the side where the bottom-emitting sub-pixel is located.

[0097] like Fig.12 As shown, the data line DT extends along the direction Y, and the plurality of data lines DT are arranged along the direction X. The data line DT includes a data line DT1, a data line DT2, a data line DT3, and a data line DT4. Fig.12 As shown, the data line DT1 , the data line DT2 , the data line DT4 , and the data line DT3 are sequentially arranged along the direction X.

[0098] like Fig.13 As shown, the via hole pattern VH2 includes an opening Ha, an opening Hb, and via holes H1 to H5.

[0099] like Fig.14 As shown, the electrode pattern EL includes a plurality of first electrodes E1. Fig.14 Four first electrodes E1 are shown. Fig.14 A first electrode E11 , a first electrode E12 , a first electrode E13 , and a first electrode E14 are shown.

[0100] like Fig.15 As shown, the pixel defining layer PDL includes a pixel defining layer PDL1 and a pixel defining layer PDL2.

[0101] like Fig.15 As shown, the pixel defining layer PDL1 has an opening PN1 , an opening PN2 , an opening PN5 , an opening PN6 , and a via hole PNh.

[0102] like Fig.16 As shown, the pixel defining layer PDL2 has an opening PN3 and an opening PN4.

[0103] Figures 8 to 23A marking line is shown in the middle of the drawing, which is a vertical line, a T-shaped line, or a cross line. The marking line can be seen as a boundary. The left side of the marking line is a top-emitting sub-pixel, and the right side of the marking line is a bottom-emitting sub-pixel. For ease of description, the plan views of the top-emitting sub-pixel and the bottom-emitting sub-pixel are placed in the same drawing.

[0104] refer to Fig.13 , Fig.21 and Fig. 22 , the via pattern VH2 includes a via pattern VH21 (reference Fig. 20 ) and via pattern VH22 (reference Fig.21 ). The via hole pattern VH21 is a via hole penetrating the passivation layer PVX, and the via hole pattern VH22 is a via hole penetrating the planarization layer PLN. Fig. 20 As shown, the via hole pattern VH21 includes an opening Ha, an opening Hb, a via hole H11, a via hole H21, a via hole H31, a via hole H41, and a via hole H51. Fig.21 As shown, the via hole pattern VH22 includes an opening Hc, an opening Hd, a via hole H12, a via hole H22, a via hole H32, a via hole H42, and a via hole H52. Fig.13 , Fig.21 and Fig. 22 The via holes H11 and H12 constitute the via hole H1, the via holes H21 and H22 constitute the via hole H2, the via holes H31 and H32 constitute the via hole H3, the via holes H41 and H42 constitute the via hole H4, and the via holes H51 and H52 constitute the via hole H5.

[0105] like Fig.14 and Fig.23 As shown, the second electrode E2 is connected to the connection electrode CEe through the via hole PNh. The connection electrode CEe is connected to the auxiliary electrode AE ​​through the via hole H5 to reduce the resistance of the second electrode E2.

[0106] like Fig.14 and Fig. 22 As shown, the first electrode E11 is connected to the third electrode plate Cc (node ​​S) through the via hole H1, the first electrode 2 is connected to the third electrode plate Cc (node ​​S) through the via hole H2, the first electrode E13 is connected to the third electrode plate Cc (node ​​S) through the via hole H3, and the first electrode E14 is connected to the third electrode plate Cc (node ​​S) through the via hole H4. Each sub-pixel has its own pixel circuit PXC.

[0107] refer to Fig. 7A , Figures 8 to 12 , Fig.18 ,as well as Fig.19As shown, the first power line PL1 is connected to one end of the connection electrode CE3 through the via hole V1, and the other end of the connection electrode CE3 is connected to one end of the connection electrode CEa through the via hole V2. The other end of the connection electrode CEa is connected to the active layer A1 (the second electrode of the first transistor T1) through the via hole V4. The third electrode plate Cc is connected to the active layer A1 (the first electrode of the first transistor T1) and the second electrode plate Cb through the via hole V3. Fig.19 In the upper left sub-pixel, the middle part of the active layer A1 is the semiconductor layer, the left side of the semiconductor layer of the active layer A1 is the first electrode of the first transistor T1, and the right side of the semiconductor layer of the active layer A1 is the second electrode of the first transistor T1.

[0108] refer to Fig. 7A , Figures 8 to 12 , Fig.18 ,as well as Fig.19 As shown, one end of the connecting electrode CEb is connected to the first electrode plate Ca through a via hole V5, and the other end of the connecting electrode CEb is connected to the active layer A2 (the first electrode of the second transistor T2) through a via hole V7. The data line DT1 is connected to the active layer A2 (the second electrode of the second transistor T2) through a via hole V8. Fig.19 In the sub-pixel at the upper left corner, the middle part of the active layer A2 is the semiconductor layer, the upper side of the semiconductor layer of the active layer A2 is the first electrode of the second transistor T2, and the lower side of the semiconductor layer of the active layer A2 is the second electrode of the second transistor T2.

[0109] refer to Fig. 7A , Figures 8 to 12 , Fig.18 ,as well as Fig.19 As shown, the third electrode plate Cc is connected to the second electrode plate Cb through a via V6.

[0110] refer to Fig. 7A , Figures 8 to 12 , Fig.18 ,as well as Fig.19 As shown, one end of the connection electrode CEc is connected to the active layer A3 (the second electrode of the third transistor T3) through the via hole V10, the other end of the connection electrode CEc is connected to one end of the connection electrode CE2 through the via hole Va, and the other end of the connection electrode CE2 is connected to the sensing line SS through the via hole Vb. The third electrode plate Cc is connected to the active layer A3 (the first electrode of the third transistor T3) through the via hole V9. Fig.19 In the sub-pixel at the upper left corner, the middle part of the active layer A3 is a semiconductor layer, the upper side of the semiconductor layer is a first electrode of the third transistor T3, and the lower side of the semiconductor layer is a second electrode of the third transistor T3.

[0111] The above describes the pixel circuit of the upper left sub-pixel. The following describes the pixel circuit of the lower left sub-pixel. Fig.19As shown, the first electrode of the third transistor T3 is connected to the third electrode plate Cc through the via hole Vc, the third electrode plate Cc is connected to the second electrode plate Cb through the via hole Vf, the data line DT is connected to the second electrode of the second transistor T2 through the via hole Vd, the first electrode of the second transistor T2 is connected to one end of the connection electrode CEb through the via hole Ve, and the other end of the connection electrode CEb is connected to the first electrode plate Ca through the via hole Vg. The third electrode plate Cc is connected to the first electrode of the first transistor T1 and the second electrode plate Cb through the via hole Vh, the second electrode of the first transistor T1 is connected to one end of the connection electrode CEa through the via hole Vi, the other end of the connection electrode CEa is connected to one end of the connection electrode CE3 through the via hole Vk, and the other end of the connection electrode CE3 is connected to the first power line PL1 through the via hole Vj. Fig.19 In the embodiment, the electrode Ea may be the third electrode plate Cc. Figures 3 to 6 The electrode Ea shown is connected to the light shielding layer SL and the first electrode of the first transistor T1 through two via holes. Fig.19 In the embodiment, the third electrode plate Cc is connected to the first electrode of the first transistor T1 and the second electrode plate Cb (light shielding layer SL) through the same via hole Vh.

[0112] like Fig.23 As shown, the double-layer structure can be formed by folding the marked line or the line extending along the direction Y. That is, the opening PN4 ​​overlaps with the opening PN6 by folding, and the opening PN3 overlaps with the opening PN5 by folding. Figures 3 to 6 The transparent area A0 shown in FIG. Figure 1 The display panel shown. Fig.23 The light emitted from the light emitting region EMR3 of the sub-pixel SP3 is shown to be emitted from the transparent region A03. Fig.23 The light emitted from the light emitting region EMR4 of the sub-pixel SP4 is shown to be emitted from the transparent region A04.

[0113] For example, Fig.23 As shown, the light emitting area of ​​at least one top-emitting sub-pixel SPT is smaller than the light emitting area of ​​at least one bottom-emitting sub-pixel SPB.

[0114] For example, Fig.15 and Fig.23 As shown, in order to improve the brightness of the bottom-emitting sub-pixel SPB, the area of ​​the orthographic projection of the transparent area A0 on the base substrate BS is greater than or equal to the area of ​​the orthographic projection of the light-emitting region EMR of the bottom-emitting sub-pixel SPB on the base substrate BS.

[0115] For the bottom-emitting sub-pixel SPB, the light-emitting area of ​​the light-emitting element does not overlap with the pixel circuit. Fig.23 As shown, the pixel circuit of the bottom-emitting sub-pixel SPB is on the left, and the light-emitting area of ​​the light-emitting element is on the right.

[0116] For a top-emitting sub-pixel SPT, the light-emitting region of the light-emitting element overlaps with the pixel circuit.

[0117] For example, Figures 3 to 6 , Fig. 7A ,as well as Fig.23 As shown, the sub-pixel SP includes a pixel circuit PXC and a light-emitting element EM, and the orthographic projection of the pixel circuit PXC of the top-emitting sub-pixel SPT on the substrate BS overlaps with the orthographic projection of the pixel circuit PXC of the bottom-emitting sub-pixel SPB on the substrate BS. This arrangement is conducive to saving area and improving the aperture ratio of the sub-pixel.

[0118] For example, Figures 3 to 6 , Fig. 7A ,as well as Fig.23 As shown, the orthographic projection of the light emitting element EM of the top-emitting sub-pixel SPT on the substrate BS overlaps with the orthographic projection of the pixel circuit PXC of the bottom-emitting sub-pixel SPB on the substrate BS. This arrangement is conducive to saving area and improving the aperture ratio of the sub-pixel.

[0119] For example, Figures 3 to 6 , Fig. 7A ,as well as Fig.23 As shown, the pixel circuit PXC of the top-emitting subpixel SPT is closer to the substrate BS than the light-emitting element EM of the top-emitting subpixel SPT, and the pixel circuit PXC of the bottom-emitting subpixel SPB is closer to the substrate BS than the light-emitting element EM of the bottom-emitting subpixel SPB.

[0120] For example, Fig. 7A and Fig.23 As shown, the pixel circuit PXC includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0121] For example, Fig. 7A , Fig.10 , Fig.17 , Fig.19 and Fig.23 As shown, the display panel further includes a gate line G0, which is connected to the gate of the second transistor T2 and the gate of the third transistor T3, and the first transistor T1 is located on a side of the storage capacitor Cst away from the gate line G0. This arrangement is conducive to the arrangement of transistors and the storage capacitor Cst.

[0122] For example, Fig.19 As shown, the second transistor T2 and the third transistor T3 are located on the side of the storage capacitor Cst close to the gate line G0. The positions of the active layers A1, A2, and A3 in the figure are the positions of the first transistor T1, the second transistor T2, and the third transistor T3 respectively.

[0123] For example, Fig.19 As shown, the display panel also includes a data line DT, a sensing line SS and a first power line PL1, the data line DT is connected to the second transistor T2, the first power line PL1 is connected to the first transistor T1, the sensing line SS is connected to the third transistor T3, and the data line DT, the sensing line SS, and the first power line PL1 are located in the same layer and are all located in the second conductive pattern LY2.

[0124] For example, Figures 3 to 6 , Fig.19 As shown, the display panel also includes an auxiliary electrode AE, and the light-emitting element EM includes a first electrode E1 connected to the pixel circuit PXC, a light-emitting functional layer FL located on the side of the first electrode E1 away from the substrate BS, and a second electrode E2 located on the side of the light-emitting functional layer FL away from the first electrode E1, the second electrode E2 is connected to the auxiliary electrode AE, and the auxiliary electrode AE ​​is located on the same layer as the data line DT, the sensing line SS, and the first power line PL1, and are all located in the second conductive pattern LY2.

[0125] For example, Figures 3 to 6 As shown, the display panel further includes a light shielding layer SL, which is located on a side of the pixel circuit PXC close to the substrate BS, and the first electrode of the first transistor T1 is connected to the first electrode E1 of the light emitting element EM. The light shielding layer SL is connected to the first electrode of the first transistor T1. Figures 3 to 6 The transistor shown may be regarded as a first transistor T1.

[0126] For example, Figures 3 to 6 ,as well as Fig.15 As shown, the display panel also includes a first pixel defining layer PDL1, which is located on the first side S1 of the display panel. The first pixel defining layer PDL1 has an opening PN1 and an opening PN5. The opening PN1 is configured to limit the light-emitting area of ​​the top-emitting sub-pixel. For example, the orthographic projection of the opening PN1 on the substrate BS overlaps with the orthographic projection of the top-emitting sub-pixel SPT on the substrate BS, and the orthographic projection of the opening PN5 on the substrate BS overlaps with the orthographic projection of the transparent area A0 on the substrate BS.

[0127] For example, Fig.15 As shown, the area of ​​the opening PN1 is smaller than the area of ​​the opening PN5. Thus, in some embodiments, the area of ​​the top-emitting sub-pixel is smaller than the area of ​​the bottom-emitting sub-pixel.

[0128] For example, Figures 3 to 6 ,as well as Fig.15As shown, the display panel further includes a second pixel defining layer PDL2, the second pixel defining layer PDL2 is located at the second side S2 of the display panel, and the second pixel defining layer PDL2 has an opening PN3, and the opening PN3 is configured to define the light emitting area of ​​the bottom-emitting sub-pixel, for example, the orthographic projection of the opening PN3 on the base substrate BS overlaps with the orthographic projection of the bottom-emitting sub-pixel SPB on the base substrate BS, and the area of ​​the opening PN3 is less than or equal to the area of ​​the opening PN5. This setting is conducive to improving the aperture ratio of the sub-pixel.

[0129] Above Fig.15 The structure of the upper and middle parts (opening PN5, opening PN1, and opening PN3) is used for explanation. Similarly, Fig.15 The lower middle part (opening PN6, opening PN2, and opening PN4) also has the structure described above, which will not be described in detail here.

[0130] In the embodiment of the present disclosure, the light emitting element may be an organic light emitting diode (OLED), but is not limited thereto.

[0131] In the embodiment of the present disclosure, the active layer of the transistor may be an oxide semiconductor, but is not limited thereto.

[0132] In the embodiment of the present disclosure, the second electrode E2 of the top-emitting sub-pixel may be a semi-transparent electrode, and the first electrode E1 of the top-emitting sub-pixel may be a reflective electrode, but is not limited thereto.

[0133] In the embodiment of the present disclosure, the second electrode E2 of the bottom-emitting sub-pixel may be a reflective electrode, and the first electrode E1 of the top-emitting sub-pixel may be a semi-transparent electrode, but is not limited thereto.

[0134] For example, at least one of the light shielding pattern LY0 , the first conductive pattern LY1 , ​​and the second conductive pattern LY may be made of a metal material.

[0135] For example, at least one of the buffer layer BF, the insulating layer GI, the insulating layer ILD, and the passivation layer PVX may be made of an inorganic insulating material, which includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0136] For example, at least one of the planarization layer PLN and the pixel definition layer PDL may be made of an organic insulating material, which includes, but is not limited to, resin.

[0137] For example, the base substrate BS may be a rigid substrate (eg, glass) or a flexible substrate (eg, polyimide).

[0138] refer to Figures 3 to 6 , Figures 8 to 23 , a method for manufacturing a backplane of a display panel includes the following steps.

[0139] (1) A light shielding pattern LY0 is formed on a base substrate.

[0140] For example, a metal film is deposited on a transparent substrate by a sputtering process, and after being patterned by photolithography and wet etching, the photoresist on the metal surface is stripped off to obtain a light-shielding pattern LY0, such as Figure 8 For example, the substrate is a glass substrate with a thickness of 50-1000 um.

[0141] (2) A buffer layer BF is formed on the light shielding pattern LY0.

[0142] For example, the buffer layer BF is deposited by plasma enhanced chemical vapor deposition (PECVD) process. The buffer layer BF may be formed by overlapping one or more of SiNx, SiOx or SiOxNy. The thickness of the buffer layer BF is 150-500 nm.

[0143] (3) An active pattern ATL is formed on the buffer layer BF.

[0144] For example, an oxide semiconductor is deposited on the buffer layer BF as a pattern ATL by a sputtering process. Fig. 9 For example, the oxide semiconductor may be an amorphous oxide such as IGZO, ZnON, or ITZO.

[0145] (4) An insulating layer GI is formed on the active pattern ATL, and a first conductive pattern LY1 is formed on the insulating layer GI. Fig.10 shown.

[0146] For example, a chemical vapor deposition (CVD) process is used to deposit an insulating film; then a sputtering process is used to deposit a gate metal layer on the insulating film, for example, the metal thickness is 200-1000nm, for example, the metal includes at least one of Al, Mo, Cr, Cu, and Ti, and the patterns of the gate lines, connecting electrodes, and capacitor plates are defined through photolithography and wet etching processes, while the photoresist is retained and not stripped off, and the photoresist on the gate metal layer is continued to be used as a mask to dry-etch the pattern of the insulating layer GI; the active pattern ATL exposed to the outside (the part not covered by the first conductive pattern LY1) is conductorized using gases such as NH3, N2, or H2 to reduce the ohmic contact resistance with the second conductive pattern LY2.

[0147] (5) An insulating layer ILD is formed on the first conductive pattern LY1, and a via hole pattern VH1 is formed. Fig.11 shown.

[0148] For example, an insulating film is deposited by a PECVD process, and a via hole connecting the second conductive pattern LY2 and the active pattern ATL is obtained by a dry etching process, and a via hole connecting the second conductive pattern LY2 and the light shielding pattern LY0 is also obtained to form an insulating layer ILD. For example, the insulating layer ILD is a single layer or multilayer film of SiNx or SiOx.

[0149] (6) A second conductive pattern LY2 is formed on the insulating layer ILD.

[0150] For example, a metal film is deposited by sputtering process, the metal may be Al, Mo, Cr, Cu, Ti, etc., with a thickness of 200-1000 nm, and a second conductive pattern LY2 is obtained by photolithography and wet etching process, such as Fig.12 .

[0151] (7) A passivation layer PVX is formed on the second conductive pattern LY2.

[0152] For example, the passivation layer PVX is deposited by using a CVD process, and the material of the passivation layer PVX may be SiO2.

[0153] (8) A planarization layer PLN is formed on the passivation layer PVX, and a via hole pattern VH2 is formed, such as Fig.13 shown.

[0154] For example, an organic material is deposited by a coating method (e.g., slit), and a pattern of a pixel area is obtained by pre-baking, exposure, and development, and water and organic solvents are removed by post-baking at a certain temperature, such as 230 degrees, to obtain a planarization layer with a thickness of 2.0 to 3.5 μm. Then, a via hole pattern VH2 is formed by exposure and etching, and the via hole in the via hole pattern VH2 is used to connect the electrode pattern EL with the components in the second conductive pattern LY2.

[0155] (9) An electrode pattern EL (a first electrode E1 of the light emitting element) is formed on the planarization layer PLN. Fig.14 shown.

[0156] For example, the first electrode E1 is deposited by sputtering process. The material of the first electrode E1 can be Al, Mo, Cu and indium tin oxide (ITO), etc., with a thickness of 100-600nm. The pattern of the first electrode E1 (electrode pattern EL) is obtained by photolithography and wet etching process.

[0157] (10) A pixel defining layer PDL is formed on the electrode pattern EL.

[0158] For example, a pixel defining layer material is deposited by a coating method (such as a slit), and the pattern of the solidified pixel area is exposed through pre-baking, exposure, and development. The water and organic solvent are removed through post-baking at a certain temperature, such as 230 degrees, to obtain a pixel defining layer PDL with a thickness of 1.8 to 2.0 μm.

[0159] After the above steps, the backplane process is completed.

[0160] In some drawings of the embodiments of the present disclosure, the plan view shows direction X and direction Y, and the cross-sectional view shows direction Z. Direction X and direction Y are both directions parallel to the main surface of the substrate substrate BS. Direction Z is a direction perpendicular to the main surface of the substrate substrate BS. For example, direction X and direction Y intersect. The embodiments of the present disclosure are described by taking the example that direction X and direction Y are perpendicular. For example, the main surface of the substrate substrate BS is the surface of the substrate substrate BS used to make various components. The upper surface and / or lower surface of the substrate substrate BS in the cross-sectional view is the main surface of the substrate substrate BS. Direction Z is perpendicular to direction X and perpendicular to direction Y.

[0161] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels.

[0162] For example, the display device may be an organic light emitting diode display device. The display device may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., which includes an organic light emitting diode display device.

[0163] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, comprising: a plurality of pixels, wherein each pixel of the plurality of pixels comprises a plurality of sub-pixels, In the same pixel, at least one of the multiple sub-pixels is a top-emitting sub-pixel, and at least one of the multiple sub-pixels is a bottom-emitting sub-pixel, and the top-emitting sub-pixel and the bottom-emitting sub-pixel emit light toward the same side of the display panel.

2. The display panel according to claim 1, wherein: The light emitting area of ​​at least one top-emitting sub-pixel is smaller than the light emitting area of ​​at least one bottom-emitting sub-pixel.

3. The display panel according to any one of claims 1 to 2, wherein: The pixel includes an even number of sub-pixels, and in the same pixel, the top-emitting sub-pixel and the bottom-emitting sub-pixel are arranged in a mirror-image manner.

4. The display panel according to any one of claims 1 to 2, wherein: The plurality of sub-pixels are four sub-pixels, two of the four sub-pixels are top-emitting sub-pixels, and the other two of the four sub-pixels are bottom-emitting sub-pixels.

5. The display panel according to claim 4, wherein: The bottom-emitting sub-pixels are sub-pixels that emit blue light and sub-pixels that emit white light, and the top-emitting sub-pixels are sub-pixels that emit red light and sub-pixels that emit green light.

6. The display panel according to any one of claims 1 to 2, wherein: The pixel includes an odd number of sub-pixels, and in the same pixel, the light-emitting area of ​​at least one sub-pixel is greater than or equal to the sum of the light-emitting areas of each sub-pixel in the other two sub-pixels.

7. The display panel according to any one of claims 1 to 2, wherein: The plurality of sub-pixels are three sub-pixels, two of the three sub-pixels are top-emitting sub-pixels, and another sub-pixel of the three sub-pixels is a bottom-emitting sub-pixel.

8. The display panel according to claim 7, wherein: The bottom-emitting sub-pixels are sub-pixels that emit blue light, and the top-emitting sub-pixels are sub-pixels that emit red light and sub-pixels that emit green light.

9. The display panel according to claim 8, wherein: The light emitting area of ​​the sub-pixel emitting blue light is larger than the light emitting area of ​​the sub-pixel emitting red light, and larger than the light emitting area of ​​the sub-pixel emitting green light.

10. The display panel according to any one of claims 1 to 2, wherein: The display panel has a base substrate, and the top-emitting sub-pixels and the bottom-emitting sub-pixels are respectively arranged on two opposite sides of the base substrate.

11. The display panel according to claim 10, wherein: The display panel includes a first side and a second side relative to each other, the first side is a light-emitting side, the top-emitting sub-pixel is located on the first side, and the bottom-emitting sub-pixel is located on the second side, and the display panel has a transparent area on the first side, and the orthographic projection of the transparent area on the substrate overlaps with the orthographic projection of the light-emitting area of ​​the bottom-emitting sub-pixel on the substrate.

12. The display panel according to claim 11, wherein: An area of ​​an orthographic projection of the transparent region on the base substrate is greater than or equal to an area of ​​an orthographic projection of a light emitting region of the bottom-emitting sub-pixel on the base substrate.

13. The display panel according to claim 11 or 12, wherein: The sub-pixel comprises a pixel circuit and a light-emitting element, and an orthographic projection of the pixel circuit of the top-emitting sub-pixel on the substrate overlaps with an orthographic projection of the pixel circuit of the bottom-emitting sub-pixel on the substrate.

14. The display panel according to claim 13, wherein: The orthographic projection of the light emitting element of the top-emitting sub-pixel on the base substrate overlaps with the orthographic projection of the pixel circuit of the bottom-emitting sub-pixel on the base substrate.

15. The display panel according to claim 13, wherein: The pixel circuit of the top-emitting sub-pixel is closer to the base substrate than the light-emitting element of the top-emitting sub-pixel, and the pixel circuit of the bottom-emitting sub-pixel is closer to the base substrate than the light-emitting element of the bottom-emitting sub-pixel.

16. The display panel according to claim 13, wherein: The pixel circuit includes a first transistor, a second transistor, a third transistor, and a storage capacitor. The display panel further includes a gate line, wherein the gate line is connected to a gate of the second transistor and a gate of the third transistor, and the first transistor is located on a side of the storage capacitor away from the gate line.

17. The display panel according to claim 16, wherein: The second transistor and the third transistor are located on a side of the storage capacitor close to the gate line.

18. The display panel according to claim 17, further comprising a data line, a sensing line and a first power line, wherein: The data line is connected to the second transistor, the first power line is connected to the first transistor, the sensing line is connected to the third transistor, and the data line, the sensing line, and the first power line are located in the same layer.

19. The display panel according to claim 18, further comprising an auxiliary electrode, wherein: The light-emitting element includes a first electrode connected to the pixel circuit, a light-emitting functional layer located on a side of the first electrode away from the substrate, and a second electrode located on a side of the light-emitting functional layer away from the first electrode, the second electrode is connected to the auxiliary electrode, and the auxiliary electrode is located on the same layer as the data line, the sensing line, and the first power line.

20. The display panel according to any one of claims 16 to 19, further comprising a light shielding layer, wherein: The light shielding layer is located on a side of the pixel circuit close to the base substrate, the first electrode of the first transistor is connected to the first electrode of the light emitting element, and the light shielding layer is connected to the first electrode of the first transistor.

21. The display panel according to any one of claims 11 to 12 and 14 to 20, further comprising a first pixel defining layer, wherein: The first pixel defining layer is located on the first side of the display panel, and the first pixel defining layer has a first opening and a second opening, the first opening is configured to define the light-emitting area of ​​the top-emitting sub-pixel, and the orthographic projection of the second opening on the base substrate overlaps with the orthographic projection of the transparent area on the base substrate.

22. The display panel according to claim 21, wherein: An area of ​​the first opening is smaller than an area of ​​the second opening.

23. The display panel according to claim 21, further comprising a second pixel defining layer, wherein: The second pixel defining layer is located on the second side of the display panel, and the second pixel defining layer has a third opening, which is configured to define the light emitting area of ​​the bottom-emitting sub-pixel, and the area of ​​the third opening is less than or equal to the area of ​​the second opening.

24. A display device comprising the display panel according to any one of claims 1-23.

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