Substrates and electronic devices

Abstract

A substrate has a plurality of edges. The substrate includes a device region and at least one bonding region, the bonding region being closer to any edge of the substrate than the device region. The substrate includes a substrate, a plurality of device groups, a plurality of signal line groups, and a plurality of conductive patterns. The plurality of device groups are located on one side of the substrate, and the plurality of device groups are located in the device region. The plurality of device groups are arranged along a first direction and a second direction, respectively. One device group includes at least one electronic component. One signal line group includes a plurality of signal lines, any one of which extends from the bonding region to the device region, and any one of which is electrically connected to a column of device groups arranged along the second direction. At least one of the plurality of conductive patterns is located in an area in which one device group is located. And / or, at least one of the plurality of conductive patterns is located in an area between two adjacent device groups. At least one signal line in at least one signal line group is electrically connected to one conductive pattern.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a substrate and an electronic device. Background Technology

[0002] A substrate typically includes electronic components and signal lines, with the signal lines electrically connected to the electronic components to enable signal transmission. Summary of the Invention

[0003] On one hand, a substrate is provided. The substrate has multiple edges. The substrate includes a device region and at least one bonding region, the bonding region being adjacent to any edge of the substrate relative to the device region. The substrate includes a substrate, multiple device groups, multiple signal line groups, and multiple conductive patterns. The multiple device groups are located on one side of the substrate and are located in the device region. The multiple device groups are arranged along a first direction and a second direction, the first direction and the second direction intersecting and being parallel to the substrate. A device group includes at least one electronic component. The multiple signal line groups are located on the same side of the substrate as the multiple device groups. A signal line group includes multiple signal lines, all extending along the second direction and spaced apart along the first direction. Any signal line extends from the bonding region to the device region, and any signal line is electrically connected to a column of device groups arranged along the second direction. The multiple conductive patterns are located on the same side of the substrate as the multiple device groups. At least one of the multiple conductive patterns is located within the region of a device group. And / or, at least one of the multiple conductive patterns is located in the region between two adjacent device groups. At least one signal line in at least one signal line group is electrically connected to a conductive pattern.

[0004] In some embodiments, multiple conductive patterns are disposed on the same layer as multiple signal line groups.

[0005] In some embodiments, the plurality of signal line groups include a first voltage line group, which includes a plurality of first voltage lines. The plurality of conductive patterns include a plurality of first conductive patterns, which are electrically connected to at least one first voltage line in the first voltage line group.

[0006] In some embodiments, the substrate further includes a plurality of first bridging portions, and at least one first conductive pattern is electrically connected to a first voltage line through the first bridging portion.

[0007] In some embodiments, at least one of the plurality of first bridging portions is a bridging resistor.

[0008] In some embodiments, at least one first conductive pattern and a first voltage line form an integral structure.

[0009] In some embodiments, at least two first conductive patterns are arranged along a first direction.

[0010] In some embodiments, at least two first conductive patterns arranged along a first direction constitute a first conductive pattern row, and a plurality of first conductive patterns constitute at least two first conductive pattern rows.

[0011] In some embodiments, there are two first conductive pattern rows, and the number of first conductive patterns included in the two first conductive pattern rows is different. The length of any device group along the second direction is L. Along the second direction, one first conductive pattern row is closer to the bonding region than the other first conductive pattern row, and the interval between the two first conductive pattern rows along the second direction ranges from 3L to 5L.

[0012] In some embodiments, the plurality of device groups include a first row of device groups, which is adjacent to the bonding region along a second direction. At least one first conductive pattern row is located within the region containing the first row of device groups.

[0013] In some embodiments, the plurality of first conductive patterns includes a first type of first conductive pattern. One end of the first type of first conductive pattern is directly connected to the end of the bonding region near the device region, and the other end of the first type of first conductive pattern is electrically connected to the first voltage line group. The number of the first type of first conductive pattern is 'a', where 'a' is less than the number of first voltage lines in the first voltage line group, and 'a' is a positive integer.

[0014] In some embodiments, a is not greater than half the number of first voltage lines in the first voltage line group.

[0015] In some embodiments, the plurality of signal line groups further includes a second voltage line group, which includes a plurality of second voltage lines. The plurality of conductive patterns further includes a plurality of second conductive patterns, which are electrically connected to at least one second voltage line in the second voltage line group.

[0016] In some embodiments, the substrate further includes a plurality of second bridging portions, and at least one second conductive pattern is electrically connected to a second voltage line through the second bridging portion.

[0017] In some embodiments, at least one of the plurality of second bridging portions is a bridging resistor.

[0018] In some embodiments, at least one second conductive pattern and a second voltage line form an integral structure.

[0019] In some embodiments, at least two second conductive patterns are arranged along a first direction.

[0020] In some embodiments, at least two second conductive patterns arranged along a first direction constitute a second conductive pattern row, and a plurality of second conductive patterns constitute at least two second conductive pattern rows.

[0021] In some embodiments, there are two second conductive pattern rows, and the number of second conductive patterns included in the two second conductive pattern rows is different. The length of any device group along the second direction is L. Along the second direction, one second conductive pattern row is closer to the bonding region than the other second conductive pattern row, and the interval between the two second conductive pattern rows along the second direction ranges from 3L to 5L.

[0022] In some embodiments, the plurality of device groups include a first row of device groups adjacent to the bonding region along a second direction. At least one second conductive pattern row is located within the region containing the first row of device groups.

[0023] In some embodiments, the plurality of second conductive patterns includes a first type of second conductive pattern. One end of the first type of second conductive pattern is directly connected to the end of the bonding region near the device region, and the other end of the first type of second conductive pattern is electrically connected to the second voltage line group. The number of the first type of second conductive patterns is b, where b is less than the number of second voltage lines in the second voltage line group, and b is a positive integer.

[0024] In some embodiments, Y is not greater than half the number of second voltage lines in the second voltage line group.

[0025] In some embodiments, the substrate further includes a plurality of third bridging portions and a plurality of fourth bridging portions. At least two first conductive patterns are electrically connected through the third bridging portions. And / or, at least two second conductive patterns are electrically connected through the fourth bridging portions.

[0026] In some embodiments, within the same first voltage line group, at least two first voltage lines are interconnected on the side away from the bonding region along the second direction. And / or, within the same second voltage line group, at least two second voltage lines are interconnected on the side away from the bonding region along the second direction.

[0027] In some embodiments, the width of the first voltage line along the first direction ranges from 0.5 mm to 1 mm. And / or, the width of the second voltage line along the first direction ranges from 0.5 mm to 1 mm.

[0028] In some embodiments, any first voltage line is located along a first direction on a first side of a group of devices electrically connected to the first voltage line. Any second voltage line is located along the first direction on a second side of a group of devices electrically connected to the second voltage line.

[0029] In some embodiments, there are multiple bonding areas, and multiple signal lines in a signal line group are electrically connected to one of the multiple bonding areas.

[0030] In some embodiments, the substrate further includes an electrostatic loop and a circuit board. The electrostatic loop is disposed around a plurality of device groups and is electrically connected to the bonding region. The circuit board is electrically connected to the bonding region.

[0031] On the other hand, an electronic device is provided. The electronic device includes a substrate as described above. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0033] Figure 1A This is a structural diagram of an electronic device according to some embodiments;

[0034] Figure 1B This is a structural diagram of an electronic device according to some other embodiments;

[0035] Figure 2A This is a structural diagram of a substrate according to some embodiments;

[0036] Figure 2B This is a structural diagram of a substrate according to some other embodiments;

[0037] Figure 2C This is a structural diagram of a device group according to some embodiments;

[0038] Figure 2D This is a structural diagram of a driver chip and device group according to some embodiments;

[0039] Figure 2E This is a structural diagram of the driver chip and device group according to some other embodiments;

[0040] Figure 2F This is a structural diagram of a substrate according to some other embodiments;

[0041] Figure 2G This is a structural diagram of a substrate according to some other embodiments;

[0042] Figure 3A This is a structural diagram of a substrate according to some other embodiments;

[0043] Figure 3B This is a structural diagram of a substrate according to some other embodiments;

[0044] Figure 3CThis is a structural diagram of a substrate according to some other embodiments;

[0045] Figure 3D This is a structural diagram of a substrate according to some other embodiments;

[0046] Figure 3E This is a structural diagram of a substrate according to some other embodiments;

[0047] Figure 3F This is a structural diagram of a substrate according to some other embodiments;

[0048] Figure 4A This is a structural diagram of a substrate according to some other embodiments;

[0049] Figure 4B This is a structural diagram of a substrate according to some other embodiments;

[0050] Figure 4C This is a structural diagram of a substrate according to some other embodiments;

[0051] Figure 5A This is a structural diagram of a substrate according to some other embodiments;

[0052] Figure 5B This is a structural diagram of a substrate according to some other embodiments;

[0053] Figure 5C This is a structural diagram of a substrate according to some other embodiments;

[0054] Figure 5D This is a structural diagram of a substrate according to some other embodiments;

[0055] Figure 5E This is a structural diagram of a substrate according to some other embodiments;

[0056] Figure 6A This is a structural diagram of a substrate according to some other embodiments;

[0057] Figure 6B This is a structural diagram of a substrate according to some other embodiments;

[0058] Figure 6C This is a structural diagram of a substrate according to some other embodiments;

[0059] Figure 7A This is a structural diagram of a substrate according to some other embodiments;

[0060] Figure 7B for Figure 7A A magnified view of a portion of region 1 in the middle;

[0061] Figure 8A This is a structural diagram of a substrate according to some other embodiments;

[0062] Figure 8B for Figure 8A A magnified view of a portion of region 2 in the middle;

[0063] Figure 8C for Figure 8A A magnified view of a portion of region 3 in the middle;

[0064] Figure 8D for Figure 8A A magnified view of a portion of region 4 in the middle. Detailed Implementation

[0065] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0066] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0067] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0068] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.

[0069] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0070] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0071] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0072] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0073] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0074] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0075] Figure 1A This is a structural diagram of an electronic device according to some embodiments.

[0076] like Figure 1A As shown, embodiments of this disclosure provide an electronic device 200. In some examples, the electronic device 200 may be a product with image display capabilities. For example, the electronic device 200 may be used to display static images, such as pictures or photographs. The electronic device 200 may also be used to display dynamic images, such as videos or game footage.

[0077] In some examples, electronic device 200 may be a laptop computer, mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display, etc.), navigator, cockpit controller and / or display, display of camera view (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, packaging and aesthetic structure (e.g., display of an image of a piece of jewelry), etc.

[0078] In other examples, electronic device 200 may also be a product that does not have image display capabilities.

[0079] The embodiments disclosed herein do not further limit the electronic device 200. The following example illustrates the electronic device 200 as a product with image display function.

[0080] Figure 1B This is a structural diagram of an electronic device according to some other embodiments.

[0081] like Figure 1B As shown, in some embodiments, the electronic device 200 may include a substrate 100 and a display panel 210. For example, the substrate 100 is used to emit light outward, and the display panel 210 is located on the light-emitting side of the substrate 100 and is used to display image information.

[0082] In some examples, the display panel 210 is a liquid crystal display panel, and the substrate 100 is used to provide backlight to the display panel 210.

[0083] In some examples, substrate 100 can be used to emit white or blue light. Display panel 210 can filter or convert the light emitted by substrate 100 to obtain red, green, and blue light, enabling electronic device 200 to display full-color images.

[0084] The following description uses display panel 210 as an example of an LCD display panel.

[0085] In some examples, such as Figure 1B As shown, the display panel 210 includes an array substrate 216, an opposing substrate 214, and a liquid crystal layer 212 located between the array substrate 216 and the opposing substrate 214. Understandably, light emitted from the substrate 100 can pass through the array substrate 216 and illuminate the liquid crystal layer 212. The liquid crystal layer 212 contains liquid crystal molecules. By controlling the deflection angle of the liquid crystal molecules, the intensity of light passing through the liquid crystal layer 212 and illuminating the opposing substrate 214 can be controlled, thereby enabling the electronic device 200 to perform image display functions.

[0086] In some examples, when substrate 100 is used to emit white light, the opposing substrate 214 may include a red filter film, a green filter film, and a blue filter film. By controlling the intensity of light irradiated onto the red filter film, the green filter film, and the blue filter film, different intensities of red light, green light, and blue light can be obtained, enabling the electronic device 200 to display color images.

[0087] In other examples, when substrate 100 is used to emit blue light, the opposing substrate 214 may include a color conversion film. For example, the color conversion film may be a quantum dot film. Blue light irradiated by a red quantum dot film can be converted into red light. Blue light irradiated by a green quantum dot film can be converted into green light. The resulting red and green light from the quantum dot film, mixed with the blue light emitted by substrate 100, enables the electronic device 200 to achieve full-color graphic display.

[0088] In some examples, the display panel 210 includes a common electrode and a plurality of pixel electrodes. An electric field can be formed between the common electrode and each pixel electrode. By controlling the voltage value of each pixel electrode, the strength of the electric field formed between the common electrode and each pixel electrode can be controlled, thereby controlling the deflection angle of the liquid crystal molecules in the liquid crystal layer 212, that is, controlling the intensity of light passing through the liquid crystal layer 212.

[0089] In some examples, pixel electrodes may be disposed on array substrate 216. Common electrodes may be disposed on array substrate 216 or opposing substrate 214.

[0090] Figure 2A This is a structural diagram of a substrate according to some embodiments. Figure 2B This is a structural diagram of a substrate according to some other embodiments. Figure 2C This is a structural diagram of a device group according to some embodiments. Figure 2D This is a structural diagram of a driver chip and device group according to some embodiments. Figure 2E This is a structural diagram of a driver chip and device group according to some other embodiments. Figure 2F This is a structural diagram of a substrate according to some other embodiments. Figure 2G This is a structural diagram of a substrate according to some other embodiments. Referring below... Figures 2A to 2G An example of substrate 100 will be given.

[0091] In some embodiments, such as Figure 2A and Figure 2B As shown, the substrate 100 has multiple edges P. Understandably, the edges P of the substrate 100 can be straight segments or curved segments. In some examples, such as... Figure 2A and Figure 2B As shown, the substrate 100 can be square or rectangular, that is, the substrate 100 can have four edges P.

[0092] In other examples, the substrate 100 may also be polygonal or other irregular shapes. The embodiments of this disclosure do not further limit the shape of the substrate 100 or the number of edges P that the substrate 100 has.

[0093] like Figure 2A and Figure 2B As shown, the substrate 100 includes a device region AA and at least one bonding region BB, with the bonding region BB being close to any edge P of the substrate 100 relative to the device region AA.

[0094] Understandably, the bonding region BB is adjacent to the edge of the device region AA near the bonding region BB. It should be noted that in the accompanying drawings of this disclosure, [the following text is incomplete and requires further context to translate accurately]. Figure 2A and Figure 2B For example, the edge of the device area AA and the edge of the bonding area BB are set apart from each other in the dashed box, just to clearly distinguish the device area AA and the bonding area BB, without further limiting the edge positions of the device area AA and the bonding area BB.

[0095] The bonding region BB is located relative to any edge P of the device region AA near the substrate 100. That is, the bonding region BB can be located between the device region AA and any edge P.

[0096] In some examples, the bonding region BB is located on one side of the device region AA along the second direction Y. For example, the second direction Y can be vertical.

[0097] In some examples, such as Figure 2A As shown, the number of bound zones (BBs) can be one. In other examples, such as... Figure 2B As shown, the number of bound areas (BBs) can also be multiple. For example, there can be two, three, or four bound areas (BBs).

[0098] Understandably, such as Figure 2B As shown, when there are multiple bonding areas BB, the multiple bonding areas BB are located on the same side of the device area AA, that is, the multiple bonding areas BB are all set on the same edge P.

[0099] In some examples, such as Figure 2B As shown, multiple binding areas BB can be spaced apart along a first direction X. For example, the first direction X can be horizontal, and it can be perpendicular to the second direction Y. Understandably, the multiple binding areas BB can be spaced at the same distance, or the spacing between any two adjacent binding areas BB can be different.

[0100] like Figure 2A and Figure 2B As shown, the substrate 100 includes a substrate 101 and a plurality of device groups 110. The plurality of device groups 110 are located on one side of the substrate 101 and are located in device region AA. The plurality of device groups 110 are arranged along a first direction X and a second direction Y, respectively, the first direction X and the second direction Y intersecting each other and being parallel to the substrate 101. Each device group 110 includes at least one electronic component 120.

[0101] In some examples, substrate 101 is a rigid substrate. In other examples, substrate 101 is a flexible substrate. For example, the material of substrate 101 includes any one of plastic, FR-4 grade material, resin, glass, quartz, polyimide (PI), or polymethyl methacrylate (PMMA).

[0102] Understandably, multiple device groups 110 are located on the same side of substrate 101 and within device region AA. In some examples, the multiple device groups 110 are spaced apart along a first direction X, and the spacing between adjacent device groups 110 is the same or approximately the same along the first direction X. The multiple device groups 110 are spaced apart along a second direction Y, and the spacing between adjacent device groups 110 is the same or approximately the same along the second direction Y. Thus, as... Figure 2A and Figure 2B As shown, multiple device groups 110 can be arranged in rows along the first direction X and in columns along the second direction Y. Understandably, the multiple rows of device groups 110 are spaced apart along the second direction Y, and the multiple columns of device groups 110 are spaced apart along the first direction X.

[0103] It should be noted that, in order to clearly show the structure of the substrate 100 in the accompanying drawings of this disclosure, only the four-row, three-column device group 110 is shown (e.g., Figure 2A ), or it shows a four-row, six-column device group 110 (e.g. Figure 2B The present disclosure does not impose further limitations on the number and arrangement of device groups 110 in the embodiments thereof.

[0104] Understandably, a device group 110 may include one electronic component 120 or multiple electronic components 120.

[0105] In some examples, when a device group 110 includes multiple electronic components 120, the multiple electronic components 120 can be components of the same type or components of different types. For example, when the substrate 100 is used to emit light, the electronic components 120 can be light-emitting devices. The multiple light-emitting devices included in a device group 110 can be used to emit light of the same color, or the multiple light-emitting devices included in a device group 110 can be used to emit light of multiple different colors. Alternatively, among the multiple electronic components 120 included in a device group 110, some (one or more) are light-emitting devices for emitting light, while other parts (one or more) are other components (e.g., sensor chips, etc.) to perform other functions.

[0106] In some examples, such as Figure 2A and Figure 2B As shown, a device group 110 may include six electronic components 120. In other examples, such as Figure 2CAs shown, a device group 110 may also include four electronic components 120. In other examples, a device group 110 may also include two, three, or five electronic components 120. Understandably, the number of electronic components 120 included in different device groups 110 may be the same or different. The embodiments of this disclosure do not further limit the number of electronic components 120 in a device group 110.

[0107] In some examples, such as Figure 2A and Figure 2B As shown, when a device group 110 includes multiple electronic components 120, the multiple electronic components 120 can be arranged in a matrix form. That is, the multiple electronic components 120 can be arranged at the four vertices of a rectangle or square, which improves the regularity of the arrangement of the multiple electronic components 120.

[0108] In other examples, when a device group 110 includes multiple electronic components 120, the multiple electronic components 120 in a device group 110 can also be arranged at the vertices of a hexagon, octagon, or other irregular shapes. Alternatively, the multiple electronic components 120 in a device group 110 can also be arranged in a circle or ellipse, etc., to meet different usage requirements.

[0109] In some examples, such as Figure 2C As shown, multiple electronic components 120 in the device group 110 are electrically connected through connecting lines 112.

[0110] For example, multiple electronic components 120 in a device group 110 can be connected in series via connecting lines 112. In this way, providing an electrical signal to any electronic component 120 in a device group 110 can provide electrical signals to all electronic components 120 in the device group 110, improving the wiring convenience of the substrate 100.

[0111] As described above, in some examples, substrate 100 can be used to provide a light source. In this case, electronic component 120 can be a light-emitting device. For example, electronic component 120 can be a light-emitting diode (LED).

[0112] In some examples, electronic component 120 can be any of a conventional LED, a mini LED, or a micro LED.

[0113] For example, a conventional LED is an LED with a size greater than or equal to 500 μm. A Mini LED is an LED with a size greater than or equal to 100 μm and less than 500 μm. A Micro LED is an LED with a size less than 100 μm. In some examples, the size of a Micro LED can be less than or equal to 50 μm.

[0114] In some examples, the electronic components 120 in each device group 110 can be used to emit light of the same color, for example, the electronic components 120 in each device group 110 can all be used to emit white light, or the electronic components 120 in each device group 110 can all be used to emit blue light, so that the substrate 100 can emit light of a specific color.

[0115] In some examples, the luminous intensity of each electronic component 120 in a device group 110 is the same. The luminous intensity of the electronic components 120 in different device groups 110 can be the same or different. By controlling the luminous intensity of the electronic components 120 in different device groups 110, the brightness of different areas of the substrate 100 can be controlled to meet different application requirements.

[0116] As described above, in some embodiments, the electronic device 200 includes a substrate 100 and a display panel 210, in which case the substrate 100 can be used to provide a light source. In other embodiments, the electronic device 200 may not include the display panel 210, but only the substrate 100. In this case, the substrate 100 is used to display image information, and the electronic components 120 in each device group 110 can emit light of different colors.

[0117] For example, when the substrate 100 is used to display image information, some (one or more) of the various device groups 110 emit red light, another group of device groups 110 emits green light, and yet another group of device groups 110 emits blue light. By controlling the light emission intensity of the electronic components 120 in different device groups 110, different intensities of red, green, and blue light can be obtained, enabling the electronic device 200 to achieve full-color image display.

[0118] The embodiments disclosed herein are illustrated by taking as an example that the substrate 100 uses glass as the substrate 101, uses Mini LED as the electronic component 120, and the substrate 100 serves as the light source providing component of the electronic device 200.

[0119] In some examples, such as Figure 2A and Figure 2BAs shown, the substrate 100 also includes a plurality of signal line groups 130. The plurality of signal line groups 130 and the plurality of device groups 110 are located on the same side of the substrate 101. Each signal line group 130 includes a plurality of signal lines 131. The plurality of signal lines 131 extend along a second direction Y, and are spaced apart along a first direction X. Any signal line 131 extends from the bonding region BB to the device region AA, and any signal line 131 is electrically connected to a row of device groups 110 arranged along the second direction Y.

[0120] It is understandable that the lengths of the multiple signal lines 131 are not exactly the same. The length of some signal lines along the second direction Y is approximately equal to the length of a group of devices along the second direction Y, while the length of other signal lines along the second direction Y is less than the length of a group of devices along the second direction Y.

[0121] Understandably, multiple signal line groups 130 and multiple device groups 110 are located on the same side of substrate 101, such that signal lines 131 in signal line group 130 can be electrically connected to device group 110.

[0122] In some examples, multiple signal line groups 130 are arranged on the same layer, that is, multiple signal line groups 130 are arranged on the same conductive layer. Understandably, in addition to multiple signal line groups 130, other traces can also be arranged on the conductive layer.

[0123] In other examples, the signal lines 131 in the multiple signal line groups 130 can be disposed on different conductive layers. For example, the signal lines 131 in the multiple signal line groups 130 can be disposed on two conductive layers respectively.

[0124] Understandably, multiple signal line groups 130 are disposed on different conductive layers, which increases the routing flexibility of the signal lines 131. However, if the orthographic projections of two signal lines 131 located on different conductive layers overlap on the substrate 101, a short circuit is likely to occur, affecting the yield of the substrate 100. Furthermore, since the substrate 100 includes at least two conductive layers, it also increases the number of fabrication steps for the substrate 100, thereby increasing the production cost of the substrate 100.

[0125] Understandably, the arrangement of multiple signal line groups 130 on the same layer can reduce the steps of patterning conductive layers, thereby simplifying the fabrication process of substrate 100, reducing the number of masks, lowering the cost of substrate 100, and also reducing the occurrence of defects such as short circuits in substrate 100, thus improving the yield of substrate 100.

[0126] The embodiments of this disclosure are illustrated by taking the arrangement of multiple signal line groups 130 on the same layer as an example.

[0127] In some examples, substrate 100 includes an insulating layer located on the side of the conductive layer away from substrate 101 and covering the conductive layer. That is, the insulating layer can cover a plurality of signal line groups 130 disposed on the conductive layer and other conductive structures disposed on the conductive layer.

[0128] A signal line group 130 includes multiple signal lines 131, which are understood to be used to transmit signals, such as analog or digital electrical signals. In some examples, multiple signal line groups 130 can be used to transmit different signals or the same signal. Each signal line 131 in a signal line group 130 is used to transmit the same signal.

[0129] In some examples, signal line 131 is made of metal or a metal alloy. For example, the material of signal line 131 may include copper or aluminum to improve the conductivity of signal line 131.

[0130] In some examples, the number of signal lines 131 included in each signal line group 130 may be the same or different. The spacing between any two adjacent signal lines 131 in a signal line group 130 along the first direction X may be the same or different.

[0131] In some examples, the bonding area BB is provided with bonding pins (not shown in the figure). There can be multiple bonding pins, which are spaced apart along the first direction X. The signal line 131 is electrically connected to the bonding pins in the bonding area BB.

[0132] For example, such as Figure 2A and Figure 2B As shown, one end of any signal line 131 is electrically connected to a bonding pin in the bonding area BB, and the other end extends along the second direction Y (or along the first direction X and the second direction Y) to extend from the bonding area BB to the device area AA, and is electrically connected to a column of device groups 110 arranged along the second direction Y. It can be understood that the signal line 131 can be directly electrically connected to the electronic components 120 in the device group 110, or it can be electrically connected to the electronic components 120 in the device group 110 through other components or conductive patterns.

[0133] In some examples, at least one signal line 131 is disposed between two rows of device groups 110 spaced apart along a first direction X to improve the area utilization of the substrate 101.

[0134] In some examples, such as Figure 2AAs shown, there is one bonding area BB, and multiple bonding pins are provided within one bonding area BB. For example, different signal line groups 130 are electrically connected to different bonding pins to reduce mutual interference during signal transmission. Multiple signal lines 131 in the same signal line group 130 can be electrically connected to one bonding pin or multiple bonding pins.

[0135] In some examples, when there is one bonding area BB, the number of signal lines 131 in a signal line group 130 is the same as the number of columns formed by the device group 110. That is, as... Figure 2A As shown, when multiple device groups 110 are arranged in three columns along the second direction Y, a signal line group 130 includes three signal lines 131. Understandably, the three signal lines 131 in a signal line group 130 can be electrically connected to three bonded pins or to one bonded pin.

[0136] In other examples, such as Figure 2B As shown, there are multiple binding areas BB. Multiple signal lines 131 in a signal line group 130 are electrically connected to one of the multiple binding areas BB.

[0137] For example, such as Figure 2B As shown, signal line group 130 includes a first signal line group 130a, a second signal line group 130b, and a third signal line group 130c. The first signal line group 130a includes a first signal line 131a, the second signal line group 130b includes a second signal line 131b, and the third signal line group 130c includes a third signal line 131c.

[0138] It should be noted that the first signal line group 130a, the second signal line group 130b, and the third signal line group 130c are only used to distinguish the three signal line groups 130 that are connected to different bonding areas BB respectively, and do not further limit the signal line groups 130. The first signal line 131a, the second signal line 131b, and the third signal line group 130c are only used to distinguish the signal line 131 in the first signal line group 130a, the second signal line group 130b, and the third signal line group 130c, and do not further limit the signal line 131.

[0139] In some examples, the first signal line group 130a, the second signal line group 130b, and the third signal line group 130c are used to transmit the same signal.

[0140] For example, such as Figure 2B As shown, the binding area BB includes the first binding area BB1, the second binding area BB2, and the third binding area BB3. It should be noted that the first binding area BB1, the second binding area BB2, and the third binding area BB3 are only used to distinguish three different binding areas BB, and do not further limit the binding areas BB.

[0141] For example, such as Figure 2B As shown, multiple first signal lines 131a in the first signal line group 130a are electrically connected to the bonding pins in the first bonding area BB1. Multiple second signal lines 131b in the second signal line group 130b are electrically connected to the bonding pins in the second bonding area BB2. A third signal line 131c in the third signal line group 130c is electrically connected to the bonding pins in the third bonding area BB3. In this way, multiple signal lines 131a in one signal line group 130 can be electrically connected to one of the multiple bonding areas BB.

[0142] This configuration allows different bonding areas BB to transmit signals to different signal line groups 130, reducing mutual interference during signal transmission and improving the reliability of the substrate 100.

[0143] In some examples, such as Figure 2B As shown, a signal line 131 (e.g., first signal line 131a) in a signal line group 130 (e.g., first signal line group 130a) is electrically connected to a bonding pin in a bonding area BB (e.g., first bonding area BB1) near the signal line group 130. This reduces the length of the signal line 131, lowers the voltage drop of the signal line 131, and improves the reliability of signal transmission. Furthermore, it also reduces the amount of material used in the signal line 131, thereby reducing the cost of the substrate 100.

[0144] In some examples, such as Figure 2A As shown, the substrate 100 also includes a first driver chip 103. The first driver chip 103 is electrically connected to at least one device group 110. That is, in some examples, such as Figure 2D As shown, the first driver chip 103 is electrically connected to only one device group 110. In other examples, such as Figure 2E As shown, the first driving chip 103 is electrically connected to four device groups 110 arranged sequentially along the second direction Y.

[0145] Understandably, a signal line 131 may be electrically connected to the first driver chip 103, or to a device group 110 or multiple device groups 110.

[0146] In some examples, a plurality of device groups 110 arranged along the second direction Y are electrically connected to a first driver chip 103. In other examples, the plurality of device groups 110 arranged along the second direction Y are electrically connected to a plurality of first driver chips 103 respectively. For example, when the plurality of device groups 110 arranged along the second direction Y are electrically connected to a plurality of first driver chips 103 respectively, the plurality of first driver chips 103 electrically connected to a row of device groups 110 are spaced apart along the second direction Y.

[0147] In some examples, such as Figure 2F and Figure 2G As shown, the device area AA includes a central area AA1 and an edge area AA2, with the edge area AA2 surrounding the central area AA1. Multiple device groups 110 are located in the central area AA1. A portion (one or more) of the signal lines 131 may be located only in the edge area AA2, while another portion (one or more) of the signal lines 131 may be located in both the edge area AA2 and the central area AA1. It is understood that this is done to clearly illustrate the positional relationship of a signal line group and the bridging portion. Figure 2F and 2G The Chinese version omits some components and other signal lines on the substrate.

[0148] like Figure 2G As shown, the edge region AA2 located between the central region AA1 and the binding region BB along the second direction Y can be defined as the lower edge region AA22; the two edge regions adjacent to the lower edge region AA22 along the second direction Y and located on both sides of the central region AA along the first direction X can be defined as the side edge regions AA21. That is, edge region AA2 includes the side edge region AA21 and the lower edge region AA22. For example, the lower edge region AA22 can also be called the fanout region.

[0149] For example, such as Figure 2F and Figure 2G As shown, multiple signal lines 131 extend along the second direction Y (or along the first direction X and the second direction Y) through the bonding area BB to the lower edge area AA22. A portion (one or more, e.g.) Figure 2F The fifth signal line 131e shown extends from the lower edge region AA22 to the side edge region AA21 and is electrically connected to a group of devices 110. That is, the fifth signal line 131e is located within the edge region AA2. Another portion (one or more, for example...) Figure 2F The fourth signal line 131d shown in the figure extends from the lower edge region AA22 to the device region AA and is electrically connected to a group of devices 110.

[0150] It should be noted that in the embodiments of this disclosure, the fourth signal line 131d and the fifth signal line 131e are only used to distinguish between the signal line 131 located in the device area AA and electrically connected to the device group 110, and the signal line 131 located in the side edge area AA21 and electrically connected to the device group 110, and do not further limit the signal line 131.

[0151] Since the length of the signal line 131 extending along the second direction Y is related to the length of the substrate 100 along the second direction Y, in some implementations, in order to minimize the voltage drop (IR drop) of the signal line 131, the resistance of the signal line 131 can be reduced by increasing the width of the signal line 131 along the first direction X or by increasing the thickness of the signal line 131.

[0152] For example, taking a 55-inch substrate 100 as an example, the width of the side edge region AA21 along the first direction X is approximately 4.125 mm, and the width of the lower edge region AA22 along the second direction Y is approximately 4.62 mm. In order to ensure that the voltage drop of the signal line 131 meets the requirements, the width of some (one or more) signal lines 131 along the first direction X needs to be set between 2 mm and 15 mm.

[0153] For example, such as Figure 2F As shown, the width of the fifth signal line 131e along the first direction X needs to be greater than 3mm (e.g., greater than 3.5mm). Furthermore, in addition to the fifth signal line 131e, other signal lines 131 are typically provided within the side edge region AA21. That is, increasing the width of the signal lines 131 along the first direction X to reduce voltage drop increases the wiring difficulty within the side edge region AA21 and also increases the width of the side edge region AA21 along the first direction X, which is detrimental to achieving a narrow bezel on the substrate 100.

[0154] On the other hand, increasing the thickness of the signal line 131 to reduce the voltage drop will increase the amount of material used in the signal line 131 and increase the manufacturing cost of the substrate 100.

[0155] Figure 3A This is a structural diagram of a substrate according to some other embodiments. Figure 3B This is a structural diagram of a substrate according to some other embodiments. Figure 3C This is a structural diagram of a substrate according to some other embodiments. Figure 3D This is a structural diagram of a substrate according to some other embodiments. Figure 3E This is a structural diagram of a substrate according to some other embodiments. Figure 3F This is a structural diagram of a substrate according to some other embodiments.

[0156] Based on this, such as Figures 3A to 3F As shown, in the embodiments of this disclosure, the substrate 100 includes a substrate 101, a plurality of device groups 110, and a plurality of signal line groups 130, as well as a plurality of conductive patterns 170. It is understood that the above embodiments of this disclosure have already provided examples of the substrate 101, the plurality of device groups 110, and the plurality of signal line groups 130, and will not be repeated here. Refer to the following... Figures 3A to 3F Examples of multiple conductive patterns 170 are given below.

[0157] In some examples, such as Figure 3A and Figure 3B As shown, multiple conductive patterns 170 and multiple device groups 110 are located on the same side of substrate 101. At least one of the multiple conductive patterns 170 is located within the region of one device group 110, and / or, at least one of the multiple conductive patterns 170 is located within the region between two adjacent device groups 110. At least one signal line 131 of at least one signal line group 130 is electrically connected to one conductive pattern 170.

[0158] It is understood that device group 110 includes multiple electronic components 120, and the region where device group 110 is located refers to the closed virtual region formed by connecting the boundaries of the outermost electronic components 120 of the device group in a clockwise or counterclockwise direction. In some examples, when the multiple electronic components 120 in device group 110 are arranged in a matrix, the region where a device group 110 is located is rectangular, and all the multiple electronic components 120 in the device group 110 are located within this rectangular region.

[0159] In other examples, when a device group 110 includes only one electronic element 120, the area where a device group 110 is located is the rectangular area surrounding the electronic element 120.

[0160] Understandably, the conductive pattern 170 is capable of conducting electricity. In some examples, the material of the conductive pattern 170 includes copper or aluminum to improve its conductivity. For example, the conductive pattern 170 can be a rectangle, a convex polygon, or other irregular shape. The shapes of the various conductive patterns 170 can be the same or different.

[0161] Multiple conductive patterns 170 and multiple device groups 110 are located on the same side of the substrate 101. As mentioned above, multiple signal line groups 130 are also located on the same side of the substrate 101 as the multiple device groups 110. That is, the multiple conductive patterns 170, the multiple signal line groups 130, and the multiple device groups 110 are all located on the same side of the substrate 101. In this way, the conductive patterns 170 can be electrically connected to the signal lines 131.

[0162] In some examples, multiple conductive patterns 170 and multiple signal line groups 130 can be disposed on the same layer to simplify the fabrication process of the substrate 100 and reduce the production cost of the substrate 100. In other examples, multiple conductive patterns 170 and multiple signal line groups 130 can also be disposed on different layers to reduce mutual interference between them.

[0163] In some examples, multiple conductive patterns 170 are located in the device region AA. In other examples, multiple conductive patterns 170 are located in both the device region AA and the bonding region BB.

[0164] In some examples, such as Figure 3A and Figure 3B As shown, at least one of the multiple conductive patterns 170 is located in the area where a device group 110 is located.

[0165] In some examples, such as Figure 3A and Figure 3B As shown, at least one of the plurality of conductive patterns 170 may also be located in the region between two adjacent device groups 110. For example, at least one conductive pattern 170 may be located in the region between two adjacent device groups 110 along the second direction Y, and at least one conductive pattern 170 may also be located in the region between two adjacent device groups 110 along the first direction X.

[0166] Understandably, such as Figure 3A and Figure 3B As shown, any conductive pattern 170 can avoid electronic components 120, connecting lines 112 that electrically connect two adjacent electronic components 120, and multiple signal line groups 130. That is, the orthographic projection of the conductive pattern 170 on the substrate 101 is outside the range of the orthographic projections of the electronic components 120 on the substrate 101, the connecting lines 112 on the substrate 101, and the multiple signal line groups 130 on the substrate 101. This arrangement can reduce the mutual interference between the conductive pattern 170 and the device group 110 and the signal line group 130, and improve the reliability of the substrate 100.

[0167] Understandably, since at least one conductive pattern 170 is located in the area where a device group 110 is located, and / or, at least one conductive pattern 170 is located in the area between two adjacent device groups 110, at least one signal line 131 in at least one signal line group 130 can be electrically connected to a conductive pattern 170.

[0168] In some examples, such as Figure 3C As shown, each signal line 131 in each signal line group 130 is electrically connected to the conductive pattern 170. In some other examples, one signal line 131 in each signal line group 130 is electrically connected to the conductive pattern 170. In still other examples, one signal line 131 in one signal line group 130 is electrically connected to the conductive pattern 170. It is understood that the conductive pattern 170 and the signal line 131 can be directly electrically connected, or they can be electrically connected through other components or traces.

[0169] In some examples, such as Figure 3A and Figure 3B As shown, at least two signal lines 131 in the same signal line group 130 can be electrically connected to the same conductive pattern 170. Understandably, signal lines 131 in different signal line groups 130 can be electrically connected to different conductive patterns 170.

[0170] Understandably, since the conductive pattern 170 is conductive, at least one signal line 131 in at least one signal line group 130 is electrically connected to a conductive pattern 170, so that the conductive pattern 170 can compensate for the voltage drop of the signal line 131. That is, by electrically connecting the conductive pattern 170 to the signal line 131, the resistance of the signal transmission path (i.e., the electrically connected signal line 131 and conductive pattern 170) is reduced, thus reducing the voltage drop of the signal line 131. This reduces signal loss during transmission, improves signal transmission reliability, and increases the luminous efficiency of the electronic component 120.

[0171] Understandably, since the voltage drop of the signal line 131 can be reduced after the conductive pattern 170 is electrically connected to the signal line 131, even if the width of the signal line 131 along the first direction X is small, or the thickness of the signal line 131 is small, the voltage drop of the signal line 131 can still meet the requirements through the compensation effect of the conductive pattern 170.

[0172] In other words, by setting the conductive pattern 170 to be electrically connected to the signal line 131, on the one hand, it is beneficial to reduce the width of the signal line 131 along the first direction X, thereby reducing the space occupied by the signal line 131 on the substrate 101 and improving the wiring convenience of the substrate 100. On the other hand, it is also beneficial to reduce the thickness of the signal line 131, thereby reducing the amount of material used for the signal line 131 and reducing the cost of the substrate 100.

[0173] In addition, such as Figure 3C As shown, when the signal line 131 (e.g., the fifth signal line 131e) located in the side edge region AA21 is electrically connected to the conductive pattern 170, the width of the signal line 131 along the first direction X is reduced, which can also reduce the space occupied by the signal line 131 in the side edge region AA21, thereby reducing the width of the side edge region AA21 and facilitating the realization of a narrow bezel (side bezel) of the substrate 100.

[0174] Furthermore, when the signal line 131 (e.g., the fifth signal line 131e) located in the side edge region AA21 is electrically connected to the conductive pattern 170, the voltage drop of the signal line 131 in the side edge region AA21 can be reduced, thereby improving the electrical performance of the signal line 131 located in the side edge region AA21.

[0175] Understandably, when the area of ​​substrate 101 is fixed, the narrower the border of substrate 100, the more device groups 110 can be arranged. When the electronic components 120 included in the device group 110 are light-emitting elements, the overall brightness of substrate 100 is greater, which can improve the performance of substrate 100.

[0176] Furthermore, since the conductive pattern 170 can avoid the device group 110 and signal line group 130, the conductive pattern 170 will not affect the function of the substrate 100, thus improving the reliability of the substrate 100.

[0177] As described above, the multiple electronic components 120 in the device group 110 are electrically connected via connecting lines 112. In some examples, such as Figure 3C As shown, multiple connection lines 112 in a device group 110 are spaced apart. Electronic component 120 includes two pins, one pin soldered to one end of a connection line 112, and the other pin soldered to one end of another connection line 112, thus, as... Figure 2F As shown, this ensures that after electronic component 120 is soldered to connecting line 112, it can be located within region Q (see the diagram showing the positional relationship between electronic component 120 and connecting line 112 after soldering). Figure 3A and Figure 3B ).

[0178] Understandably, except for the area of ​​the connecting line 112 that is exposed by the insulating layer when it connects to the pin, the other areas are covered by the insulating layer.

[0179] In some embodiments, a plurality of conductive patterns 170 are disposed on the same layer as a plurality of signal line groups 130.

[0180] Understandably, "same layer" refers to forming a whole layer structure using a single film deposition process, and then using a patterning process to form specific patterns in different areas. Depending on the specific pattern, the patterning process may include at least one exposure, development, or etching process, and the individual specific patterns may be continuous or discontinuous, and these specific patterns may also have different heights or different thicknesses.

[0181] In some examples, multiple conductive patterns 170 and multiple signal line groups 130 can be on the same layer and made of the same material, which simplifies the fabrication process of the substrate 100 and reduces production costs.

[0182] The following example illustrates the preparation method of substrate 100.

[0183] In some examples, the substrate 101 is made of glass. For example, a buffer layer can be formed on one side of the substrate 101 using a magnetron sputtering process. For example, the buffer layer can be made of at least one of tungsten, titanium, nickel, aluminum, nickel alloys, and titanium-tungsten alloys.

[0184] A conductive layer is formed on the side of the buffer layer away from the substrate 101. For example, the material of the conductive layer includes copper. In some examples, a magnetron sputtering process can be used to form the conductive layer on the side of the buffer layer away from the substrate 101. In other examples, an electroplating process can also be used to form the conductive layer on the side of the buffer layer away from the substrate 101. In still other examples, both magnetron sputtering and electroplating processes can be used to form the conductive layer on the side of the buffer layer away from the substrate 101.

[0185] The conductive layer is patterned through processes such as cleaning, coating, baking, imaging, developing, hard baking, etching, and stripping to form multiple signal line groups 130 and multiple conductive patterns 170.

[0186] An insulating layer is formed on the side of the patterned conductive layer away from the substrate 101. The insulating layer covers the conductive layer to provide electrical isolation. For example, the insulating layer can be formed using magnetron sputtering, chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0187] Understandably, the co-layer arrangement of multiple conductive patterns 170 and multiple signal line groups 130 simplifies the process steps when patterning the conductive layer, reduces the number of masks, lowers the BOM (Bill of Material) cost, and thus reduces the production cost of the substrate 100.

[0188] On the other hand, the co-layer arrangement of multiple conductive patterns 170 and multiple signal line groups 130 can increase the area of ​​the orthogonal projection of the conductive structures (e.g., signal line groups 130 and conductive patterns 170) on the conductive layer onto the substrate 101.

[0189] For example, when the conductive pattern 170 is not provided, the area of ​​the orthographic projection of the conductive structure (multiple signal line groups 130) on the conductive layer onto the substrate 101 is approximately 20% of the area of ​​the substrate 101. However, after the conductive pattern 170 is provided, the area of ​​the orthographic projection of the conductive structure (multiple signal line groups 130 and multiple conductive patterns 170) on the conductive layer onto the substrate 101 is approximately 75% of the area of ​​the substrate 101.

[0190] In other words, taking Cu as the material of the conductive layer as an example, multiple conductive patterns 170 and multiple signal line groups 130 are arranged in the same layer, which can increase the ratio of the area of ​​Cu in the conductive layer to the area of ​​the substrate 101 from about 20% to about 75%, thereby increasing the area of ​​Cu in the conductive layer, reducing the amount of etching solution used in the etching process, and reducing the cost of the substrate 100.

[0191] In some embodiments, such as Figure 3A and Figure 3B As shown, the substrate 100 also includes a plurality of bridging portions 140. The plurality of bridging portions 140 are located on the same side of the substrate 101 as the plurality of device groups 110, and at least one bridging portion 140 is located in the device region AA.

[0192] Understandably, the bridging portion 140 serves to conduct electricity. In some examples, the bridging portion 140 is made of a conductive material, such as copper or aluminum. In other examples, the bridging portion 140 may also be an electrical component, such as a resistor or capacitor. Understandably, multiple bridging portions 140 may be the same or different.

[0193] Understandably, the multiple bridging portions 140 and the multiple device groups 110 are located on the same side of the substrate 101. That is, the multiple bridging portions 140, the multiple device groups 110, the multiple conductive patterns 170 and the multiple signal line groups 130 are all located on the same side of the substrate 101.

[0194] Understandably, at least one bridging portion 140 is located in device region AA such that at least one bridging portion 140 is electrically connected to conductive pattern 170, and / or such that at least one bridging portion 140 is electrically connected to signal line 131.

[0195] As described above, multiple conductive patterns 170 and multiple signal line groups 130 are disposed on the same layer. In some examples, multiple bridging portions 140 are located on the side of the multiple conductive patterns 170 and multiple signal line groups 130 away from the substrate 101, thereby avoiding the bridging portions 140 from affecting the signal lines 131 and conductive patterns 170.

[0196] In some examples, a protective layer is provided on the side of the plurality of bridging portions 140 away from the substrate 101. The protective layer can cover the plurality of bridging portions 140 to provide electrical isolation and also to protect the plurality of bridging portions 140.

[0197] In some embodiments, such as Figure 3A and Figure 3B As shown, the multiple signal line groups 130 include a first voltage line group 150, and the first voltage line group 150 includes a multiple first voltage lines 151.

[0198] In some examples, the first voltage line 151 is used to power the electronic components 120 in the various device groups 110. Examples include... Figure 3A and Figure 3B As shown, one end of the first voltage line 151 is electrically connected to the bonding pin in the bonding area BB, and the other end extends to the device area AA and is electrically connected to a column of devices 110 arranged along the second direction Y. That is, the column of devices 110 arranged along the second direction Y shares a first voltage line 151.

[0199] In some examples, such as Figure 3A and Figure 3B As shown, a first voltage line 151 in the first voltage line group 150 may be located in the side edge region AA21, such that the first voltage line 151 can be electrically connected to a column of devices 110 adjacent to the side edge region AA21 along the first direction X.

[0200] In some examples, such as Figure 3D As shown, the substrate 100 also includes a circuit board 107, which is electrically connected to the bonding area BB.

[0201] For example, such as Figure 3D As shown, circuit board 107 includes a flexible printed circuit board (FPC) 105 and a printed circuit board (PCB) 106. One end of the flexible printed circuit board 105 is bonded to a bonding pin in the bonding area BB, and the other end is bonded to the printed circuit board 106, so that signals can be transmitted between multiple signal line groups 130 and the printed circuit board 106, thereby realizing the driving of multiple device groups 110.

[0202] In some examples, an external power supply to the substrate 100 is electrically connected to a first voltage line 151 via a printed circuit board 106 and bonding pins, enabling the power supply to power electronic components 120 in a group of devices 110 via the first voltage line 151, thereby enabling the electronic components 120 to emit light.

[0203] In some examples, such as Figure 3A and Figure 3B As shown, the multiple signal line groups 130 also include a second voltage line group 160, which includes multiple second voltage lines 161.

[0204] In some examples, the second voltage line (GND) 161 is used to ground the first driver chip 103. For example, ... Figure 3A and Figure 3B As shown, one end of the second voltage line 161 is electrically connected to the bonding pin in the bonding area BB, and the other end extends to the device area AA and is electrically connected to the first driver chip 103. As can be seen from the above, the first driver chip 103 is electrically connected to the device group 110, so that the second voltage line 161 can be electrically connected to the device group 110 through the first driver chip 103.

[0205] In some examples, such as Figure 3A and Figure 3B As shown, a second voltage line 161 in the second voltage line group 160 can be located in the side edge region AA21, so that the second voltage line 161 can be electrically connected to a row of device groups 110 adjacent to the side edge region AA21 along the first direction X.

[0206] In some examples, such as Figure 3E As shown, the first driver chip 103 includes a first output port CH1, a second output port CH2, a third output port CH3, and a fourth output port CH4. The first output port CH1, the second output port CH2, the third output port CH3, and the fourth output port CH4 are electrically connected to four device groups 110, respectively, so that one first driver chip 103 can be electrically connected to four device groups 110.

[0207] In some examples, such as Figure 3D and Figure 3E As shown, the substrate 100 also includes a second driver chip 104. For example, the second driver chip 104 may be disposed on a printed circuit board 106.

[0208] In some examples, the second driver chip 104 is a Tx IC (Transmit Integrated Circuit), and the first driver chip 103 is an Rx IC (Receive Integrated Circuit). The signal emitted by the second driver chip 104 is transmitted to the first driver chip 103 through the bonding pins and signal line group 130 (e.g., the second voltage line group 160), thereby driving the device group 110.

[0209] In some examples, such as Figure 3E As shown, the second driver chip 104 has a first ground port GND1 and a second ground port GND2. The first driver chip 103 also has a first ground port GND1 and a second ground port GND2. The second voltage line 161 includes a first second voltage line 161a and a second voltage line 161b.

[0210] like Figure 3E As shown, one end of the first second voltage line 161a is electrically connected to the first ground port GND1 of the second driver chip 104 via the bonding pin of the bonding area BB. The other end of the first second voltage line 161a is electrically connected to the first ground port GND1 of the first driver chip 103. One end of the second second voltage line 161b is electrically connected to the second ground port GNDb of the second driver chip 104 via the bonding pin of the bonding area BB. The other end of the second second voltage line 161b is electrically connected to the second ground port GND2 of the first driver chip 103.

[0211] It should be noted that the first second voltage line 161a and the second second voltage line 161b are only used to distinguish the two second voltage lines 161, and do not further define the second voltage line 161.

[0212] In other examples, the first driver chip 103 may also include only a ground port. In this case, one end of a second voltage line 161 is electrically connected to the ground port of the second driver chip 104 through the bonding pin of the bonding area BB, and the other end is electrically connected to the ground port of the first driver chip 103 to ground the first driver chip 103.

[0213] In some examples, such as Figure 3E As shown, when a column of devices 110 arranged along the second direction Y is electrically connected to a plurality of first driving chips 103, the plurality of first driving chips 103 electrically connected to the same column of devices 110 can share a second voltage line 161.

[0214] like Figure 3A and Figure 3B As shown, the plurality of conductive patterns 170 include a plurality of first conductive patterns 171, and the plurality of first conductive patterns 171 are electrically connected to at least one first voltage line 151 in the first voltage line group 150.

[0215] In some examples, a first voltage line 151 in the first voltage line group 150 is electrically connected to the first conductive pattern 171. In other examples, multiple first voltage lines 151 in the first voltage line group 150 are electrically connected to the first conductive pattern 171.

[0216] In some examples, such as Figure 3A and Figure 3B As shown, at least two first voltage lines 151 are electrically connected to the same first conductive pattern 171.

[0217] As described above, the first voltage line 151 is used to provide a constant high-level signal to the electronic components 120 in each device group 110. Therefore, the width of the first voltage line 151 along the first direction X is usually relatively large. In this way, by electrically connecting the first conductive pattern 171 to at least one of the first voltage lines 151 in the first voltage line group 150, on the one hand, the reliability of the power supply signal transmission can be improved, thereby increasing the luminous efficiency of the electronic components 120. On the other hand, it is beneficial to reduce the width of the first voltage line 151 along the first direction X, thereby improving the wiring convenience of the substrate 100. Furthermore, it is also beneficial to reduce the thickness of the first voltage line 151, thereby reducing the material usage of the first voltage line 151 and lowering the cost of the substrate 100.

[0218] like Figure 3A and Figure 3B As shown, a first voltage line 151 in the first voltage line group 150 may be located in the side edge region AA21. For example, a first conductive pattern 171 may be electrically connected to the first voltage line 151 located in the side edge region AA21 to reduce the width of the first voltage line 151 in the first direction X within the side edge region AA21, thereby facilitating the reduction of the width of the side edge region AA21 in the first direction X and facilitating the realization of a narrow bezel (side bezel) of the substrate 100.

[0219] In some embodiments, the width of the first voltage line 151 along the first direction X ranges from 0.5 mm to 1 mm.

[0220] Understandably, when the conductive pattern 170 is not set, in order to meet the voltage drop requirements, the width of the first voltage line 151 along the first direction X ranges from 2mm to 15mm.

[0221] In the embodiments disclosed herein, the first conductive pattern 171 is electrically connected to the first voltage line 151, so that the first conductive pattern 171 can compensate for the voltage drop of the first voltage line 151, which helps to reduce the width of the first voltage line 151 along the first direction X, so that the value range of the width of the first voltage line 151 along the first direction X can be reduced to 0.5mm to 1mm, which helps to achieve a narrow border of the substrate 100.

[0222] Understandably, setting the width of the first voltage line 151 along the first direction X to a range of 0.5mm to 1mm avoids the width of the first voltage line 151 along the first direction X being too large (e.g., greater than 1mm), thereby facilitating the realization of a narrow bezel on the substrate 100. Furthermore, it also avoids the width of the first voltage line 151 along the first direction X being too small (e.g., less than 0.5mm), improving the transmission reliability of the constant voltage high-level signal.

[0223] In some examples, the width of the first voltage line 151 along the first direction X can be in the range of 0.6mm to 0.9mm or 0.7mm to 0.8mm, etc. For example, the width of the first voltage line 151 along the first direction X can be 0.6mm, 0.7mm, 0.8mm or 0.9mm, etc.

[0224] Understandably, the widths of the multiple first voltage lines 151 along the first direction X can be the same or different.

[0225] In some embodiments, such as Figure 3A and Figure 3B As shown, the plurality of conductive patterns 170 include a plurality of second conductive patterns 172, and the plurality of second conductive patterns 172 are electrically connected to at least one second voltage line 161 in the second voltage line group 160.

[0226] In some examples, one of the second voltage lines 161 in the second voltage line group 160 is electrically connected to the second conductive pattern 172. In other examples, multiple second voltage lines 161 in the second voltage line group 160 are electrically connected to the second conductive pattern 172.

[0227] In some examples, such as Figure 3A and Figure 3B As shown, at least two second voltage lines 161 are electrically connected to the same second conductive pattern 172.

[0228] As described above, the second voltage line 161 is used to ground the first driver chip 103; therefore, the width of the second voltage line 161 along the first direction X is typically large. By electrically connecting the second conductive pattern 172 to at least one of the second voltage lines 161 in the second voltage line group 160, the reliability of the power supply signal transmission can be improved. Furthermore, it is beneficial to reduce the width of the second voltage line 161 along the first direction X, thereby improving the wiring convenience of the substrate 100. Additionally, it is beneficial to reduce the thickness of the second voltage line 161, thereby reducing the material usage of the second voltage line 161 and lowering the cost of the substrate 100.

[0229] like Figure 3A and Figure 3BAs shown, a second voltage line 161 in the second voltage line group 160 may be located in the side edge region AA21. For example, the second conductive pattern 172 may be electrically connected to the second voltage line 161 located in the side edge region AA21 to reduce the width of the second voltage line 161 in the first direction X within the side edge region AA21, thereby facilitating the reduction of the width of the side edge region AA21 in the first direction X and facilitating the realization of a narrow bezel (side bezel) of the substrate 100.

[0230] In some embodiments, the width of the second voltage line 161 along the first direction X ranges from 0.5 mm to 1 mm.

[0231] Understandably, when the conductive pattern 170 is not set, in order to meet the voltage drop requirements, the width of the second voltage line 161 along the first direction X ranges from 2mm to 15mm.

[0232] In the embodiments disclosed herein, the second conductive pattern 172 is electrically connected to the second voltage line 161, so that the second conductive pattern 172 can compensate for the voltage drop of the second voltage line 161, which helps to reduce the width of the second voltage line 161 along the first direction X, so that the range of the width of the second voltage line 161 along the first direction X can be reduced to 0.5mm to 1mm, which helps to achieve a narrow border of the substrate 100.

[0233] Understandably, setting the width of the second voltage line 161 along the first direction X to a range of 0.5mm to 1mm avoids the second voltage line 161 being too wide along the first direction X (e.g., greater than 1mm), which is beneficial for achieving a narrow bezel on the substrate 100. Furthermore, it also avoids the second voltage line 161 being too narrow along the first direction X (e.g., less than 0.5mm), improving the reliability of electrical signal transmission.

[0234] In some examples, the width of the second voltage line 161 along the first direction X can be in the range of 0.6mm to 0.9mm or 0.7mm to 0.8mm, etc. For example, the width of the second voltage line 161 along the first direction X can be 0.6mm, 0.7mm, 0.8mm or 0.9mm, etc.

[0235] Understandably, the widths of the multiple second voltage lines 161 along the first direction X can be the same or different. The width of the first voltage line 151 along the first direction X can be the same as or different from the width of the second voltage lines 161 along the first direction X.

[0236] In some embodiments, such as Figure 3A and Figure 3B As shown, a first voltage line 151 electrically connected to a group of devices 110 and a second voltage line 161 electrically connected to the group of devices 110 are arranged at intervals along a first direction X.

[0237] In some examples, such as Figure 3A and Figure 3B As shown, a first voltage line 151 is located on one side of the central region AA1 along the first direction X, and a second voltage line 161 is located on the side of the central region AA1 away from the first voltage line 151 along the first direction X.

[0238] In some examples, such as Figure 3A and Figure 3B As shown, any first voltage line 151 is located along the first direction X on the first side of a group of devices 110 electrically connected to the first voltage line 151. It can be understood that the first side can be either side of the group of devices 110 along the first direction X.

[0239] In some examples, such as Figure 3A and Figure 3B As shown, a first voltage line 151 and a first driver chip 103, electrically connected to the same column of device group 110, are located on opposite sides of the column of device group 110 along the first direction X. For example, a first end of device group 110 is electrically connected to the first driver chip 103, and a second end is electrically connected to the first voltage line 151. The first end and the second end are positioned opposite each other along the first direction X, such that the first voltage line 151 and the first driver chip 103, electrically connected to the same column of device group 110, are located on opposite sides of the column of device group 110 along the first direction X.

[0240] In some examples, such as Figure 3A and Figure 3B As shown, any second voltage line 161 is located on the second side of a group of devices 110 electrically connected to the first direction X along the first direction X. It can be understood that the second side can be either side of the group of devices 110 along the first direction X.

[0241] As described above, any first voltage line 151 along the first direction X is located on the first side of a group of devices 110 electrically connected to that first voltage line 151. In some examples, the first side and the second side are opposite sides of a group of devices 110 along the first direction X. That is, as... Figure 3A and Figure 3B As shown, the first voltage line 151 and the second voltage line 161, which are electrically connected to a group of devices 110, are located on both sides of the group of devices 110 along the first direction X. This arrangement reduces the mutual influence between the first voltage line 151 and the second voltage line 161.

[0242] In some examples, such as Figure 3A and Figure 3BAs shown, the second voltage line 161 and the first driver chip 103, which are electrically connected to the same column of device group 110, are located on the same side of the column of device group 110 along the first direction X.

[0243] As described above, the substrate 100 includes a plurality of bridging portions 140. In some embodiments, such as Figure 3A and Figure 3B As shown, the substrate 100 also includes a plurality of first bridging portions 141, and at least one first conductive pattern 171 is electrically connected to a first voltage line 151 through the first bridging portion 141.

[0244] For example, such as Figure 3A and Figure 3B As shown, one end of the first bridging portion 141 is electrically connected to the first conductive pattern 171, and the other end is electrically connected to the first voltage line 151, so that at least one first conductive pattern 171 can be electrically connected to the first voltage line 151 through the first bridging portion 141.

[0245] As described above, the insulating layer can cover the conductive layer (that is, the insulating layer can cover multiple signal line groups 130 and multiple conductive patterns 170) to provide electrical isolation. In some examples, after the insulating layer is formed, a first through-hole can be formed on the insulating layer, and the first bridging portion 141 is electrically connected to the first conductive pattern 171 and the first voltage line 151 through the first through-hole.

[0246] Understandably, by providing the first bridging portion 141, even if other conductive structures (such as other signal lines 131) are provided between the first conductive pattern 171 and the first voltage line 151, the first bridging portion 141 can electrically connect the two, thereby improving the wiring flexibility of the substrate 100 and meeting different usage requirements.

[0247] Furthermore, by adjusting the width and thickness of the first bridging portion 141, its current-carrying capacity can be adjusted. In some examples, the width and thickness of the first bridging portion 141 can be increased to give it a larger current-carrying capacity. In other examples, the width and thickness of the first bridging portion 141 can be decreased to give it a smaller current-carrying capacity, thus meeting different application requirements and improving the applicability of the substrate 100.

[0248] In some embodiments, such as Figure 3A and Figure 3B As shown, at least one first conductive pattern 171 and a first voltage line 151 form an integral structure.

[0249] Understandably, the first conductive pattern 171 and the first voltage line 151 form an integral structure, that is, the first conductive pattern 171 and the first voltage line 151 are directly electrically connected, and there are no other conductive structures (such as the first bridging part 141) between them.

[0250] By providing at least one first conductive pattern 171 and a first voltage line 151 to form an integral structure, the reliability of the electrical connection between the first conductive pattern 171 and the first voltage line 151 can be improved, and no other conductive structure is required, which simplifies the structure of the substrate 100 and reduces the cost of the substrate 100.

[0251] Understandably, when multiple first conductive patterns 171 are electrically connected to the first voltage line 151, a portion (one or more) of the first conductive patterns 171 and the first voltage line 151 can be electrically connected through the first bridging portion 141, while another portion (one or more) of the first conductive patterns 171 and the first voltage line 151 form an integral structure.

[0252] In some embodiments, such as Figure 3A and Figure 3B As shown, the substrate 100 also includes a plurality of second bridging portions 142, and at least one second conductive pattern 172 is electrically connected to a second voltage line 161 through the second bridging portion 142.

[0253] For example, such as Figure 3A and Figure 3B As shown, one end of the second bridging portion 142 is electrically connected to the second conductive pattern 172, and the other end is electrically connected to the second voltage line 161, so that at least one second conductive pattern 172 can be electrically connected to the second voltage line 161 through the second bridging portion 142.

[0254] As described above, the insulating layer can cover the conductive layer (that is, the insulating layer can cover multiple signal line groups 130 and multiple conductive patterns 170) to provide electrical isolation. In some examples, after the insulating layer is formed, a second through-hole can be formed on the insulating layer, and the second bridging portion 142 is electrically connected to the second conductive pattern 172 and the second voltage line 161 through the first through-hole.

[0255] Understandably, by providing the second bridging portion 142, even if other conductive structures (such as other signal lines 131) are provided between the second conductive pattern 172 and the second voltage line 161, the second bridging portion 142 can electrically connect the two, improving the wiring flexibility of the substrate 100 and meeting different usage requirements.

[0256] Furthermore, by adjusting the width and thickness of the second bridging portion 142, its current-carrying capacity can be adjusted. In some examples, the width and thickness of the second bridging portion 142 can be increased to give it a larger current-carrying capacity. In other examples, the width and thickness of the second bridging portion 142 can be decreased to give it a smaller current-carrying capacity, thus meeting different application requirements and improving the applicability of the substrate 100.

[0257] As described above, two adjacent electronic components 120 are electrically connected via a connecting line 112. In some examples, the connecting line 112 is also disposed on a conductive layer, that is, the connecting line 112 is disposed on the same layer as multiple signal line groups 130 and multiple conductive patterns 170 (including a first conductive pattern 171 and a second conductive pattern 172). A third through-hole is also provided on the insulating layer, exposing a portion of the connecting line 112. The exposed area of ​​the connecting line 112 forms a pad, allowing the pins of the electronic components 120 to be electrically connected to the pad. Multiple electronic components 120 in a device group 110 can be connected in series via the connecting line 112.

[0258] The following example illustrates the method of creating through holes (including the first through hole, the second through hole, and the third through hole) in the insulating layer.

[0259] In some examples, a photoresist layer can be formed on the side of the insulating layer away from the conductive layer using processes such as coating, imaging, and development. The photoresist layer is then patterned using an etching process to expose the insulating layer where the openings are needed. The exposed insulating layer is then removed using another etching process to form vias (including first, second, and third vias).

[0260] In some examples, after the insulating layer is patterned, the electronic component 120 can be soldered to the pads first, and then the bridging portion 140 (including the first bridging portion 141 and the second bridging portion 142) can be electrically connected to the signal line 131 (including the first voltage line 151 and the second voltage line 161) and the conductive pattern 170 (including the first conductive pattern 171 and the second conductive pattern 172).

[0261] In some embodiments, such as Figure 3F As shown, at least one second conductive pattern 172 and a second voltage line 161 form an integral structure.

[0262] Understandably, the second conductive pattern 172 and the second voltage line 161 form an integral structure, that is, the second conductive pattern 172 and the second voltage line 161 are directly electrically connected, and there are no other conductive structures (such as the first bridging part 141) between them.

[0263] By providing at least one second conductive pattern 172 and a second voltage line 161 to form an integral structure, the reliability of the electrical connection between the second conductive pattern 172 and the second voltage line 161 can be improved, and no other conductive structure is required, which simplifies the structure of the substrate 100 and reduces the cost of the substrate 100.

[0264] Understandably, when multiple second conductive patterns 172 are electrically connected to the second voltage line 161, a portion (one or more) of the second conductive patterns 172 and the second voltage line 161 can be electrically connected through the first bridging portion 141, while another portion (one or more) of the second conductive patterns 172 and the second voltage line 161 form an integral structure.

[0265] In some embodiments, at least one of the plurality of bridging portions 140 is a bridging resistor.

[0266] Understandably, a bridging resistor is a special-purpose resistor with a very small resistance value, not exactly zero. In some examples, an automated pick-and-place machine or automated insertion machine can be used to place the bridging resistor between two points on the substrate 100 that cannot be directly connected by a wire, in order to achieve an electrical connection between the two points.

[0267] In some examples, all of the multiple bridging portions 140 may be bridging resistors, while in other examples, some (one or more) of the multiple bridging portions 140 may be bridging resistors.

[0268] Understandably, by setting at least one of the multiple bridging portions 140 as a bridging resistor, the ease of fabrication of the substrate 100 can be improved, and the cost of the substrate 100 can be reduced. Furthermore, since the resistance value of the bridging resistor is very small, the voltage drop is small, thereby improving the reliability of signal transmission.

[0269] In some embodiments, at least one of the plurality of first bridging portions 141 is a bridging resistor.

[0270] This configuration improves the ease of fabrication of the substrate 100 and reduces its cost. Furthermore, because the resistance of the bridging resistor is very small, the voltage drop is minimal, improving the reliability of signal transmission.

[0271] In some examples, all of the multiple first bridging portions 141 may be bridging resistors. In other examples, a portion (one or more) of the multiple first bridging portions 141 may be bridging resistors.

[0272] In some embodiments, at least one of the plurality of second bridging portions 142 is a bridging resistor.

[0273] This configuration improves the ease of fabrication of the substrate 100 and reduces its cost. Furthermore, because the resistance of the bridging resistor is very small, the voltage drop is minimal, improving the reliability of signal transmission.

[0274] In some examples, all of the multiple second bridging portions 142 may be bridging resistors. In other examples, some (one or more) of the multiple second bridging portions 142 may be bridging resistors.

[0275] As described above, the multiple signal line groups 130 include a first voltage line group 150 and a second voltage line group 160. See below for further details. Figure 3D and Figure 3E Examples of other signal line groups 130 among the multiple signal line groups 130 are given below.

[0276] In some examples, such as Figure 3D and Figure 3E As shown, the multiple signal line groups 130 also include a power line group 135, which includes multiple power lines 132.

[0277] In some examples, the power line (full name: Volt Current Condenser, abbreviated as VCC) 132 is used to power the first driver chip 103. For example, as shown... Figure 3D and Figure 3E As shown, one end of the power line 132 is electrically connected to the bonding pin in the bonding area BB, and the other end extends to the device area AA and is electrically connected to the first driver chip 103. As can be seen from the above, the first driver chip 103 is electrically connected to the device group 110, so that the power line 132 can be electrically connected to the device group 110 through the first driver chip 103.

[0278] In some examples, such as Figure 3E As shown, the first driver chip 103 has a power supply port Vcc. One end of the power line 132 is electrically connected to the external power supply of the substrate 100 through the bonding pin and the printed circuit board 106, and the other end is electrically connected to the power supply port Vcc of the first driver chip 103, so that the power line 132 can provide power to the first driver chip 103.

[0279] In some examples, such as Figure 3D and Figure 3E As shown, any power line 132 is located on the second side of a group of devices 110 electrically connected to the same power line 132 along the first direction X. That is, the power line 132 and the second voltage line 161 electrically connected to the same group of devices 110 are located on the same side of the same group of devices 110 along the first direction X.

[0280] In some examples, such as Figure 3D and Figure 3E As shown, the multiple signal line groups 130 also include a data line group 136, which includes multiple data lines 133.

[0281] In some examples, the Data cable (full name: Data) 133 is used to transmit data signals. For example, such as... Figure 3D and Figure 3E As shown, one end of the data line 133 is electrically connected to the bonding pin in the bonding area BB, and the other end extends to the device area AA and is electrically connected to the first driver chip 103. As can be seen from the above, the first driver chip 103 is electrically connected to the device group 110, so that the data line 133 can be electrically connected to the device group 110 through the first driver chip 103.

[0282] In some examples, such as Figure 3D and Figure 3E As shown, the first driver chip 103 has a data port Dip, and the second driver chip 104 has a first data port Dip1 to an Nth data port DipN. One end of a data line 133 is electrically connected to the first data port Dip1 of the second driver chip 104 via a bonding pin and a printed circuit board 106, and the other end is electrically connected to the data port Dip of one or more of the first driver chips 103 that are electrically connected to a column of device groups 110. One end of another data line 133 is electrically connected to the second data port Dip2 of the second driver chip 104 via a bonding pin and a printed circuit board 106, and the other end is electrically connected to the data port Dip of one or more of the first driver chips 103 that are electrically connected to another column of device groups 110, and so on, up to the Nth data port DipN. Understandably, N is a positive integer. In some examples, the value of N is the same as the number of columns of device groups 110 arranged along the second direction Y.

[0283] In some examples, such as Figure 3D and Figure 3E As shown, any data line 133 is located on the second side of a group of devices 110 electrically connected to the data line 133 along the first direction X. That is, the data line 133 and the second voltage line 161 electrically connected to the same group of devices 110 are located on the same side of the group of devices 110 along the first direction X.

[0284] In some examples, such as Figure 3D and Figure 3EAs shown, there are multiple first driver chips 103 electrically connected to a group of devices 110. For example, the multiple first driver chips 103 electrically connected to a group of devices 110 include a first first driver chip 103a, a second first driver chip 103b, a third first driver chip 103c, a fourth first driver chip 103d, and so on up to the m-th first driver chip 103m. It can be understood that the multiple first driver chips 103 are cascaded.

[0285] For example, such as Figure 3E As shown, the first driver chip 103a to the m-th driver chip 103m move away from the bonding area BB sequentially along the second direction Y. Understandably, m is greater than 4 and is a positive integer.

[0286] It should be noted that the first first driver chip 103a, the second first driver chip 103b, the third first driver chip 103c, the fourth first driver chip 103d, and so on up to the mth first driver chip 103m are only used to distinguish the multiple first driver chips 103 that are electrically connected to a column of device groups 110, and do not further limit the first driver chip 103.

[0287] In some examples, such as Figure 3D and Figure 3E As shown, the multiple signal line groups 130 also include input / output line groups 137, which include input / output lines (also called addressing signal lines) 134. For example, ... Figure 3D and Figure 3E As shown, the input / output line 134 includes input line 1341 and output line 1342.

[0288] In some examples, such as Figure 3E As shown, the second driver chip 104 has an input port DiN and an output port DoN. The first driver chip 103 has an input port Dis and an output port Dos.

[0289] For example, such as Figure 3EAs shown, there are multiple input lines 1341. One end of one input line 1341 is electrically connected to the input port DiN of the second driver chip 104 via a bonding pin, and the other end is electrically connected to the input port Dis of the first driver chip 103a. One end of another input line 1341 is electrically connected to the output port Dos of the first driver chip 103a, and the other end is electrically connected to the input port Dis of the second driver chip 103b. Another input line 1341 is electrically connected to the output port Dos of the second driver chip 103b, and the other end is electrically connected to the input port Dis of the third driver chip 103c, and so on, until the m-th first driver chip 103m that is furthest from the bonding region BB along the second direction Y.

[0290] For example, such as Figure 3E As shown, the output terminal Dos of the m-th first driver chip 103m is electrically connected to the bonding pin in the bonding area BB through the output line 1342. That is, multiple first driver chips 103 electrically connected to a column of devices 110 are cascaded through the input line 1341 and the output line 1342.

[0291] In this way, the signal output by the second driver chip 104 can be transmitted to multiple first driver chips 103 through the input line 1341, and then fed back to the second driver chip 104 through the output line 1342, so that the second driver chip 104 can drive multiple first driver chips 103.

[0292] In some examples, such as Figure 3D and Figure 3E As shown, any input / output line 134 along the first direction X is located on the second side of a column of devices 110 electrically connected to the input / output line 134. That is, the input / output line 134 and the second voltage line 161 electrically connected to the same column of devices 110 are located on the same side of the column of devices 110.

[0293] In some examples, such as Figure 3D and Figure 3E As shown, the input / output line 134 surrounds the second voltage line 161 to save wiring space and improve the area utilization of the substrate 101.

[0294] In some examples, such as Figure 3D and Figure 3E As shown, along a line of devices 110 to the first driver chip 103 electrically connected to the line of devices 110, a first voltage line 151, a power line 132, a data line 133, an input line 1341, a second voltage line 161, and an output line 1342 are arranged in sequence.

[0295] In some examples, such as Figure 3Dand Figure 3E As shown, the substrate 100 also includes an electrostatic loop 108. The electrostatic loop 108 is disposed around the plurality of device groups 110 and is electrically connected to the bonding region BB.

[0296] For example, both ends of the electrostatic loop 108 are electrically connected to the bonding pins in the bonding area BB, so that the electrostatic loop 108 can not only wrap around multiple device groups 110, but also around multiple signal line groups 130 that are electrically connected to the multiple device groups 110.

[0297] Understandably, the electrostatic loop 108 can release static electricity, thereby protecting the multiple device groups 110 and the multiple signal line groups 130 and improving the reliability of the substrate 100.

[0298] Understandably, the arrangement order of the bonding pins in the bonding area BB along the first direction X is the same as the arrangement order of the electrostatic loop 108, the first voltage line 151, the power line 132, the data line 133, the input line 1341, the second voltage line 161, and the output line 1342 along the first direction.

[0299] This configuration shortens the distance between signal line 131 and electrostatic loop 108 and the bonding pin, thereby reducing the length of the traces (including signal line 131 and electrostatic loop 108), decreasing the voltage drop of the traces (including signal line 131 and electrostatic loop 108), and improving the reliability of the substrate 100. It also reduces material usage and lowers costs.

[0300] As can be seen from the above, by electrically connecting at least one signal line 131 in at least one signal line group 130 to a conductive pattern 170, the voltage drop of the signal line 131 can be reduced.

[0301] Referring to Table 1 below, examples are given of the voltage drops of the first voltage line 151, the second voltage line 161, and the power line 132 when the conductive pattern 170 is provided and when the conductive pattern 170 is not provided.

[0302] Table 1

[0303]

[0304] As shown in Table 1, taking Cu as the material of the conductive layer as an example, simulation tests were conducted on the first voltage line group 150, the second voltage line group 160, and the power line group 135.

[0305] Table 1 shows the resistance values ​​and voltage drops of the longest first voltage line 151 in the first voltage line group 150, the longest second voltage line 161 in the second voltage line group 160, and the longest power line 132 in the power line group 135. For example, in both cases with and without the conductive pattern 170, the lengths of the first voltage line 151, the second voltage line 161, and the power line 132 are the same. Furthermore, in both cases with and without the conductive pattern 170, the width of the first voltage line 151 along the first direction X is approximately 4 mm, the width of the second voltage line 161 along the first direction X is approximately 3.3 mm, and the width of the power line 132 along the first direction X is approximately 0.34 mm. That is, in both cases with and without the conductive pattern 170, the widths of the first voltage line 151, the second voltage line 161, and the power line 132 along the first direction X are the same. Based on this, by controlling the thickness of the three components, different resistance values ​​and voltage drops were obtained.

[0306] As shown in Table 1, when the conductive pattern 170 is not provided, the resistances of the first voltage line 151, the second voltage line 161, and the power line 132 are all relatively high, resulting in large voltage drops. For example, the voltage drop of the first voltage line 151 reaches 0.2632V, the voltage drop of the second voltage line 161 reaches 0.3122V, and the voltage drop of the power line 132 reaches 0.1439V. Furthermore, the sum of the voltage drops of the second voltage line 161 and the power line 132 reaches 0.4561V.

[0307] Typically, the voltage drop across the first voltage line 151 needs to be less than 0.5V, the voltage drop across the second voltage line 161 needs to be less than 0.4V, and the sum of the voltage drops across the second voltage line 161 and the power line 132 needs to be less than 0.45V. Understandably, since the second voltage line 161 is used to ground the first driver chip 103, and the power line 132 is used to supply power to the first driver chip 103, if the voltage drops across the second voltage line 161 and the power line 132 are too large (e.g., greater than 0.45V), it will lead to increased power consumption of the first driver chip 103, causing its temperature to rise and affecting its reliability.

[0308] As can be seen from Table 1, when the conductive pattern 170 is not set, even if the thickness of Cu is large (e.g., 4.5 μm), the sum of the voltage drop of the second voltage line 161 and the voltage drop of the power line 132 is 0.4561V, which still cannot meet the requirements and reduces the reliability of the first driver chip 103.

[0309] In the embodiments of this disclosure, by setting the conductive pattern 170 to be electrically connected to the signal line 131 (e.g., the first voltage line 151 and the second voltage line 161), the conductive pattern 170 can compensate for the voltage drop of the signal line 131.

[0310] For example, as shown in Table 1, after the first conductive pattern 171 is electrically connected to the first voltage line 151 and the second conductive pattern 172 is electrically connected to the second voltage line 161, the voltage drop of the first voltage line 151 can be reduced to 0.3392V, the voltage drop of the second voltage line 161 can be reduced to 0.2218V, and the sum of the voltage drop of the second voltage line 161 and the voltage drop of the power line 132 can be reduced to 0.3452V. That is, by setting the conductive pattern 170, even if the thickness of Cu is small (e.g., 3.6μm), the voltage drop can meet the requirements, reducing the amount of Cu used and reducing the cost of the substrate 100.

[0311] As described above, the input / output line 134 includes input line 1341 and output line 1342. In some examples, such as... Figure 3D As shown, the input / output line 134 includes a first input / output line 134a, which is located within the side edge region AA21 and electrically connected to a group of devices 110 adjacent to the side edge region AA2 along the first direction X. For example, the first input / output line 134a includes a first input line 1341a and a first output line 1342a.

[0312] In some examples, such as Figure 3D As shown, the first output line 1342a extends from the side edge region AA21 to the center region AA1 and is electrically connected to other output lines 1342. In this way, the first output line 1342a does not need to occupy the space of the side edge region AA21, which helps to reduce the width of the side edge region AA21, thereby facilitating the realization of a narrow bezel (side bezel) of the substrate 100.

[0313] In some examples, the first output line 1342a extends to the central region AA1 and is electrically connected to the output line 1342 adjacent to the first output line 1342a along the first direction X.

[0314] Figure 4A This is a structural diagram of a substrate according to some other embodiments. Figure 4B This is a structural diagram of a substrate according to some other embodiments. Figure 4C This is a structural diagram of a substrate according to some other embodiments.

[0315] As can be seen from the above, by electrically connecting the conductive pattern 170 (including the first conductive pattern 171 and the second conductive pattern 172) to the signal line 131 (e.g., the first voltage line 151 and the second voltage line 161), the width of the signal line 131 along the first direction X can be reduced, thereby facilitating the reduction of the width of the side edge region AA21 of the substrate 100 and enabling the realization of a narrow bezel of the substrate 100. (Refer to the following...) Figures 4A to 4C Let's continue with an example of substrate 100.

[0316] In some implementations, such as Figure 4A As shown, signal lines 131 (e.g., first voltage line 151 and second voltage line 161) within device region AA need to extend along the first direction X and the second direction Y within lower edge region AA22 to be electrically connected to bonding pins within bonding region BB. Understandably, extending signal lines 131 along the first direction X within lower edge region AA22 increases the space occupied by signal lines 131 within that region. Furthermore, a large number of signal lines 131 increases the difficulty of wiring within lower edge region AA22, which is detrimental to achieving a narrow bezel (lower bezel) on substrate 100.

[0317] In some implementations, such as Figure 4B As shown, the bonding area BB includes a pin area BBa and a floating bonding area BBb. Understandably, the bonding pins are located within the pin area BBa, and a dummy pin is located within the floating bonding area BBb. By setting the dummy pin, the pin map of the bonding pins can be adjusted, shortening the distance between the signal line 131 and the bonding pin electrically connected to it, thereby shortening the length of the signal line 131 extending along the first direction X within the lower edge area AA22.

[0318] In related technologies, the bonding area BB includes multiple bonding pins arranged at equal intervals along a first direction X, and each signal line group 130 is electrically connected to a portion of the bonding pins in the bonding area BB. The bonding area BB includes a first bonding area BB1, a second bonding area BB2, and a third bonding area BB3, which are respectively connected to different signal line groups 130. The first bonding area BB1, the second bonding area BB2, and the third bonding area BB3 are continuously arranged along the first direction X. The inventors of this disclosure have discovered that, as Figure 4CAs shown, the first bonding area BB1 is electrically connected to the first signal line group 130a. If the central axis of the first signal line group 130a along the second direction Y is far away from the central axis of the first bonding area BB1 along the second direction Y in the first direction X, the signal line 131 needs to extend a certain distance along the first direction X within the lower edge area AA22 to connect with the first bonding area BB1, which is not conducive to realizing the narrow bezel of the substrate 100. If the central axis of the signal line group 130 (e.g., the first signal line group 130a) electrically connected to a certain bonding area BB (e.g., the first bonding area BB1) along the second direction Y is set as close as possible to the central axis of the bonding area BB (e.g., the first bonding area BB1) along the second direction Y in the first direction X, then a floating bonding area BBb that is not connected to any signal line needs to be set between different bonding pins in the bonding area BB. When there are many signal lines 131, there are many bonding pins, which means there is not enough space to set up a large number of floating bonding areas BBb. As a result, the signal lines 131 still need to extend a long distance along the first direction X within the lower edge area AA22, which is not conducive to realizing the narrow bezel of the substrate 100.

[0319] Therefore, it can be seen that the method of setting the floating bonding area BBB has poor applicability and cannot effectively improve the problem of the wide bottom bezel of the substrate 100.

[0320] Figure 5A This is a structural diagram of a substrate according to some other embodiments. Figure 5B This is a structural diagram of a substrate according to some other embodiments. Figure 5C This is a structural diagram of a substrate according to some other embodiments. Figure 5D This is a structural diagram of a substrate according to some other embodiments.

[0321] In some embodiments, such as Figure 5A and Figure 5B As shown, at least two first conductive patterns 171 are arranged along the first direction X.

[0322] Understandably, in the first voltage line group 150, at least two first voltage lines 151 can be electrically connected to the same first conductive pattern 171. Therefore, at least two first conductive patterns 171 are arranged along the first direction X, such that a plurality of first voltage lines 151 can be electrically connected through at least two first conductive patterns 171 arranged along the first direction X.

[0323] Understandably, by electrically connecting multiple first voltage lines 151 through at least two first conductive patterns 171 arranged along the first direction X, the voltage drop of the first voltage lines 151 can be reduced, which is beneficial for reducing the thickness of the first voltage lines 151 and lowering the cost of the substrate 100. Furthermore, since the multiple first voltage lines 151 are electrically connected through at least two first conductive patterns 171, connecting any one of the electrically connected first voltage lines 151 to the bonding area BB allows signal transmission between the bonding pin and the electrically connected multiple first voltage lines 151, improving the wiring convenience of the substrate 100.

[0324] In some examples, such as Figure 5A and Figure 5B As shown, the first conductive pattern 171 includes a second type of first conductive pattern 171b, which is located in the central region AA1. A plurality of first voltage lines 151 are electrically connected through a plurality of second type first conductive patterns 171b arranged along the first direction X.

[0325] Understandably, since the second type of first conductive pattern 171b is located in the central region AA1, multiple first voltage lines 151 can be electrically connected sequentially within the central region AA1. That is, multiple first voltage lines 151 do not need to be electrically connected to the bonding region BB separately within the lower edge region AA22. Instead, they can be electrically connected to each other in the central region AA1 through the second type of first conductive pattern 171b, and then connected to the bonding pins in the bonding region BB through one or more (fewer than the number of first voltage lines 151) electrical structures (such as conductive patterns 170 and bridging portions 140, etc.).

[0326] In this way, the multiple first voltage lines 151 do not need to extend along the first direction X within the lower edge region AA22, which helps to reduce the width of the lower edge region AA22 and facilitates the realization of a narrow bezel (lower bezel) of the substrate 100. Furthermore, there is no need to adjust the position of the bonding pins connected to the first voltage line group 150, simplifying the fabrication process of the substrate 100. In addition, by setting a second type of first conductive pattern 171b to electrically connect the multiple first voltage lines 151, the narrow bezel of the substrate 100 is achieved, offering high applicability and meeting various wiring requirements.

[0327] In some examples, after the plurality of first voltage lines 151 are electrically connected, they are electrically connected to at least one bonding pin via a conductive structure (e.g., a first conductive pattern 171 or a first bridging portion 141). It is understood that the central axis of the region where the at least one bonding pin, to which the plurality of first voltage lines 151 belong, is located along the second direction Y, substantially coincides with the central axis of the conductive structure along the second direction Y.

[0328] In some embodiments, such as Figure 5C and Figure 5D As shown, at least two second conductive patterns 172 are arranged along the first direction X.

[0329] Understandably, in the second voltage line group 160, at least two second voltage lines 161 can be electrically connected to the same second conductive pattern 172. Therefore, at least two second conductive patterns 172 are arranged along the first direction X, such that a plurality of second voltage lines 161 can be electrically connected through at least two second conductive patterns 172 arranged along the first direction X.

[0330] Understandably, by electrically connecting multiple second voltage lines 161 through at least two second conductive patterns 172 arranged along the first direction X, the voltage drop of the second voltage lines 161 can be reduced, which is beneficial for reducing the thickness of the second voltage lines 161 and lowering the cost of the substrate 100. Furthermore, since the multiple second voltage lines 161 are electrically connected through at least two second conductive patterns 172, connecting any one of the electrically connected second voltage lines 161 to the bonding area BB allows signal transmission between the bonding pin and the electrically connected multiple second voltage lines 161, improving the wiring convenience of the substrate 100.

[0331] In some examples, such as Figure 5C and Figure 5D As shown, the second conductive pattern 172 includes a second type of second conductive pattern 172b, which is located in the central region AA1. A plurality of second voltage lines 161 are electrically connected through the plurality of second type second conductive patterns 172b arranged along the first direction X.

[0332] Understandably, due to the central region AA1 of the second type of second conductive pattern 172b, multiple second voltage lines 161 can be sequentially electrically connected within the central region AA1. That is, multiple second voltage lines 161 do not need to be electrically connected to the bonding region BB separately within the lower edge region AA22. Instead, they can be electrically connected to each other in the central region AA1 through the second type of second conductive pattern 172b, and then connected to the bonding pins within the bonding region BB through one or more electrical structures (less than the number of first voltage lines 151) (such as conductive patterns 170 and bridging portions 140, etc.).

[0333] In this way, the multiple second voltage lines 161 do not need to extend along the first direction X within the lower edge region AA22, which helps to reduce the width of the lower edge region AA22 and facilitates the realization of a narrow bezel (lower bezel) of the substrate 100. Furthermore, there is no need to adjust the position of the bonding pins connected to the second voltage line group 160, simplifying the fabrication process of the substrate 100. In addition, by electrically connecting the multiple second voltage lines 161 using a second type of second conductive pattern 172b, the narrow bezel of the substrate 100 is achieved, offering high applicability and meeting various wiring requirements.

[0334] In some examples, after the plurality of second voltage lines 161 are electrically connected, they are electrically connected to at least one bonding pin via a conductive structure (e.g., a second conductive pattern 172 or a second bridging portion 142). It is understood that the central axis of the region containing the at least one bonding pin connected to the second voltage line group 160 to which the plurality of second voltage lines 161 belong, along the second direction Y, substantially coincides with the central axis of the conductive structure along the second direction Y.

[0335] In some embodiments, such as Figure 5B As shown, at least two first conductive patterns 171 arranged along the first direction X constitute a first conductive pattern row 181, and multiple first conductive patterns 171 constitute at least two first conductive pattern rows 181.

[0336] Understandably, the number of first conductive patterns 171 contained in at least two rows of first conductive patterns 181 may be the same or different.

[0337] In some examples, at least two first conductive pattern rows 181 are electrically connected to a plurality of first voltage lines 151 in the first voltage line group 150, respectively. In other examples, a portion (two or more) of the first voltage lines 151 in the first voltage line group 150 are electrically connected through one first conductive pattern row 181, and another portion (two or more) of the first voltage lines 151 are electrically connected through another first conductive pattern row 181.

[0338] In some examples, at least two rows 181 of first conductive patterns are spaced apart along a second direction Y. In other examples, at least two rows 181 of first conductive patterns are spaced apart along a first direction X.

[0339] Understandably, by setting multiple first conductive patterns 171 to form at least two first conductive pattern rows 181, multiple first voltage lines 151 can be electrically connected through at least two first conductive pattern rows 181, thereby improving the wiring flexibility of the substrate 100.

[0340] In some embodiments, such as Figure 5BAs shown, there are two first conductive pattern rows 181, and the number of first conductive patterns 171 included in the two first conductive pattern rows 181 is different.

[0341] Understandably, the shape and size of the first conductive patterns 171 belonging to the same first conductive pattern row 181 may not be exactly the same, and are not limited here. Some (one or more) first conductive patterns 171 belonging to the same first conductive pattern row 181 are in direct contact with the adjacent first voltage line 151 and form an integral structure, while other (one or more) first conductive patterns 171 are spaced apart from the first voltage line 151 and connected by the first bridging part 141.

[0342] This configuration allows for different numbers of first conductive patterns 171 to be included in different rows of first conductive patterns 181 according to usage requirements, thereby improving the wiring flexibility of the substrate 100.

[0343] In some embodiments, such as Figure 5B As shown, the length of any device group 110 along the second direction Y is L. Along the second direction Y, a first conductive pattern row 181 (e.g.) Figure 5B The first conductive pattern row 181a) in the middle is relative to another first conductive pattern row 181 (e.g. Figure 5B The first conductive pattern row 181b) is close to the bonding area BB and along the second direction Y. The interval between the two first conductive pattern rows 181 (first conductive pattern row 181a and first conductive pattern row 181b) is 3L to 5L.

[0344] Understandably, the first conductive pattern row 181a and the first conductive pattern row 181b are only used to distinguish the two first conductive pattern rows 181 that are spaced apart along the second direction Y, and do not further limit the first conductive pattern row 181. Since the length of any device group 110 along the second direction Y is L, that is, there are 3 to 5 device groups 110 between the first conductive pattern row 181a and the first conductive pattern row 181b.

[0345] This configuration avoids the spacing between the first conductive pattern rows 181a and 181b along the second direction Y being too small (e.g., less than 3L), which prevents the multiple first conductive patterns 171 from being arranged too densely, causing excessive current in a part of the substrate 100 and resulting in localized overheating of the substrate 100. Furthermore, it also avoids the spacing between the first conductive pattern rows 181a and 181b along the second direction Y being too large (e.g., greater than 5L), which would affect the compensation effect of the first conductive patterns 171 on the voltage drop of the first voltage line 151.

[0346] That is, setting the interval between the first conductive pattern row 181a and the first conductive pattern row 181b to a value ranging from 3L to 5L can improve the heat uniformity of the substrate 100 at different locations, avoid local overheating of the substrate 100, and thus improve the reliability of the substrate 100. Furthermore, it can also improve the compensation effect of the first conductive pattern 171 on the voltage drop of the first voltage line 151, reducing the voltage drop of the first voltage line 151. In some examples, the interval between the first conductive pattern row 181a and the first conductive pattern row 181b can be 3L, 4L, or 5L, etc.

[0347] In some embodiments, such as Figure 5D As shown, at least two second conductive patterns 172 arranged along the first direction X constitute a second conductive pattern row 182, and multiple second conductive patterns 172 constitute at least two second conductive pattern rows 182.

[0348] Understandably, the number of second conductive patterns 172 contained in at least two rows of second conductive patterns 182 may be the same or different.

[0349] In some examples, at least two second conductive pattern rows 182 are electrically connected to a plurality of second voltage lines 161 in the second voltage line group 160, respectively. In other examples, a portion (two or more) of the second voltage lines 161 in the second voltage line group 160 are electrically connected through one second conductive pattern row 182, and another portion (two or more) of the second voltage lines 161 are electrically connected through another second conductive pattern row 182.

[0350] In some examples, at least two rows 182 of the second conductive pattern are spaced apart along a second direction Y. In other examples, at least two rows 182 of the second conductive pattern are spaced apart along a first direction X.

[0351] Understandably, by setting multiple second conductive patterns 172 to form at least two second conductive pattern rows 182, multiple second voltage lines 161 can be electrically connected through at least two second conductive pattern rows 182, thereby improving the wiring flexibility of the substrate 100.

[0352] In some embodiments, such as Figure 5D As shown, there are two second conductive pattern rows 182, and the number of second conductive patterns 172 included in the two second conductive pattern rows 182 is different.

[0353] Understandably, the shape and size of the second conductive patterns 172 belonging to the same second conductive pattern row 182 may not be exactly the same, and are not limited here. Some (one or more) second conductive patterns 172 belonging to the same second conductive pattern row 182 are in direct contact with the adjacent second voltage line 161 and form an integral structure, while other (one or more) second conductive patterns 172 are spaced apart from the second voltage line 161 and connected by the second bridging part 142.

[0354] This configuration allows for different numbers of second conductive patterns 172 to be included in different rows of second conductive patterns 182 according to usage requirements, thereby improving the wiring flexibility of the substrate 100.

[0355] In some embodiments, such as Figure 5D As shown, the length of any device group 110 along the second direction Y is L. Along the second direction Y, a second conductive pattern row 182 (e.g.) Figure 5D The second conductive pattern row 182a) is relative to another second conductive pattern 182 (e.g. Figure 5D The second conductive pattern row 182b is close to the binding area BB and along the second direction Y. The interval between the two second conductive pattern rows 182 (second conductive pattern row 182a and second conductive pattern row 182b) is 3L to 5L.

[0356] Understandably, the second conductive pattern row 182a and the second conductive pattern row 182b are only used to distinguish between two second conductive pattern rows 182 spaced apart along the second direction Y, and do not further define the second conductive pattern row 182. Since the length of any device group 110 along the second direction Y is L, that is, there are 3 to 5 device groups 110 spaced between the second conductive pattern row 182a and the second conductive pattern row 182b.

[0357] This configuration avoids the spacing between the second conductive pattern rows 182a and 182b along the second direction Y being too small (e.g., less than 3L), which prevents the multiple second conductive patterns 172 from being too densely arranged, causing excessive current in a part of the substrate 100 and resulting in localized overheating of the substrate 100. Furthermore, it also avoids the spacing between the second conductive pattern rows 182a and 182b along the second direction Y being too large (e.g., greater than 5L), which would affect the compensation effect of the second conductive patterns 172 on the voltage drop of the second voltage line 161.

[0358] That is, by setting the interval between the second conductive pattern row 182a and the second conductive pattern row 182b to a value ranging from 3L to 5L, the heat uniformity of the substrate 100 at different locations can be improved, preventing local overheating of the substrate 100 and thus improving the reliability of the substrate 100. Furthermore, it can also improve the compensation effect of the second conductive pattern 172 on the voltage drop of the second voltage line 161, reducing the voltage drop of the second voltage line 161.

[0359] In some examples, the interval between the second conductive pattern row 182a and the second conductive pattern row 182b can be 3L, 4L, or 5L, etc.

[0360] Understandably, the distance between the second conductive pattern row 182a and the second conductive pattern row 182b can be the same as or different from the distance between the first conductive pattern row 181a and the first conductive pattern row 181b.

[0361] Figure 5E This is a structural diagram of a substrate according to some other embodiments.

[0362] In some embodiments, such as Figure 5E As shown, the multiple device groups 110 include a first row of device groups 111, which is adjacent to the bonding area BB along the second direction Y. It can be understood that the first row of device groups 111 is the row of device groups 110 that is closest to the bonding area BB along the second direction Y among the multiple rows of device groups 110.

[0363] In some examples, at least one first conductive pattern row 181 is located in the area where the first row of device group 111 is located, that is, multiple first conductive patterns 171 in at least one first conductive pattern row 181 are located in the area where each device group 110 in the first row of device group 111 is located.

[0364] This configuration shortens the distance between the first conductive pattern row 181 and the binding area BB, improving the ease of electrical connection between the first conductive pattern 171 in the first conductive pattern row 181 and the binding area BB.

[0365] As can be seen from the above, the first conductive pattern row 181a is closer to the bonding area BB than the first conductive pattern row 181b. That is, the first conductive pattern row 181a can be located in the area where the first row of device group 111 is located.

[0366] In some embodiments, such as Figure 5E As shown, at least one second conductive pattern row 182 is located within the area where the first row of device group 111 is located.

[0367] At least one second conductive pattern row 182 is located in the area where the first row of device group 111 is located, that is, multiple second conductive patterns 172 in at least one second conductive pattern row 182 are located in the area where each device group 110 in the first row of device group 111 is located.

[0368] This configuration reduces the distance between the second conductive pattern row 182 and the binding area BB, improving the ease of electrical connection between the second conductive pattern 172 in the second conductive pattern row 182 and the binding area BB.

[0369] As can be seen from the above, the second conductive pattern row 182a is closer to the bonding area BB than the second conductive pattern row 182b. That is, the second conductive pattern row 182a can be located in the area where the first row of device group 111 is located.

[0370] In some examples, such as Figure 5E As shown, when the second conductive pattern row 182 is located in the area where the first row of device group 111 is located, the first conductive pattern row 181 is located along the second direction Y on the side of the second conductive pattern row 182 away from the bonding area BB.

[0371] As can be seen from the above, in some examples, multiple signal lines 131 (including the first voltage line 151 and the second voltage line 161) are electrically connected in the central area AA1 and then electrically connected to the bonding pins in the bonding area BB.

[0372] The following example illustrates how multiple signal lines 131 are electrically connected together and then electrically connected to the bonding pins in the bonding area BB.

[0373] See you again Figure 5C and Figure 5D In some embodiments, at least one signal line 131 in at least one signal line group 130 is electrically connected to the bonding area BB via a conductive pattern 170.

[0374] In some examples, such as Figure 5C and Figure 5D After at least two signal lines 131 (e.g., first voltage line 151) in a signal line group 130 (e.g., first voltage line group 150) are electrically connected, they are then electrically connected to the bonding pins in the bonding area BB through the conductive pattern 170.

[0375] Understandably, providing at least two signal lines 131 with electrical connections reduces the voltage drop across the signal lines 131, which helps to reduce the thickness of the signal lines 131. Furthermore, after at least two signal lines 131 are electrically connected, they are then electrically connected to the bonding pins in the bonding area BB via the conductive pattern 170, which improves the ease of electrical connection between the at least two signal lines 131 and the bonding pins.

[0376] In other examples, a signal line 131 in a signal line group 130 is electrically connected to a bonding pin in the bonding area BB via a conductive pattern 170, to meet different usage requirements and improve the flexibility of the substrate 100.

[0377] Understandably, by providing at least one signal line 131 in at least one signal line group 130 with the bonding area BB, the reliability of the electrical connection between the signal line 131 and the bonding pin can be improved, the voltage drop can be reduced, and thus the reliability of the substrate 100 can be improved.

[0378] In some embodiments, such as Figure 5E As shown, the plurality of first conductive patterns 171 include a first type of first conductive pattern 171a. One end of the first type of first conductive pattern 171a is directly connected to the end of the bonding region BB near the device region AA, and the other end of the first type of first conductive pattern 171a is electrically connected to the first voltage line group 150.

[0379] Understandably, the first type of first conductive pattern 171a can extend from the bonding region BB to the device region AA. One end of the first type of first conductive pattern 171a is directly connected to the end of the bonding region BB near the device region AA, that is, one end of the first type of first conductive pattern 171a is directly electrically connected to the end of the bonding region BB near the device region AA, and no other conductive structure is provided between the two. Understandably, the first type of first conductive pattern 171a can be electrically connected to multiple bonding pins within the bonding region BB.

[0380] The other end of the first conductive pattern 171a is electrically connected to the first voltage line group 150, that is, the other end of the first conductive pattern 171a is electrically connected to a plurality of first voltage lines 151 in the first voltage line group 150.

[0381] As can be seen from the above, in some examples, such as Figure 5B As shown, a plurality of first voltage lines 151 in the first voltage line group 150 are electrically connected via a second type of first conductive pattern 171b. For example, one end of the first type of first conductive pattern 171a away from the bonding region BB is electrically connected to the second type of first conductive pattern 171b, such that the first type of first conductive pattern 171a can electrically connect the plurality of first voltage lines 151 and the bonding pins.

[0382] Understandably, since the conductive pattern 170 (including the first conductive pattern 171a of the first type) has a strong current carrying capacity, the first voltage line group 150 is electrically connected to the bonding pin in the bonding area BB through the first conductive pattern 171a of the first type, thereby improving the reliability of the electrical connection between the first voltage line group 150 and the bonding pin.

[0383] In some embodiments, the number of first conductive patterns 171a of the first class is a, where a is less than the number of first voltage lines 151 in the first voltage line group 150, and a is a positive integer.

[0384] Understandably, the number 'a' of the first type of first conductive patterns 171a is less than the number of first voltage lines 151. That is, after multiple first voltage lines 151 are electrically connected to the second type of first conductive patterns 171b located in the device region AA, they are electrically connected to the bonding region BB through the first type of first conductive patterns 171a, which are fewer in number than the first voltage lines 151. On the one hand, this reduces the number of bonding pins electrically connected to the first voltage lines 151, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing costs. On the other hand, it simplifies the structure of the substrate 100 and improves the ease of wiring of the substrate 100.

[0385] In some examples, the value of a can be 2. That is, the plurality of first voltage lines 151 in the first voltage line group 150 are electrically connected to the bonding pins in the bonding area BB through two first type first conductive patterns 171a.

[0386] In other examples, the value of a can be 1. That is, the plurality of first voltage lines 151 in the first voltage line group 150 are electrically connected to the bonding pins in the bonding area BB through a first type of first conductive pattern 171a.

[0387] In some embodiments, a is not greater than half the number of first voltage lines 151 in the first voltage line group 150.

[0388] Understandably, 'a' is greater than half the number of first voltage lines 151 in the first voltage line group 150, that is, 'a' is less than or equal to half the number of first voltage lines 151. This configuration reduces the number of first conductive patterns 171a of the first type, thereby reducing the number of bonding pins electrically connected to the first voltage lines 151, reducing the width of the flexible circuit board 105 along the first direction X, and lowering the cost of the substrate 100.

[0389] In some examples, when the value of a is small (e.g., when the value of a is 1 or 2), the width of the first type of first conductive pattern 171a along the first direction X can be increased, so that the first type of first conductive pattern 171a can be bonded to a larger number of bonding pins, thereby reducing the current value on the first type of first conductive pattern 171a, reducing the heat dissipation of the first type of first conductive pattern 171a, and improving the reliability of the substrate 100.

[0390] In some embodiments, such as Figure 5EAs shown, the plurality of second conductive patterns 172 include a first type of second conductive pattern 172a. One end of the first type of second conductive pattern 172a is directly connected to the end of the bonding region BB near the device region AA, and the other end of the first type of second conductive pattern 172a is electrically connected to the second voltage line group 160.

[0391] Understandably, the first type of second conductive pattern 172a can extend from the bonding region BB to the device region AA. One end of the first type of second conductive pattern 172a is directly connected to the end of the bonding region BB near the device region AA, that is, one end of the first type of second conductive pattern 172a is directly electrically connected to the end of the bonding region BB near the device region AA, and no other conductive structure is provided between the two. Understandably, the first type of second conductive pattern 172a can be electrically connected to multiple bonding pins within the bonding region BB.

[0392] The other end of the first type of second conductive pattern 172a is electrically connected to the second voltage line group 160, that is, the other end of the first type of second conductive pattern 172a is electrically connected to a plurality of second voltage lines 161 in the second voltage line group 160.

[0393] As can be seen from the above, in some examples, such as Figure 5D As shown, a plurality of second voltage lines 161 in the second voltage line group 160 are electrically connected via a second type of second conductive pattern 172b. For example, one end of the first type of second conductive pattern 172a away from the bonding region BB is electrically connected to the second type of second conductive pattern 172b, such that the first type of second conductive pattern 172a can electrically connect the plurality of electrically connected second voltage lines 161 and the bonding pins.

[0394] Understandably, since the conductive pattern 170 (including the first type of second conductive pattern 172a) has a strong current carrying capacity, the second voltage line group 160 is electrically connected to the bonding pin in the bonding area BB through the first type of second conductive pattern 172a, which improves the reliability of the electrical connection between the second voltage line group 160 and the bonding pin.

[0395] In some embodiments, the number of the first type of second conductive pattern 172a is b, where b is less than the number of the second voltage lines 161 in the second voltage line group 160, and b is a positive integer.

[0396] Understandably, the number 'a' of the first type of second conductive patterns 172a is less than the number of second voltage lines 161. That is, multiple second voltage lines 161 can be electrically connected to the bonding area BB through the first type of second conductive patterns 172a, which is less numerous than the number of second voltage lines 161, after being electrically connected to the second type of second conductive patterns 172b located in the device area AA. On the one hand, this reduces the number of bonding pins electrically connected to the second voltage lines 161, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing costs. On the other hand, it simplifies the structure of the substrate 100 and improves the ease of wiring of the substrate 100.

[0397] In some examples, the value of b can be 2. That is, the plurality of second voltage lines 161 in the second voltage line group 160 are electrically connected to the bonding pins in the bonding area BB through two first type second conductive patterns 172a.

[0398] In other examples, the value of b can be 1. That is, the plurality of second voltage lines 161 in the second voltage line group 160 are electrically connected to the bonding pins in the bonding area BB through a first type of second conductive pattern 172a.

[0399] Understandably, the values ​​of a and b can be the same or different.

[0400] In some embodiments, b is not greater than half the number of second voltage lines 161 in the second voltage line group 160.

[0401] Understandably, b is greater than half the number of second voltage lines 161 in the second voltage line group 160, that is, b is less than or equal to half the number of second voltage lines 161. This configuration reduces the number of first-type second conductive patterns 172a, thereby reducing the number of bonding pins electrically connected to the second voltage lines 161, reducing the width of the flexible circuit board 105 along the first direction X, and lowering the cost of the substrate 100.

[0402] In some examples, when the value of b is small (e.g., when the value of b is 1 or 2), the width of the first type of second conductive pattern 172a along the first direction X can be increased, so that the first type of second conductive pattern 172a can be bonded to a larger number of bonding pins, thereby reducing the current value on the first type of second conductive pattern 172a, reducing the heat dissipation of the first type of second conductive pattern 172a, and improving the reliability of the substrate 100.

[0403] In some examples, the first type of first conductive pattern 171a and the first type of second conductive pattern 172a are arranged alternately to avoid local overheating of the substrate 100 and improve the heat uniformity of the substrate 100 at different locations.

[0404] See you again Figure 3A and Figure 3B As described above, the substrate 100 includes a plurality of bridging portions 140. In some embodiments, the substrate 100 further includes a plurality of third bridging portions 143, through which at least two first conductive patterns 171 are electrically connected.

[0405] Understandably, two first conductive patterns 171 spaced apart along the first direction X can be electrically connected through the third bridging portion 143, and two first conductive patterns 171 spaced apart along the second direction Y can also be electrically connected through the third bridging portion 143.

[0406] By providing the third bridging portion 143, the first conductive patterns 171 that are spaced apart can be connected through the third bridging portion 143, thereby improving the wiring flexibility of the substrate 100.

[0407] Understandably, by adjusting the width and thickness of the third bridging portion 143, its current-carrying capacity can be adjusted. In some examples, the third bridging portion 143 can be configured to have a larger width and thickness to improve its current-carrying capacity. In other examples, the third bridging portion 143 can be configured to have a smaller width and thickness to meet different application requirements.

[0408] In some examples, a fourth through-hole is also provided on the insulating layer to expose a portion of the surface of the first conductive pattern 171, and the third bridging portion 143 is electrically connected to at least two exposed surface areas of the first conductive pattern 171.

[0409] In some embodiments, such as Figure 3A and Figure 3B As shown, the substrate 100 also includes a plurality of fourth bridging portions 144, and at least two second conductive patterns 172 are electrically connected through the fourth bridging portions 144.

[0410] Understandably, two second conductive patterns 172 spaced apart along the first direction X can be electrically connected through the fourth bridging portion 144, and two second conductive patterns 172 spaced apart along the second direction Y can also be electrically connected through the fourth bridging portion 144.

[0411] By providing the fourth bridging portion 144, the spaced second conductive patterns 172 can be connected through the fourth bridging portion 144, thereby improving the wiring flexibility of the substrate 100.

[0412] Understandably, by adjusting the width and thickness of the fourth bridging portion 144, its current-carrying capacity can be adjusted. In some examples, the fourth bridging portion 144 can be configured to have a larger width and thickness to improve its current-carrying capacity. In other examples, the fourth bridging portion 144 can be configured to have a smaller width and thickness to meet different application requirements.

[0413] In some examples, a fifth through-hole is also provided on the insulating layer, exposing a portion of the surface of the second conductive pattern 172, and the fourth bridging portion 144 is electrically connected to at least two exposed surface areas of the second conductive pattern 172.

[0414] In some embodiments, in the same first voltage line group 150, at least two first voltage lines 151 are interconnected on the side away from the bonding region BB along the second direction Y.

[0415] Understandably, by connecting at least two first voltage lines 151 to each other along the second direction Y away from the bonding area BB, the voltage drop of the first voltage lines 151 can be reduced, which is beneficial to reducing the width of the first voltage lines 151 along the first direction X, which is beneficial to achieving a narrow bezel of the substrate 100, and also beneficial to reducing the thickness of the first voltage lines 151, thereby reducing the cost of the substrate 100.

[0416] In some embodiments, in the same second voltage line group 160, at least two second voltage lines 161 are interconnected on the side away from the bonding region BB along the second direction Y.

[0417] Understandably, by setting at least two second voltage lines 161 to be interconnected on the side away from the bonding region BB along the second direction Y, the voltage drop of the second voltage lines 161 can be reduced, which is beneficial to reducing the width of the second voltage lines 161 along the first direction X, which is beneficial to achieving a narrow bezel of the substrate 100, and also beneficial to reducing the thickness of the second voltage lines 161, thereby reducing the cost of the substrate 100.

[0418] Figure 6A This is a structural diagram of a substrate according to some other embodiments. Figure 6B This is a structural diagram of a substrate according to some other embodiments. Figure 6C This is a structural diagram of a substrate according to some other embodiments.

[0419] As can be seen from the above, in some examples, at least two signal lines 131 in a signal line group 130 can be electrically connected through a bridging portion 140 and / or a conductive pattern 170.

[0420] In other examples, such as Figure 6A and Figure 6BAs shown, at least two signal lines 131 in at least one signal line group 130 are electrically connected through a bridging section 140.

[0421] For example, such as Figure 6A and Figure 6B As shown, at least two signal lines 131 in at least one signal line group 130 may be electrically connected only through the bridging portion 140, without passing through the conductive pattern 170. Understandably, after at least two signal lines 131 in a signal line group 130 are electrically connected through the bridging portion 140, the voltage drop of the signal lines 131 can be reduced, thereby facilitating a reduction in the width of the signal lines 131 along the first direction X, enabling a narrow bezel of the substrate 100, and also facilitating a reduction in the thickness of the second voltage line 161, thus lowering the cost of the substrate 100.

[0422] Furthermore, in some examples, such as Figure 6A and Figure 6B As shown, at least one bridging portion 140 is located in the central region AA1, and at least two signal lines 131 in a signal line group 130 can be electrically connected within the central region AA1 via the bridging portion 140. This allows multiple electrically connected signal lines 131 to share electrical connections with bonding pins within the bonding region BB. On one hand, this eliminates the need for the signal lines 131 to extend along the first direction X within the lower edge region AA22, reducing the space occupied by the signal lines 131 within the lower edge region AA22 and thus reducing the width of the lower edge region AA22, thereby facilitating the achievement of a narrow bezel for the substrate 100. On the other hand, it also improves the ease of electrical connection between multiple signal lines 131 and bonding pins, thereby improving the wiring convenience of the substrate 100.

[0423] As can be seen from the above, in some examples, the first type of first conductive pattern 171a is electrically connected to the first voltage line group 150, and the first type of second conductive pattern 172a is electrically connected to the second voltage line group 160. In some examples, such as Figure 6A and Figure 6B As shown, after the plurality of first voltage lines 151 in the first voltage line group 150 are electrically connected through the bridging portion 140, they are electrically connected to the bonding pins through the first type of first conductive pattern 171a. After the plurality of second voltage lines 161 in the second voltage line group 160 are electrically connected through the bridging portion 140, they are electrically connected to the bonding pins through the first type of second conductive pattern 172a.

[0424] Understandably, after multiple first voltage lines 151 are electrically connected, and then electrically connected to bonding pins via a first type of first conductive pattern 171a, the number of bonding pins electrically connected to the multiple first voltage lines 151 can be reduced, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing costs.

[0425] Similarly, after multiple second voltage lines 161 are electrically connected, and then electrically connected to bonding pins via a first type of second conductive pattern 172a, the number of bonding pins electrically connected to the multiple second voltage lines 161 can be reduced, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing costs.

[0426] In some examples, such as Figure 6A As shown, a bridging portion 140, which electrically connects at least two signal lines 131, is located between two adjacent device groups 110 along the second direction Y. This arrangement allows the bridging portion 140 to be located outside the area where the device group 110 is located, reducing the impact of the bridging portion 140 on the light emission of the electronic components 120 in the device group 110 and improving the reliability of the substrate 100.

[0427] In other examples, such as Figure 6B As shown, the bridging portion 140, which electrically connects at least two signal lines 131, may overlap with the area where the device group 110 is located, thereby improving the wiring flexibility of the substrate 100.

[0428] In some embodiments, such as Figure 6B As shown, at least one first voltage line 151 in the first voltage line group 150 includes at least two first sub-sections 152, which are spaced apart along the second direction Y. A plurality of bridging sections 140 include a plurality of fifth bridging sections 145, which electrically connect two adjacent first sub-sections 152 within the same first voltage line 151.

[0429] like Figure 6B As shown, two adjacent first sub-sections 152 in the same first voltage line 151 are connected by a fifth bridging portion 145. Understandably, by adjusting the thickness and width of the fifth bridging portion 145, its current-carrying capacity can be adjusted. In some examples, the fifth bridging portion 145 can be set to have a larger width and thickness to improve its current-carrying capacity. In other examples, the fifth bridging portion 145 can be set to have a smaller width and thickness to meet different application requirements.

[0430] Understandably, the greater the current carrying capacity of the fifth bridging portion 145, the smaller the current carrying capacity of the first sub-portion 152 can be, which helps to reduce the width of the first sub-portion 152 along the first direction X, which helps to achieve a narrow bezel of the substrate 100, and also helps to reduce the thickness of the first sub-portion 152, thereby reducing the cost of the substrate 100.

[0431] In some examples, such as Figure 6BAs shown, each first voltage line 151 in the first voltage line group 150 includes at least two first sub-sections 152. For example, at least one first sub-section 152 of one first voltage line 151 can be electrically connected to the first sub-section 152 of another first voltage line 151 via a bridging portion 140.

[0432] This allows the first sub-sections 152 to be electrically connected between different first voltage lines 151, thereby reducing the voltage drop on the first sub-sections 152, which is beneficial for reducing the width of the first sub-sections 152 along the first direction X, and also for reducing the thickness of the first sub-sections 152, thus reducing the cost of the substrate 100.

[0433] In some examples, such as Figure 6B As shown, any first voltage line 151 includes two first sub-sections 152. For example, the two first sub-sections 152 include a first first sub-section 152a and a second first sub-section 152b. The first first sub-section 152a and the second first sub-section 152b are located on either side of the center line Q of the central region AA1 along the second direction Y. It can be understood that the center line Q extends along the first direction X and is located at the center of the central region AA1 along the second direction Y.

[0434] It should be noted that the first first sub-part 152a and the second first sub-part 152b are only used to distinguish between two different first sub-parts 152, and do not further limit the first sub-part 152.

[0435] In some examples, such as Figure 6B As shown, the first sub-part 152a is farther away from the binding area BB relative to the second sub-part 152b.

[0436] In some examples, such as Figure 6B As shown, the first first sub-sections 152a of a plurality of first voltage lines 151 are electrically connected through a bridging section 140, and the second first sub-sections 152a of the plurality of first voltage lines 151 are also electrically connected through a bridging section 140. One of the first first sub-sections 152a of a first voltage line 151 is electrically connected to the second first sub-section 152a of that first voltage line 151 through a fifth bridging section 145.

[0437] For example, after the first first sub-section 152a of the plurality of first voltage lines 151 is electrically connected, it can be electrically connected to the conductive pattern 170 (e.g., a first type of first conductive pattern 171a) via the bridging portion 140. After the second first sub-section 152b of the plurality of first voltage lines 151 is electrically connected, it can also be electrically connected to the conductive pattern 170 (e.g., a first type of first conductive pattern 171a) via the bridging portion 140.

[0438] Understandably, by setting the first first sub-section 152a and the second first sub-section 152b along the second direction Y, located on both sides of the center line Q of the central region AA1, and electrically connecting the first first sub-section 152a of the plurality of first voltage lines 151 and the second first sub-section 152b of the plurality of first voltage lines 151, the current on each first sub-section 152 (including the first first sub-section 152a and the second first sub-section 152b) can be reduced.

[0439] For example, a first voltage line 151 includes two first sub-sections 152, each of which carries half the current value required for a single first voltage line 151. Because each first sub-section 152 carries a smaller current, the design requirements (e.g., line width, line thickness, or materials used) of the first sub-section 152 can be reduced. In some examples, this arrangement allows for a significant reduction in the thickness of the first sub-sections 152 included in the first voltage line 151, reducing material usage and lowering the cost of the substrate 100.

[0440] In some embodiments, such as Figure 6B As shown, at least one second voltage line 161 in the second voltage line group 160 includes at least two second sub-sections 162, which are spaced apart along a second direction Y. A plurality of bridging sections 140 include a plurality of sixth bridging sections 146, which electrically connect two adjacent second sub-sections 162 within the same second voltage line 161.

[0441] like Figure 6B As shown, two adjacent second sub-sections 162 in the same second voltage line 161 are connected by a sixth bridging portion 146. Understandably, by adjusting the thickness and width of the sixth bridging portion 146, its current-carrying capacity can be adjusted. In some examples, the sixth bridging portion 146 can be configured with a larger width and thickness to improve its current-carrying capacity. In other examples, the sixth bridging portion 146 can be configured with a smaller width and thickness to meet different application requirements.

[0442] Understandably, the greater the current carrying capacity of the sixth bridging portion 146, the smaller the current carrying capacity of the first sub-portion 152 can be, which helps to reduce the width of the first sub-portion 152 along the first direction X, facilitates the realization of a narrow bezel of the substrate 100, and also helps to reduce the thickness of the first sub-portion 152, thereby reducing the cost of the substrate 100.

[0443] In some examples, such as Figure 6BAs shown, each of the second voltage lines 161 in the second voltage line group 160 includes at least two second sub-sections 162. For example, at least one second sub-section 162 of one second voltage line 161 can be electrically connected to a second sub-section 162 of another second voltage line 161 via a bridging portion 140.

[0444] This allows the second sub-sections 162 to be electrically connected between different second voltage lines 161, thereby reducing the voltage drop on the second sub-sections 162, which is beneficial for reducing the width of the first sub-section 152 along the first direction X, and also for reducing the thickness of the first sub-section 152, thus reducing the cost of the substrate 100.

[0445] In some examples, such as Figure 6B As shown, any second voltage line 161 includes two second sub-sections 162. For example, the two second sub-sections 162 include a first second sub-section 162a and a second second sub-section 162b. The first second sub-section 162a and the second second sub-section 162b are located on both sides of the center line Q of the central region AA1 along the second direction Y.

[0446] It should be noted that the first second sub-part 162a and the second second sub-part 162b are only used to distinguish between two different second sub-parts 162, and do not further limit the second sub-part 162.

[0447] In some examples, such as Figure 6B As shown, the first second sub-part 162a is farther away from the binding area BB relative to the second second sub-part 162b.

[0448] In some examples, such as Figure 6B As shown, the first second sub-sections 162a of a plurality of second voltage lines 161 are electrically connected via bridging sections 140, and the second second sub-sections 162a of the plurality of second voltage lines 161 are also electrically connected via bridging sections 140. The first second sub-section 162a of one of the second voltage lines 161 is electrically connected to the second second sub-section 162a of that second voltage line 161 via a sixth bridging section 146.

[0449] For example, after the first second sub-section 162a of the plurality of second voltage lines 161 is electrically connected, it can be electrically connected to the conductive pattern 170 (e.g., a first type of second conductive pattern 172a) via the bridging portion 140. After the second second sub-section 162b of the plurality of second voltage lines 161 is electrically connected, it can also be electrically connected to the conductive pattern 170 (e.g., a first type of second conductive pattern 172a) via the bridging portion 140.

[0450] Understandably, by setting the first second sub-section 162a and the second second sub-section 162b along the second direction Y, located on both sides of the center line Q of the central region AA1, and electrically connecting the first second sub-section 162a of the plurality of second voltage lines 161 and the second second sub-section 162b of the plurality of second voltage lines 161, the current on each second sub-section 162 (including the first second sub-section 162a and the second first sub-section 152b) can be reduced.

[0451] For example, a second voltage line 161 includes two second sub-sections 162, each of which carries half the current value required to carry a single second voltage line 161. Because each second sub-section 162 carries a smaller current, the design requirements for the second sub-sections 162 (e.g., line width, line thickness, or materials used) can be reduced. In some examples, this arrangement allows for a significant reduction in the thickness of the second sub-sections 162 of the second voltage line 161, reducing material usage and lowering the cost of the substrate 100.

[0452] In some embodiments, such as Figure 6C As shown, at least two second conductive patterns 172 arranged along the second direction Y constitute a second conductive pattern column 183. The second conductive pattern column 183, which is adjacent to an edge P of the substrate 101 along the first direction X, overlaps with the region where a group of devices 110 arranged in a row along the second direction Y is located.

[0453] Understandably, such as Figure 6C As shown, the second conductive pattern column 183 includes a plurality of second conductive patterns 172. In some examples, such as Figure 6C As shown, any one of the second conductive patterns 172 in the second conductive pattern column 183 is adjacent to the edge P of the substrate 101 along the first direction X.

[0454] The area where the second conductive pattern column 183 overlaps with the area where a column of device groups 110 arranged along the second direction Y is located, that is, multiple second conductive patterns 172 in the second conductive pattern column 183 are located within the area where the column of device groups 110 arranged along the second direction Y is located. It can be understood that the area where a column of device groups 110 is located includes the area where each device group 110 in the column of device groups 110 is located, as well as the area between two adjacent device groups 110 in the column of device groups 110 along the second direction Y.

[0455] Understandably, the overlapping of the second conductive pattern column 183 with the area where a column of device groups 110 arranged along the second direction Y is located can improve the area utilization of the substrate 101, allowing more device groups 110 to be arranged on the substrate 101.

[0456] In some examples, the second conductive pattern column 183 is located in the region where a group of devices 110 is adjacent to the edge P of the substrate 101 along the first direction X. This arrangement can reduce the distance between the multiple second conductive patterns 172 in the second conductive pattern column 183 and one side edge P of the substrate 101 along the first direction X, thereby reducing the distance between the second conductive pattern column 183 and the side edge region AA21, and improving the ease of electrical connection between the signal line 131 (e.g., the second voltage line 161) in the side edge region AA21 and the second conductive pattern column 183.

[0457] In some examples, such as Figure 6C As shown, the signal line 131 (e.g., the second voltage line 161) within the side edge region AA21 can be electrically connected to the bonding pins within the bonding region BB via the second conductive pattern array 183. That is, by setting the second conductive pattern array 183, the signal line 131 within the side edge region AA21 does not need to extend into the lower edge region AA22, which helps to reduce the width of the lower edge region AA22, thereby facilitating the realization of a narrow bezel (lower bezel) of the substrate 100.

[0458] In some examples, such as Figure 6C As shown, the first driving chip 103 is located within the central region AA1, and the second voltage line 161 extends into the central region AA1 and is electrically connected to the first driving chip 103. This arrangement eliminates the need for the first driving chip 103 to occupy the space of the side edge region AA21, thereby reducing the width of the side edge region AA21 along the first direction X, which in turn facilitates the realization of a narrow bezel on the substrate 100.

[0459] In some examples, when a group of devices 110 is electrically connected to a plurality of first driver chips 103, such as Figure 6C As shown, the second voltage line 161 includes a plurality of sub-segments 1621, which are spaced apart along the second direction Y, and one sub-segment 1621 is electrically connected to a first driver chip 103.

[0460] Understandably, the bridging portion 140 may have a certain angle with either the first direction X or the second direction Y, such as... Figure 6C As shown, the bridging part 140X is neither parallel to the first direction X nor parallel to the second direction Y.

[0461] Figure 7A This is a structural diagram of a substrate according to some other embodiments. Figure 7B for Figure 7A A magnified view of a portion of region 1.

[0462] As can be seen from the above, in some examples, by setting the conductive pattern 170 and the bridging part 140, multiple signal lines 131 in a signal line group 130 can be electrically connected, and the voltage drop of the signal line 131 can be reduced by the compensation of the conductive pattern 170.

[0463] In some examples, the device area AA is divided into P regions along the first direction X. The P regions are arranged adjacent to each other along the first direction X, and each region has at least two columns of device groups 110. Understandably, the number of columns of device groups 110 in different regions can be the same or different. In some examples, the absolute value of the difference in the number of columns of device groups 110 in any two regions is less than or equal to 2.

[0464] Understandably, one region corresponds to one bound region (BB). In some examples, such as... Figure 7A and Figure 7B As shown, the substrate 100 has four bonding regions BB, that is, the device group AA can be divided into four regions (P=4) along the first direction X.

[0465] Understandably, at least two groups of devices 110 belonging to the same region are connected to the same bonding area BB. For example, within the same region, multiple signal line groups 130 connected to a bonding area BB include a first voltage line group 150 and a second voltage line group 160.

[0466] For example, taking any region in device area AA as an example, at least two first voltage lines 151 in the first voltage line group 150 are electrically connected through a second type of first conductive pattern 171b located in device group AA, and then electrically connected to a bonding pin in a bonding area BB through two first type of first conductive patterns 171a. At least two second voltage lines 161 in the second voltage line group 160 are electrically connected through a second type of second conductive pattern 172b located in device group AA, and then electrically connected to a bonding pin in a bonding area BB through two first type of second conductive patterns 172a.

[0467] Understandably, since there are four bonding areas BB, four flexible circuit boards 105 are required to be electrically connected to the bonding areas BB. In other words, a larger number of bonding areas BB will increase the number of flexible circuit boards 105, thereby increasing the cost.

[0468] Figure 8A This is a structural diagram of a substrate according to some other embodiments. Figure 8B for Figure 8A A magnified view of a portion of region 2 in the middle. Figure 8C for Figure 8A A magnified view of a portion of region 3 in the middle. Figure 8D for Figure 8A A magnified view of a portion of region 4 in the middle.

[0469] Based on this, in some embodiments, such as Figure 8A and Figure 8B As shown, the substrate 100 has only one bonding region BB. In some examples, the bonding region BB coincides with the center line of the device group AA along the second direction Y.

[0470] Understandably, since the substrate 100 is provided with only one bonding area BB, the signal lines 131 in the multiple signal line groups 130 (including the first voltage line group 150 and the second voltage line group 160) need to be electrically connected to the bonding pins in the same bonding area BB.

[0471] Understandably, setting the number of bonding areas BB to one can reduce the number of flexible circuit boards 105, thereby reducing costs.

[0472] The following example illustrates how the first voltage line group 150 and the second voltage line group 160 are electrically connected to the bonding area BB.

[0473] As described above, at least two first conductive patterns 171 arranged along the first direction X constitute a first conductive pattern row 181. It is understood that in some examples, the number of first conductive pattern rows 181 can be at least two. In other examples, the number of first conductive pattern rows 181 can be one. The embodiments of this disclosure use a single first conductive pattern row 181 as an example to illustrate the electrical connection relationship between the first voltage line group 150 and the bonding area BB.

[0474] In some examples, such as Figure 8B and Figure 8C As shown, at least two first conductive patterns 171 arranged along the second direction Y constitute a first conductive pattern column 184. Figure 8C As shown, the first conductive pattern row 181 is electrically connected to the first conductive pattern column 184, as follows: Figure 8B As shown, the first conductive pattern 171a is electrically connected to the first conductive pattern column 184. Understandably, the first conductive pattern row 181 and the first conductive pattern column 184 can be located within the central region AA1 of the device region AA to avoid the first conductive pattern row 181 and the first conductive pattern column 184 occupying the space of the edge region AA2 (including the side edge region AA21 and the lower edge region AA22), which is beneficial to realizing the narrow bezel of the substrate 100.

[0475] In some examples, such as Figure 8CAs shown, multiple first voltage lines 151 in the first voltage line group 150 can be electrically connected via a first conductive pattern row 181. A first conductive pattern 171 in the first conductive pattern column 184 is electrically connected to the first conductive pattern row 181 via a bridging portion 140. As... Figure 8B As shown, another first conductive pattern 171 in the first conductive pattern column 184 is electrically connected to the first type of first conductive pattern 171a through the bridging part 140, thereby enabling the multiple first voltage lines 151 in the first voltage line group 150 to be electrically connected to the bonding pins.

[0476] Understandably, since the multiple first conductive patterns 171 in the multiple first conductive pattern columns 184 are arranged in a column along the second direction Y, the multiple first voltage lines 151 after electrical connection can be electrically connected to the bonding pins in a bonding area BB through the first type of first conductive pattern 171a. That is, by setting the first conductive pattern row 181 and the first conductive pattern column 184, the multiple first voltage lines 151 can be electrically connected to the bonding pins in a bonding area BB.

[0477] This reduces the number of flexible circuit boards 105 that are bonded to the bonding pins, thereby reducing the cost of the substrate 100.

[0478] In some examples, the first conductive pattern column 184 is electrically connected to the bonding pins via a first type of first conductive pattern 171a. Reducing the number of first type of first conductive patterns 171a can reduce the number of bonding pins electrically connected to the first voltage line 151, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing the cost of the substrate 100.

[0479] That is, by setting the first conductive pattern row 181 and the first conductive pattern column 184, the substrate 100 can reduce the number of bonding areas BB and the number of bonding pins electrically connected to the first voltage line group 150 while achieving a narrow bezel, thereby reducing costs.

[0480] Furthermore, by setting up electrical connections through multiple first voltage lines 151 via a first conductive pattern array 184 to bond pins within a bond area BB, the number of bridging portions 140 can be reduced, thereby simplifying the fabrication process of the substrate 100, improving the production efficiency of the substrate 100, and reducing costs.

[0481] In some embodiments, the first conductive pattern row 181 is located at the center of the device region AA along the second direction Y.

[0482] Understandably, the first conductive pattern row 181 is positioned at the center of the device region AA along the second direction Y, so that multiple first voltage lines 151 can be electrically connected at the center position along the second direction Y. In this way, the current value that the first voltage line 151 needs to carry is half the current value that the first voltage line 151 needs to carry without the first conductive pattern row 181.

[0483] That is, by setting the first conductive pattern row 181 at the center of the device region AA along the second direction Y, the current value that the first voltage line 151 needs to carry can be reduced, the risk of overload of the first voltage line 151 can be reduced, and the reliability of the substrate 100 can be improved. In addition, it can also facilitate the thinning of the first voltage line 151 and reduce the cost of the substrate 100.

[0484] In some examples, the first conductive pattern row 181 is positioned at the center of the device region AA along the second direction Y, such that the thickness of the first voltage line 151 can be reduced to half the thickness of the first voltage line 151 when the first conductive pattern row 181 is not provided.

[0485] As can be seen from the above, in some embodiments, such as Figure 8D As shown, in a second voltage line group 160, a plurality of second voltage lines 161 are interconnected on the side away from the bonding region BB along the second direction Y. Furthermore, at least two second conductive patterns 172 arranged along the second direction Y constitute a second conductive pattern column 183.

[0486] In some embodiments, such as Figure 8B and Figure 8D As shown, the second conductive pattern array 183 is electrically connected to the side of a plurality of second voltage lines 161 in a second voltage line group 160 away from the bonding region BB, and the first type of second conductive pattern 172a is electrically connected to the second conductive pattern array 183. It can be understood that the plurality of second voltage lines 161 in a second voltage line group 160 are interconnected on the side away from the bonding region BB along the second direction Y, so that the plurality of second voltage lines 161 in a second voltage line group 160 can be electrically connected.

[0487] like Figure 8B and Figure 8D As shown, in the second conductive pattern column 183, one second conductive pattern 172 is electrically connected to the end of one or more second voltage lines 161 away from the bonding region BB. Figure 8B As shown, another second conductive pattern 172 in the second conductive pattern column 183 is electrically connected to the first type of second conductive pattern 172a, so that a plurality of second voltage lines 161 can be electrically connected to the bonding pins through the second conductive pattern column 183.

[0488] Understandably, since the multiple second conductive patterns 172 in the multiple second conductive pattern columns 183 are arranged in a column along the second direction Y, the multiple second voltage lines 161 after electrical connection can be electrically connected to the bonding pins in a bonding area BB through the first type of second conductive pattern 172a. That is, by setting the second conductive pattern columns 183, the multiple second voltage lines 161 can be electrically connected to the bonding pins in a bonding area BB.

[0489] This reduces the number of flexible circuit boards 105 that are bonded to the bonding pins, thereby reducing the cost of the substrate 100.

[0490] In some examples, the second conductive pattern column 183 is electrically connected to the bonding pins via a first type of second conductive pattern 172a. Reducing the number of first type of second conductive patterns 172a can reduce the number of bonding pins electrically connected to the second voltage line 161, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing the cost of the substrate 100.

[0491] That is, by setting the second conductive pattern column 183, the substrate 100 can reduce the number of bonding areas BB and the number of bonding pins electrically connected to the second voltage line group 160 while achieving a narrow bezel, thereby reducing costs.

[0492] Furthermore, by setting up electrical connections through multiple second voltage lines 161 via a second conductive pattern array 183 to bond pins within a bond area BB, the number of bridging portions 140 can be reduced, thereby simplifying the fabrication process of the substrate 100, improving the production efficiency of the substrate 100, and reducing costs.

[0493] Understandably, a plurality of second voltage lines 161 in a second voltage line group 160 extend along the second direction Y, and one second voltage line 161 is located on the second side of a column of devices 110 electrically connected to the second voltage line 161. The plurality of second voltage lines 161 do not extend to the lower edge region AA22, but are interconnected on the side away from the bonding region BB along the second direction Y. Thus, the second conductive pattern column 183 can be electrically connected to the plurality of second voltage lines 161 on the side away from the bonding region BB along the second direction Y.

[0494] That is, in the embodiments of this disclosure, a plurality of second voltage lines 161 in the second voltage line group 160 can be interconnected on the side away from the bonding area BB along the second direction Y, and electrically connected to the bonding pin through a column of second conductive patterns 183.

[0495] Understandably, the multiple second voltage lines 161 in a second voltage line group 160 are interconnected on the side away from the bonding region BB along the second direction Y, increasing the area of ​​the conductive structure (multiple signal line groups 130 and multiple conductive patterns 170) projected onto the substrate 101. For example, when the material of the conductive layer is Cu, the interconnection of multiple second voltage lines 161 in a second voltage line group 160 on the side away from the bonding region BB along the second direction Y can increase the ratio of the area of ​​Cu in the conductive layer to the area of ​​the substrate 101, thereby improving the ESD (Electro Static Discharge) capability of the substrate 100 and improving the reliability of the substrate 100.

[0496] In some examples, such as Figures 8B to 8D As shown, the substrate 100 also includes a packaging portion 122. The packaging portion 122 is located on the side of the electronic component 120 away from the substrate 101 and covers the electronic component 120.

[0497] Understandably, the encapsulation part 122 can protect the electronic component 120. On the one hand, it prevents external water or oxygen from corroding the electronic component 120; on the other hand, it reduces the risk of the electronic component 120 being scratched and dropped under external force, extends the service life of the electronic component 120, and improves the reliability of the substrate 100.

[0498] In some examples, when the electronic component 120 is a light-emitting diode (LED), the encapsulation portion 122 covering the LED is made of a transparent material (e.g., transparent silicone) to reduce the light obstruction by the encapsulation portion 122. When the electronic component 120 is not a light-emitting element or a photosensitive element, the encapsulation portion 122 can be made of a non-transparent material.

[0499] In some examples, the package portion 122 may be mushroom-shaped or approximately mushroom-shaped. Understandably, the shape of the package portion 122 covering different electronic components 120 may be the same or different.

[0500] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A substrate having a plurality of edges; the substrate including a device region and at least one bonding region, the bonding region being adjacent to any edge of the substrate relative to the device region; the substrate comprising: Substrate; Multiple device groups are located on one side of the substrate, and the multiple device groups are located in the device region; The plurality of device groups are arranged along a first direction and a second direction, respectively; the first direction and the second direction intersect each other and are parallel to the substrate; each device group includes at least one electronic component; Multiple signal line groups are located on the same side of the substrate as the multiple device groups; each signal line group includes multiple signal lines; the multiple signal lines all extend along the second direction and are spaced apart along the first direction; any one signal line extends from the bonding region to the device region, and any one of the signal lines is electrically connected to a column of the device groups arranged along the second direction; as well as, Multiple conductive patterns are located on the same side of the substrate as the multiple device groups; at least one of the multiple conductive patterns is located within the region of one of the device groups. And / or, at least one of the plurality of conductive patterns is located in the region between two adjacent groups of devices; Wherein, at least one of the signal lines in at least one of the signal line groups is electrically connected to one of the conductive patterns; A first driving chip is electrically connected to at least one of the device groups. The number of first driving chips electrically connected to a column of the device groups is multiple, and the multiple first driving chips are cascaded. The plurality of signal line groups include: A first voltage line group, comprising a plurality of first voltage lines; The plurality of conductive patterns includes a plurality of first conductive patterns, and the plurality of first conductive patterns are electrically connected to at least one first voltage line in the first voltage line group. The plurality of signal line groups also include: The second voltage line group includes a plurality of second voltage lines; The plurality of conductive patterns further includes a plurality of second conductive patterns, the plurality of second conductive patterns being electrically connected to at least one second voltage line in the second voltage line group; The substrate further includes: a plurality of first bridging portions, at least one first conductive pattern being electrically connected to a first voltage line through the first bridging portion; at least one of the plurality of bridging portions is located outside the area where the device group is located.

2. The substrate according to claim 1, wherein, The plurality of conductive patterns are arranged on the same layer as the plurality of signal line groups.

3. The substrate according to claim 1, wherein, At least one of the plurality of first bridging portions is a bridging resistor.

4. The substrate according to claim 1, wherein, At least one of the first conductive patterns and one of the first voltage lines form an integral structure.

5. The substrate according to claim 1, wherein, At least two of the first conductive patterns are arranged along the first direction.

6. The substrate according to claim 5, wherein, At least two of the first conductive patterns arranged along the first direction constitute a first conductive pattern row, and the plurality of first conductive patterns constitute at least two first conductive pattern rows.

7. The substrate according to claim 6, wherein, The number of the first conductive pattern rows is two, and the number of the first conductive patterns included in the two first conductive pattern rows is different; the length of any device group along the second direction is L; along the second direction, one first conductive pattern row is closer to the bonding area than the other first conductive pattern row, and the interval between the two first conductive pattern rows along the second direction is in the range of 3L~5L.

8. The substrate according to claim 6, wherein, The plurality of device groups includes a first row of device groups, which is adjacent to the bonding area along the second direction; At least one of the first conductive pattern rows is located within the area where the first row of devices is located.

9. The substrate according to claim 1, wherein, The plurality of first conductive patterns includes a first type of first conductive pattern; One end of the first type of first conductive pattern is directly connected to the end of the bonding area near the device area, and the other end of the first type of first conductive pattern is electrically connected to the first voltage line group. The number of the first conductive patterns of the first type is 'a', where 'a' is less than the number of the first voltage lines in the first voltage line group, and 'a' is a positive integer.

10. The substrate according to claim 9, wherein, a is not greater than one-half of the number of the first voltage lines in the first voltage line group.

11. The substrate according to claim 10, further comprising: Multiple second bridging portions, at least one second conductive pattern is electrically connected to a second voltage line through the second bridging portion.

12. The substrate according to claim 11, wherein, At least one of the plurality of second bridging portions is a bridging resistor.

13. The substrate according to claim 1, wherein, At least one of the second conductive patterns and one of the second voltage lines form an integral structure.

14. The substrate according to claim 1, wherein, At least two of the second conductive patterns are arranged along the first direction.

15. The substrate according to claim 14, wherein, At least two second conductive patterns arranged along the first direction constitute a second conductive pattern row, and the plurality of second conductive patterns constitute at least two second conductive pattern rows.

16. The substrate according to claim 15, wherein, The number of the second conductive pattern rows is two, and the number of the second conductive patterns included in the two second conductive pattern rows is different; the length of any device group along the second direction is L; along the second direction, one second conductive pattern row is closer to the bonding area than the other second conductive pattern row, and the interval between the two second conductive pattern rows along the second direction is in the range of 3L~5L.

17. The substrate according to claim 15, wherein, The plurality of device groups includes a first row of device groups, which is adjacent to the bonding area along the second direction; At least one of the second conductive pattern rows is located within the area where the first row of devices is located.

18. The substrate according to claim 1, wherein, The plurality of second conductive patterns includes a first type of second conductive pattern; One end of the first type of second conductive pattern is directly connected to the end of the bonding area near the device area, and the other end of the first type of second conductive pattern is electrically connected to the second voltage line group. The number of the second conductive patterns in the first type is b, where b is less than the number of the second voltage lines in the second voltage line group, and b is a positive integer.

19. The substrate according to claim 18, wherein, Y is not greater than half the number of the second voltage lines in the second voltage line group.

20. The substrate according to claim 1, further comprising: Multiple third bridging portions, at least two of the first conductive patterns are electrically connected through the third bridging portions; And / or, Multiple fourth bridging portions, at least two of the second conductive patterns are electrically connected through the fourth bridging portions.

21. The substrate according to claim 1, wherein, In the same first voltage line group, at least two first voltage lines are interconnected on the side away from the bonding region along the second direction; and / or, In the same second voltage line group, at least two second voltage lines are interconnected on the side away from the bonding area along the second direction.

22. The substrate according to claim 1, wherein, The width of the first voltage line along the first direction ranges from 0.5mm to 1mm; and / or, the width of the second voltage line along the first direction ranges from 0.5mm to 1mm.

23. The substrate according to claim 1, wherein, Any one of the first voltage lines is located on the first side of a column of the device group electrically connected to the first voltage line along the first direction; any one of the second voltage lines is located on the second side of a column of the device group electrically connected to the second voltage line along the first direction.

24. The substrate according to claim 1, wherein, The number of the bonding areas is multiple, and multiple signal lines in one of the signal line groups are electrically connected to one of the bonding areas.

25. The substrate according to any one of claims 1 to 24, further comprising: An electrostatic loop is provided around the plurality of device groups and is electrically connected to the bonding area; The circuit board is electrically connected to the bonding area.

26. An electronic device comprising a substrate as claimed in any one of claims 1 to 25.

Images