Adjust host speed using free space values

Abstract

The method, system, and apparatus include receiving a current free space value and historical increment values. An increment value is calculated using the current free space value, a target free space value, and the historical increment values. An increment region is determined using the increment value. A new host rate is calculated using the determined increment region, the calculated increment value, and the historical increment value. The new host rate is sent to a host device, causing the host device to change its current host rate to the new host rate.

Description

Technical Field

[0001] This disclosure generally relates to host rate adjustment, and more specifically, to host rate adjustment using free space values. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 Example charts illustrating host speed and increment regions according to some embodiments of this disclosure.

[0006] Figure 3A , 3B The 3C specification describes a flowchart of an example method for adjusting host speed using free space values ​​according to some embodiments of the present disclosure.

[0007] Figure 4 This is a flowchart of an example method for adjusting host speed using free space values, according to some embodiments of the present disclosure.

[0008] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0009] This disclosure relates to adjusting host speed using free space values ​​in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0010] Memory devices can be non-volatile memory devices. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A die in a package may be assigned one or more channels for communication with a memory subsystem controller. Each die may consist of one or more planes. Planes may be divided into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane consists of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0011] Depending on the cell type, a cell can store one or more binary information bits and has various logic states related to the number of bits stored. Logic states can be represented by binary values ​​(e.g., "0" and "1") or combinations of such values. Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC can store one information bit and has two logic states.

[0012] Conventional memory systems receive data from the host system to write to memory, including non-volatile memory (e.g., NAND flash memory devices). NAND flash memory devices are subdivided into blocks of writable cells (e.g., pages). Pages are typically not overwritten. Therefore, free space must exist to write to the NAND flash memory device. To create free space, the memory subsystem performs a scrap collection process, which involves erasing all data from a block or a portion of a block while writing valid data to a new block. When the memory subsystem reaches a steady state, the amount of available free space is determined by the scrap collection rate (the rate at which space is freed) and the host rate (the rate at which space is consumed). When the scrap collection rate is higher than the host rate, there is plenty of free space, but files may be more scattered, resulting in higher random write input / output operations per second (IOPS). Conversely, when the host rate is higher than the scrap collection rate, there may not be enough available space, and the host may have to wait for scrap collection before writing, thus degrading performance.

[0013] This disclosure addresses the aforementioned and other shortcomings by adjusting the host speed based on the current and target free space. The amount of free space can be adjusted by changing the host speed. For example, increasing the host speed will reduce the amount of free space, and vice versa. By adjusting the host speed to achieve the desired amount of free space, the memory subsystem can achieve optimal random write IOPS while reducing the likelihood of the host waiting for discarded items to be collected and written.

[0014] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0015] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0016] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0017] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0018] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110.

[0019] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 For example, memory subsystem 110 is described. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0020] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0021] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0022] Although a non-volatile memory device (e.g., NAND-type memory (e.g., 2D NAND, 3D NAND) and a 3D cross-point array of non-volatile memory cells) is described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0023] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled by controller 115 on a command bus). The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0024] The memory subsystem controller 115 may include a processing means 117 (e.g., a processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0025] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem 110).

[0026] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations associated with memory device 130, such as wear leveling operations, discard item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses). The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0027] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0028] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 from an external source (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] The memory subsystem 110 includes a host rate adjuster 113 capable of changing the host rate based on the amount of free space. In some embodiments, the controller 115 includes at least a portion of the host rate adjuster 113. For example, the controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the host rate adjuster 113 is part of the host system 120, an application, or an operating system.

[0030] The host rate adjuster component 113 can adjust the host rate based on the difference between the current free space and the target free space, and the difference between the previous free space and the target free space. Further details regarding the operation of the host rate adjuster 113 are described below.

[0031] Figure 2 This describes an example host rate and free space graph 200 according to some embodiments of the present disclosure. The host rate graph 200 includes a target free space line 205, a positive ideal free space line 210, a negative ideal free space line 215, a positive fine-tuning free space line 220, a negative fine-tuning free space line 225, a positive coarse-tuning free space line 230, a negative coarse-tuning free space line 235, a positive steady-state free space line 240, and a negative steady-state free space line 245.

[0032] The vertical axis of the host speed and free space chart 200 represents the incremental free space value (i.e., the incremental value). Host speed adjuster (e.g.) Figure 1 The host rate adjuster 113) determines the increment value using the current free space value, the target free space value, and historical increment values. The current free space value represents the memory device (e.g., one that does not store data or does not store valid data) that does not store data. Figure 1 The value of the amount of space in the memory device 140. For example, free space may contain scan space for source blocks to be deleted during the discarded item collection. The host rate adjuster 113 determines the increment value at a given time t by the following equation: DeltaValue(t) = FreeSpace(t) - TargetFreeSpace + HistoricDeltaValue(t), where (t) represents the time of the current host rate adjustment. The historical increment value is a value representing one or more previous increment values ​​from one or more host adjustment iterations performed by the host rate adjuster 113. For example, the historical increment value is the increment value used for a previous host rate adjustment and is determined by the following equation: HistoricDeltaValue(t) = FreeSpace(t-1) - TargetFreeSpace + HistoricDeltaValue(t-1), where (t-1) represents the time of the previous host rate adjustment. In some embodiments, the host rate adjuster 113 also tracks the number of stored samples and clears HistoricDeltaValue when the number of stored samples reaches a sample threshold. The sampling threshold can be predetermined or determined based on system characteristics (e.g., frequency adjustment based on desired host rate).

[0033] Target free space line 205 indicates the memory subsystem (e.g. Figure 1The optimal free space of the memory subsystem 110. The target free space line 205 (i.e., the target free space value) is a free space value that indicates the balance between the generation of free space (e.g., as a result of the collection of discarded items) and the consumption of free space (e.g., attributable to host writes). Each of the positive free space lines 210, 220, 230, and 240 indicates a positive difference (i.e., an increment) between the free space value and the target free space line 205. In other words, positive free space lines 210, 220, 230, and 240 represent free space values ​​greater than the target free space line 205. Conversely, each of the negative free space lines 215, 225, 235, and 245 indicates a negative difference (i.e., an increment) between the free space value and the target free space line 205, meaning that the free space value is less than the target free space line 205.

[0034] The actual incremental free space values ​​of free space lines 210, 215, 220, 225, 230, 235, 240, and 245 are calculated using their relationship to the value of the target free space line 205. Each of the free space line pairs—positive and negative ideal free space lines 210 and 215, positive and negative fine-tuning free space lines 220 and 225, positive and negative coarse-tuning free space lines 230 and 235, and positive and negative steady-state free space lines 240 and 245—has an absolute value equal to that of the corresponding pair. The value of the target free space line 205 is represented by TargetFreeSpace. The remaining free space lines are calculated based on FS. target The calculations are as follows: The values ​​of the ideal free space lines 210 and 215 are derived from... This indicates that the values ​​of the free space lines 220 and 225 were fine-tuned from... This indicates that the values ​​of the coarse adjustment free space lines 230 and 235 are determined by... This indicates that the values ​​of the steady-state free space lines 240 and 245 are determined by... express.

[0035] Each of the values ​​a, b, c, and d depends on the host system and the memory subsystem (e.g., Figure 1The requirements and advantages of the host system 120 and memory subsystem 110 may differ. For example, a system with a higher performance consistency target may also have lower values ​​for a, b, c, and d. The performance consistency target is measured using the slowest IOPS at a given percentile divided by the average IOPS. For example, performance consistency can be measured using the slowest IOPS at the 99.9th percentile divided by the average IOPS, resulting in a performance consistency target of 0.1%. However, the corresponding tiers of the values ​​a, b, c, and d remain constant. The maximum value is a, then b, then c, and the minimum value is d. In some embodiments, the differences between the values ​​also remain constant. For example, the maximum difference between consecutive values ​​is between a and b, then between b and c, and the minimum difference between consecutive values ​​is between c and d. In one such embodiment, a = 64, b = 16, c = 4, and d = 2. In this embodiment, the ideal free space lines 210 and 215 are... It indicates that the free space lines 220 and 225 have been fine-tuned. This indicates that the coarse adjustment free space lines 230 and 235 are... This indicates that the steady-state free space lines 240 and 245 are... express.

[0036] The host rate graph 200 also includes regions between free space lines, including an ideal region 255, a positive fine-tuning region 260, a negative fine-tuning region 265, a positive buffer 270, a negative buffer 275, a positive coarse-tuning region 280, and a negative coarse-tuning region 285. Each of these regions indicates a continuous range of incremental free space values ​​between a pair of corresponding free space lines. For example, the ideal region 255 is the range of values ​​between the positive ideal free space line 210 and the negative ideal free space line 215. The positive fine-tuning region 260 is the range of values ​​between the positive fine-tuning free space line 220 and the positive ideal free space line 210. The positive buffer 270 is the range of values ​​between the positive coarse-tuning free space line 230 and the positive fine-tuning free space line 220. The positive coarse-tuning region 280 is the range of values ​​between the positive steady-state free space line 240 and the positive coarse-tuning free space line 230. The negative fine-tuning region 265 is the range of values ​​between the negative fine-tuning free space line 225 and the negative ideal free space line 215. The negative buffer 275 is the range of values ​​between the negative coarse-adjustment free space line 235 and the negative fine-adjustment free space line 225. The negative coarse-adjustment zone 285 is the range of values ​​between the negative steady-state free space line 245 and the negative coarse-adjustment free space line 235.

[0037] As explained above, the maximum value is a, then b, then c, and the minimum value is d. Similarly, in some embodiments, the maximum difference between consecutive values ​​is between a and b, then between b and c, and the minimum difference between consecutive values ​​is between c and d. In such embodiments, the ideal region 255 is the smallest region, followed by fine-tuning regions 260 and 265, then buffers 270 and 275, and coarse-tuning regions 280 and 285 are the largest regions.

[0038] Host rate regulator (e.g.) Figure 1The host rate adjuster 113 updates the host rate according to the host rate chart 200. In some embodiments, the host rate adjuster 113 updates the scrap collection rate instead. Because the scrap collection rate is the reciprocal of the host rate (i.e., host rate + scrap collection rate = constant), embodiments using the scrap collection rate will have the reverse operation (e.g., increasing the scrap collection rate instead of decreasing the host rate). For fine-tuning zones 260 and 265, the host rate adjuster 113 increases or decreases the host rate by a fine-tuning value β. The host rate adjuster 113 determines whether to increase or decrease the host rate (i.e., determine the adjustment polarity) based on the increment value and historical increment values. The host rate adjuster 113 compares the historical increment value with the polarity of the increment value. When the historical increment value has the opposite polarity to the increment value, the increment free space has moved from one side of the ideal free space line 210 to the fine-tuning zone 260 or 265 on the other side. For example, when the historical increment value is negative and the increment value is positive, the incremental free space has moved from below the target free space line 205 to the positive fine-tuning zone 260 above the target free space line 205. Therefore, the host rate adjuster 113 increases the host rate by the fine-tuning value β to allow the host to consume free space at a rate exceeding the free space released by discarded items, ultimately causing the incremental free space value to decrease closer to the ideal zone 255 and the target free space line 205. When the historical increment value and the increment value have the same polarity, the incremental free space has remained on the same side of the ideal free space line 210. Previous increment values ​​may have been in the coarse-tuning zones 280 and 285, buffer zones 270 and 275, fine-tuning zones 260 and 265, or the ideal zone 255. Therefore, the host rate adjuster 113 adjusts the host rate based on the difference between the increment value and the historical increment value. For example, when both the historical increment value and the increment value are positive and the increment value is greater than the historical increment value, the incremental free space has moved away from the target free space line 205. Therefore, the host rate adjuster 113 increases the host rate by the fine-tuning value β to consume more free space, thereby ultimately causing the incremental free space value to decrease closer to the ideal region 255 and the target free space line 205. When both the historical incremental value and the incremental value are positive but the incremental value is less than the historical incremental value, the incremental free space has shifted towards the target free space line 205. To prevent overcorrection, the host rate adjuster 113 reduces the host rate by the fine-tuning value β to create more free space.

[0039] The fine-tuning value β is determined based on performance consistency targets. For example, for performance consistency measured using the slowest IOPS at the 99.9th percentile divided by the average IOPS, the performance consistency target is 0.1%. Therefore, to achieve the performance consistency target, any adjustments to the host rate should be less than 0.1%. Consequently, the fine-tuning value β needs to be at least less than the performance consistency target.

[0040] In some embodiments, when the system does not have time for proper calibration, the host rate adjuster 113 uses hysteresis to prevent rapid host rate switching. For example, instead of comparing the incremental value with historical incremental values, the host rate adjuster 113 compares the incremental value with a hysteresis condition. The host rate regulator 113 compares the historical increment value with the hysteresis buffer. When the increment value is outside this hysteresis buffer region, the host rate regulator 113 changes the host rate, thereby allowing the system time to stabilize. The host rate regulator 113 can use the following equation... and To determine whether to adjust the host rate. The value of e can be preset or determined by several factors, including the system's natural hysteresis. For example, e depends on the time it takes for the free space to change in response to a change in the host rate or on the time interval between host rate changes. Therefore, the longer the free space takes to change in response to a change in the host rate, the higher the value of e. Additionally, in embodiments with this hysteresis effect, the host rate adjuster 113 does not always update the host rate while in fine-tuning zones 260 and 265. In some embodiments, when the host rate adjuster 113 does not update the host rate, these attempts are tracked and may be represented by NumAttempts. In such embodiments, the host rate adjuster 113 divides the increment value by the number of attempts and compares it to the hysteresis buffer. The host rate adjuster 113 may use the following equation... and To determine whether to adjust the host rate, NumAttempts = 1 for the first attempt and increments by 1 each time. In some embodiments, NumAttempts is set to 0 when the number of stored samples reaches a sample threshold to prevent the system from getting stuck in fine-tuning areas 260 and 265.

[0041] For ideal zone 255 and buffers 270 and 275, host rate adjuster 113 maintains the current host rate. For example, host rate adjuster 113 sets the host rate to be equal to the previous host rate or otherwise does not change the host rate. When in ideal zone 255, the host rate is already ideal and does not need to be changed. When in buffers 270 and 275, the host rate is maintained to avoid host rate overcorrection. Therefore, buffers 270 and 275 provide a range of free space in which the host rate remains unchanged, thereby allowing the effects of previous host rate changes to be seen in the available free space. Buffers 270 and 275 allow host rate adjuster 113 to slowly adjust the host rate to ideal zone 255, thereby avoiding significant overcorrection.

[0042] For coarse adjustment zones 280 and 285, host rate adjuster 113 increases or decreases the host rate by one of the coarse adjustment values ​​α1 or α2. Host rate adjuster 113 determines whether to increase or decrease the host rate (i.e., determine the adjustment polarity) based on the increment value, the current free space value, historical increment values, and the target free space value. Host rate adjuster 113 determines whether to use coarse adjustment value α1 or α2 based on a comparison of historical increment values ​​and the polarity of the increment values.

[0043] When the historical increment value has the opposite polarity to the increment value, the increment free space has moved from one side of the target free space line 205 to the coarse adjustment zone 280 or 285 on the other side. For example, when the historical increment value is negative and the increment value is positive, the increment free space has moved from below the target free space line 205 to the positive coarse adjustment zone 280 above the target free space line 205. Opposite polarity may indicate an unsuitable zone configuration, such as values ​​for free space lines 210, 215, 220, 225, 230, 235, 240, and 245 that are unsuitable for the current application. For example, an unsuitable zone configuration includes free space line values ​​that result in a zone size that is too large or too small. Opposite polarity may also indicate an unsuitable host rate that is too large or too small due to host rate adjustment. Therefore, the host rate adjuster 113 adjusts the host rate to a smaller coarse adjustment value α2. The host rate adjuster 113 compares the current free space value with the target free space value to determine whether to increase or decrease the host rate to the smaller coarse adjustment value α2. For example, if the current free space value is greater than the target free space value, then the increment value of the current sample (excluding the previous increment value) is positive, indicating that the free space has increased since the last adjustment. Therefore, the host rate adjuster 113 increases the host rate by a smaller coarse adjustment value α2 to slow down the host rate adjustment and minimize overcorrection.

[0044] When the historical increment value and the increment value have the same polarity, the increment free space remains on the same side of the target free space line 205 and the free space is still in the region furthest from the ideal region 255. The host rate adjuster 113 determines whether to adjust the host rate to a larger coarse adjustment value α1 or to maintain the current host rate. For example, the host rate adjuster 113 compares the increment value with the magnitude (i.e., absolute value) of the historical increment value. When the magnitude of the historical increment value is greater than the magnitude of the increment value, the increment free space has moved closer to the target free space line 205. Therefore, the host rate adjuster 113 maintains the current host rate to prevent overcorrection. When the magnitude of the increment value is greater than the magnitude of the historical increment value, the increment free space has moved further away from the ideal free space line 210. Therefore, the host rate adjuster 113 adjusts the host rate to a larger coarse adjustment value α1, thereby ultimately causing the increment free space value to decrease closer to the ideal region 255 and the target free space line 205. The host rate adjuster 113 determines whether to increase or decrease the host rate to a larger coarse adjustment value α1 based on the polarity of the increment value. For example, when the increment value is positive, the increment free space is in the positive coarse adjustment zone 280 and the historical increment value is above the target free space line 205. Therefore, the host rate adjuster 113 increases the host rate by a larger coarse adjustment value α1 to occupy more free space, thereby ultimately causing the increment free space value to decrease closer to the ideal zone 255 and the target free space line 205. In some embodiments, since the increment value and the historical increment value have the same polarity, the rate adjuster 113 determines whether to increase or decrease the host rate by a larger coarse adjustment value α1 based on the polarity of the historical increment value.

[0045] Just as the fine-tuning value β is valued, the coarse-tuning values ​​α1 and α2 are determined based on the performance consistency target. For example, for performance consistency measured using the slowest IOPS at the 99.9th percentile divided by the average IOPS, the performance consistency target is 0.1%. Therefore, to achieve the performance consistency target, any adjustments to the host rate should be less than 0.1%. Thus, the coarse-tuning values ​​α1 and α2 need to be at least less than the performance consistency target. Furthermore, the coarse-tuning value α1 is greater than the coarse-tuning value α2, and the coarse-tuning value α2 is greater than the fine-tuning value β. Therefore, the following relationship applies to the performance consistency target and the adjustment values: PerformanceConsistencyTarget > a1 > a2 > β. In one embodiment, when the performance consistency target is 0.1%, a1 = 0.0977%, a2 = 0.0488%, and β = 0.0244%.

[0046] Figure 3A , 3BThe 3C specification describes a flowchart of an example method 300 for adjusting host speed using free space values ​​according to some embodiments of this disclosure. Method 300 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The host rate adjuster 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0047] At operation 302, the processing device determines whether the device is in a steady state. For example, the host rate regulator 113 determines whether the memory device or a portion thereof (e.g., Figure 1 The processing device determines whether the memory device 140 is in a steady state. In some embodiments, the processing device determines whether the memory device is in a steady state by monitoring performance consistency. For example, the host rate adjuster 113 monitors IOPS and uses the slowest IOPS at a given percentile divided by the average IOPS to determine performance consistency. When performance consistency remains within a predetermined threshold over a given time period, the processing device determines that the memory device is in a steady state. In other embodiments, the processing device determines that the memory device is in a steady state after the memory device has been running for a predetermined time period during its operation. In yet another embodiment, the processing device uses other metrics to determine whether the memory device is in a steady state, such as monitoring the transient behavior of the memory device. When the memory device is in a steady state, method 300 proceeds to operation 304. When the memory device is not in a steady state, method 300 returns to operation 302. If the memory device is not yet in a steady state, there may still be transient behaviors that could lead to unpredictable or unexpected changes in free space. Therefore, method 300 continues until the probability of transient behavior has decreased (e.g., the memory device is in a steady state).

[0048] At operation 304, the processing device receives a current free space value and a historical increment value. For example, the host rate adjuster 113 receives the current free space value and the historical increment value based on the free space of the memory device. The current free space value is a value representing the amount of space in the memory device that has no data or no valid data. In some embodiments, the processing device receives data from local memory (e.g., ...). Figure 1The local memory 119 receives the current free space value and historical increment values. In other embodiments, the processing device receives the current free space value as a result of scanning the free space of the memory device.

[0049] At operation 306, the processing device calculates the increment value. For example, host rate adjuster 113 calculates the increment value using the current free space value, the target free space value, and historical increment values, as described above. The historical increment values ​​may store information from multiple previous increment values ​​(e.g., average, median, mean, sum, or other values ​​determined from multiple previous increment values). In other embodiments, host rate adjuster 113 calculates the increment value using the current free space value, the target free space value, and multiple historical increment values.

[0050] At operation 308, the processing device determines the region into which the increment value falls. For example, host rate adjuster 113 determines a range of increment values ​​that include the calculated increment value. The range of increment values ​​is predetermined based on memory device, performance consistency targets, and other metrics, as described above. When the processing device determines that the increment region is an ideal region (e.g., Figure 2 Either the ideal region 255) or the buffer zone (e.g., Figure 2 When the buffers 270 and 275 are selected, method 300 proceeds to operation 310. When the processing device determines that the incremental region is either of the coarse adjustment regions (e.g., ...), method 300 proceeds to operation 310. Figure 2 When the coarse adjustment areas 280 and 285 are selected, method 300 proceeds to operation 318 via the off-page connector A. When the processing device determines that the incremental area is either of the fine adjustment areas (e.g., ...), ... Figure 2 When fine-tuning areas 260 and 265 are reached, method 300 proceeds to operation 332 via the off-page connector B.

[0051] At operation 310, the processing device sets the host rate to the previous host rate. For example, the host rate adjuster 113 sends the host rate to the host device (e.g., Figure 1 The host system 120 causes the host device to maintain its host rate at the previous host rate. In some embodiments, because the updated host rate is the same as the previous host rate, the processing device does not send a new host rate to keep the host rate the same.

[0052] At operation 312, the processing device updates the historical increment value. For example, the host rate adjuster 113 updates the historical increment value by adding the increment value to the historical increment value. In some embodiments, the host rate adjuster 113 averages the increment value with the historical increment value. In some embodiments, the processing device also increments the number of historical samples.

[0053] At operation 314, the processing device determines whether the number of historical samples meets a threshold. For example, the host rate adjuster 113 determines whether the number of increment values ​​represented by historical increment values ​​is greater than the threshold. In some embodiments, the threshold is predetermined based on the rate of host rate change, the rate at which free space updates in response to the host rate change, and other variables. When the processing device determines that the number of historical samples is greater than the threshold, method 300 proceeds to operation 316. When the processing device determines that the number of historical samples is not greater than the threshold, method 300 returns to operation 304.

[0054] At operation 316, the processing device resets the historical increment value. For example, the host rate adjuster 113 sets the historical increment value to 0 or another number indicating that no historical increment value has been stored. In embodiments using multiple historical increment values, the host rate adjuster 113 removes the oldest historical increment value to make room for the new increment value.

[0055] At operation 318, the processing device determines whether the historical increment value and the increment value have the same polarity. For example, the host rate regulator 113 determines whether the historical increment value and the calculated increment value have the same polarity. When the processing device determines that the calculated increment value and the historical increment value have the same polarity, method 300 proceeds to operation 319. When the processing device determines that the calculated increment value and the historical increment value have opposite polarities, method 300 proceeds to operation 322.

[0056] At operation 319, the processing device determines whether the magnitude of the increment value is greater than the magnitude of the historical increment value. For example, the host rate regulator 113 determines whether the magnitude (i.e., absolute value) of the calculated increment value is greater than the magnitude (i.e., absolute value) of the historical increment value. When the processing device determines that the magnitude of the increment value is greater than the magnitude of the historical increment value, method 300 proceeds to the off-page connector D. Figure 3A Operation 310. When the processing device determines that the value of the incremental value is not greater than the value of the historical incremental value, method 300 proceeds to operation 320.

[0057] At operation 320, the processing device determines whether the polarity of the calculated increment value is positive. For example, the host speed regulator 113 determines whether the increment value is greater than 0. When the processing device determines that the increment value is positive, method 300 proceeds to operation 324. When the processing device determines that the increment value is not positive, method 300 proceeds to operation 326.

[0058] At operation 322, the processing device determines whether the current free space value is greater than the target free space value. For example, the host rate adjuster 113 determines whether the free space value of the current sample is greater than the target free space value (i.e., whether only the increment value of the current sample is greater than 0). When the processing device determines that the current free space value is greater than the target free space value, method 300 proceeds to operation 328. When the processing device determines that the increment value is not positive, method 300 proceeds to operation 330.

[0059] At operation 324, the processing device increases the host speed by a large coarse adjustment value α1. For example, the host speed adjuster 113 sends the new host speed (i.e., the previous host speed increased by a large coarse adjustment value α1) to the host device, for example... Figure 1 The host system 120. This causes the host device to update its host speed to the new host speed.

[0060] At operation 326, the processing device reduces the host rate by a large coarse adjustment value α1. For example, the host rate adjuster 113 sends a new host rate (i.e., the previous host rate reduced by a large coarse adjustment value α1) to the host device. This causes the host device to update its host rate to the new host rate.

[0061] At operation 328, the processing device increases the host rate by a small coarse adjustment value α2. For example, the host rate adjuster 113 sends a new host rate (i.e., the previous host rate increased by the small coarse adjustment value α2) to the host device. This causes the host device to update its host rate to the new host rate.

[0062] At operation 330, the processing device reduces the host rate by a small coarse adjustment value α2. For example, the host rate adjuster 113 sends a new host rate (i.e., the previous host rate reduced to the small coarse adjustment value α2) to the host device. This causes the host device to update its host rate to the new host rate.

[0063] At operation 332, the processing device determines whether the polarity of the historical increment value is positive. When the processing device determines that the historical increment value is positive, method 300 proceeds to operation 334. When the processing device determines that the increment value is not positive, method 300 proceeds to operation 336.

[0064] At operation 334, the processing device determines whether the polarity of the increment value is positive. When the processing device determines that the increment value is positive, method 300 proceeds to operation 338. When the processing device determines that the increment value is not positive, method 300 proceeds to operation 342.

[0065] At operation 336, the processing device determines whether the polarity of the increment value is positive. When the processing device determines that the increment value is positive, method 300 proceeds to operation 344. When the processing device determines that the increment value is not positive, method 300 proceeds to operation 340.

[0066] At operation 338, the processing device determines whether the incremental value is greater than the historical incremental value. If the processing device determines that the incremental value is greater than the historical incremental value, method 300 proceeds to operation 344. If the processing device determines that the incremental value is not greater than the historical incremental value, method 300 proceeds to operation 342.

[0067] In some embodiments, the processing device compares the incremental value with a historical incremental value, wherein there are positive and negative thresholds on either side of the historical incremental value. For example, the threshold may be a small fraction of the historical incremental value (e.g., 1 / e times the historical incremental value). In an exemplary embodiment, the value of e is 5 and therefore the threshold is 1 / 5 of the historical incremental value. In this embodiment, the processing device therefore determines that the incremental value is greater than 6 / 5 times the historical incremental value (i.e., It is still less than 4 / 5 times the historical increment (i.e., When the processing device determines that the increment value is greater than 6 / 5 times the historical increment value, method 300 proceeds to operation 344. When the processing device determines that the increment value is less than 4 / 5 times the historical increment value, method 300 proceeds to operation 342. When neither of these conditions is met (i.e., the increment value is between 4 / 5 times and 6 / 5 times the historical increment value), method 300 exits and returns to... Figure 3A Operation 310 (unspecified connection). The fraction 1 / e multiplied by the historical increment value may vary. For example, e may depend on the time it takes for free space to change in response to a change in host rate. Therefore, the longer it takes for free space to change in response to a change in host rate, the higher the value of e.

[0068] In some embodiments, the processing device counts the number of attempts to adjust the host rate (i.e., the number of times the increment value is between 4 / 5 and 6 / 5 of the historical increment value). In such embodiments, when compared with historical increment values ​​having positive and negative thresholds as described above, the processing device divides the increment value by the number of attempts.

[0069] At operation 340, the processing device determines whether the incremental value is greater than the historical incremental value. If the processing device determines that the incremental value is greater than the historical incremental value, method 300 proceeds to operation 342. If the processing device determines that the incremental value is not greater than the historical incremental value, method 300 proceeds to operation 344.

[0070] At operation 342, the processing device increases the host rate by a fine-tuning value β. For example, host rate adjuster 113 sends a new host rate (i.e., the previous host rate increased by the fine-tuning value β) to the host device. This causes the host device to update its host rate to the new host rate.

[0071] In some embodiments, the processing device compares the incremental value with a historical incremental value, wherein there are positive and negative thresholds on either side of the historical incremental value. For example, the threshold could be a small fraction of the historical incremental value (e.g., 1 / e times the historical incremental value). In an exemplary embodiment, the value of e is 5 and therefore the threshold is 1 / 5 of the historical incremental value. In this embodiment, the processing device therefore determines that the incremental value is greater than 6 / 5 of the historical incremental value (i.e., ) times, or less than 4 / 5 of the historical increment (i.e., When the processing device determines that the increment value is greater than 6 / 5 times the historical increment value, method 300 proceeds to operation 342. When the processing device determines that the increment value is less than 4 / 5 times the historical increment value, method 300 proceeds to operation 344. When neither of these conditions is met (i.e., the increment value is between 4 / 5 times and 6 / 5 times the historical increment value), method 300 exits and returns to... Figure 3A Operation 310 (unspecified connection). The fraction 1 / e multiplied by the historical increment value may vary. For example, e may depend on the time it takes for free space to change in response to a change in host rate. Therefore, the longer it takes for free space to change in response to a change in host rate, the higher the value of e.

[0072] In some embodiments, the processing device counts the number of attempts to adjust the host rate (i.e., the number of times the increment value is between 4 / 5 and 6 / 5 of the historical increment value). In such embodiments, when compared with historical increment values ​​having positive and negative thresholds, the processing device divides the increment value by the number of attempts.

[0073] At operation 344, the processing device reduces the host rate to the fine-tuning value β. For example, host rate adjuster 113 sends a new host rate (i.e., the previous host rate reduced to the fine-tuning value β) to the host device. This causes the host device to update its host rate to the new host rate.

[0074] Figure 4 This is a flowchart of an example method 400 for adjusting host speed using free space values ​​according to some embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1The host rate adjuster 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0075] At operation 405, the processing device receives a current free space value and a historical increment value. For example, the host rate adjuster 113 receives the current free space value and the historical increment value based on the free space of the memory device. The current free space value is a value representing the amount of space in the memory device that has no data or no valid data. In some embodiments, the free space includes discarded item blocks without valuable data (e.g., blocks that have failed due to discarded item collection). In other embodiments, the free space includes scanned space for victim blocks (e.g., source blocks awaiting deletion during discarded item collection). In some embodiments, the processing device retrieves data from local memory (e.g., from local memory). Figure 1 The local memory 119 receives the current free space value and historical increment values. In other embodiments, the processing device receives the current free space value as a result of scanning the free space of the memory device.

[0076] At operation 410, the processing device calculates the increment value. For example, the host rate adjuster 113 calculates the increment value using the current free space value, the target free space value, and historical increment values. The target free space value is the memory subsystem (e.g., Figure 1 The optimal free space of the memory subsystem 110. The target free space value is a free space value that indicates a good balance between the generation of free space (e.g., as a result of the collection of discarded items) and the consumption of free space (e.g., attributable to host writes). Historical increment values ​​can store information from multiple previous increment values. In other embodiments, the host rate adjuster 113 uses the current free space value, the target free space value, and multiple historical increment values ​​to calculate the increment value.

[0077] At operation 415, the processing device determines the increment region. For example, the host rate adjuster 113 determines a range of increment values ​​that include the calculated increment values. The increment value range is predetermined based on memory devices, performance consistency targets, and other metrics.

[0078] At operation 420, the processing unit calculates the new host rate. For example, host rate adjuster 113 uses the calculated increment value, historical increment value, and determined increment zone to calculate the host rate. The processing unit calculates the host rate according to the operation explained in detail above. For example, when the determined increment zone is an ideal zone or buffer zone, the processing unit can calculate the new host rate as the current host rate, as referenced... Figure 3A As described in operation 310. When it is determined that the incremental region is a coarse adjustment region, the processing device can calculate the new host rate because the current host rate has increased or decreased by α1 or α2 or is the same as the current host rate, as referenced. Figure 3B As described in operations 318, 319, 310, 320, and 322. When the incremental region is determined to be a fine-tuning region, the processing device can calculate the new host rate because the current host rate has increased or decreased by β, as referenced. Figure 3C Operations 332, 334, 336, 338 and 340 are described.

[0079] At operation 425, the processing device sends a host rate to the host device. For example, host rate adjuster 113 sends a new host rate to the host device. This causes the host device to update its host rate to the new host rate. In some embodiments, when the updated host rate is the same as the previous host rate, the processing device does not send a new host rate to the host device, thereby causing the host device to maintain the same host rate.

[0080] Figure 5 An example machine illustrating computer system 500 is provided, within which a set of instructions can be executed to cause the machine to perform any one or more methodologies discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of host rate adjuster 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0081] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying the actions to be taken by that machine. Furthermore, while describing a single machine, the term "machine" should also be considered to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any of the methodologies discussed herein.

[0082] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 518, which communicate with each other via a bus 530.

[0083] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations thereof. Processing device 502 may also be one or more special-purpose processing devices, such as an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communicating via network 520.

[0084] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) storing one or more sets of instructions 526 or software embodying any of the methodologies or functions described herein. The instructions 526 may also reside wholly or at least partially within the main memory 504 and / or the processing device 502 during execution by the computer system 500, which also constitutes a machine-readable storage medium. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0085] In one embodiment, instruction 526 includes instructions for implementing a component corresponding to a host rate adjuster (e.g., Figure 1 The machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0086] Some portions of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that leads to a desired result. These operations are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0087] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device, which manipulates and converts data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0088] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. For example, a computer system or other data processing system (e.g., controller 115) may implement computer implementation methods 300 and 400 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in memory or other non-transitory machine-readable storage media. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0089] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will appear as described below. Furthermore, this disclosure is not described with reference to any particular programming language. It will be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0090] This disclosure may be provided as a computer program product or software that may include machine-readable media having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0091] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method comprising: The incremental free space value is calculated using a current free space value representing the current amount of free space in the memory device, a target free space value representing the target amount of free space in the memory device, and a historical increment value, wherein the historical increment value is determined using one or more previous incremental free space values, and wherein the one or more previous incremental free space values ​​are the incremental free space values ​​calculated at a previous time. The incremental free space values ​​are used to determine an incremental region among a plurality of incremental regions, wherein each of the plurality of incremental regions contains a continuous range of incremental free space values ​​and wherein the determined incremental region contains the calculated incremental free space values. The new host speed is calculated using the determined increment region and the current host speed; and The new host rate is sent to the host device, wherein the host device changes the current host rate to the new host rate.

2. The method according to claim 1, further comprising: The historical increment value is updated using the calculated increment free space value.

3. The method according to claim 2, wherein the plurality of incremental regions comprises an ideal region, a positive fine-tuning region, a negative fine-tuning region, a positive buffer zone, a negative buffer zone, a positive coarse-tuning region, and a negative coarse-tuning region, wherein: The ideal region includes the target free space value and is bounded by the positive ideal line and the negative ideal line; The positive fine-tuning zone is defined by the positive ideal line and the positive fine-tuning line; The negative fine adjustment zone is defined by the negative ideal line and the negative fine adjustment line; The positive buffer zone is defined by the positive fine adjustment line and the positive coarse adjustment line; The negative buffer zone is defined by the negative fine adjustment line and the negative coarse adjustment line; The positive coarse adjustment zone is defined by the positive coarse adjustment line and the positive steady-state line; The negative coarse adjustment region is defined by the negative coarse adjustment line and the negative steady-state line; and Each of the positive ideal line, the negative ideal line, the positive fine-tuning line, the negative fine-tuning line, the positive coarse-tuning line, the negative coarse-tuning line, the positive steady-state line, and the negative steady-state line is determined by the distance to the target free space value.

4. The method of claim 3, wherein calculating the new host rate when the determined incremental region is the ideal region, the positive buffer, or the negative buffer includes using the current host rate as the new host rate.

5. The method of claim 3, wherein calculating the new host rate when the determined incremental region is the positive or negative coarse adjustment region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; Set the adjusted polarity to the current polarity; Compare the current polarity with the historical polarity; The coarse adjustment value is determined using the comparison, wherein the coarse adjustment value when the current polarity is equal to the historical polarity is greater than the coarse adjustment value when the current polarity is opposite to the historical polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and the coarse adjustment value.

6. The method of claim 3, wherein calculating the new host rate when the determined incremental region is the positive or negative coarse adjustment region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; The sample polarity is determined using the current free space value and the target free space value; Set the polarity to the sample polarity; Compare the current polarity with the historical polarity; The coarse adjustment value is determined using the comparison, wherein the coarse adjustment value when the current polarity is equal to the historical polarity is greater than the coarse adjustment value when the current polarity is opposite to the historical polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and the coarse adjustment value.

7. The method of claim 3, wherein calculating the new host rate when the determined incremental region is the positive or negative fine-tuning region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; Compare the current polarity with the historical polarity; In response to the current polarity being opposite to the historical polarity, the adjusted polarity is set to the current polarity; as well as The new host speed is calculated using the current host speed, the adjustment polarity, and the fine-tuning value.

8. The method of claim 3, wherein calculating the new host rate when the determined incremental region is the positive or negative fine-tuning region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; Compare the current polarity with the historical polarity; In response to the current polarity being equal to the historical polarity, the calculated incremental free space value is compared with the historical incremental value; In response to the calculated incremental free space value being greater than the historical incremental value, the adjustment polarity is set to the current polarity; as well as The new host speed is calculated using the current host speed, the adjustment polarity, and the fine-tuning value.

9. The method of claim 3, wherein calculating the new host rate when the determined incremental region is the positive or negative fine-tuning region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; Compare the current polarity with the historical polarity; In response to the current polarity being equal to the historical polarity, the calculated incremental free space value is compared with the historical incremental value; and In response to the calculated incremental free space value being less than the historical incremental value, the adjustment polarity is determined to be opposite to the current polarity; and The new host speed is calculated using the current host speed, the adjustment polarity, and the fine-tuning value.

10. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to: The incremental free space value is calculated using a current free space value representing the current amount of free space in the memory device, a target free space value representing the target amount of free space in the memory device, and a historical increment value, wherein the historical increment value is determined using one or more previous incremental free space values, and wherein the one or more previous incremental free space values ​​are the incremental free space values ​​calculated at a previous time. The incremental free space values ​​are used to determine an incremental region among a plurality of incremental regions, wherein each of the plurality of incremental regions contains a continuous range of incremental free space values ​​and wherein the determined incremental region contains the calculated incremental free space values. The new host speed is calculated using the determined increment region and the current host speed; and The new host rate is sent to the host device, wherein the host device changes the current host rate to the new host rate.

11. The non-transitory computer-readable storage medium of claim 10, wherein the processing means is further configured to: The historical increment value is updated using the calculated increment free space value.

12. The non-transitory computer-readable storage medium of claim 11, wherein the plurality of incremental regions comprises an ideal region, a positive fine-tuning region, a negative fine-tuning region, a positive buffer, a negative buffer, a positive coarse-tuning region, and a negative coarse-tuning region, wherein: The ideal region includes the target free space value and is bounded by the positive ideal line and the negative ideal line; The positive fine-tuning zone is defined by the positive ideal line and the positive fine-tuning line; The negative fine adjustment zone is defined by the negative ideal line and the negative fine adjustment line; The positive buffer zone is defined by the positive fine adjustment line and the positive coarse adjustment line; The negative buffer zone is defined by the negative fine adjustment line and the negative coarse adjustment line; The positive coarse adjustment zone is defined by the positive coarse adjustment line and the positive steady-state line; The negative coarse adjustment region is defined by the negative coarse adjustment line and the negative steady-state line; and Each of the positive ideal line, the negative ideal line, the positive fine-tuning line, the negative fine-tuning line, the positive coarse-tuning line, the negative coarse-tuning line, the positive steady-state line, and the negative steady-state line is determined by the distance to the target free space value.

13. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined incremental region is the ideal region, the positive buffer, or the negative buffer includes using the current host rate as the new host rate.

14. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined incremental region is the positive or negative coarse adjustment region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; Set the adjusted polarity to the current polarity; Compare the current polarity with the historical polarity; The coarse adjustment value is determined using the comparison, wherein the coarse adjustment value when the current polarity is equal to the historical polarity is greater than the coarse adjustment value when the current polarity is opposite to the historical polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and the coarse adjustment value.

15. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined incremental region is the positive or negative coarse adjustment region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; The sample polarity is determined using the current free space value and the target free space value; Set the polarity to the sample polarity; Compare the current polarity with the historical polarity; The coarse adjustment value is determined using the comparison, wherein the coarse adjustment value when the current polarity is equal to the historical polarity is greater than the coarse adjustment value when the current polarity is opposite to the historical polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and the coarse adjustment value.

16. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined incremental region is the positive or negative fine-tuning region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; Compare the current polarity with the historical polarity; In response to the current polarity being opposite to the historical polarity, the adjusted polarity is set to the current polarity; as well as The new host speed is calculated using the current host speed, the adjustment polarity, and the fine-tuning value.

17. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined incremental region is the positive or negative fine-tuning region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; Compare the current polarity with the historical polarity; In response to the current polarity being equal to the historical polarity, the calculated incremental free space value is compared with the historical incremental value; In response to the calculated incremental free space value being greater than the historical incremental value, the adjustment polarity is set to the current polarity; as well as The new host speed is calculated using the current host speed, the adjustment polarity, and the fine-tuning value.

18. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined incremental region is the positive or negative fine-tuning region comprises: Determine the current polarity and the historical polarity, wherein the current polarity is the polarity of the calculated incremental free space value and wherein the historical polarity is the polarity of the historical incremental value; Compare the current polarity with the historical polarity; In response to the current polarity being equal to the historical polarity, the calculated incremental free space value is compared with the historical incremental value; and In response to the calculated incremental free space value being less than the historical incremental value, the adjustment polarity is determined to be opposite to the current polarity; and The new host speed is calculated using the current host speed, the adjustment polarity, and the fine-tuning value.

19. A system comprising: Multiple memory devices; and Processing device, operatively coupled to the plurality of memory devices to: The incremental free space value is calculated using a current free space value representing the current amount of free space in the memory device, a target free space value representing the target amount of free space in the memory device, and a historical increment value, wherein the historical increment value is determined using one or more previous incremental free space values, and wherein the one or more previous incremental free space values ​​are the incremental free space values ​​calculated at a previous time. The incremental free space values ​​are used to determine an incremental region among a plurality of incremental regions, wherein each of the plurality of incremental regions contains a continuous range of incremental free space values ​​and wherein the determined incremental region contains the calculated incremental free space values. The new host speed is calculated using the determined increment region and the current host speed; and Sending the new host rate to the host device, wherein the host device changes the current host rate to the new host rate; and The historical increment value is updated using the calculated increment free space value.

20. The system of claim 19, wherein the plurality of incremental regions comprises an ideal region, a positive fine-tuning region, a negative fine-tuning region, a positive buffer zone, a negative buffer zone, a positive coarse-tuning region, and a negative coarse-tuning region, wherein: The ideal region includes the target free space value and is bounded by the positive ideal line and the negative ideal line; The positive fine-tuning zone is defined by the positive ideal line and the positive fine-tuning line; The negative fine adjustment zone is defined by the negative ideal line and the negative fine adjustment line; The positive buffer zone is defined by the positive fine adjustment line and the positive coarse adjustment line; The negative buffer zone is defined by the negative fine adjustment line and the negative coarse adjustment line; The positive coarse adjustment zone is defined by the positive coarse adjustment line and the positive steady-state line; The negative coarse adjustment region is defined by the negative coarse adjustment line and the negative steady-state line; and Each of the positive ideal line, the negative ideal line, the positive fine-tuning line, the negative fine-tuning line, the positive coarse-tuning line, the negative coarse-tuning line, the positive steady-state line, and the negative steady-state line is determined by the distance to the target free space value.

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