Frequency divider for non-overlapping clock signals

Abstract

There is provided a frequency divider comprising a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or more. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls the setting of the latch, and the remaining one of the logic gates in the corresponding pair controls the resetting of the latch. Each latch outputs a pair of overlapping clock signals that divide the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and an input clock signal to provide a non-overlapping clock signal having the same frequency as the overlapping clock signal but having a duty cycle of (50 / N)%.

Description

Technical Field

[0001] The present application relates to frequency dividers, and more particularly to frequency dividers that generate non-overlapping clock signals. Background Art

[0002] Among multiple non-overlapping clock signals, only one of the clock signals will be in a binary true state at any given time. The binary true state can be a supply voltage in a binary high convention or a ground in a binary low convention. Regardless of the binary high (or low) convention, non-overlapping clock signals have many uses in electronic systems. For example, modern receivers can use passive mixers driven by multiple N non-overlapping clock signals, where N is a complex positive integer. However, the generation of non-overlapping clock signals typically consumes a lot of power and may suffer from excessive phase noise. Summary of the invention

[0003] A frequency divider for generating non-overlapping clock signals is provided, the frequency divider comprising: a plurality of stages arranged in series from a first stage to an Nth stage, wherein N is an integer of three or greater and each stage comprises: a 3-input logic gate having an output terminal coupled to a first input terminal of a 2-input logic gate, and wherein the output terminal of the 2-input logic gate in each previous stage in the series is coupled to the first input terminal of the 3-input logic gate in a subsequent stage in the series, and wherein the output terminal of the 2-input logic gate in the Nth stage is coupled to the first input terminal of the 3-input logic gate in the first stage.

[0004] In addition, a frequency divider is provided, the frequency divider comprising: a differential clock source, the differential clock source being configured to output a positive input clock signal and a negative input clock signal as a complement of the positive input clock signal; a plurality of N latches, wherein N is a complex positive integer greater than two; a plurality of N first logic gates, each of the first logic gates having a first output terminal coupled to a reset input terminal of a corresponding one of the latches, each of the first logic gates being configured to process only one of a plurality of 2N overlapping clock signals using one of the positive input clock signal and the negative input clock signal; a pair of overlapping clock signals to output a corresponding non-overlapping clock signal in a first plurality of N non-overlapping clock signals at the first output terminal; and a plurality of N second logic gates, each second logic gate having a second output terminal coupled to a set input terminal of a corresponding one of the latches, each second logic gate being configured to process a unique pair of overlapping clock signals in the plurality of 2N overlapping clock signals using one of the positive input clock signal and the negative input clock signal to output a corresponding non-overlapping clock signal in a second plurality of N non-overlapping clock signals at the second output terminal.

[0005] In addition, a frequency divider is provided, which includes: a differential clock source, which is configured to make a positive input clock signal and a negative input clock signal cycle at a first frequency, wherein the negative input clock signal is a complement of the positive input clock signal; a plurality of N latches, each latch being configured to output a corresponding pair of overlapping clock signals among 2N overlapping clock signals that cycle at a second frequency, wherein the second frequency is 1 / N of the first frequency and has a duty cycle of approximately 50%, wherein N is an integer of 3 or greater; and a plurality of 2N logic gates, which are configured to output 2N non-overlapping clock signals that cycle at the second frequency and have a duty cycle of approximately (50 / N)%, each logic gate being configured to process two overlapping clock signals among the 2N overlapping clock signals using one of the negative input clock signal and the positive input clock signal to output a corresponding one of the 2N non-overlapping clock signals at an output terminal of the logic gate.

[0006] Finally, a frequency division method is provided, which includes: dividing an input clock signal by a divisor N into a plurality of 2N overlapping clock signals; wherein N is an integer of three or greater, and each overlapping clock signal has a duty cycle of approximately 50%; and utilizing the input clock signal to process pairs of the overlapping clock signals so as to divide the input clock signal by the divisor N into a plurality of 2N non-overlapping clock signals, each non-overlapping clock signal having a duty cycle of approximately (50 / N)%.

[0007] These and other advantageous features will be better understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a circuit diagram of a divide-by-3 frequency divider according to one aspect of the present disclosure.

[0009] Figure 1B It is for Figure 1A Timing diagram of the clock signal.

[0010] Figure 1C yes Figure 1A An alternative circuit diagram of a divide-by-3 frequency divider.

[0011] Figure 2A is a circuit diagram of a divide-by-4 frequency divider according to one aspect of the present disclosure.

[0012] Figure 2B It is for Figure 2A Timing diagram of the clock signal.

[0013] Figure 3 is a timing diagram illustrating the time differences between three example overlapping clock signals according to one aspect of the present disclosure.

[0014] Figure 4 is a circuit diagram of a divide-by-N frequency divider according to one aspect of the present disclosure, where N is an odd number.

[0015] Figure 5 is a circuit diagram of a divide-by-N frequency divider according to one aspect of the present disclosure, where N is an even number.

[0016] Figure 6 is a flow chart of an example method of operation for a fractional-N frequency divider according to one aspect of the present disclosure.

[0017] Figure 7 Some example electronic devices including a frequency divider according to one aspect of the present disclosure are illustrated.

[0018] The specific implementation of the present disclosure and its advantages may be best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the accompanying drawings. DETAILED DESCRIPTION

[0019] A frequency divider is provided that divides an input clock signal into a plurality of 2N non-overlapping clock signals according to a positive integer N, where N is three or greater. The input clock signal circulates at a frequency f having a period T. Therefore, each non-overlapping clock signal has a frequency f / N and a period N*T. In the following discussion, when the non-overlapping clock signal is in a binary true state, each non-overlapping clock signal is considered to be "asserted", regardless of whether the binary true state is represented using a binary high convention or a binary low convention. In a specific implementation in which a binary high convention is used, each non-overlapping clock signal is therefore asserted by being charged to a power supply voltage. Conversely, in a specific implementation using a binary low convention, each non-overlapping clock signal is asserted by being discharged to ground. Regardless of which convention is used, each non-overlapping clock signal is asserted only for T / 2 in each period N*T. The input clock signal has a 50% duty cycle, so that it is also asserted for T / 2 in each period T.

[0020] The frequency divider also divides the input clock signal into a plurality of 2N overlapping clock signals, each having a 50% duty cycle. Similar to the non-overlapping clock signals, each overlapping clock signal has a frequency of f / N and a period of N*T. Given a 50% duty cycle, each overlapping clock signal is asserted in half of its period (equal to NT / 2). Since the assertion time for each non-overlapping clock signal is T / 2, the non-overlapping assertion time is 1 / N of the assertion time for each overlapping clock signal. Therefore, the duty cycle of each non-overlapping clock signal is 50% / N.

[0021] The 2N overlapping clock signals can be considered to be arranged from the first overlapping clock signal to the 2N overlapping clock signal. For this order or arrangement, the i-th overlapping clock signal is timed so as to be delayed by T / 2 for the (i-1)th overlapping clock signal, where i is an integer ranging from 2 to 2N. The first overlapping clock signal is delayed by T / 2 for the 2Nth overlapping clock signal. In order to form these 2N overlapping clock signals with such an interleaved or progressive time delay relationship, the frequency divider includes a plurality of N set-reset latches. Each latch generates a corresponding pair of overlapping clock signals. The latches can be considered to be arranged in series from the first latch to the Nth latch. For this order, the i-th latch generates the (i+1)th overlapping clock signal and the ((i+1)+N)th overlapping clock signal, where i is an integer ranging from 1 to (N-1). The Nth latch generates the first overlapping clock signal and the (N+1)th overlapping clock signal.

[0022] Since each latch is a set-reset latch, each latch has a reset input terminal and a set input terminal. When the i-th latch is set by the assertion of the voltage of its set input terminal, it asserts the (i+1)th overlapping clock signal. Similarly, when the i-th latch is reset by the assertion of the voltage of its reset input terminal, it asserts the (i+(N+1))th overlapping clock signal. Given a time delay of T / 2 from one overlapping clock signal to the next overlapping clock signal, the pair of overlapping clock signals generated by each latch will have a time difference of NT / 2. When set, the N-th latch asserts the (N+1)th overlapping clock signal. Similarly, when reset, the N-th latch asserts the first overlapping clock signal.

[0023] The set input terminal of each latch is controlled by a corresponding three-input logic gate. Since there are N latches, there are N corresponding three-input logic gates to control the setting of the N latches. Similarly, there are N corresponding three-input logic gates to control the reset of the N latches. Therefore, each latch is coupled to a first three-input logic gate that drives the set terminal of the latch and is coupled to a second three-input logic gate that drives the reset terminal of the latch. Therefore, there are a plurality of N three-input first logic gates and a plurality of N three-input second logic gates.

[0024] The following discussion will assume that each three-input first logic gate and each three-input second logic gate are 3-input NOR gates, but it should be understood that 3-input NAND gates may also be used in alternative implementations. Each 3-input logic gate generates a corresponding one of the 2N non-overlapping clock signals. Figure 1AAn example frequency divider 100 is shown in FIG, where N is equal to 3. Since the frequency division is 3, there are three latches including a first latch 125, a second latch 130, and a third latch 135. In the case where N is 3, there are 2N=6 overlapping clock signals, each of which is represented by E and its index. Therefore, the first overlapping clock signal is designated as E1, the second overlapping clock signal is designated as E2, the third overlapping clock signal is designated as E3, and so on, so that the sixth overlapping clock signal is designated as E6.

[0025] When set by assertion of the set (S) terminal, the first latch 125 asserts the E2 clock signal and resets (de-asserts) the E5 clock signal. Conversely, when reset by assertion of the reset (R) terminal, the first latch 125 asserts the E5 clock signal and resets the E2 clock signal. Therefore, the E2 clock signal and the E5 clock signal are complements of each other. Since each consecutive E clock signal is delayed by T / 2, the E5 clock signal is delayed by 3T / 2 for the E2 clock signal. Similarly, when set, the second latch 130 asserts the E3 clock signal and resets the E6 clock signal. When reset, the second latch 130 also resets the E3 clock signal and asserts the E6 clock signal. Therefore, the E3 clock signal and the E6 clock signal are complements of each other. In addition, when set, the third latch 135 asserts the E4 clock signal and resets the E1 clock signal. Finally, when reset, the third latch 135 asserts the E1 clock signal and resets the E4 clock signal. Thus, the E1 clock signal and the E4 clock signal are complements of each other. More generally, each latch generates a complementary pair of overlapping clock signals.

[0026] Each latch has its set terminal voltage controlled by a corresponding 3-input NOR gate. Similarly, each latch has its reset terminal voltage controlled by another corresponding 3-input NOR gate. Since there are N latches, there are 2N=6 3-input NOR gates for setting and resetting the N latches. Each 3-input NOR gate generates or outputs a corresponding non-overlapping clock signal. Therefore, there are 6 non-overlapping clock signals generated by the divider 100. The non-overlapping clock signals are represented by the letter P and the corresponding index. In particular, the divider 100 generates six P clock signals ranging from the P1 clock signal to the P6 clock signal. Similar to the overlapping clock signals, each consecutive non-overlapping clock signal is delayed by T / 2 for the previous non-overlapping clock signal. Therefore, the P2 clock signal is delayed by T / 2 for the P1 clock signal. Similarly, the P3 clock signal is delayed by T / 2 for the P2 clock signal, the P4 clock signal is delayed by T / 2 for the P3 clock signal, and so on, so that the P6 clock signal is delayed by T / 2 for the P5 clock signal.

[0027] Since the setting and resetting of each latch controls the generation of paired overlapping clock signals of each latch, the overlapping clock signals from any given latch are complementary. For example, the E2 clock signal and the E5 clock signal generated by the first latch 125 are complements of each other. Although there is no overlap between the E2 clock signal and the E5 clock signal, it should be noted that it is still accurate to refer to the E2 clock signal and the E5 clock signal as overlapping clock signals. For example, in addition to the E5 clock signal, the E2 clock signal overlaps with every other E clock signal. Similarly, in addition to the E2 clock signal, the E5 clock signal overlaps with every other E clock signal. More generally, each latch generates a complementary pair of E signals that overlap with all remaining E clock signals. Therefore, the frequency divider 100 is used to divide the clkn input clock signal and the clkp input clock signal by a divisor N using a plurality of N latches, and each latch is configured to output a corresponding pair of overlapping clock signals from 2N overlapping clock signals, where N is equal to 3.

[0028] Given that each successive E clock signal has a T / 2 delay with respect to its previous E clock signal, each successive E clock signal will have an overlap T with the previous clock signal, where in this divide-by-3 implementation, both E clock signals are in a binary false state (which is ground in the binary high convention). For example, the E2 clock signal has such an overlap T with the E1 clock signal. The NOR gate exploits this T overlap by gating each successive E clock signal with the previous E clock signal with a gating clock signal selected from the positive input clock signal (clkp) and the negative input clock signal (clkn) as generated by the differential clock source 120. For example, the 3-input NOR gate 155 NORs the E1 clock signal with the E2 clock signal and with the clkp input clock signal to generate the P2 clock signal to drive the reset input terminal of the second latch 130. Note how this gating is advantageous: without gating by the selected input clock signal, both the E1 and E2 clock signals will be in the binary zero state for T in each of their cycles because the E2 clock signal is delayed by T / 2 with respect to the E1 clock signal. The output signal from the NOR gate 155 will then pulse high during this long period of time T when both the E1 and E2 clock signals are in the binary zero state. Note that if each non-overlapping clock signal has an assertion time of T, the divider 100 cannot produce non-overlapping clock signals. But when gated by one of the input clock signals, the output signal from the NOR gate 155 can form the desired non-overlapping P2 clock signal.

[0029] In this regard, it is known to construct a frequency divider from a set of flip-flops arranged in series. Such a set of flip-flops arranged in series can produce the equivalent of an overlapping clock signal with a 50% duty cycle. But then a separate combinational logic circuit will be required to process the overlapping clock signals from such a frequency divider to obtain a non-overlapping clock signal. In sharp contrast, the frequency divider 100 itself produces not only an E clock signal (overlapping clock signal), but also a P clock signal (non-overlapping clock signal). The result is a significant reduction in the semiconductor die space for implementing the frequency divider 100. In addition, the frequency divider 100 can be easily modified as explained herein to accommodate any desired even or odd value N. In addition, the frequency divider 100 reduces power consumption compared to using a separate combinational logic circuit. Another advantage of the frequency divider 100 is that the phase noise in the E clock signal and the P clock signal is reduced.

[0030] The remaining set input terminals and reset input terminals for the latches in the frequency divider 100 are coupled to corresponding 3-input NOR gates that NOR the appropriate E clock signal (a pair of E signals with a time delay T / 2 between them) with the appropriate gate clock. Which of the clkp input clock signal or the clkn input clock signal is used to gate the NOR gate output depends on which P clock signal is being generated. For example, the 3-input NOR gate 145 generates the P1 clock signal to drive the reset input terminal of the first latch 125 by the NOR operation of the E1 clock signal, the E6 clock signal, and the clkn input clock signal. Note that the clkp input clock signal can also be selected. But no matter which input clock signal is selected, this determines the input clock signal selection for the NOR gate that generates the subsequent P clock signal. Therefore, the NOR gate 155 is gated by the clkp input clock signal because the NOR gate 145 is gated by the clkn input clock signal. Similarly, the 3-input NOR gate 165 generates the P3 clock signal by NOR operation to drive the reset terminal of the third latch 135 by NOR operation of the E2 clock signal and the E3 clock signal with the clkn input clock signal. In summary, the clkn input clock signal and the clkp input clock signal are alternately provided to the inputs of a series of NOR gates 145-170.

[0031] The setting of the latch is controlled by a similar 3-input NOR gate. For example, the 3-input NOR gate 150 NORs the E3 clock signal with the E4 clock signal and with the clkp input clock signal to generate the P4 clock signal to control the setting of the first latch 125. Note that the NOR gate 150 is gated by the complement of the input clock signal that gates the NOR gate 145. This is because of the T / 2 delay between each successive non-overlapping clock signal and its previous non-overlapping clock signal. In this case, therefore, the P4 clock signal is delayed by 3T / 2 with respect to the P1 clock signal. If the NOR gate 150 is instead gated by the clkn input clock signal, the P4 clock signal will overlap with P3. However, by gating the NOR gate 150 with the clkp input clock signal, the desired non-overlapping time shift is achieved. Similarly, the NOR gate 160 performs a NOR operation on the E5 clock signal and the E4 clock signal with the clkn input clock signal to generate a P5 clock signal to control the setting of the second latch 130. Finally, the NOR gate 170 performs a NOR operation on the E6 clock signal and the E5 clock signal with the clkp input clock signal to generate a P6 clock signal to control the setting of the third latch 135.

[0032] Each latch may be implemented using a cross-coupled pair of logic gates (e.g., NAND gates, NOR gates, etc.). In one implementation, each latch is formed using a cross-coupled pair of NOR gates 110 and 115 as shown for the example cross-coupled NOR gate latch 105. When the set input terminal (S) of latch 110 is asserted, the corresponding E clock signal generated at the Q output terminal will then be asserted. Similarly, when the reset input terminal (R) of latch 110 is asserted, the corresponding E clock signal generated at the QB output terminal will then be asserted. Note that in an alternative implementation, a pair of cross-coupled NAND gates may alternatively be used to generate the latches in divider 100.

[0033] exist Figure 1BResulting timing of the E clock signal and the P clock signal in the frequency divider 100 as controlled by the clkp input clock signal and the clkn input clock signal is shown in FIG. The E1 clock signal begins a cycle at time t0 by rising from ground to the power supply voltage as triggered by a corresponding edge in one of the input clock signals. In this specific implementation, the rising edge of the clkp input clock signal triggers the rising edge of the E1 clock signal. In an alternative specific implementation, the rising edge of the clkn input clock signal can be used to trigger the rising edge of the E1 clock signal. In the case where the rising edge of the E1 clock signal occurs at time t0, the E2 clock signal therefore has a rising edge at time t1, which is T / 2 after time t0, because each successive E clock signal is delayed by T / 2 for the previous E clock signal. Similarly, the E3 clock signal has a rising edge at time t2, which is T / 2 after time t1. The E4 clock signal has a rising edge at time t3, which is T / 2 after time t2, and the E5 clock signal has a rising edge at time t4, which is T / 2 after time t3. Similarly, the E6 clock signal has a rising edge at time t5, which is T / 2 after time t4. The E clock period is N*T, which is 3T in this divide-by-3 implementation. Therefore, the E1 clock signal begins another cycle at time t6, which is T / 2 after time t5 and 3T after time t0. Therefore, each E clock signal in the three-frequency implementation has a period that is 3 times the period T of the input clock signal.

[0034] First, the reset of the latch and the corresponding assertion of the clock signals P1, P2, and P3 will be discussed. The clock signals E1 and E6 are both in the binary zero state from time t3 to time t5. The clkn input clock signal is binary zero from time t4 to time t5, so that the "NOR" gate 145 asserts the P1 clock signal at this time. The P1 clock signal assertion resets the first latch 125, so that the E5 clock signal has a rising edge at time t3. Similarly, the E2 clock signal and the E1 clock signal are both in the binary zero state from time t4 to time t6. The clkp input clock signal is binary zero from time t5 to time t6, so that the "NOR" gate 155 asserts the P2 clock signal at this time. The P2 clock signal assertion resets the second latch 130, so that the E6 clock signal has a rising edge at time t5. The E2 clock signal and the E3 clock signal are both in the binary zero state from time t5 to time t7, which is T / 2 after time t6. The clkn input clock signal is a binary zero from time t6 to time t7, causing NOR gate 165 to assert the P3 clock signal at this time. The assertion of the P3 clock signal resets the third latch 135, causing the clock signal E1 to have a rising edge at time t7.

[0035] The setting of the latches and the corresponding assertion of the clock signals P4, P5, and P6 will now be discussed. The clock signals E3 and E4 are both in a binary zero state from time t6 to time t8, which is T / 2 after time t7. The input clock signal clkp is a binary zero from time t7 to time t8, causing the NOR gate 150 to assert the P4 clock signal at this time. The assertion of the P4 clock signal sets the first latch 125, causing the E3 clock signal to have a rising edge at time t7. The clock signals E5 and E4 are both in a binary zero state from time t7 to time t9, which is T / 2 after time t8. The input clock signal clkn is a binary zero from time t8 to time t9, causing the NOR gate 160 to assert the P5 clock signal at this time. The P5 clock signal asserts the second latch 130, causing the E3 clock signal to have a rising edge at time t8. Finally, the clock signals E6 and E5 are both in a binary zero state from time t8 to time t10, which is T / 2 after time t9. The input clock signal clkp is binary zero from time t9 to time t10, causing the NOR gate 170 to assert the P6 clock signal at this time. The assertion of the P6 clock signal sets the third latch 135, causing the clock signal E4 to have a rising edge at time t9. The clock signal P1 will then begin a new cycle (not illustrated) at time t10.

[0036] Where each latch is implemented using a pair of cross-coupled 2-input NOR gates as discussed with respect to latch 105, it can be seen that the resulting 3-input NOR gates and 2-input NOR gates form a plurality of 2N (in this case, six) stages arranged in a serial ring, each stage comprising a corresponding 3-input NOR gate and a corresponding 2-input NOR gate. For example, frequency divider 100 may be configured as follows: Figure 1C The illustration includes an example stage 180. Referring again to Figure 1A , it is noted that NOR gate 155 is driving the reset input terminal of second latch 130 with the P2 clock signal. Where the latch is implemented with cross-coupled 2-input NOR gates as shown for latch 105, the corresponding NOR gate in second latch 130 having an input terminal coupled to the output terminal of NOR gate 155 is designated as NOR gate 130-A. NOR gate 130-A is cross-coupled with NOR gate 130-B which outputs the E6 clock signal. NOR gates 130-A and 130-B form Figure 1A The output terminal of the NOR gate 130-A is coupled to the input terminal of the NOR gate 165 to drive the NOR gate 165 with the E3 clock signal.

[0037] NOR gate 165 forms another stage with NOR gate 135-A from third latch 135. As already discussed, the NOR gates NOR the E3 clock signal and the E2 clock signal with the clkn input clock signal to output the P3 clock signal. NOR gate 135-A is cross-coupled with NOR gate 135-B to form Figure 1A Similarly, NOR gate 125-A is cross-coupled with NOR gate 125-B to form a third latch 135. Figure 1A The first latch 125. Figure 1A and Figure 1C A comparison of demonstrates the equivalence of the two representations of the divider 100. Therefore, no further discussion will be given. Figure 1C of the remaining components.

[0038] It should be understood that frequency divider 100 is only one specific implementation for a particular value of N (3 in this case). However, the principles from frequency divider 100 can be generalized to produce frequency dividers for any integer divisor N greater than 3. For example, Figure 2A The illustrated divider 200 divides the input clock signals clkp and clkn by four (N=4) to generate a plurality of (8) overlapping clock signals (E1 to E8) and a plurality of (8) non-overlapping clock signals (P1 to P8). Since N is four, the divider 200 has a serial arrangement of four latches formed by a first latch 205, a second latch 210, a third latch 215, and a fourth latch 220. Each latch controls a corresponding pair of E clock signals. However, it should be noted that the period of the E clock signal for the divider 400 is now 4T, so that each E clock signal is in a binary zero state (or a binary high state) for 2T per clock cycle. Since the gating at the 3-input NOR gate utilizes paired E signals with T overlap, each 3-input NOR gate in the divider 200 does not process continuous paired E signals as is done in the divider 100. In particular, each 3-input NOR gate in the frequency divider 100 processes a pair of E clock signals, one of which is delayed by T / 2 with respect to the other. However, in the frequency divider 200, each 3-input NOR gate processes a pair of E clock signals, one of which is delayed by T with respect to the other. In this way, T overlap for mutual binary zero states is achieved.

[0039] Now combine Figure 2BThe timing diagram for the divider 200 shown is used to further explain the structure of the divider 200. The E1 clock signal has a rising edge at time t0. The E2 clock signal has a rising edge at time t1 which is T / 2 after time t0, the E3 clock signal has a rising edge at time t2 which is T / 2 after time t1, and so on. For example, the E4 clock signal rising edge is at time t3, the E5 clock signal rising edge is at time t4, the E6 clock signal rising edge is at time t5, the E7 clock signal rising edge is at time t6, and the E8 clock signal rising edge is at time t7. Each E clock signal can be paired with another E clock signal to form a pair of E clock signals with an overlap T, wherein both E clock signals are in a binary zero state. For example, the E1 clock signal and the E7 clock signal have such an overlap T that both signals are binary zero from time t4 to time t6.

[0040] The reset of the latch will be discussed first, followed by the setting of the latch. The NOR gate 225 that performs a NOR operation on the E1 clock signal and the E7 clock signal with the clkn input clock signal will then assert the P1 clock signal at time t5. The assertion of the P1 clock signal resets the first latch 205, causing the clock signal E6 to have a rising edge at time t5. The E2 clock signal and the E8 clock signal have an overlap T, causing both signals to be binary zeros from time t5 to time t7. The NOR gate 235 that performs a NOR operation on the E2 clock signal and the E8 clock signal with the clkp input clock signal will then assert the P2 clock signal at time t6. The assertion of the P2 clock signal resets the second latch 210, causing the clock signal E7 to have a rising edge at time t6. The E1 clock signal and the E3 clock signal have an overlap T, causing both signals to be binary zeros from time t6 to time t8, which is T / 2 after time t7. The NOR gate 245 that performs a NOR operation on the E1 clock signal and the E3 clock signal with the clkn input clock signal will then assert the P3 clock signal at time t7. The assertion of the P3 clock signal resets the third latch 215, causing the clock signal E8 to have a rising edge at time t7. Finally, the E2 clock signal and the E4 clock signal have an overlap T, causing both signals to be binary zeros from time t7 to time t9, which is T / 2 after time t8. The NOR gate 255 that performs a NOR operation on the E2 clock signal and the E4 clock signal with the clkp input clock signal will then assert the P4 clock signal at time t8. The assertion of the P3 clock signal resets the fourth latch 220, causing the clock signal E1 to have a rising edge at time t8.

[0041] With respect to the setting of the latches, the E3 clock signal and the E5 clock signal have an overlap T such that both signals are binary zeros from time t8 to time t10, T / 2 after time t9. The NOR gate 230, which NORs the E3 clock signal and the E5 clock signal with the clkn input clock signal, will then assert the P5 clock signal from time t9 to time t10. The assertion of the P5 clock signal sets the first latch 205 such that the clock signal E2 has a rising edge at time t9. Similarly, the NOR gate 240, which NORs the E6 clock signal and the E4 clock signal with the clkp input clock signal, will then assert the P6 clock signal from time t10 to time t11, T / 2 after time t10. The assertion of the P6 clock signal sets the second latch 210 such that the E3 clock signal has a rising edge at time t10. In addition, the NOR gate 250 that performs a NOR operation on the E7 clock signal and the E5 clock signal with the clkn input clock signal will then assert the P7 clock signal from time t11 to time t12, which is T / 2 after time t11. The assertion of the P7 clock signal sets the third latch 215, so that the E4 clock signal has a rising edge at time t11. Finally, the NOR gate 260 that performs a NOR operation on the E6 clock signal and the E8 clock signal with the clkp input clock signal will then assert the P8 clock signal from time t12 to time t13, which is T / 2 after time t12. The assertion of the P8 clock signal sets the fourth latch 220, so that the E5 clock signal has a rising edge at time t12.

[0042] Comparison of the frequency dividers 100 and 200 shows the general pattern for odd and even values ​​of N. For example, the latches can be considered to be arranged from the first latch to the Nth latch. The first N P clock signals of the plurality of 2N P clock signals can also be considered to have the same arrangement, from the P1 clock signal to the PN clock signal. Regardless of whether the divisor N is odd or even, each latch is reset by the corresponding P clock signal. For example, the P1 clock signal resets the first latch, the P2 clock signal resets the second latch, and so on, such that the PN clock signal resets the Nth latch. Similarly, the second N P clock signals ranging from the P(N+1) clock signal to the P2N clock signal control the setting of the latches. Therefore, the P(N+1) clock signal sets the first latch, the P(N+2) clock signal sets the second latch, and so on, such that the P2N clock signal sets the Nth latch.

[0043] The plurality of 2N E-clock signals may also be viewed as forming a first half ranging from the E1 clock signal to the EN clock signal, and a second half ranging from the E(N+1) clock signal to the E2N clock signal. The first half is processed by a 3-input NOR gate that controls the reset of the latches. For example, the 3-input NOR gate that controls the reset of the first latch processes the E1 clock signal. Similarly, the 3-input NOR gate that controls the reset of the second latch processes the E2 clock signal, and so on, such that the 3-input NOR gate that controls the reset of the Nth latch processes the EN clock signal. Each of these reset NOR gates also processes an E-clock signal that has T overlap with another E-clock signal being processed. The selection of the E-clock signal depends on the divisor N. For example, consider Figure 3 The E1 clock signal shown. Regardless of the value of the divisor N, the corresponding frequency divider divided by the divisor N will generate the E1 clock signal. As already discussed, each successive E clock signal is delayed by T / 2 for its previous E clock signal. Therefore, there is an E2 clock signal (not shown) delayed by T / 2 for the E1 clock signal, and so on. Therefore, the E(N+1) clock signal will have a rising edge at the falling edge of the E1 clock signal. This is true because the half cycle of each E clock signal is NT / 2. Therefore, each half cycle can be divided into N parts, each of which is T / 2. Therefore, the rising edge of the E(N+1) clock signal will be delayed by NT / 2 from the rising edge of the E1 clock signal. In order to overlap T with E1, an E clock signal delayed by T from the E(N+1) clock signal is selected. Since T is two and a half input clock cycles, such an E clock signal is the second E clock signal after the E(N+1) clock signal. Therefore, the E(N+3) clock signal will provide the desired T overlap with the E1 clock signal, regardless of whether N is an odd or even number. The 3-input NOR gate that controls the reset of the first latch and processes the E1 clock signal will then also process the E(N+3) clock signal. Similar reasoning shows that the reset 3-input NOR operation for each consecutive latch is indexed by 1 starting from the reset of the first latch. For example, the 3-input NOR gate that controls the reset of the second latch will process the E2 clock signal and the E(N+4) clock signal, and so on. If the index results in a value greater than 2N, the modulo 2N value is taken. For example, an index that does not take any modulo results in a 3-input NOR gate that controls the reset of the Nth latch to process the EN clock signal and the E(2N+2) clock signal. Because (2N+2) is greater than 2N, the modulo 2N value is taken, which is 2. Therefore, the reset of the Nth latch is controlled by the NOR operation of the EN clock signal, the E2 clock signal, and one of the input clock signals.

[0044] As previously noted, it is arbitrary which input clock signal is processed by the 3-input NOR gate that resets the first latch. But once a choice is made, the reset of each subsequent latch is controlled by the complement of the input clock signal that controls the reset of the previous latch. Similarly, the setting of the first latch is controlled by the complement of the input clock signal that controls the setting of the Nth latch. This results in two general modes depending on whether the divisor N is an even number or an odd number. If the divisor N is an even number, then the reset of the Nth latch is controlled by the complement of the input clock that controls the reset of the first latch. On the contrary, if the divisor N is an odd number, then the reset of the Nth latch is controlled by the same input clock signal that controls the reset of the first latch. This is visible for the divider 100 where the divisor N is an odd number: both NOR gates 145 and 165 process the clkn input clock signal. But in the divider 200, the NOR gate 225 processes the clkn input clock signal, while the NOR gate 255 processes the clkp input clock signal.

[0045] The latch reset for odd divisors N can be done as follows Figure 44 and generalized for frequency divisor 400 as shown in FIG. There are N latches ranging from the first latch 405 to the Nth latch 420. The NOR gate 425 NORs the E1 clock signal and the E(N+3) clock signal with one of the input clock signals to generate the P1 clock signal to reset the first latch 405. In this implementation, the clkn input clock signal is selected, although the clkp input clock signal may be selected for alternative implementations. The selection of the input clock signal for the gating of the NOR gate 425 then determines the input clock selection for all remaining latch reset and latch set NOR gates. In response to being reset, the first latch 405 asserts the E(N+2) clock signal and resets the E2 clock signal. To control the reset of the second latch 410, the NOR gate 435 performs a NOR operation on the E(N+4) clock signal and the E2 clock signal with the clkp input clock signal to generate the P2 clock signal. The clkp input clock signal is selected because the P2 clock signal is delayed by T / 2 with respect to the P1 clock signal. In response to being reset, the second latch 410 asserts the E(N+3) clock signal and resets the E3 clock signal. To control the reset of the third latch 415, the NOR gate 445 performs a NOR operation on the E(N+5) clock signal and the E3 clock signal with the clkn input clock signal to generate the P3 clock signal. In response to being reset, the third latch 415 asserts the E(N+4) clock signal and resets the E4 clock signal. More generally, it will be appreciated that the i-th latch (i being between 1 and less than or equal to 2N) is reset by a NOR gate that NORs the E(i) clock signal and the E(i+N+2) clock signal together with the appropriate input clock signal to produce the Pi clock signal. In response to the assertion of the Pi clock signal, the i-th latch asserts the E(i+N+1) clock signal and resets the E(i+1) clock signal. If (i+N+1) exceeds 2N, the modulo 2N value is taken. This general pattern is true for the N-th latch 420 because it is reset by a NOR gate that NORs the EN clock signal. When i is N, the E(i+N+2) clock signal is E2. Therefore, the N-th latch 420 is reset by a NOR gate 455 that NORs E2 and EN. In response to being reset, the Nth latch 420 asserts the E1 clock signal and resets the E(N+1) clock signal. The gate clock for NOR gate 455 has the same polarity selected for the gate of NOR gate 425 because there are an odd number of latches. Since the clkn input clock signal is processed by NOR gate 425, the same input clock signal is also processed by NOR gate 455.

[0046] A similar pattern exists for the setting of each latch in the divider 400. Each latch is set by a 3-input NOR gate that NORs the E signal with the same index as the latch plus N. For example, the first latch 405 is reset by a NOR gate 430 that NORs the E(N+1) clock signal. As previously discussed, the corresponding E signal that overlaps the i-th E clock signal is E(i+N+2). Adding N+2 to the index of the E(N+1) clock signal results in the E3 clock signal because 2N+3 is greater than 2N. Therefore, the NOR gate 430 NORs the E(N+1) clock signal and the E3 clock signal to produce the P(N+1) clock signal. Since the PN clock is gated by the clkn input clock signal, the NOR gate 430 is gated by the clkp input clock signal. In response to being set, the first latch 405 asserts the E2 clock signal and resets the E(N+2) clock signal. The setting of each consecutive latch is controlled by a "NOR" operation of a pair of E clock signals, the index of which is incremented by one for the pair of E clock signals for the previous latch. Therefore, the "NOR" gate 440 that generates the P(N+2) clock signal to set the second latch 410 is used to perform a "NOR" operation on the E4 clock signal with the E(N+2) clock signal and the clkp input clock signal. In response to being set, the second latch 410 asserts the E3 clock signal and resets the E(N+3) clock signal. Similarly, the "NOR" gate 450 that generates the P(N+3) clock signal to set the third latch 415 is used to perform a "NOR" operation on the E5 clock signal with the E(N+3) clock signal and the clkn input clock signal. In response to being set, the third latch 410 asserts the E4 clock signal and resets the E(N+4) clock signal. Finally, the NOR gate 460 asserts the P2N clock signal to control the setting of the Nth latch 420. To generate the P2N clock signal, the NOR gate 460 performs a NOR operation on the E2N clock signal and the E(N+2) clock signal with the clkn input clock signal.

[0047] For even divisors N, Figure 5An example frequency divider 500 is shown in . It can be seen that for the 3-input NOR gate in the frequency divider 500, the same selection of the E clock signal occurs as discussed for the frequency divider 400. Similar to the frequency divider 400, the frequency divider 500 has N latches arranged from the first latch 505 to the Nth latch 520. The NOR gate 525 that resets the first latch with the P1 clock signal performs a NOR operation on the E1 clock signal and the E(N+3) clock signal with the clkn input clock signal, as discussed with respect to the NOR gate 425. Similarly, the NOR gate 535 performs a NOR operation on the E2 clock signal and the E(N+4) clock signal to reset the second latch 510 with the P2 clock signal. Therefore, the NOR gate 535 is equivalent to the NOR gate 435. In the same manner, NOR gate 545 performs NOR operation on the E(N+5) clock signal and the E3 clock signal to reset the third latch 515 with the P3 clock signal. However, since there are an even number of latches, the N latch 520 is reset by the NOR gate 555 gated by the clkp input clock signal. In contrast, the NOR gate 455 is gated by the clkn input clock signal.

[0048] The setting of the latches in the frequency divider 500 is also similar to the setting of the latches in the frequency divider 400. For example, the NOR gate 530 performs a NOR operation on the E3 clock signal and the E(N+1) clock signal to control the setting of the first latch 505 using the P(N+1) clock signal. However, the gating of the NOR gate 530 is controlled by the clkn input clock signal because the clkp input clock signal gates the setting of the Nth latch 520. The setting of the second latch 510 by the NOR gate 540 is therefore gated by the clkp input clock signal. Similarly, the setting of the third latch 515 by the NOR gate 550 is therefore gated by the clkn input clock signal. Finally, the setting of the Nth latch 520 by the NOR gate 560 is gated by the clkp input clock signal. In addition to the input clock selection, it can be seen that the set and reset NOR gates of divider 500 are NORing the E clock signal similar to that discussed with respect to divider 400 .

[0049] Now for Figure 6 The method of frequency division according to the present disclosure is discussed with reference to the flowchart of FIG. The method includes: dividing the input clock signal by a divisor N into a plurality of 2N overlapping clock signals in action 600; wherein N is an integer of three or greater, and each overlapping clock signal has a duty cycle of about 50%. Figure 1A , Figure 2A , Figure 4 and Figure 5The discussed division of the input clock signal to form a plurality of E clock signals is an example of act 600. The method also includes act 605 of processing pairs of overlapping clock signals using the input clock signal to divide the input clock signal by a divisor N into a plurality of 2N non-overlapping clock signals, each non-overlapping clock signal having a duty cycle of approximately (50 / N)%. Figure 1A , Figure 2A , Figure 4 and Figure 5 The process of forming the P clock signal by the 3-input logic gate of is an example of action 605.

[0050] The frequency divider disclosed herein may be incorporated into any suitable mobile device or electronic system. Figure 7 As shown, a cellular phone 700, a laptop computer 705, and a tablet PC 710 may each include a frequency divider according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers may also be configured with a frequency divider constructed according to the present disclosure.

[0051] The present disclosure will now be summarized in the following series of clauses:

[0052] Clause 1. A frequency divider, the frequency divider comprising:

[0053] A plurality of stages, the plurality of stages being arranged in series from the first stage to the Nth stage, where N is three or

[0054] A larger integer and each level includes:

[0055] a 3-input logic gate having an output terminal coupled to a first input terminal of the 2-input logic gate, and

[0056] wherein the output terminal of the 2-input logic gate in each previous stage in the series is coupled to the first input terminal of the 3-input logic gate in the subsequent stage in the series, and wherein the output terminal of the 2-input logic gate in the Nth stage is coupled to the first input terminal of the 3-input logic gate in the first stage.

[0057] Clause 2. The frequency divider of clause 1, wherein the 2-input logic gates are cross-coupled to form N latches.

[0058] Clause 3. The frequency divider of any of clauses 1 to 2, wherein each three-input logic gate has a second input terminal coupled to a clock source.

[0059] Clause 4. The frequency divider of Clause 3, wherein the three-input logic gate of each stage has a third input terminal coupled to the output terminal of the 2-input terminal in another one of the stages.

[0060] Clause 5. A frequency divider, the frequency divider comprising:

[0061] A differential clock source, the differential clock source being configured to output a positive input clock signal and a negative input clock signal that is a complement of the positive input clock signal;

[0062] a plurality of N latches, wherein N is a complex positive integer greater than two;

[0063] a plurality of N first logic gates, each of the first logic gates having a first output terminal coupled to a reset input terminal of a corresponding one of the latches, each of the first logic gates being configured to process a unique pair of overlapping clock signals in a plurality of 2N overlapping clock signals using one of the positive input clock signal and the negative input clock signal to output a corresponding non-overlapping clock signal in a first plurality of N non-overlapping clock signals at the first output terminal;

[0064] Signals; and

[0065] a plurality of N second logic gates, each second logic gate having a second output terminal coupled to a set input terminal of a corresponding one of the latches, each second logic gate being configured to process a unique pair of overlapping clock signals among the plurality of 2N overlapping clock signals using one of the positive input clock signal and the negative input clock signal to output a corresponding non-overlapping clock signal among the second plurality of N non-overlapping clock signals at the second output terminal.

[0066] Clause 6. The frequency divider of Clause 5, wherein each latch in the plurality of N latches comprises a pair of cross-coupled logic gates.

[0067] Clause 7. The frequency divider of Clause 6, wherein the cross-coupled pair of logic gates in each latch of the plurality of N latches comprises a cross-coupled pair of NOR gates.

[0068] Clause 8. The frequency divider of any one of Clauses 5 to 7, wherein the plurality of N first logic gates comprises a first plurality of N 3-input NOR gates.

[0069] Clause 9. The frequency divider of any one of clauses 5 to 8, wherein the plurality of N second logic gates comprises a second plurality of N 3-input NOR gates.

[0070] Item 10. A frequency divider according to Item 8, wherein the first plurality of N 3-input NOR gates are arranged from a first 3-input NOR gate to an N 3-input NOR gate, and the first plurality of N non-overlapping clock signals are arranged from a first non-overlapping clock signal to an N 3-input NOR signal, and wherein the first 3-input NOR gate is configured to output the first non-overlapping clock signal, the second 3-input NOR gate is configured to output a second non-overlapping clock signal, and so on, such that the N 3-input NOR gate is configured to output the N 3-non-overlapping clock signal.

[0071] Item 11. A frequency divider according to Item 9, wherein the second plurality of N 3-input NOR gates are arranged from the (N+1)th 3-input NOR gate to the 2Nth 3-input NOR gate, and the second plurality of N non-overlapping clock signals are arranged from the (N+1)th non-overlapping clock signal to the 2Nth non-overlapping clock signal, and wherein the (N+1)th 3-input NOR gate is configured to output the (N+1)th non-overlapping clock signal, the (N+2)th 3-input NOR gate is configured to output the (N+2)th non-overlapping clock signal, and so on, so that the 2Nth 3-input NOR gate is configured to output the 2Nth non-overlapping clock signal.

[0072] Clause 12. The frequency divider of any one of clauses 5 to 11, wherein N is an even integer greater than two.

[0073] Clause 13. The frequency divider of any one of clauses 5 to 11, wherein N is an even-odd integer greater than two.

[0074] Clause 14. The frequency divider of any one of clauses 5 to 11, wherein the frequency divider is incorporated into a cellular telephone.

[0075] Clause 15. A fractional-N frequency divider, the fractional-N frequency divider comprising:

[0076] A differential clock source is configured to cycle a positive input clock signal and a negative input clock signal at a first frequency, wherein the negative input clock signal is

[0077] The complement of the positive input clock signal;

[0078] a plurality of N latches, each latch configured to output a corresponding pair of overlapping clock signals among 2N overlapping clock signals cycled at a second frequency, the second frequency being 1 / N of the first frequency and having an approximately 50% duty cycle, wherein N is an integer of 3 or greater;

[0079] and

[0080] a plurality of 2N logic gates, the plurality of 2N logic gates being configured to output 2N non-overlapping clock signals cycling at the second frequency and having a duty cycle of approximately (50 / N)%, each logic gate being configured to process two of the 2N overlapping clock signals using one of the negative input clock signal and the positive input clock signal to output a corresponding one of the 2N non-overlapping clock signals at an output terminal of the logic gate.

[0081] Clause 16. The divide-by-N frequency divider of Clause 15, wherein N equals three, and wherein the second frequency is 1 / 3 of the first frequency.

[0082] Clause 17. The divide-by-N frequency divider of Clause 16, wherein the plurality of N latches comprises a first latch, a second latch, and a third latch, and wherein the plurality of 2N logic gates comprises:

[0083] a first logic gate having an output terminal coupled to a reset terminal of the first latch;

[0084] a second logic gate having an output terminal coupled to a set terminal of the first latch;

[0085] a third logic gate, an output terminal of the third logic gate being coupled to a reset terminal of the second latch;

[0086] a fourth logic gate, an output terminal of the fourth logic gate being coupled to a set terminal of the second latch;

[0087] a fifth logic gate having an output terminal coupled to a reset terminal of the third latch; and

[0088] A sixth logic gate has an output terminal coupled to the set terminal of the third latch.

[0089] Clause 18. The divide-by-N frequency divider of clause 17, wherein each logic gate comprises a 3-input NOR gate.

[0090] Item 19. A divide-by-N frequency divider according to Item 18, wherein the corresponding pair of overlapping clock signals of the first latch includes a second overlapping clock signal and a fifth overlapping clock signal, the corresponding pair of overlapping clock signals of the second latch includes a second overlapping clock signal and a fifth overlapping clock signal, and the corresponding pair of overlapping clock signals of the third logic gate includes a first overlapping clock signal and a fourth overlapping clock signal.

[0091] Clause 20. The divide-by-N frequency divider of Clause 15, wherein N equals four, and wherein the second frequency is ¼ of the first frequency.

[0092] Clause 21. The divide-by-N frequency divider of Clause 20, wherein the plurality of N latches comprises a first latch, a second latch, a fourth latch, and a third latch, and wherein the plurality of 2N logic gates comprises:

[0093] a first logic gate having an output terminal coupled to a reset terminal of the first latch;

[0094] a second logic gate having an output terminal coupled to a set terminal of the first latch;

[0095] a third logic gate, an output terminal of the third logic gate being coupled to a reset terminal of the second latch;

[0096] a fourth logic gate, an output terminal of the fourth logic gate being coupled to a set terminal of the second latch;

[0097] a fifth logic gate, an output terminal of the fifth logic gate being coupled to a reset terminal of the third latch;

[0098] a sixth logic gate, an output terminal of the sixth logic gate being coupled to a set terminal of the third latch;

[0099] a seventh logic gate having an output terminal coupled to a reset terminal of the fourth latch; and

[0100] An eighth logic gate, an output terminal of the eighth logic gate is coupled to the set terminal of the fourth latch.

[0101] Clause 22. The frequency divider of clause 21, wherein each logic gate comprises a 3-input NOR gate.

[0102] Clause 23. A method of frequency division, the method comprising:

[0103] The input clock signal is divided into multiple 2N overlapping clock signals according to the divisor N;

[0104] N is an integer of three or greater, and each overlapping clock signal has a duty cycle of approximately 50%;

[0105] as well as

[0106] The pairs of overlapping clock signals are processed using the input clock signal to divide the input clock signal by a divisor N into a plurality of 2N non-overlapping clock signals, each of which has a duty cycle of approximately (50 / N)%.

[0107] Clause 24. The method of clause 23, wherein processing each pair of the overlapping clock signals comprises a NOR operation of the pair of the overlapping clock signals with the input clock signal to output a corresponding non-overlapping clock signal in the plurality of 2N non-overlapping clock signals.

[0108] Item 25. A method according to Item 23, wherein the input clock signal is a differential input clock signal including a positive input clock signal and a negative output clock signal, and wherein the processing of each pair of overlapping clock signals includes a "NOR" operation of the overlapping clock signal with one of the positive input clock signal and the negative output signal.

[0109] Clause 26. The method of clause 24, wherein the overlapping clock signals in each pair of overlapping clock signals have a delay with respect to each other of (N+2) times half a period of the input clock signal.

[0110] It should be understood that many modifications, substitutions and changes may be made to the materials, devices, configurations and methods of use of the device of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the specific implementations illustrated and described herein (because they are only some examples of the present disclosure), but should be completely equivalent to the attached claims and their functional equivalents.

Claims

1. A frequency divider, comprising: A plurality of stages, the plurality of stages being arranged in series from a first stage to an Nth stage, wherein N is an integer of three or greater and each stage comprises: a 3-input logic gate having an output terminal coupled to a first input terminal of the 2-input logic gate, and wherein the output terminal of the 2-input logic gate in each previous stage in the series is coupled to the first input terminal of the 3-input logic gate in the subsequent stage in the series, and wherein the output terminal of the 2-input logic gate in the Nth stage is coupled to the first input terminal of the 3-input logic gate in the first stage.

2. The frequency divider of claim 1, wherein the 2-input logic gates are cross-coupled to form N latches.

3. The frequency divider of claim 1, wherein each three-input logic gate has a second input terminal coupled to a clock source.

4. The frequency divider of claim 3, wherein the three-input logic gate of each stage has a third input terminal coupled to the output terminal of the 2-input terminal in another of the stages.

5. A frequency divider, comprising: A differential clock source, the differential clock source being configured to output a positive input clock signal and a negative input clock signal that is a complement of the positive input clock signal; a plurality of N latches, wherein N is a complex positive integer greater than two; a plurality of N first logic gates, each of the first logic gates having a first output terminal coupled to a reset input terminal of a corresponding one of the latches, each of the first logic gates being configured to process a unique pair of overlapping clock signals in a plurality of 2N overlapping clock signals using one of the positive input clock signal and the negative input clock signal to output a corresponding non-overlapping clock signal in a first plurality of N non-overlapping clock signals at the first output terminal; and a plurality of N second logic gates, each second logic gate having a second output terminal coupled to a set input terminal of a corresponding one of the latches, each second logic gate being configured to process a unique pair of overlapping clock signals among the plurality of 2N overlapping clock signals using one of the positive input clock signal and the negative input clock signal to output a corresponding non-overlapping clock signal among the second plurality of N non-overlapping clock signals at the second output terminal.

6. The frequency divider of claim 5, wherein each latch of the plurality of N latches comprises a pair of cross-coupled logic gates.

7. The frequency divider of claim 6, wherein the cross-coupled pair of logic gates in each of the plurality of N latches comprises a cross-coupled pair of NOR gates.

8. The frequency divider of claim 5 , wherein the plurality of N first logic gates comprises a first plurality of N 3-input NOR gates.

9. The frequency divider of claim 5, wherein the plurality of N second logic gates comprises a second plurality of N 3-input NOR gates.

10. The frequency divider of claim 8, wherein the first plurality of N 3-input NOR gates are arranged from a first 3-input NOR gate to an N 3-input NOR gate, and the first plurality of N non-overlapping clock signals are arranged from a first non-overlapping clock signal to an N 3-input NOR signal, and wherein the first 3-input NOR gate is configured to output the first non-overlapping clock signal, the second 3-input NOR gate is configured to output a second non-overlapping clock signal, and so on, such that the N 3-input NOR gate is configured to output the N 3-non-overlapping clock signal.

11. The frequency divider of claim 9, wherein the second plurality of N 3-input NOR gates are arranged from the (N+1)th 3-input NOR gate to the 2Nth 3-input NOR gate, and the second plurality of N non-overlapping clock signals are arranged from the (N+1)th non-overlapping clock signal to the 2Nth non-overlapping clock signal, and wherein the (N+1)th 3-input NOR gate is configured to output the (N+1)th non-overlapping clock signal, the (N+2)th 3-input NOR gate is configured to output the (N+2)th non-overlapping clock signal, and so on, so that the 2Nth 3-input NOR gate is configured to output the 2Nth non-overlapping clock signal.

12. The frequency divider of claim 5, wherein N is an even integer greater than two.

13. The frequency divider of claim 5, wherein N is an even or odd number greater than two.

14. The frequency divider of claim 5, wherein the frequency divider is incorporated into a cellular telephone.

15. A divide-by-N frequency divider, the divide-by-N frequency divider comprising: a differential clock source configured to cycle a positive input clock signal and a negative input clock signal at a first frequency, wherein the negative input clock signal is a complement of the positive input clock signal; a plurality of N latches, each latch configured to output a corresponding pair of overlapping clock signals among 2N overlapping clock signals cycled at a second frequency, the second frequency being 1 / N of the first frequency and having an approximately 50% duty cycle, wherein N is an integer of 3 or greater; and a plurality of 2N logic gates, the plurality of 2N logic gates being configured to output 2N non-overlapping clock signals cycling at the second frequency and having a duty cycle of approximately (50 / N)%, each logic gate being configured to process two of the 2N overlapping clock signals using one of the negative input clock signal and the positive input clock signal to output a corresponding one of the 2N non-overlapping clock signals at an output terminal of the logic gate.

16. The fractional-N frequency divider of claim 15, wherein N equals three, and wherein the second frequency is 1 / 3 of the first frequency.

17. The divide-by-N frequency divider of claim 16, wherein the plurality of N latches comprises a first latch, a second latch, and a third latch, and wherein the plurality of 2N logic gates comprises: a first logic gate having an output terminal coupled to a reset terminal of the first latch; a second logic gate having an output terminal coupled to a set terminal of the first latch; a third logic gate, an output terminal of the third logic gate being coupled to a reset terminal of the second latch; a fourth logic gate, an output terminal of the fourth logic gate being coupled to a set terminal of the second latch; a fifth logic gate, an output terminal of the fifth logic gate being coupled to a reset terminal of the third latch; as well as A sixth logic gate has an output terminal coupled to the set terminal of the third latch.

18. The divide-by-N frequency divider of claim 17, wherein each logic gate comprises a 3-input NOR gate.

19. The divide-by-N frequency divider of claim 18, wherein the corresponding pair of overlapping clock signals of the first latch comprises a second overlapping clock signal and a fifth overlapping clock signal, the corresponding pair of overlapping clock signals of the second latch comprises a second overlapping clock signal and a fifth overlapping clock signal, and the corresponding pair of overlapping clock signals of the third logic gate comprises a first overlapping clock signal and a fourth overlapping clock signal.

20. The fractional-N frequency divider of claim 15, wherein N equals four, and wherein the second frequency is 1 / 4 of the first frequency.

21. The divide-by-N frequency divider of claim 20, wherein the plurality of N latches comprises a first latch, a second latch, a fourth latch, and a third latch, and wherein the plurality of 2N logic gates comprises: a first logic gate having an output terminal coupled to a reset terminal of the first latch; a second logic gate having an output terminal coupled to a set terminal of the first latch; a third logic gate, an output terminal of the third logic gate being coupled to a reset terminal of the second latch; a fourth logic gate, an output terminal of the fourth logic gate being coupled to a set terminal of the second latch; a fifth logic gate, an output terminal of the fifth logic gate being coupled to a reset terminal of the third latch; a sixth logic gate, an output terminal of the sixth logic gate being coupled to a set terminal of the third latch; a seventh logic gate, an output terminal of the seventh logic gate being coupled to a reset terminal of the fourth latch; as well as An eighth logic gate, an output terminal of the eighth logic gate is coupled to the set terminal of the fourth latch.

22. The frequency divider of claim 21, wherein each logic gate comprises a 3-input NOR gate.

23. A frequency division method, the frequency division method comprising: Divide the input clock signal into multiple 2N overlapping clock signals according to the divisor N; in N is an integer of three or greater, and each overlapping clock signal has a duty cycle of approximately 50%; as well as The pairs of overlapping clock signals are processed using the input clock signal to divide the input clock signal by a divisor N into a plurality of 2N non-overlapping clock signals, each of which has a duty cycle of approximately (50 / N)%.

24. The method of claim 23, wherein processing each pair of the overlapping clock signals comprises a NOR operation of the pair of the overlapping clock signals with the input clock signal to output a corresponding non-overlapping clock signal in the plurality of 2N non-overlapping clock signals.

25. The method of claim 23, wherein the input clock signal is a differential input clock signal comprising a positive input clock signal and a negative output clock signal, and wherein the processing of each pair of the overlapping clock signals comprises a "NOR" operation of the overlapping clock signal with one of the positive input clock signal and the negative output signal.

26. The method of claim 24, wherein the overlapping clock signals in each pair of overlapping clock signals have a delay with respect to each other of (N+2) times half a period of the input clock signal.

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