Capacitive voltage regulator in integrated circuit package

Abstract

The invention relates to a capacitive voltage regulator in an integrated circuit package. Embodiments herein relate to techniques for integrating a capacitive voltage regulator in an integrated circuit (IC) package. The voltage regulator may provide power supply to one or more load domains in the IC package. Transistors of the voltage regulator may be included on the same die as one or more load domains, on another die, and / or on middleware of the IC package. The capacitor may be included in the same die as the transistor, included in middleware, included in an encapsulation layer (e.g., an encapsulation core), and / or included in the same die as one or more load domains. Thus, the voltage regulator can be integrated at a location proximate to the associated load domain, delivering power in a short current path, providing reduced input impedance, output impedance, and associated loss compared to prior art. Other embodiments may be described and claimed.

Description

Technical Field

[0001] The present application relates generally to the field of integrated circuits and, more particularly, to capacitive voltage regulators in integrated circuit packages. Background Art

[0002] Computing devices often rely on voltage converters, also known as voltage regulators, to obtain power. For example, a direct current (DC) to DC voltage converter can convert a power supply at one DC voltage to another, usually lower DC voltage. The voltage converter can convert the main supply voltage (e.g., 12-48V) of a computing device down to a lower voltage (e.g., about 1V). The lower voltage can be used by various components in the computing device, such as a Universal Serial Bus (USB) interface, a memory such as a dynamic random access memory (DRAM), and a processing resource such as a central processing unit (CPU). However, it is challenging to supply power in an efficient and economical manner. Summary of the invention

[0003] According to one aspect of the present application, a device is provided, comprising: a first die including a load; and a capacitive voltage regulator for providing power supply to the load, wherein the capacitive voltage regulator comprises a transistor and a capacitor, and wherein the transistor is included in the first die or in a second die different from the first die.

[0004] According to another aspect of the present application, an integrated circuit (IC) package is provided, comprising: a packaging layer; a middleware coupled to the packaging layer; a first die coupled to the middleware, wherein the first die comprises a load; and a voltage regulator for providing power supply to the load, wherein the voltage regulator comprises a transistor and a capacitor, and wherein the transistor is included in the middleware or in a second die coupled to the middleware.

[0005] According to another aspect of the present application, a system is provided, comprising: a battery interface for receiving a power supply from a battery; and an integrated circuit (IC) package, the IC package comprising: middleware; a first die coupled to the middleware, wherein the first die comprises a load domain; and a capacitive voltage regulator for receiving an input voltage corresponding to the power supply and generating an output voltage provided to the load domain, wherein a capacitor of the capacitive voltage regulator is included in one or more of: the first die, the middleware, or a second die coupled to the middleware. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments of the present disclosure will be more fully understood through the detailed description given below and through the drawings of various embodiments of the present disclosure, however the detailed description and drawings should not be understood as limiting the present disclosure to specific embodiments but are only for illustration and understanding.

[0007] Figure 1 An example integrated circuit (IC) package with a capacitive voltage regulator is illustrated in accordance with various embodiments.

[0008] Figure 2A An example capacitive voltage regulator and associated current paths are illustrated in accordance with various embodiments.

[0009] Figure 2B An example capacitive voltage regulator is illustrated in accordance with various embodiments.

[0010] Figure 3A Another example IC package according to various embodiments is illustrated.

[0011] Figure 3B Another example IC package according to various embodiments is illustrated.

[0012] Figure 3C Another example IC package according to various embodiments is illustrated.

[0013] Figure 3D Another example IC package according to various embodiments is illustrated.

[0014] Figure 4A Another example IC package according to various embodiments is illustrated.

[0015] Figure 4B Another example IC package according to various embodiments is illustrated.

[0016] Figure 5 Another example IC package according to various embodiments is illustrated.

[0017] Fig. 6A Another example IC package according to various embodiments is illustrated.

[0018] Figure 6B Another example IC package according to various embodiments is illustrated.

[0019] Fig. 7A Another example IC package according to various embodiments is illustrated.

[0020] Figure 7B Another example IC package according to various embodiments is illustrated.

[0021] Figure 7C Another example IC package according to various embodiments is illustrated.

[0022] Fig. 8A Another example IC package according to various embodiments is illustrated.

[0023] Figure 8B Another example IC package according to various embodiments is illustrated.

[0024] Fig. 9 Another example IC package according to various embodiments is illustrated.

[0025] Fig.10 Another example IC package according to various embodiments is illustrated.

[0026] Fig.11 The illustrations illustrate examples of components that may be present in a computing system for implementing the techniques (eg, operations, processes, methods, and approaches) described herein, according to various embodiments. DETAILED DESCRIPTION

[0027] Various embodiments herein provide techniques for integrating capacitive voltage regulators (also referred to as voltage converters) in integrated circuit (IC) packages. The voltage regulator may include a transistor (e.g., a field effect transistor (FET)) and a capacitor. The voltage regulator may provide power supply for one or more load domains in the IC package. The load domain may, for example, include a processor circuit (e.g., a central processing unit (CPU) circuit, a graphics processor circuit, etc.), a memory circuit, an input / output circuit, and / or other appropriate circuit loads. In an embodiment, the transistor of the voltage regulator may be included on the same die with one or more load domains, included on another die, and / or included on an interposer of the IC package. The capacitor may be included in the same die as the transistor, included in the interposer (including or not including the transistor in the interposer), included in the packaging layer (e.g., the packaging core), and / or included in the same die with one or more load domains.

[0028] The capacitors can be implemented using silicon-based bulk capacitor technology to create small, high current density capacitive voltage regulators. This allows the voltage regulator to be integrated close to the associated load domain, delivering power with a short current path, thereby providing reduced input impedance (Zin), output impedance (Zout), and associated I 2 R and voltage margin loss.

[0029] Furthermore, since bulk capacitors offer much higher energy density compared to in-package inductors, capacitive voltage regulators can provide superior performance in terms of efficiency, power density, and Vin / Vout capability.

[0030] As computing performance demands increase, the current requirements of the IC power domain are also increasing. This requirement increases the input voltage required when the current enters the socket due to current / socket limitations.

[0031] At the same time, to improve power efficiency, performance per watt, and performance to TCO (total cost of ownership) ratios, finer-grained power domains are needed to more precisely control where and when power is consumed.

[0032] In addition, the industry is moving from single-die products to multi-chip packaging solutions that increasingly rely on advanced packaging. Advanced packaging provides the opportunity to connect several dies (also called tiles or cores) closer together than before, but it may also increase the impedance Zin of the input power delivery network (PDN) and the impedance Zout of the output PDN because the current must pass through multiple dies, bumps, through-silicon vias (TSVs), etc., thereby increasing the resistive I 2 R losses and / or voltage margin requirements.

[0033] These trends combined mean that voltage converters and regulators are increasingly burdened with 1) providing larger Vin / Vout ratios; 2) maintaining or improving efficiency; and 3) doing this in a smaller footprint / volume to minimize cost.

[0034] Today's popular solutions rely on inductor-based switch-mode voltage converters. However, there are physical limits on how small an inductor can be while still providing good performance (e.g., inductance, quality factor, equivalent series resistance, etc.). As a result, these inductors tend to be large in terms of footprint and / or volume and must be integrated into the package structure. This approach not only creates significant practical difficulties, as the associated inductor routing may obstruct other routing (e.g., signal routing, I / O routing, etc.), but also increases the length of the current loop, thereby increasing path resistance and losses.

[0035] Some IC packages use linear regulators. These regulators may be much smaller and can be scaled appropriately for the load domain requirements, but they do not reduce the input current. Therefore, they do not provide a viable solution for a wide variety of product segments. In addition, the lack of transformer effect also means that their efficiency is very sensitive to their input PDN impedance Zin, which tends to limit multi-threaded performance.

[0036] As described above, the embodiments of the present invention provide a capacitive voltage regulator integrated in an IC package close to the relevant load domain. Compared with the previous technology, the voltage regulator can have a shorter current path and reduced input impedance (Zin), output impedance (Zout) and associated I 2 R and the voltage margin loss provide power to the load domain. Aspects of various embodiments will be further described below with reference to the accompanying drawings.

[0037] Figure 1 An IC package 100 is illustrated according to various embodiments. The IC package 100 includes a die 102 with load domains 104a-b. The die 102 also includes a voltage regulator (VR) circuit 106 and a capacitor 108 forming a voltage regulator. The VR circuit 106 may include a transistor (e.g., a power FET). The die 102 may be coupled to an intermediary (e.g., a silicon intermediary) 110 via microbumps 112. The intermediary 110 may be coupled to a package structure 114 via bumps 116.

[0038] The voltage regulator may provide power supply to one or more of the load domains 104a-b. The load domains 104a-b may include, for example, processor circuits (eg, CPU circuits, graphics processor circuits, etc.), memory circuits, input / output circuits, and / or other appropriate circuit loads.

[0039] Figure 1 Also illustrated are input current path 118, load (output) current path 120, and Vss current path 122. Figure 2A A voltage regulator 200 is schematically illustrated, which may be used with Figure 1 The voltage regulator 200 corresponds to the voltage regulator 106, having the VR circuit 106 and the capacitor 108. The voltage regulator 200 can receive an input voltage Vin and generate an output voltage Vout. In addition, the voltage regulator 200 can have an associated input impedance Zin and an output impedance Zout.

[0040] Figure 2BAn example circuit of a switched capacitor voltage regulator 250 (voltage regulator 250) according to various embodiments is illustrated. Voltage regulator 250 may correspond to voltage regulator 200. Voltage regulator 250 may include one or more phases, such as a first phase 202 and a second phase 204 coupled in parallel between an input terminal 206 and an output terminal 208. First phase 202 includes a capacitor 214 and transistors 216a-d (depicted as switches). Transistors 216a and 216b may receive a first control signal (Φ1), and transistors 216c and 216d may receive a second control signal (Φ2). Both the first and second control signals may alternate between a first logic value (e.g., logic 0) and a second logic value (e.g., logic 1). When the second control signal has a second logic value, the first control signal may have a first logic value; and when the second control signal has a first logic value, the first control signal may have a second logic value. In some embodiments, the first and second control signals may have a 50% duty cycle and / or may correspond to pulse width modulation (PWM) and / or pulse frequency modulation (PFM) control signals.

[0041] Transistors 216a-d may be turned on and off in response to first and second control signals to repeatedly switch capacitor 214 between a first state and a second state. In the first state, capacitor 214 may be coupled between input terminal 206 and output terminal 208. In the second state, capacitor 214 may be coupled between output terminal 208 and ground 218.

[0042] Obviously, the voltage regulator 250 is presented as just one example of a capacitive voltage regulator, and other configurations of capacitive voltage regulators may also be used according to various embodiments.

[0043] In other IC package configurations that use a voltage regulator with one or more inductors, the inductor is typically implemented in the package structure 114 to enable an inductor of sufficient size and performance to be implemented. However, this results in relatively long input and output current paths, from the VR circuit on the top die through the middleware, through the package core to the package inductor, and then back through the middleware to the load domain. The large current loop results in higher resistance and associated losses. In contrast, the capacitive voltage regulator of IC package 100 provides a significantly shorter current path than the prior art, and has lower input impedance (Zin), output impedance (Zout), and associated I 2 R and voltage margin loss are reduced. For example, Figure 1As shown, input circuit path 118 and output circuit path 120 may be routed through middleware 110. However, the top metal layer of package structure 114 may also be used to distribute the output current, which may still provide a shorter current path than an inductor-based voltage regulator and may provide lower resistance than the on-die metal layer.

[0044] In various embodiments, capacitor 108 may be implemented using silicon-based bulk capacitor technology to create a small volume, high current density capacitor and enable the capacitor to be located close to VR circuit 106 (e.g., as shown in FIG. Figure 1 For example, capacitor 108 may include a metal-oxide-semiconductor (MOS) capacitor, a device capacitor (e.g., a transistor connected to form a capacitor), a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, a deep trench capacitor, and / or other suitable types of capacitors or combinations thereof.

[0045] As previously described, the voltage regulator formed by the VR circuit 106 and the capacitor 108 can receive an input voltage and generate an output voltage provided to the load domains 104a-b. For example, the input voltage can be a supply voltage of a battery and / or a main power supply. In some embodiments, the associated device can have a main voltage regulator to convert the supply voltage of the battery and / or the main power supply to an intermediate voltage (e.g., lower than the supply voltage), and the intermediate voltage can be provided as an input voltage to the voltage regulator of the IC package 100. The output voltage can be the supply voltage used by the load domains 104a-b and / or other suitable voltages.

[0046] Figure 3A Another example IC package 300 is illustrated in accordance with various embodiments. IC package 300 may be similar to IC package 100, except that VR circuit 306 and capacitor 308 are included in a separate die 302a from die 302b and 302c, which include respective load domains 304a-b. Dies 302a-c are coupled to middleware 310 via microbumps 312. In other embodiments, dies 302a-c may be coupled to middleware 310 via hybrid bonds 324 (also referred to as hybrid bonded interconnects (HBIs)) on middleware 310 instead of microbumps, such as Figure 3B The IC package 350 is shown in FIG.

[0047] Having VR circuit 306 on a separate die from the load domain enables a different manufacturing process to be used for VR circuit 306 than for the load domain. For example, VR circuit 306 may use a less advanced process than the load domain, which may reduce the cost of IC package 300. Additionally, or alternatively, the process used for VR circuit 306 may produce larger transistors than those used in load domains 304a-b, which may provide better power delivery performance.

[0048] Figure 3C Another example IC package 360 ​​is illustrated that includes a redistribution layer (RDL) 326 coupled to the die 302a-c and the middleware 310. For example, a first side of the RDL 326 can be coupled to the die 302a-c, and a second side (opposite the first side) of the RDL 326 can be coupled to the middleware 310. The input current and / or output current of the voltage regulator can be routed through the RDL 326. The RDL 326 can include a thicker metal layer than is typically used in the middleware 310 and / or the packaging structure 314, thereby providing reduced resistance. Therefore, the RDL 326 can improve the lateral wiring resistance from the voltage regulator to the load domain 304a-b, thereby reducing the output impedance Zout and the associated resistance losses and voltage margin requirements. Hybrid bonding and / or microbumps can be used to couple the die 302a-c to the RDL 326, and / or to couple the RDL 326 to the middleware 310. For example, Figure 3C The IC package 360 ​​shown in FIG. 3 includes hybrid bonds 326 a for coupling the dies 302 a - c to the RDL 326 , and hybrid bonds 326 b for coupling the RDL 326 to the middleware 310 . Figure 3D Another similar IC package 370 is illustrated that includes hybrid bonding 326 for coupling the dies 302 a - c to the RDL 326 and micro bumps 312 for coupling the RDL 326 to the interposer 310 .

[0049] Figure 4A Another example IC package 400 is illustrated in accordance with various embodiments. The IC package 400 includes Figure 3C 4. The RDL 426 of the die 402a-c can be coupled to the RDL 426 on the opposite side of the die 402a-c. For example, a first side (e.g., front side) of the die 402a-c can be coupled to the interposer 410 (e.g., via microbumps 412), and the RDL 426 can be coupled to a second side (e.g., back side) of the die 402a-c (e.g., via hybrid bonding). The die 402a-c can include TSVs 428 to couple the circuitry of the die 402a-c to the RDL 426.

[0050] The configuration of IC package 400 enables power distribution to be performed on the backside of die 402a-c through RDL 426. This frees up more microbumps 412 and / or die area on the frontside for distributing I / O signals and / or other signals, thereby enabling increased bandwidth.

[0051] Figure 4B Another example IC package 450 is illustrated in accordance with various embodiments. IC package 450 may be similar to IC package 400, except that capacitor 408 may be located on a side of die 402a adjacent to RDL 426 (as opposed to IC package 400, where capacitor 408 is located on a side of die 402a adjacent to middleware 410). IC package 450 may include TSVs 428a to couple circuits of load domains 404a-b to RDL 426, and TSVs 428b to couple VR circuit 406 to middleware 410 via microbumps 412.

[0052] In some embodiments, some or all of the capacitors of the voltage regulator may be included in a different die or structure than the die that includes the VR circuit. Figure 5 An example IC package 500 is illustrated in which a VR circuit 506 is included in a die 502a and a capacitor 508 is included in an interposer 510. This enables the capacitor 508 to be arranged in a larger area and / or volume, which can enable the use of a larger capacitor. A larger capacitor can provide increased output current capability and efficiency, among other benefits. Alternatively, or additionally, a larger capacitor can enable the voltage regulator to handle a larger input voltage.

[0053] Fig. 6A Another IC package 600 according to various embodiments is illustrated. In the IC package 600, the VR circuit 606 and the associated capacitor 608 are both included in the middleware 610 (eg, active middleware). The middleware 610 can be connected to the middleware 610 via a hybrid bond 624 (eg, Fig. 6A ), microbumps, and / or other suitable mechanisms are coupled to a die 602 including one or more load domains 604. For example, Figure 6B Illustrated is an IC package 650 , which is similar to IC package 600 , except that microbumps 612 are used to couple die 602 to interposer 610 .

[0054] The configuration of IC packages 600 and / or 650 may enable output current to flow vertically from the voltage regulator to the load domain 604 , and may further shorten the length of the current path and provide better efficiency.

[0055] Fig. 7A , Figure 7B and Figure 7C A further example of an IC package is illustrated in which VR circuit 706 is included in middleware 710, according to various embodiments. As shown, VR circuit 706 is implemented in only a portion of the cross-sectional area of ​​middleware 710. This can enable active middleware 710 to also include other circuits, such as memory circuits, I / O circuits, etc. The IC package may include multiple areas of VR circuit 706, which may implement one or more voltage regulators.

[0056] Fig. 7A An example IC package 700 is illustrated in which a capacitor 708 is also implemented in the middleware 710. The capacitor 708 may be arranged in a larger cross-sectional area than the VR circuit 706. Figure 5 As described, this may enable the use of larger capacitors, thereby providing increased output current capability and efficiency and / or the ability to handle higher input voltages.

[0057] Figure 7B Another example IC package 750 is illustrated in which VR circuit 706 is implemented in middleware 710 and capacitor 708 is implemented in die 702 including load domain 704. As shown, capacitor 708 may be arranged in a larger cross-sectional area than VR circuit 706, or may be arranged in the same or smaller cross-sectional area.

[0058] Figure 7C Another example IC package 760 is illustrated, in which the VR circuit 706 and the capacitor 708 are included in the middleware 710, and the VR circuit 706 and the capacitor 708 only occupy a portion of the cross-sectional area of ​​the middleware 710. Figure 7C As shown, capacitor 708 may be arranged in substantially the same cross-sectional area as VR circuit 706. In some configurations, it may be beneficial to not place capacitor 708 in close proximity to other circuits (e.g., input / output circuits) that may interfere with capacitor 708 and / or otherwise degrade performance.

[0059] Fig. 8A Another example IC package 800 according to various embodiments is illustrated. IC package 800 can be similar to IC package 700 of FIG. 7 , with VR circuit 806 and capacitor 808 included in middleware 810. However, IC package 800 can include RDL 826 coupled between middleware 810 and die 802 including load domain 804. For some load domains, the current consumption profile is significantly non-uniform across the die area. Additionally, or alternatively, when VR circuit 806 does not occupy the entire cross-sectional area of ​​the middleware, there may still be a large amount of lateral current flowing. Including RDL 826 in IC package 800 can reduce lateral conduction losses.

[0060] like Fig. 8A As shown in the example implementation of the IC package 800 in , the RDL 826 can be coupled to the die 802 via hybrid bonding 824 and can be coupled to the interposer 810 via micro bumps 812 . Figure 8B Illustrated is an IC package 850 that is similar to IC package 800 except that various hybrid bonds 824a-b are used to couple RDL 826 to die 802 and interposer 810. Obviously, other mechanisms and / or combinations of interconnect / routing structures may be used in various embodiments.

[0061] Fig. 9 Another example IC package 900 is illustrated in accordance with various embodiments. The IC package 900 includes a VR circuit 906 in a middleware 910 and an associated capacitor 908 in a package structure 914 (e.g., in the core of the package structure 914). The IC package 900 also includes an RDL 926 coupled between the middleware 910 and a die 902 including a load domain 904. In other embodiments, the RDL 926 may be omitted, and the middleware 910 may be coupled to the die 902 via microbumps, hybrid bonding, and / or other suitable mechanisms.

[0062] In some embodiments, capacitor 908 may be integrated onto a die embedded in a package structure 914 (e.g., a package core). The thickness of the package structure and / or package core may enable the use of a larger volume capacitor compared to embodiments where capacitor 908 is included in other parts of the IC package. Additionally, or alternatively, the cost of integrating capacitor 908 into package structure 914 may be lower than other configurations. The current path of IC package 900 may be longer than other configurations described herein, but still shorter than prior art utilizing an inductor in the package structure.

[0063] Obviously, Figure 1-Figure 9 The IC packages shown in are only example implementations, and these techniques and configurations may be combined in any suitable manner according to various embodiments. For example, in some embodiments, capacitors of a voltage regulator may be arranged at multiple locations within an IC package.

[0064] Fig.10 An example IC package 1000 is illustrated in accordance with various embodiments. The IC package 1000 includes a VR circuit 1006 in a middleware 1010. The voltage regulator's associated capacitors 1008a-e are included in a die 1002, which includes a load domain 1004, the middleware 1010, and a packaging structure 1014. In embodiments, these capacitors 1008a-e may be electrically coupled in parallel, or may be unique capacitors in a given capacitive voltage regulator topology.

[0065] Placing capacitors in different locations on the IC package may enable the use of capacitors of different sizes and / or types, which may provide one or more benefits, such as improved performance, reduced cost, etc.

[0066] Fig.11 1100 illustrates an example of components that may be present in a computing system 1150 for implementing the techniques (e.g., operations, processes, methods, and approaches) described herein, according to various embodiments. Voltage regulator 1100 may correspond to a voltage regulator described herein (e.g., reference Figure 1-Figure 10 ), and may provide a power supply (e.g., an output voltage) to one or more components (which may correspond to load domains described herein) of computing system 1150. In some embodiments, the voltage may be controlled by a control signal provided by processor circuit 1152 (e.g., a power management unit included in processor circuit 1152).

[0067] The memory circuit 1154 may store instructions, and the processor circuit 1152 may execute the instructions to perform the functions described herein.

[0068] The computing system 1150 may include any combination of the hardware or logic components mentioned herein. These components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or combinations thereof adapted in the computing system 1150, or as components otherwise contained within a housing of a larger system. For one embodiment, at least one processor 1152 may be packaged together with the computing logic 1182 and configured to implement aspects of the various example embodiments described herein to form a system-in-package (SiP) or system-on-chip (SoC).

[0069] System 1150 includes a processor circuit in the form of one or more processors 1152. Processor circuit 1152 includes circuits such as (but not limited to): one or more processor cores and one or more of the following: cache memory, low drop-out (LDO) voltage regulator, interrupt controller, serial interface such as SPI, I2C or general programmable serial interface circuit, real time clock (RTC), timer-counter including interval and watchdog timer, general I / O, memory card controller such as secure digital / multi-media card (SD / MMC) or similar interface, mobile industry processor interface (MIPI) interface and joint test access group (JTAG) test access port. In some implementations, processor circuit 1152 may include one or more hardware accelerators (e.g., the same or similar to acceleration circuit 1164), which may be microprocessors, programmable processing devices (e.g., FPGA, ASIC, etc.), etc. The one or more accelerators may include, for example, computer vision and / or deep learning accelerators. In some implementations, the processor circuit 1152 may include on-chip memory circuitry, which may include any suitable volatile and / or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, and / or any other type of memory device technology, such as those discussed herein.

[0070] The processor circuit 1152 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acorn RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio-frequency integrated circuits (RFICs), one or more microprocessors or controllers, multi-core processors, multi-threaded processors, ultra-low voltage processors, embedded processors, or any other known processing elements, or any suitable combination of these. The processor (or core) 1152 may be coupled to or may include a memory / storage device, and may be configured to execute instructions stored in the memory / storage device to enable various applications or operating systems to run on the platform 1150. The processor (or core) 1152 is configured to operate application software to provide specific services to users of the platform 1150. In some embodiments, the (one or more) processors 1152 may be (or may be configured to) be (one or more) dedicated processors / controllers configured to operate according to various embodiments herein.

[0071] As an example, the processor(s) 1152 may include Core based architecture TM Processors such as i3, i5, i7, i9 based processors; Microcontroller-based processors such as Quark TM 、Atom TM Or other MCU-based processors; (one or more) Processor(s), processor, or available from Santa Clara, California However, any number of other processors may be used, such as one or more of the following: Advanced Micro Devices (AMD) Architecture, such as (one or more) or Processor, Accelerated Processing Unit (APU), MxGPU, (one or more) processor, etc.; from The company's (one or more) A5-A12 and / or S1-S4 processors, from Snapdragon(s) from technology companies TM or Centriq TM Processor, Texas Instruments, (One or more) Open Multimedia Applications Platform (OMAP) TM Processors; MIPS-based designs from MIPS Technologies Inc., such as the MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holdings plc, such as the ARM Cortex-A, Cortex-R, and Cortex-M series processors; and processors manufactured by Cavium TM Provided by the company In some implementations, the processor(s) 1152 may be part of a system on a chip (SoC), a system-in-Package (SiP), a multi-chip package (MCP), etc., where the processor(s) 1152 and other components are formed as a single integrated circuit, or a single package, such as from Edison TM or Galileo TM SoC Board. Other examples of processor(s) 1152 are mentioned elsewhere in this disclosure.

[0072] The system 1150 may include or be coupled to an acceleration circuit 1164, which may be implemented by one or more AI / ML accelerators, neural compute sticks, neuromorphic hardware, FPGAs, arrangements of GPUs, one or more SoCs (including programmable SoCs), one or more CPUs, one or more digital signal processors, dedicated ASICs (including programmable ASICs), PLDs (such as complex PLDs (CPLDs) or high complexity PLDs (HCPLDs)), and / or other forms of specialized processors or circuits designed to implement one or more specialized tasks. These tasks may include AI / ML processing (e.g., including training, inference, and classification operations), visual data processing, network data processing, object detection, rule analysis, and the like. In an FPGA-based implementation, the acceleration circuit 1164 may include logic blocks or logic architectures and other interconnected resources that may be programmed (configured) to perform various functions, such as the processes, methods, functions, and the like of the various embodiments discussed herein. In such an implementation, the acceleration circuit 1164 may also include a memory unit (e.g., EPROM, EEPROM, flash memory, static memory (e.g., SRAM, antifuse, etc.) for storing logic blocks, logic architectures, data, etc. in a LUT, etc.

[0073] In some implementations, the processor circuit 1152 and / or the acceleration circuit 1164 may include hardware elements specifically customized for machine learning and / or artificial intelligence (AI) functions. In these implementations, the processor circuit 1152 and / or the acceleration circuit 1164 may be or may include an AI engine chip that, once loaded with appropriate weighting and training code, can run many different kinds of AI instruction sets. Additionally or alternatively, the processor circuit 1152 and / or the acceleration circuit 1164 may be or may include (one or more) AI accelerators, which may be one or more of the above-mentioned hardware accelerators designed for hardware acceleration of AI applications. As an example, these processors or accelerators may be a cluster of the following: artificial intelligence (AI) GPU, The company developed the tensor processing unit (TPU), The Real AI Processor (RAP TM ), Nervana provided by the company TM Neural Network Processor (NNP), Movidius TM Myriad TM XVision Processing Unit (VPU), based on PX TM GPU, General Provided NM500 chip, Hardware provided by the company 3. Provided by Epiphany TM In some embodiments, the processor circuit 1152 and / or the acceleration circuit 1164 and / or the hardware accelerator circuit may be implemented as (one or more) AI acceleration coprocessors, such as Hexagon 685DSP, Imagination Technologies PowerVR 2NX Neural Net Accelerator (NNA) provided, The Neural Engine core inside the A11 or A12 Bionic SoC, The neural processing unit (NPU) within the HiSilicon Kirin 970 provided, etc. In some hardware-based implementations, the individual subsystems of the system 1150 can be operated by various AI acceleration coprocessors, AI GPUs, TPUs or hardware accelerators (e.g., FPGAs, ASICs, DSPs, SoCs, etc.), etc., which are configured with appropriate logic blocks, (one or more) bitstreams, etc. to perform their respective functions.

[0074] The system 1150 also includes a system memory 1154. Any number of memory devices may be used to provide a fixed amount of system memory. As an example, the memory 1154 may be or may include volatile memory, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), Dynamic Random Access Memory (DRAM) Dynamic Random Access Memory, ), and / or any other desired type of volatile memory device. Additionally or alternatively, the memory 1154 may be or may include a non-volatile memory, such as a read-only memory (ROM), an erasable programmable ROM (EPROM), an electrically erasable programmable (EEPROM), flash memory, a non-volatile RAM, a ferroelectric RAM, a phase-change memory (PCM), flash memory, and / or any other desired type of non-volatile memory device. Access to the memory 1154 is controlled by a memory controller. Individual memory devices may have any number of different package types, such as a single die package (SDP), a dual die package (DDP), or a quad die package (Q17P). Any number of other memory implementations may be used, such as different types of dual inline memory modules (DIMMs), including but not limited to microDIMMs or MiniDIMMs.

[0075] Storage circuitry 1158 provides persistent storage of information such as data, applications, operating systems, and the like. In one example, storage 1158 may be implemented via a solid-state disk drive (SSDD) and / or a high-speed electrically erasable memory (commonly referred to as "flash memory"). Other devices that may be used for storage 1158 include flash memory cards, such as SD cards, microSD cards, XD picture cards, and the like, and USB flash drives. In one example, the memory device may be or may include a memory device using chalcogenide glass, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level phase change memory (PCM), a resistive memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an antiferroelectric memory, a magnetoresistive random access memory (MRAM) memory including memristor technology, a phase change RAM (PRAM), a resistive memory including a metal oxide substrate, an oxygen vacancy substrate and a conductive bridge random access memory (CB-RAM), or a spin transfer torque (STT)-MRAM, a device based on a spin electronic magnetic junction memory, a device based on a magnetic tunneling junction (MTJ), a device based on a domain wall (DW) and a spin orbit transfer (SOT), a semiconductor thyristor-based memory device, a hard disk drive (HDD) drive, HDD), micro HDD, or a combination of these, and / or any other memory. Memory circuit 1154 and / or storage circuit 1158 may also include and Three-dimensional (3D) cross-point (XPOINT) memory.

[0076] The memory circuit 1154 and / or the storage circuit 1158 are configured to store computing logic 1183 in the form of software, firmware, microcode, or hardware-level instructions to implement the techniques described herein. The computing logic 1183 may be employed to store a working copy and / or permanent copy of programming instructions, or data used to create programming instructions, for use with various components of the operating system 1150 (e.g., drivers, libraries, application programming interfaces (APIs), etc.), the operating system of the system 1150, one or more applications, and / or for implementing the embodiments discussed herein. The computing logic 1183 may be stored or loaded into the memory circuit 1154 as instructions 1182 or data used to create instructions 1182, and then accessed by the processor circuit 1152 for execution to implement the functions described herein. The processor circuit 1152 and / or the acceleration circuit 1164 access the memory circuit 1154 and / or the storage circuit 1158 via the interconnect (IX) 1156. The instructions 1182 direct the processor circuit 1152 to perform a particular sequence of actions or flow, for example, as described with reference to the previously depicted flowchart(s) and block diagram(s) of operations and functions. The various elements may be implemented by assembly instructions or a high-level language supported by the processor circuit 1152, which may be compiled into instructions 1188, or data used to create instructions 1188, for execution by the processor circuit 1152. A permanent copy of the programming instructions may be placed into a persistent storage device of the storage circuit 1158 at the factory or in the field, for example, via a distribution medium (not shown), via a communication interface (e.g., from a distribution server (not shown)), over the air (OTA), or any combination of these.

[0077] IX 1156 couples processor 1152 to communication circuitry 1166 for communication with other devices, such as a remote server (not shown), etc. Communication circuitry 1166 is a hardware element, or a collection of hardware elements, for communicating over one or more networks 1163 and / or communicating with other devices. In one example, communication circuitry 1166 is or includes transceiver circuitry configured to implement wireless communications using any number of frequencies and protocols, such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 (and / or variants thereof), IEEE 802.23.4, and / or Low energy ( low energy, BLE), LoRaWAN TM(Long Range Wide Area Network), cellular protocols such as 3GPP LTE and / or Fifth Generation (5G) / New Radio (NR), etc. Additionally or alternatively, the communication circuit 1166 is or includes one or more network interface controllers (NICs) to enable wired communications using, for example, an Ethernet connection, a Controller Area Network (CAN), a Local Interconnect Network (LIN), DeviceNet, ControlNet, Data Highway+, or PROFINET, etc.

[0078] IX 1156 also couples processor 1152 to interface circuitry 1170 for connecting system 1150 to one or more external devices 1172. External devices 1172 may include, for example, sensors, actuators, positioning circuits (e.g., global navigation satellite system (GNSS) / Global Positioning System (GPS) circuits), client devices, servers, network appliances (e.g., switches, hubs, routers, etc.), integrated photonics devices (e.g., optical neural network (ONN) integrated circuits (ICs), etc.), and / or other similar devices.

[0079] In some optional examples, various input / output (I / O) devices may be present in or connected to the system 1150, which are referred to as input circuits 1186 and output circuits 1184. The input circuits 1186 and output circuits 1184 include one or more user interfaces designed to enable a user to interact with the platform 1150, and / or peripheral component interfaces designed to enable peripheral components to interact with the platform 1150. The input circuit 1186 may include any physical or virtual device for accepting input, including, in particular, one or more physical or virtual buttons (e.g., reset buttons), physical keyboards, keypads, mice, touch pads, touch screens, microphones, scanners, headsets, and the like. The output circuit 1184 may be included to show information or otherwise convey information, such as sensor readings, (one or more) actuator positions, or other similar information. Data and / or graphics may be displayed on one or more user interface components of the output circuit 1184. Output circuitry 1184 may include any number and / or combination of audio or visual displays, including, in particular, one or more simple visual outputs / indicators (e.g., binary status indicators (e.g., light emitting diodes (LEDs)) and multi-character visual outputs, or more complex outputs such as display devices or touch screens (e.g., liquid crystal displays (LCDs)). Display, LCD), LED display, quantum dot display, projector, etc.), where output of characters, graphics, multimedia objects, and the like is generated or produced from the operation of platform 1150. Output circuitry 1184 may also include speakers and / or other audio emitting devices, (one or more) printers, and the like. Additionally or alternatively, (one or more) sensors may be used as input circuitry 1184 (e.g., image capture devices, motion capture devices, and the like) and one or more actuators may be used as output device circuitry 1184 (e.g., actuators to provide tactile feedback or the like). Peripheral component interfaces may include, but are not limited to, non-volatile memory ports, USB ports, audio jacks, power supply interfaces, and the like. In some embodiments, in the context of the present system, display or console hardware may be used to provide output and receive input to an edge computing system; manage components or services of an edge computing system; identify the state of an edge computing component or service; or perform any other number of management or administrative functions or service use cases.

[0080] The components of the system 1150 may communicate via the IX 1156. The IX 1156 may include any number of technologies including ISA, extended ISA, I2C, SPI, point-to-point interface, power management bus (PMBus), PCI, PCIe, PCIx, UPI, Accelerator Link, CXL, CAPI, OpenCAPI, QPI, UPI, OPA IX, RapidIO TM System IX, CCIX, Gen-Z Consortium IX, HyperTransport Interconnect, NVLink, a Time-Trigger Protocol (TTP) system, a FlexRay system, PROFIBUS, and / or any number of other IX technologies provided. IX 1156 can be a proprietary bus used, for example, in a SoC-based system.

[0081] The number, capabilities, and / or capacity of the elements of the system 1150 may vary, depending on whether the computing system 1150 is used as a fixed computing device (e.g., a server computer in a data center, a workstation, a desktop computer, etc.) or a mobile computing device (e.g., a smart phone, a tablet computing device, a laptop computer, a gaming console, an IoT device, etc.). In various implementations, the computing device system 1150 may include one or more components of a data center, a desktop computer, a workstation, a laptop computer, a smart phone, a tablet device, a digital camera, a smart home appliance, a smart home hub, a network appliance, and / or any other device / system that processes data.

[0082] The techniques described herein may be performed in part or in whole by software or other instructions provided in a machine-readable storage medium (e.g., memory). The software is stored as processor-executable instructions (e.g., instructions that implement any other process discussed herein). The instructions associated with the flow charts (and / or various embodiments) and executed to implement embodiments of the disclosed subject matter may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of sequences of instructions.

[0083] The storage medium may be a tangible, non-transitory machine-readable medium, such as read only memory (ROM), random access memory (RAM), flash memory devices, floppy disks and other removable disks, magnetic storage media, optical storage media (e.g., Compact Disk Read-Only Memory (CD ROMS), Digital Versatile Disk (DVD)), and the like.

[0084] The storage medium may be included in, for example, a communication device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communication device, a cellular phone, a notebook computer, a tablet device, a game console, a set-top box, an embedded system, a TV (television), or a personal desktop computer.

[0085] Example

[0086] Some non-limiting examples of various embodiments are provided below.

[0087] Example 1 is a device comprising: a first die including a load; and a capacitive voltage regulator to provide power supply to the load, wherein the capacitive voltage regulator comprises a transistor and a capacitor, and wherein the transistor is included in the first die or in a second die different from the first die.

[0088] Example 2 is the apparatus of Example 1, wherein the capacitor is included in the second die.

[0089] Example 3 is the apparatus of Example 1 or Example 2, further comprising middleware, wherein the first die and the second die are coupled to the middleware.

[0090] Example 4 is the apparatus of Example 3, wherein the first die and the second die are coupled to the interposer via microbumps or hybrid bonding.

[0091] Example 5 is the apparatus of Example 3, further comprising a redistribution layer (RDL) coupled to the middleware and the first and second dies.

[0092] Example 6 is the apparatus of Example 3 or Example 4, further comprising a redistribution layer (RDL) coupled to the first die and the second die on a side opposite the middleware.

[0093] Example 7 is the apparatus of any of Examples 3-6, wherein at least some of the capacitors are included in the middleware.

[0094] Example 8 is the apparatus of Example 1 or Example 2, wherein the second die is an active middleware, and wherein the first die is mounted on the active middleware.

[0095] Example 9 is the apparatus of Example 8, wherein the active middleware comprises a plurality of voltage regulators.

[0096] Example 10 is the apparatus of any of Examples 1-9, wherein the capacitor encompasses a larger cross-sectional area than the transistor.

[0097] Example 11 is the apparatus of any of Examples 1-10, wherein at least some of the capacitors are included in the first die.

[0098] Example 12 is the apparatus of any of Examples 1-11, further comprising an encapsulation layer, wherein at least some of the capacitors are included in the encapsulation layer.

[0099] Example 13 is an apparatus as described in any of Examples 1-12, wherein the capacitor includes one or more metal-oxide-semiconductor capacitors, device capacitors, metal-insulator-metal capacitors, metal-oxide-metal capacitors, or deep trench capacitors.

[0100] Example 14 is an integrated circuit (IC) package, which includes: a packaging layer; an intermediate piece coupled to the packaging layer; a first die coupled to the intermediate piece, wherein the first die includes a load; and a voltage regulator to provide power supply to the load, wherein the voltage regulator includes a transistor and a capacitor, and wherein the transistor is included in the intermediate piece or in a second die coupled to the intermediate piece.

[0101] Example 15 is the IC package of Example 14, wherein at least some of the capacitors are included in the interposer, the second die, the first die, or the packaging layer.

[0102] Example 16 is the IC package of Example 14 or Example 15, wherein the transistor and the capacitor are included in the second die, and wherein the IC package further comprises a redistribution layer (RDL) coupled to the first die and the second die.

[0103] Example 17 is the IC package of any of Examples 14-16, wherein the capacitor encompasses a larger cross-sectional area than the transistor.

[0104] Example 18 is an IC package as described in any of Examples 14-17, wherein the capacitor includes one or more metal-oxide-semiconductor capacitors, device capacitors, metal-insulator-metal capacitors, metal-oxide-metal capacitors, or deep trench capacitors.

[0105] Example 19 is the IC package of any of Examples 14-18, wherein the voltage regulator does not include an inductor.

[0106] Example 20 is a system comprising: a battery interface to receive a power supply from a battery; and an integrated circuit (IC) package. The IC package comprises: middleware; a first die coupled to the middleware, wherein the first die comprises a load domain; and a capacitive voltage regulator to receive an input voltage corresponding to the power supply and generate an output voltage provided to the load domain, wherein a capacitor of the capacitive voltage regulator is included in one or more of the following: the first die, the middleware, or a second die coupled to the middleware.

[0107] Example 21 is the system of Example 20, wherein the input voltage is the power supply or an intermediate voltage generated from the power supply.

[0108] Example 22 is the system of Example 20 or Example 21, wherein the transistor of the capacitive voltage regulator is included in the middleware or in the second die.

[0109] Example 23 is the system of Example 22, wherein the capacitor encompasses a larger cross-sectional area than the transistor.

[0110] Example 24 is the system of any of Examples 20-23, further comprising the battery or a display coupled to the IC package.

[0111] Various operations may be described in turn as a plurality of discrete actions or operations in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as meaning that these operations must be dependent on the order. Specifically, these operations may not be performed in the order presented. The operations described may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0112] The terms "substantially," "close," "roughly," "approximately," and "about" generally refer to within + / -10% of a target value. Unless otherwise indicated, the use of ordinal adjectives "first," "second," and "third," etc., to describe common objects simply indicates that different instances of similar objects are referenced, and is not intended to imply that the objects so described must be in a given sequence in time, space, ranking, or in any other manner.

[0113] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0114] The description may use the phrases "in one embodiment" or "in an embodiment", each of which may refer to one or more identical or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in embodiments of the present disclosure are synonymous.

[0115] As used herein, the term "circuitry" may refer to, be a part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), a combinational logic circuit, and / or other suitable hardware components that provide the described functionality. As used herein, a "computer-implemented method" may refer to any method performed by one or more processors, a computer system having one or more processors, a mobile device such as a smart phone (which may include one or more processors), a tablet device, a laptop computer, a set-top box, a game console, and the like.

[0116] The terms "coupled," "communicatively coupled," and their derivatives are used herein. The term "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, may mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and / or may mean that one or more other elements are coupled or connected between the elements allegedly coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact with each other. The term "communicatively coupled" may mean that two or more elements are in contact with each other by means of communication, including by wires or other interconnections, by wireless communication channels or links, and the like.

[0117] References in the specification to "an embodiment", "one embodiment", "some embodiments" or "other embodiments" mean that the particular features, structures or characteristics described in connection with these embodiments are included in at least some embodiments, but not necessarily in all embodiments. The various appearances of "an embodiment", "one embodiment" or "some embodiments" do not necessarily all refer to the same embodiment. If the specification states that a component, feature, structure or characteristic "may", "might" or "could" be included, that particular component, feature, structure or characteristic is not required to be included. If the specification or claims refer to "an" element, it does not mean that there is only one of that element. If the specification or claims refer to "an additional" element, it does not exclude that there is more than one of that additional element.

[0118] In addition, in one or more embodiments, specific features, structures, functions or characteristics can be combined in any appropriate manner. For example, the first embodiment can be combined with the second embodiment at any place where the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0119] Although the present disclosure has been described in conjunction with its specific embodiments, many alternatives, modifications and variations of such embodiments will be apparent to those skilled in the art from the foregoing description. The embodiments of the present disclosure are intended to encompass all such alternatives, modifications and variations falling within the broad scope of the appended claims.

[0120] In addition, for simplicity of illustration and discussion, and in order not to obscure the present disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the given figures. In addition, the arrangement may be shown in block diagram form to avoid obscuring the present disclosure, and also taking into account the fact that the specific details of the implementation of such block diagram arrangements are highly dependent on the platform in which the present disclosure is to be implemented (i.e., such specific details should be fully within the scope of those skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the present disclosure, it should be clear to those skilled in the art that the present disclosure may be implemented without these specific details, or with variations of these specific details. The specification should therefore be considered illustrative, not restrictive.

[0121] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A device comprising: A first die including a load; as well as A capacitive voltage regulator is used to provide power supply to the load, wherein the capacitive voltage regulator includes a transistor and a capacitor, and wherein the transistor is included in the first die or in a second die different from the first die.

2. The device according to claim 1, wherein: The capacitor is included in the second die.

3. The device according to claim 1 or 2, further comprising a middleware, wherein: The first die and the second die are coupled to the middleware.

4. The device as claimed in claim 3, wherein: The first die and the second die are coupled to the interposer via microbumps or hybrid bonding.

5. The apparatus of claim 3, further comprising a redistribution layer (RDL) coupled to the middleware and the first and second dies.

6. The apparatus of claim 3, further comprising a redistribution layer (RDL) coupled to the first die and the second die on a side opposite the interposer.

7. The device according to any one of claims 3 to 6, wherein: At least some of the capacitors are included in the intermediate piece.

8. The device according to claim 1 or 2, wherein: The second die is an active middleware, and wherein the first die is mounted on the active middleware.

9. The device of claim 8, wherein: The active middleware includes a plurality of voltage regulators.

10. The device of claim 1, wherein: At least some of the capacitors are included in the first die.

11. The device of claim 1, further comprising an encapsulation layer, wherein: At least some of the capacitors are included in the encapsulation layer.

12. An integrated circuit (IC) package, comprising: Encapsulation layer; a middleware coupled to the encapsulation layer; a first die coupled to the middleware, wherein the first die includes a load; and A voltage regulator is used to provide power supply to the load, wherein the voltage regulator includes a transistor and a capacitor, and wherein the transistor is included in the middleware or in a second die coupled to the middleware.

13. The IC package of claim 12, wherein: At least some of the capacitors are included in the middleware, the second die, the first die, or the packaging layer.

14. The IC package according to claim 12 or 13, wherein: The transistor and the capacitor are included in the second die, and wherein the IC package further includes a redistribution layer (RDL) coupled to the first die and the second die.

15. The IC package of any one of claims 12 to 14, wherein: The voltage regulator does not include an inductor.

16. A system comprising: A battery interface for receiving power supply from a battery; as well as An integrated circuit (IC) package, the IC package comprising: middleware; a first die coupled to the middleware, wherein the first die includes a load domain; and A capacitive voltage regulator for receiving an input voltage corresponding to the power supply and generating an output voltage provided to the load domain, wherein a capacitor of the capacitive voltage regulator is included in one or more of the following: the first tube core, the middleware, or a second tube core coupled to the middleware.

17. The system of claim 16, wherein: The input voltage is the power supply or an intermediate voltage generated from the power supply.

18. The system of claim 16 or 17, wherein: The transistors of the capacitive voltage regulator are included in the middleware or in the second die.

19. The system of claim 17 or 18, wherein: The capacitor encompasses a larger cross-sectional area than the transistor.

20. The system of any one of claims 16 to 19, further comprising the battery or a display coupled to the IC package.

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