Dynamic binary translation method and device integrating translation rule set and computing equipment

Abstract

The invention discloses a dynamic binary translation method and device integrating a translation rule set and computing equipment, the method is executed in the computing equipment based on a second architecture processor, the translation rule set is integrated in the computing equipment, an application program is deployed in the computing equipment, and the method comprises the following steps: scanning a real-time instruction stream when the application program runs, to obtain one or more first architecture machine instruction sequences from the real-time instruction stream; disassembling the first architecture machine instruction sequence into a first architecture assembly instruction sequence; selecting a translation rule matched with the first architecture assembly instruction sequence from the translation rule set as a target translation rule; based on a target translation rule, translating the first architecture assembly instruction sequence into a corresponding second architecture assembly instruction sequence; and assembling the second architecture assembly instruction sequence into a second architecture machine instruction sequence and executing the second architecture machine instruction sequence. According to the method, the translation efficiency can be improved, and the problems of complexity and performance loss caused by using intermediate representation are avoided.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a dynamic binary translation method, a dynamic binary translation device and a computing device integrating a translation rule set. Background Art

[0002] Static binary translation is the process of converting source binary code into binary code for the target platform before the program runs. This conversion process includes disassembling the source code to obtain its assembly language representation, followed by optimization and rewriting, and finally recompiling into code suitable for the target platform. The advantage of static translation is that it can perform comprehensive optimizations before the program runs, including performance optimization, size optimization, and adaptability optimization to ensure efficient execution on the target platform. However, the challenge of static translation is that it may result in poor performance or limited functionality due to differences in the target platform.

[0003] Dynamic binary translation is a technique that dynamically converts source binary code into target platform code while the program is running. This method usually includes decoding and analyzing the source code, translating it into a sequence of instructions for the target platform, and performing real-time optimization to adapt to the current execution environment. The main advantage of dynamic translation is that it enables more flexible cross-platform execution because it can dynamically adjust the translation and optimization strategies according to the current running environment. This method is often used for virtual machines, simulators, and other applications that need to run on different hardware or operating systems.

[0004] Existing dynamic binary translation (DBT) systems are usually implemented in a similar way to traditional compilers. Specifically, according to existing dynamic binary translation systems, client instructions are first converted into an intermediate representation (IR), which is usually an abstraction level that helps convert between different computer architectures. Each client instruction is translated into one or more IR pseudo-instructions, which capture the semantics and operations of the original instruction. Then, these IR pseudo-instructions are further translated into binary codes of the target host, and finally the processor executes these binary codes. However, in existing DBT systems, all translation rules need to be manually created and optimized, including defining how to map each client instruction to an IR pseudo-instruction and how to map the IR pseudo-instruction to the actual instruction of the target host. Due to the need to cover and handle various changes and complexities in the source platform instruction set, this process is very complicated and consumes a lot of engineering resources and time investment. Furthermore, the existing DBT system has the following defects: 1) Complex translation rule management: The statically defined translation rule set needs to cover the various instruction formats and execution methods of the source platform in detail. With the expansion of the instruction set and the introduction of new architectures, rule management becomes complex and time-consuming. 2) Performance loss: Due to the hard-coded implementation and static definition of the rules, the existing DBT system is often unable to effectively cope with changes in dynamic application scenarios and system environments, resulting in poor performance and efficiency. 3) Lack of adaptability and flexibility: When adapting to new hardware architectures or operating system versions, the existing DBT system needs to rewrite and optimize a large number of translation rules, which will limit its scope of application and flexibility in a rapidly changing technical environment.

[0005] Therefore, a dynamic binary translation method integrating a translation rule set is needed to solve the problems existing in the above technical solutions. Summary of the invention

[0006] To this end, the present invention provides a dynamic binary translation method and device integrating a translation rule set to solve or at least alleviate the above problems.

[0007] According to one aspect of the present invention, a dynamic binary translation method with an integrated translation rule set is provided, which is executed in a computing device based on a second architecture processor, wherein the computing device is integrated with a translation rule set, the translation rule set includes multiple translation rules, each of the translation rules includes a first architecture parameterized assembly code block and a corresponding second architecture parameterized assembly code block, and an application is deployed in the computing device, the method includes: scanning a real-time instruction stream when the application is running to obtain one or more first architecture machine instruction sequences from the real-time instruction stream; disassembling the first architecture machine instruction sequence into a first architecture assembly instruction sequence; selecting a translation rule that matches the first architecture assembly instruction sequence from the translation rule set as a target translation rule; translating the first architecture assembly instruction sequence into a corresponding second architecture assembly instruction sequence based on the target translation rule; and assembling the second architecture assembly instruction sequence into a second architecture machine instruction sequence so that the second architecture machine instruction sequence can be executed by the second architecture processor.

[0008] Optionally, in the dynamic binary translation method of the integrated translation rule set according to the present invention, a translation rule matching the first architecture assembly instruction sequence is selected from the translation rule set as a target translation rule; based on the target translation rule, the first architecture assembly instruction sequence is translated into a corresponding second architecture assembly instruction sequence, including: for each first architecture assembly instruction in the first architecture assembly instruction sequence, determining the first architecture opcode, the first architecture operand type, and the first architecture operand number in the first architecture assembly instruction to determine the target instruction mode corresponding to the first architecture assembly instruction; from the translation rule set, a translation rule matching the target instruction mode is selected as a target translation rule; based on the target translation rule, the first architecture assembly instruction is translated into a corresponding second architecture assembly instruction.

[0009] Optionally, in the dynamic binary translation method of the integrated translation rule set according to the present invention, the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction are determined to determine the target instruction mode corresponding to the first architecture assembly instruction, including: decomposing the first architecture assembly instruction into multiple basic elements to determine the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction, wherein the multiple basic elements include the first architecture opcode and one or more first architecture operands; constructing an instruction pattern library corresponding to the first architecture assembly instruction, the instruction pattern library containing multiple instruction patterns and features of the instruction patterns, the features of the instruction patterns including opcode, operand type, and operand quantity; comparing the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction with each instruction pattern in the instruction pattern library to determine the target instruction mode corresponding to the first architecture assembly instruction.

[0010] Optionally, in the dynamic binary translation method of the integrated translation rule set according to the present invention, the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction are compared with each instruction pattern in the instruction pattern library to determine the target instruction pattern corresponding to the first architecture assembly instruction, including: comparing the first architecture opcode with the opcodes of each instruction pattern in the instruction pattern library respectively to obtain one or more first candidate instruction patterns that match the first architecture opcode; comparing the first architecture operand type with the operand type of each of the first candidate instruction patterns respectively to obtain one or more second candidate instruction patterns that match the first architecture opcode and the first architecture operand type; comparing the first architecture operand quantity with the operand quantity of each of the second candidate instruction patterns respectively to obtain a target instruction pattern that successfully matches the first architecture opcode, the first architecture operand type, and the first architecture operand quantity.

[0011] Optionally, in the dynamic binary translation method of the integrated translation rule set according to the present invention, based on the target translation rule, the first architecture assembly instruction is translated into a corresponding second architecture assembly instruction, including: parsing the first architecture operand of the first architecture assembly instruction to obtain a parsing result of the first architecture operand, wherein the parsing result includes detailed information of the first architecture operand; based on the target translation rule and the parsing result of the first architecture operand, translating the first architecture assembly instruction into one or more corresponding second architecture assembly instructions.

[0012] Optionally, in the dynamic binary translation method with integrated translation rule set according to the present invention, it also includes: using a translation model to convert multiple first architecture actual assembly code blocks into corresponding multiple second architecture actual assembly code blocks respectively, so as to establish a mapping relationship between multiple first architecture actual assembly code blocks and multiple second architecture actual assembly code blocks; parameterizing the operands in each of the first architecture actual assembly code blocks and the corresponding second architecture actual assembly code blocks to obtain each first architecture parameterized assembly code block and the corresponding second architecture parameterized assembly code block; and generating a translation rule set based on each of the first architecture parameterized assembly code blocks and the corresponding second architecture parameterized assembly code blocks.

[0013] Optionally, in the dynamic binary translation method of the integrated translation rule set according to the present invention, based on the target translation rule, the first architecture assembly instruction is translated into the corresponding second architecture assembly instruction, including: obtaining each first architecture operand in the first architecture assembly instruction, the first architecture operand including one or more of a first architecture register, a first architecture memory address, and a first architecture immediate value; determining the second architecture operand corresponding to each first architecture operand; based on the target translation rule and the second architecture operand corresponding to each first architecture operand, translating the first architecture assembly instruction into the corresponding second architecture assembly instruction.

[0014] Optionally, in the dynamic binary translation method of the integrated translation rule set according to the present invention, it also includes: dynamically counting the number of successful matches of each translation rule in the translation rule set; sorting the individual translation rules in the translation rule set according to the number of successful matches to generate a translation rule list; obtaining a predetermined number of translation rules with the highest number of successful matches from the translation rule list as important translation rules; and performing formal verification on each of the important translation rules to determine whether the first architecture parameterized assembly code block in the important translation rule is equivalent to the second architecture parameterized assembly code block, and determine whether the important translation rule is correct.

[0015] Optionally, in the dynamic binary translation method of the integrated translation rule set according to the present invention, each of the important translation rules is formally verified to determine whether the first architecture parameterized assembly code block and the second architecture parameterized assembly code block in the important translation rule are equivalent, including: respectively passing the first architecture parameterized assembly code block and the second architecture parameterized assembly code block in the important translation rule to a symbolic execution engine; using the symbolic execution engine, respectively symbolizing the first state of the first architecture parameterized assembly code block and the second state of the second architecture parameterized assembly code block to obtain a first symbolic value of the first architecture parameterized assembly code block and a second symbolic value of the second architecture parameterized assembly code block, wherein the first state includes a first register, a second register, and a third register. a memory address, the second state includes a second register and a second memory address; performing symbolic execution based on the first symbolic value of the first architecture parameterized assembly code block and the second symbolic value of the second architecture parameterized assembly code block to obtain a first final state of the first architecture parameterized assembly code block and a second final state of the second architecture parameterized assembly code block; extracting a first register value and a first memory address value from the first final state, and extracting a second register value and a second memory address value from the second final state to construct an equivalence verification formula; solving the equivalence verification formula using an SMT solver to determine whether the first final state of the first architecture parameterized assembly code block is equivalent to the second final state of the second architecture parameterized assembly code block

[0016] Optionally, in the dynamic binary translation method of the integrated translation rule set according to the present invention, it also includes: disassembling multiple binary files to obtain a first architecture sample assembly code block and a second architecture sample assembly code block corresponding to each line of source code; inputting the first architecture sample assembly code block and the second architecture sample assembly code block into a pre-training module to extract the first architecture instruction embedding information corresponding to the first architecture sample assembly code block and the second architecture instruction embedding information corresponding to the second architecture sample assembly code block; based on the first architecture sample assembly code block, the first architecture instruction embedding information, the second architecture sample assembly code block, and the second architecture instruction embedding information, the translation module is trained to obtain the translation model.

[0017] Optionally, in the dynamic binary translation method of the integrated translation rule set according to the present invention, multiple binary files are disassembled to obtain the first architecture sample assembly code block and the second architecture sample assembly code block corresponding to each line of source code, including: obtaining multiple source code files based on multiple programming languages; compiling each of the source code files to generate the first architecture binary file and the second architecture binary file corresponding to the source code file; disassembling the first architecture binary file and the second architecture binary file respectively to obtain the corresponding first architecture assembly code file and the second architecture assembly code file; obtaining each first architecture sample assembly code block from the first architecture assembly code file, and obtaining each second architecture sample assembly code block from the second architecture assembly code file; establishing a mapping relationship between each first architecture sample assembly code block and each second architecture sample assembly code block and each line of source code in the source code file to obtain the first architecture sample assembly code block and the second architecture sample assembly code block corresponding to each line of source code.

[0018] Optionally, in the dynamic binary translation method integrating a translation rule set according to the present invention, the first architecture is an x86 architecture, and the second architecture is an ARM architecture.

[0019] According to one aspect of the present invention, a dynamic binary translation apparatus is provided, which is deployed in a computing device based on a second architecture processor, wherein a translation rule set is integrated in the dynamic binary translation apparatus, wherein the translation rule set includes multiple translation rules, wherein each translation rule includes a first architecture parameterized assembly code block and a corresponding second architecture parameterized assembly code block, respectively, and an application is deployed in the computing device, wherein the apparatus includes: a scanning unit, adapted to scan a real-time instruction stream when the application is running, so as to obtain one or more first architecture machine instruction sequences from the real-time instruction stream; a disassembly unit, adapted to disassemble the first architecture machine instruction sequence into a first architecture assembly instruction sequence; a selection unit, adapted to select a translation rule matching the first architecture assembly instruction sequence from the translation rule set as a target translation rule; a translation unit, adapted to translate the first architecture assembly instruction sequence into a corresponding second architecture assembly instruction sequence based on the target translation rule; and an assembly unit, adapted to assemble the second architecture assembly instruction sequence into a second architecture machine instruction sequence, so as to execute the second architecture machine instruction sequence through the second architecture processor.

[0020] According to one aspect of the present invention, there is provided a computing device, comprising: at least one processor; and a memory storing program instructions, wherein the program instructions are configured to be suitable for execution by the at least one processor, and the program instructions include instructions for executing the dynamic binary translation method with integrated translation rule set as described above.

[0021] According to one aspect of the present invention, a computer program product is provided, comprising a computer program / instruction, wherein the computer program / instruction implements the method as described above when executed by a processor.

[0022] According to one aspect of the present invention, a readable storage medium storing program instructions is provided. When the program instructions are read and executed by a computing device, the computing device executes the dynamic binary translation method integrating the translation rule set as described above.

[0023] According to the technical solution of the present invention, a dynamic binary translation method integrating a translation rule set is provided. By integrating the translation rule set in a computing device based on a second architecture processor, when the application is running, the first architecture assembly instruction sequence in the application can be directly translated into the corresponding second architecture assembly instruction sequence based on the translation rule set, and then the second architecture assembly instruction sequence is assembled into a second architecture machine instruction sequence and executed. In this way, the present invention adopts a direct translation method when the application is running, which can not only improve the translation efficiency, but also avoid the complexity and performance loss caused by the use of intermediate representation.

[0024] In addition, the present invention utilizes the translation model to generate a translation rule set, which can reduce manual intervention, further improve translation efficiency, translation accuracy and performance optimization capabilities, and facilitate efficient management of large-scale translation rule sets.

[0025] In addition, the present invention can ensure the correctness and reliability of important translation rules and eliminate potential hidden errors in important rules by screening important translation rules and performing formal verification on them. Furthermore, the formal verification method based on symbolic execution has a high degree of automation and versatility.

[0026] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to achieve the above and related purposes, some illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. By reading the following detailed description in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present invention will become more apparent. Throughout the present invention, the same reference numerals generally refer to the same parts or elements.

[0028] Figure 1 A schematic diagram of a computing device 100 provided according to an embodiment of the present invention is shown;

[0029] Figure 2 A schematic flow chart of a dynamic binary translation method 200 integrating a translation rule set provided according to an embodiment of the present invention is shown;

[0030] Figure 3 A schematic diagram of the process of training and generating a translation model according to an embodiment of the present invention is shown;

[0031] Figure 4 A schematic diagram of a dynamic binary translation device 400 provided according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0032] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0033] In order to facilitate understanding, the terms involved in the present invention are first explained below.

[0034] Dynamic Binary Translation (DBT): A technology that dynamically translates the machine language code of one computer into the machine language code of another computer. It is often used in scenarios such as virtualization, emulation, and cross-platform compatibility to improve the operating efficiency and portability of applications on different hardware or operating systems.

[0035] Symbolic execution: A program analysis technique used to infer how a program processes input data. In this invention, it is used to verify the semantic equivalence of translation rules generated by deep learning models.

[0036] Intermediate Representation (IR): In existing DBT systems, an intermediate format used to represent between the source platform and the target platform.

[0037] In view of the fact that the existing DBT system requires manual creation of translation rules, and the translation process needs to be converted into an intermediate representation (IR), which leads to problems such as a complicated translation process and performance loss, the present invention proposes a dynamic binary translation method with an integrated translation rule set. First, the direct translation method is adopted, which can not only improve the translation efficiency, but also avoid the complexity and performance loss caused by the use of intermediate representations. Secondly, the translation model is used to generate a translation rule set, which can reduce manual intervention and further improve translation efficiency, translation accuracy and performance optimization capabilities. In addition, by formally verifying important translation rules, the correctness and reliability of important translation rules can be ensured.

[0038] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figure 1 FIG. 1 is a schematic diagram of a computing device 100 provided according to an embodiment of the present invention. Figure 1 As shown, in a basic configuration, the computing device 100 includes at least one processing unit 102 and a system memory 104. According to one aspect, depending on the configuration and type of the computing device, the processing unit 102 can be implemented as a processor. The system memory 104 includes, but is not limited to, volatile storage (e.g., random access memory), non-volatile storage (e.g., read-only memory), flash memory, or any combination of such memories. According to one aspect, the system memory 104 includes an operating system 105.

[0040] According to one aspect, operating system 105 is suitable for controlling the operation of computing device 100, for example. Furthermore, examples are practiced in conjunction with graphics libraries, other operating systems, or any other application programs, and are not limited to any particular application or system. Figure 1 The basic configuration is shown in FIG. 1 by those components within the dashed lines. According to one aspect, computing device 100 has additional features or functionality. For example, according to one aspect, computing device 100 includes additional data storage devices (removable and / or non-removable), such as magnetic disks, optical disks, or tapes. Such additional storage Figure 1 1 is illustrated by a removable storage device 109 and a non-removable storage device 110.

[0041] As stated above, according to one aspect, a program module 103 is stored in the system memory 104. According to one aspect, the program module 103 may include one or more application programs, and the present invention does not limit the type of application program, for example, the application program may include: email and contact application programs, word processing application programs, spreadsheet application programs, database application programs, slide show application programs, drawing or computer-aided application programs, web browser application programs, etc.

[0042] According to one aspect, the program module 103 may include a plurality of program instructions suitable for executing the dynamic binary translation method 200 with integrated translation rule set of the present invention, so that the computing device 100 is configured to execute the dynamic binary translation method 200 with integrated translation rule set of the present invention.

[0043] According to one aspect, the program module 103 may include a dynamic binary translation device 400 , and the dynamic binary translation device 400 may be configured to execute the dynamic binary translation method 200 integrating a translation rule set of the present invention.

[0044] According to one aspect, the examples may be practiced on a circuit comprising discrete electronic components, a packaged or integrated electronic chip containing logic gates, a circuit utilizing a microprocessor, or a single chip containing electronic components or a microprocessor. Figure 1 Each or many components shown in can be integrated into a system on a chip (SOC) on a single integrated circuit to practice examples. According to one aspect, such a SOC device may include one or more processing units, a graphics unit, a communication unit, a system virtualization unit, and various application functions, all of which are integrated (or "burned") into a chip substrate as a single integrated circuit. When operated via SOC, the functions described in this article can be operated via a dedicated logic integrated with other components of the computing device 100 on a single integrated circuit (chip). Embodiments of the present invention can also be practiced using other technologies capable of performing logical operations (such as AND, OR, and NOT), including but not limited to mechanical, optical, fluid, and quantum technologies. In addition, embodiments of the present invention can be practiced in a general-purpose computer or in any other circuit or system.

[0045] According to one aspect, the computing device 100 may also have one or more input devices 112, such as a keyboard, a mouse, a pen, a voice input device, a touch input device, etc. Output devices 114 may also be included, such as a display, a speaker, a printer, etc. The aforementioned devices are examples and other devices may also be used. The computing device 100 may include one or more communication connections 116 that allow communication with other computing devices 118. Examples of suitable communication connections 116 include, but are not limited to: RF transmitter, receiver and / or transceiver circuits; Universal Serial Bus (USB), parallel and / or serial ports.

[0046] The term computer-readable medium as used herein includes computer storage media. Computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (e.g., computer-readable instructions, data structures, or program modules 103). System memory 104, removable storage device 109, and non-removable storage device 110 are all examples of computer storage media (i.e., memory storage). Computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical storage, cassettes, tapes, disk storage or other magnetic storage devices, or any other products that can be used to store information and can be accessed by computing device 100. According to one aspect, any such computer storage medium can be a part of computing device 100. Computer storage media do not include carrier waves or other propagated data signals.

[0047] According to one aspect, communication media is implemented by computer readable instructions, data structures, program modules 103, or other data in a modulated data signal (e.g., a carrier wave or other transport mechanism), and includes any information delivery media. According to one aspect, the term "modulated data signal" describes a signal that has one or more characteristics set or changed in such a manner as to encode information in the signal. By way of example and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared, and other wireless media.

[0048] In an embodiment according to the present invention, the processing unit 102 of the computing device 100 can be implemented as a second architecture processor, that is, the computing device 100 is a computing device based on the second architecture processor. The computing device 100 can be configured to perform the dynamic binary translation method 200 of the integrated translation rule set of the present invention. Specifically, the computing device 100 includes one or more processors (second architecture processors), and one or more readable storage media storing program instructions. When the program instructions are configured to be executed by one or more processors (second architecture processors), the computing device executes the dynamic binary translation method 200 of the integrated translation rule set in the embodiment of the present invention.

[0049] In an embodiment according to the present invention, a dynamic binary translation device 400 is deployed in the computing device 100, and the dynamic binary translation device 400 can run on the operating system of the computing device 100, and the dynamic binary translation device 400 is suitable for executing the dynamic binary translation method 200 of the present invention with an integrated translation rule set.

[0050] Figure 2 A flow chart of a dynamic binary translation method 200 with integrated translation rule set according to an embodiment of the present invention is shown. The dynamic binary translation method 200 with integrated translation rule set can be executed in a computing device based on a second architecture processor (eg, the aforementioned computing device 100).

[0051] It should be noted that a translation rule set is integrated in the computing device 100 (dynamic binary translation device 400), and the translation rule set includes multiple translation rules. Each translation rule can include a first architecture parameterized assembly code block and a corresponding second architecture parameterized assembly code block, and an application is deployed in the computing device, and the application includes one or more first architecture machine instruction sequences.

[0052] By executing the dynamic binary translation method 200 with an integrated translation rule set of the present invention, the computing device 100 can directly convert a first architecture machine instruction sequence in an application program into a second architecture machine instruction sequence and execute it when the application program is running.

[0053] In some embodiments of the present invention, the first architecture may be an x86 architecture, and the second architecture may be an ARM architecture. It should be noted that, in the following specific embodiments, the present invention only takes the first architecture as an x86 architecture and the second architecture as an ARM architecture as an example to specifically illustrate the dynamic binary translation method 200 of the integrated translation rule set, but the present invention is not limited to the specific types of the first architecture and the second architecture.

[0054] like Figure 2 As shown, the dynamic binary translation method 200 integrating the translation rule set includes the following steps 210-250.

[0055] Step 210: During the running of the application, the computing device 100 may scan the real-time instruction stream (i.e., the instruction sequence executed by the machine) of the above application when it is running, so as to obtain one or more first architecture machine instruction sequences to be converted from the real-time instruction stream.

[0056] In some embodiments, the computing device 100 may utilize a dynamic binary translation engine to scan the real-time instruction stream when the above-mentioned application is running, and then obtain one or more first architecture machine instruction sequences to be converted from the real-time instruction stream.

[0057] It should be noted that the first architecture machine instruction sequence in the real-time instruction stream cannot be executed in the computing device 100 based on the second architecture processor. Therefore, it is necessary to convert the first architecture machine instruction sequence into a second architecture machine instruction sequence that can be executed in the computing device 100 according to the following steps.

[0058] Step 220 : The computing device 100 deassembles the first architecture machine instruction sequence into a first architecture assembly instruction sequence.

[0059] Step 230: The computing device 100 may select a translation rule that matches the first architecture assembly instruction sequence from the translation rule set as a target translation rule.

[0060] Step 240: The computing device 100 may translate the first architecture assembly instruction sequence into a corresponding second architecture assembly instruction sequence (ie, a second architecture assembly instruction sequence equivalent to the first architecture assembly instruction sequence) based on the target translation rule.

[0061] Step 250: The computing device 100 may assemble the second architecture assembly instruction sequence into a second architecture machine instruction sequence so as to execute the second architecture machine instruction sequence through a second architecture processor.

[0062] In some embodiments, steps 230 to 240 may be specifically performed in the following manner: First, for each first architecture assembly instruction in the first architecture assembly instruction sequence, the computing device 100 may analyze and determine the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction. In a specific embodiment, the computing device 100 may decompose the first architecture assembly instruction into a plurality of basic elements (tokens), and the plurality of basic elements may include the first architecture opcode, one or more first architecture operands, and may also include comments and labels. Furthermore, the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction may be determined based on the plurality of basic elements. In one embodiment, before decomposing the first architecture assembly instruction into a plurality of basic elements, the first architecture assembly instruction may be preprocessed (instruction format standardization processing) in advance to remove redundant blanks in the first architecture assembly instruction, and to standardize the comments and punctuation in the first architecture assembly instruction.

[0063] Subsequently, the computing device 100 may determine the target instruction mode corresponding to the first architecture assembly instruction based on the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction. In a specific embodiment, the computing device 100 may pre-build an instruction mode library corresponding to the first architecture assembly instruction, the instruction mode library comprising a plurality of instruction modes and features of each instruction mode, the features of the instruction mode comprising an opcode, an operand type (the operand type comprises, for example, a register, a memory address, an immediate number), the number of operands, and may also comprise an addressing mode, etc. It is to be understood that each instruction mode may be defined as a corresponding set of features in the instruction mode library.

[0064] Furthermore, the computing device 100 can use a pattern matching algorithm to compare the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction with each instruction pattern in the instruction pattern library to determine the target instruction pattern corresponding to the first architecture assembly instruction. Specifically, the first architecture opcode can be compared with the opcodes of each instruction pattern in the instruction pattern library to obtain one or more first candidate instruction patterns that match the first architecture opcode; then, the first architecture operand type is compared with the operand type of each first candidate instruction pattern to obtain one or more second candidate instruction patterns that match the first architecture opcode and the first architecture operand type; and then the first architecture operand quantity is compared with the operand quantity of each second candidate instruction pattern to obtain a target instruction pattern that successfully matches the first architecture opcode, the first architecture operand type, and the first architecture operand quantity. Accordingly, the target instruction pattern corresponding to the first architecture assembly instruction can be determined. It should be understood that the target instruction pattern is an instruction pattern that successfully matches the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction. In addition, if the matching fails in the above pattern matching process and the target instruction pattern corresponding to the first architecture assembly instruction is not matched, the first architecture assembly instruction can be further analyzed or the first architecture assembly instruction can be marked as an unrecognized instruction pattern.

[0065] It should be noted that the target instruction mode can represent the instruction type and instruction format of the first architecture assembly instruction. Instruction types generally include the following: data transfer instructions, such as MOV, PUSH, POP, used to transfer data between registers and memory; arithmetic operation instructions, such as ADD, SUB, MUL, DIV, used to perform basic mathematical operations; logical operation instructions, such as AND, OR, XOR, NOT, used to perform logical operations; control flow instructions, such as JMP, CALL, RET, CMP, used to control the execution flow of the program. The instruction format includes information such as instruction length, opcode length, operand position, etc. The opcode is used to indicate the type of operation performed by the instruction. Different opcodes correspond to different functions. The opcodes include MOV, ADD, JMP, etc. The operand is used to indicate the operation object involved in the operation. The operand types include registers (registers involved in the instruction, such as EAX, EBX, etc.), memory addresses (memory addresses involved in the instruction, including direct addresses and addresses calculated by register plus offset), immediate values ​​(constant values ​​contained in the instruction, used for mathematical operations or logical operations), labels, etc. The number of operands refers to the number of operands used in the instruction (such as unary, binary or ternary instructions). The number of operands may be different for different instructions. For example, MOV reg, reg has two operands and is a binary operation, while INC reg has only one operand and is a unary operation.

[0066] For example, several typical instruction patterns in the instruction pattern library are as follows:

[0067] MOV reg,reg: register to register transfer.

[0068] MOV reg,mem: load from memory address to register.

[0069] ADD reg,imm: Addition of a register and an immediate value.

[0070] JMP label: unconditional jump instruction.

[0071] In the above embodiment, for the first architecture assembly instruction MOV EAX, [EBX+4], the computing device 100 may decompose it into the following basic elements:

[0072] Opcode: MOV

[0073] Operand 1: EAX (register)

[0074] Operand 2: [EBX+4] (memory address)

[0075] Among them, the opcode MOV indicates that the first architecture assembly instruction is a transfer instruction, and all instruction modes with the opcode MOV in the instruction mode library can be used as the first candidate instruction mode. EAX represents a register, [EBX+4] represents a memory address, and the first architecture assembly instruction MOV EAX, [EBX+4] has two operands. It can be seen that the first architecture assembly instruction matches the instruction mode MOV reg, mem, and the instruction mode MOV reg, mem is determined as the target instruction mode corresponding to the first architecture assembly instruction MOV EAX, [EBX+4].

[0076] After determining the target instruction mode corresponding to the first architecture assembly instruction, the computing device 100 can select a translation rule that matches the target instruction mode from the translation rule set as the target translation rule corresponding to the first architecture assembly instruction. Furthermore, the first architecture assembly instruction can be translated into a corresponding second architecture assembly instruction (a second architecture assembly instruction equivalent to the first architecture assembly instruction) based on the target translation rule. It should be understood that by translating each first architecture assembly instruction in the first architecture assembly instruction sequence into a corresponding second architecture assembly instruction based on the corresponding target translation rule, a second architecture assembly instruction sequence can be finally obtained based on each second architecture assembly instruction corresponding to each first architecture assembly instruction.

[0077] It should be noted that in the process of translating the first architecture assembly instructions into corresponding second architecture assembly instructions based on the target translation rules, the operand format, instruction format and possible register allocation can be adjusted to ensure that the second architecture assembly instructions can be executed in a computing device of the second architecture.

[0078] In addition, in some embodiments, when translating the first architecture assembly instruction into the corresponding second architecture assembly instruction based on the target translation rule, the first architecture operand of the first architecture assembly instruction can also be parsed in more detail to obtain the parsing result of the first architecture operand containing the detailed information of the first architecture operand. Furthermore, the first architecture assembly instruction can be translated into one or more corresponding second architecture assembly instructions based on the target translation rule and the parsing result of the first architecture operand. Based on this, it can be ensured that the type and structure of the operand of the complex first architecture assembly instruction can be correctly processed in the subsequent translation process.

[0079] In a specific embodiment, during the parsing of the first architecture operand of the complex first architecture assembly instruction, if the first architecture operand type is a register, the parsing result includes the register name and the corresponding architecture, for example, the registers EAX and EBX in the first architecture assembly instruction MOV EAX,EBX are parsed as R0 and R1. If the first architecture operand type is a memory address, the parsing result includes the addressing mode of the memory address (such as direct addressing mode, base plus offset addressing mode, etc.), for example, the first architecture assembly instruction MOV EAX, [EBX + 4] uses the base plus offset addressing mode, and needs to parse EBX as the base register and 4 as the offset. If the first architecture operand type is an immediate number, the parsing result includes whether the immediate number needs to be passed through a register (first loaded into the register and then operated) or whether it is directly encoded in the second architecture assembly instruction. For example, for the first architecture assembly instruction ADD EAX, 1000, if the immediate number 1000 in the ARM instruction is too large to be directly encoded, it needs to be loaded into the register first and then operated.

[0080] It should also be noted that, in an embodiment of the present invention, for simple first architecture assembly instructions, such as register-to-register transfer instructions, the first architecture assembly instructions can be directly translated into corresponding second architecture assembly instructions based on target translation rules. For example, the first architecture assembly instruction MOV EAX, EBX can be directly translated into the second architecture assembly instruction MOV R0, R1. For complex first architecture assembly instructions, such as memory operation instructions, it may be necessary to generate multiple second architecture assembly instructions. In this case, the first architecture operand of the first architecture assembly instruction can be parsed in more detail to obtain a parsing result of the first architecture operand containing detailed information of the first architecture operand. Furthermore, based on the target translation rules and the parsing result of the first architecture operand, the first architecture assembly instruction can be translated into multiple corresponding second architecture assembly instructions. For example, the first architecture assembly instruction MOV EAX, [EBX+4] can be translated into the following two second architecture assembly instructions:

[0081] ADD R1,R1,#4 (base address plus offset)

[0082] LDR R0,[R1] (load value from memory into register)

[0083] In addition, for complex first-architecture assembly instructions such as instructions with prefixes and string operations, they need to be translated based on special translation rules. For example, the first-architecture assembly instruction REP MOVSB ​​instruction does not have a directly equivalent second-architecture assembly instruction, and translation needs to be achieved through loops or batch memory operations. In addition, in some cases, the pattern matching algorithm may need to dynamically adjust the translation rules according to the specific situation. For example, the memory addressing mode of some first-architecture assembly instructions is less efficient on the second architecture, and the translation rules can be optimized during translation. For example, the first-architecture assembly instruction with a complex base plus offset addressing mode may need to be completed step by step through multiple instructions on the second architecture. During translation, the instruction combination can be adjusted according to the value of the operand to improve execution efficiency.

[0084] In some embodiments, a translation model may be pre-trained and generated, and the translation rule set may be generated using the translation model.

[0085] Figure 3 A schematic diagram of a process for training and generating a translation model according to an embodiment of the present invention is shown.

[0086] In a specific embodiment, the specific method of training and generating the translation model is as follows: First, disassemble multiple binary files to obtain the first architecture sample assembly code block and the second architecture sample assembly code block corresponding to each line of source code. A training data set can be formed based on the first architecture sample assembly code block and the second architecture sample assembly code block corresponding to each line of source code. Then, Figure 3 As shown, each first architecture sample assembly code block and second architecture sample assembly code block in the training data set can be input into a pre-training module (feature extractor) to extract the first architecture instruction embedding information corresponding to the first architecture sample assembly code block and the second architecture instruction embedding information corresponding to the second architecture sample assembly code block. Furthermore, the translation module (i.e., the translation model to be trained) can be trained based on the first architecture sample assembly code block, the first architecture instruction embedding information, the second architecture sample assembly code block, and the second architecture instruction embedding information to obtain a translation model. It should be noted that the translation model obtained after training can be used to convert the first architecture actual assembly code block into the corresponding second architecture actual assembly code block.

[0087] In some embodiments, the translation module may adopt a seq2seq structure.

[0088] In one implementation, a specific method for disassembling multiple binary files to obtain the first architecture sample assembly code block and the second architecture sample assembly code block corresponding to each line of source code is as follows: obtain multiple source code files (covering various application scenarios) based on multiple programming languages ​​(for example, including multiple programming languages ​​such as C / C++), and compile each source code file to generate the first architecture binary file and the second architecture binary file corresponding to the source code file. Specifically, different compilers (such as GCC, LLVM) and compilation options can be used to compile each source code file to generate the first architecture binary file and the second architecture binary file corresponding to each source code file. Then, the disassembly component of binary ninja can be used to disassemble the first architecture binary file and the second architecture binary file respectively to obtain the corresponding first architecture assembly code file and the second architecture assembly code file. Next, each first architecture sample assembly code block can be obtained from the first architecture assembly code file, and each second architecture sample assembly code block can be obtained from the second architecture assembly code file. Finally, based on the debugging information (such as DWARF) and symbol table information at the source code level, a mapping relationship can be established between each first architecture sample assembly code block and each second architecture sample assembly code block and each line of source code in the source code file to obtain the first architecture sample assembly code block and the second architecture sample assembly code block corresponding to each line of source code.

[0089] In some embodiments, the translation model obtained after the above training can be used to generate a translation rule set, as follows: First, the translation model can be used to convert multiple first architecture actual assembly code blocks in the actual operating environment into corresponding multiple second architecture actual assembly code blocks, so as to establish a mapping relationship between multiple first architecture actual assembly code blocks and multiple second architecture actual assembly code blocks. Subsequently, by parameterizing (symbolizing) the operands (such as registers, immediate numbers, memory addresses) in each first architecture actual assembly code block and the corresponding second architecture actual assembly code block, each first architecture parameterized assembly code block and the corresponding second architecture parameterized assembly code block can be obtained. For example, the symbols reg0, reg1, etc. of the register can be used to replace the specific register name, so as to realize the parameterization of the register. Further, a translation rule set can be generated based on each first architecture parameterized assembly code block and the corresponding second architecture parameterized assembly code block. Wherein, each translation rule in the translation rule set can respectively include the first architecture parameterized assembly code block and the corresponding second architecture parameterized assembly code block.

[0090] After the translation model is used to generate a translation rule set, the translation rule set can be integrated into the computing device 100 (dynamic binary translation device 400) so that during the running of the application, the first architecture assembly instruction sequence in the application can be translated into the corresponding second architecture assembly instruction sequence based on the translation rule set, and the second architecture assembly instruction sequence can be assembled into a second architecture machine instruction sequence and executed.

[0091] It should be noted that, since the operands in the translation rules of the present invention are parameterized, each translation rule can match multiple first architecture assembly instruction sequences having the same instruction sequence but different operands.

[0092] The following is an example of a parameterized translation rule (including a first architecture parameterized assembly code block and a corresponding second architecture parameterized assembly code block):

[0093]

[0094] In this example, Guest represents the first architecture and Host represents the second architecture. Specific registers such as rax and rbx are used in the original first architecture actual assembly code block (x86 code), which are replaced with symbols such as reg0 and reg1 in the first architecture parameterized assembly code block of the parameterized translation rule. In addition, symbols such as imm0 are used to represent immediate values. In addition, for labels, the $Label form is used in the first architecture parameterized assembly code block of the translation rule, and the #Label form is used in the corresponding second architecture parameterized assembly code block to keep consistent with the assembly syntax of the second architecture (ARM64).

[0095] In this embodiment, when translating the first architecture assembly instruction into the corresponding second architecture assembly instruction based on the target translation rule (the target translation rule that has been parameterized), each first architecture operand in the first architecture assembly instruction can be obtained, and the first architecture operand includes, for example, one or more of the first architecture register, the first architecture memory address, and the first architecture immediate value. Then, the second architecture operand corresponding to each first architecture operand is determined, for example: the second architecture register corresponding to the first architecture register in the first architecture assembly instruction can be determined, the second architecture memory address corresponding to the first architecture memory address in the first architecture assembly instruction can be determined, and the second architecture immediate value corresponding to the first architecture immediate value in the first architecture assembly instruction can be determined. Furthermore, the first architecture assembly instruction can be translated into the corresponding second architecture assembly instruction based on the target translation rule and the second architecture operand corresponding to each first architecture operand, that is, the corresponding operand parameter in the target translation rule is instantiated based on the second architecture operand corresponding to each first architecture operand to obtain the second architecture assembly instruction.

[0096] Here, the process of translating the first architecture assembly instruction into the corresponding second architecture assembly instruction based on the target translation rule is the process of instantiating the target translation rule.

[0097] In some embodiments, operand mapping tables for the first architecture and the second architecture may be pre-established, including a register mapping table, a memory address mapping table, an immediate value mapping table, and the like. The register mapping table is used to map the first architecture register to the corresponding second architecture register, the memory address mapping table is used to map the first architecture memory address to the corresponding second architecture memory address, and the immediate value mapping table is used to map the first architecture immediate value to the corresponding second architecture immediate value. In this way, in the above translation process, the second architecture register corresponding to the first architecture register in the first architecture assembly instruction may be determined based on the register mapping table, the second architecture memory address corresponding to the first architecture memory address in the first architecture assembly instruction may be determined based on the memory address mapping table, and the second architecture immediate value corresponding to the first architecture immediate value in the first architecture assembly instruction may be determined based on the immediate value mapping table.

[0098] In addition, in some embodiments, if the second architecture register corresponding to the first architecture register does not exist in the register mapping table, a new register mapping can be created in the mapping buffer (g_reg_map_buf), and the new register mapping can be added to the register mapping table so as to determine the second architecture register corresponding to the first architecture register based on the new register mapping. Before adding the new register mapping to the register mapping table, it can be pre-checked whether the buffer index exceeds the maximum length (MAX_MAP_BUF_LEN) to ensure that the mapping buffer does not overflow, thereby ensuring the stability of the dynamic binary translation process. It should be noted that only the correct register mapping can ensure that the translated second architecture instructions can be executed correctly, and any mapping errors may cause runtime errors or security issues. Therefore, before adding a new register mapping to the mapping buffer, checking whether the buffer index exceeds the maximum length is a defensive programming practice that helps prevent potential memory access errors and ensures the security and stability of the system. If the mapping buffer is full, you can take measures such as expanding the buffer size, optimizing the mapping logic, or return an error or exception when the buffer index exceeds the maximum length.

[0099] In some embodiments, considering that a large number of translation rules generated by the translation model have varying qualities, important translation rules can be screened to improve the efficiency and reliability of dynamic binary translation. Specifically, for multiple translation rules that have been parameterized, the applicability of each translation rule can be evaluated to conduct a preliminary screening of the translation rules, including checking whether the rules can cover a variety of instruction sets and application scenarios, evaluating their versatility in different programs and operating environments, and considering the adaptability and flexibility of the rules to new situations. Furthermore, important translation rules that frequently appear in actual applications and have a greater impact on performance can be further screened from the translation rule set, and formal verification can be performed to ensure the correctness and reliability of important translation rules.

[0100] In a specific embodiment, the computing device 200 can filter out important translation rules from the translation rule set and perform formal verification in the following manner: the computing device 200 can dynamically count the number of successful matches of each translation rule in the translation rule set during the dynamic binary translation. The number of successful matches of the translation rule, that is, the number of times the translation rule is selected as the target translation rule. Specifically, when any translation rule is successfully matched (selected as the target translation rule), the counter of any translation rule can be added by 1, so as to realize the dynamic statistics of the number of successful matches of each translation rule in the translation rule set. After counting for a period of time, the various translation rules in the translation rule set can be sorted from high to low according to the number of successful matches to generate a translation rule list. Next, a predetermined number of translation rules with the highest number of successful matches can be obtained from the translation rule list as important translation rules (that is, translation rules that appear frequently and have a greater impact on performance). Specifically, a predetermined number of translation rules with the highest number of successful matches in the translation rule list can be marked as important translation rules. Furthermore, each important translation rule can be formally verified to determine whether the first architecture parameterized assembly code block and the second architecture parameterized assembly code block in the important translation rule are equivalent, and to determine whether the important rule is correct. It should be noted that by formally verifying the important translation rules, the correctness and reliability of the important rules can be verified, and thus hidden errors that may exist in the important rules can be eliminated.

[0101] It should be noted that formal verification is a technique that uses mathematical methods to ensure the correctness of a program or system. For binary translation scenarios, formal verification helps verify the accuracy and completeness of translation rules.

[0102] Symbolic execution is a program analysis technique commonly used in software testing. It uses symbols instead of specific input values ​​to execute a program, thereby exploring multiple paths that the program may take at the same time, which enables symbolic execution to achieve comprehensive program coverage. In some embodiments of the present invention, equivalence can be verified by evaluating the symbolic execution results of registers, memory addresses, and branch conditions.

[0103] Specifically, in some embodiments, the computing device 100 can perform formal verification on each important translation rule in the following manner to determine whether the states of the first assembly code and the second assembly code in the important translation rule are equivalent: First, the first architecture parameterized assembly code block and the second architecture parameterized assembly code block in the important translation rule are respectively passed to the symbolic execution engine (angr). Subsequently, the symbolic execution engine (angr) can be used to symbolize the first state of the first architecture parameterized assembly code block (including the first register and the first memory address of the first architecture parameterized assembly code block) and the second state of the second architecture parameterized assembly code block (including the second register and the second memory address of the second architecture parameterized assembly code block) respectively, and obtain the first symbol value of the first architecture parameterized assembly code block and the second symbol value of the second architecture parameterized assembly code block. Then, symbolic execution can be performed based on the first symbol value of the first architecture parameterized assembly code block and the second symbol value of the second architecture parameterized assembly code block to obtain the first final state of the first architecture parameterized assembly code block and the second final state of the second architecture parameterized assembly code block. Next, the first register value and the first memory address value can be extracted from the first final state, and the second register value and the second memory address value can be extracted from the second final state, and an equivalence verification formula can be constructed based on the first register value, the first memory address value, the second register value, and the second memory address value. Finally, the equivalence verification formula can be solved using an SMT solver (e.g., Z3) to determine whether the first final state of the first architecture parameterized assembly code block is equivalent to the second final state of the second architecture parameterized assembly code block. Specifically, using an SMT solver (e.g., Z3) to solve the equivalence verification formula can determine whether the first final state of the first architecture parameterized assembly code block is always equivalent to the second final state of the second architecture parameterized assembly code block under all possible symbol values. If the first final state is equivalent to the second final state of the second architecture parameterized assembly code block, it is determined that the important translation rule is correct; otherwise, it is determined that the important translation rule is incorrect, and then the hidden errors that may exist in the important rule can be eliminated.

[0104] It should be noted that in the above embodiments, through formal verification, the correctness of important translation rules can be strictly proved from the perspective of mathematics and logic, and then the hidden errors that may exist in important translation rules can be eliminated, providing a guarantee for the practical application of translation rules. Furthermore, the formal verification method based on symbolic execution has a high degree of automation and versatility, and is easy to apply to new translation rules and new system architectures.

[0105] Figure 4 A schematic diagram of a dynamic binary translation device 400 provided according to an embodiment of the present invention is shown. The dynamic binary translation device 400 can be deployed in a computing device 100 based on a second architecture processor, and the dynamic binary translation device 400 can be configured to execute the dynamic binary translation method 200 of the present invention with an integrated translation rule set.

[0106] In the embodiment of the present invention, a translation rule set is integrated in the dynamic binary translation device 400, and the translation rule set includes multiple translation rules, each of which includes a first architecture parameterized assembly code block and a corresponding second architecture parameterized assembly code block. An application is deployed in the computing device.

[0107] like Figure 4 As shown, in the embodiment of the present invention, the dynamic binary translation device 400 includes a scanning unit 410, a disassembly unit 420, a selection unit 430, a translation unit 440 and an assembly unit 450 which are sequentially communicatively connected.

[0108] The scanning unit 410 is used to scan the real-time instruction stream when the application is running, so as to obtain one or more first architecture machine instruction sequences from the real-time instruction stream.

[0109] The disassembly unit 420 is used to disassemble the first architecture machine instruction sequence into a first architecture assembly instruction sequence.

[0110] The selection unit 430 is used to select a translation rule that matches the first architecture assembly instruction sequence from the translation rule set as a target translation rule.

[0111] The translation unit 440 is used to translate the first architecture assembly instruction sequence into a corresponding second architecture assembly instruction sequence based on the target translation rule.

[0112] The assembly unit 450 is used to assemble the second architecture assembly instruction sequence into a second architecture machine instruction sequence so as to execute the second architecture machine instruction sequence.

[0113] It should be noted that the scanning unit 410, the disassembling unit 420, the selecting unit 430, the translating unit 440 and the assembling unit 450 are respectively used to execute the aforementioned steps 210 to 250. Here, the specific execution logic of each unit can be found in the description of steps 210 to 250 in the method 200 above, which will not be repeated here.

[0114] According to the dynamic binary translation method 200 with integrated translation rule set in the embodiment of the present invention, by integrating the translation rule set in the computing device based on the second architecture processor, when the application is running, the first architecture assembly instruction sequence in the application can be directly translated into the corresponding second architecture assembly instruction sequence based on the translation rule set, and then the second architecture assembly instruction sequence is assembled into the second architecture machine instruction sequence and executed. In this way, the present invention adopts the direct translation method when the application is running, which can not only improve the translation efficiency, but also avoid the complexity and performance loss caused by the use of intermediate representation.

[0115] In addition, the present invention utilizes the translation model to generate a translation rule set, which can reduce manual intervention, further improve translation efficiency, translation accuracy and performance optimization capabilities, and facilitate efficient management of large-scale translation rule sets.

[0116] In addition, the present invention can ensure the correctness and reliability of important translation rules and eliminate potential hidden errors in important rules by screening important translation rules and performing formal verification on them. Furthermore, the formal verification method based on symbolic execution has a high degree of automation and versatility.

[0117] In addition, the embodiment of the present invention also discloses: A7, a method as described in A2, wherein, based on the target translation rule, translating the first architecture assembly instruction into the corresponding second architecture assembly instruction comprises: obtaining each first architecture operand in the first architecture assembly instruction, wherein the first architecture operand comprises one or more of a first architecture register, a first architecture memory address, and a first architecture immediate value; determining the second architecture operand corresponding to each first architecture operand; translating the first architecture assembly instruction into the corresponding second architecture assembly instruction based on the target translation rule and the second architecture operand corresponding to each first architecture operand. A8, a method as described in any one of A1-A7, wherein, it further comprises: dynamically counting the number of successful matches of each translation rule in the translation rule set; sorting the translation rules in the translation rule set according to the number of successful matches to generate a translation rule list; obtaining a predetermined number of translation rules with the highest number of successful matches from the translation rule list as important translation rules; formally verifying each of the important translation rules to determine whether the first architecture parameterized assembly code block in the important translation rule is equivalent to the second architecture parameterized assembly code block, and determining whether the important translation rule is correct. A9. A method as described in A8, wherein each of the important translation rules is formally verified to determine whether the first architecture parameterized assembly code block and the second architecture parameterized assembly code block in the important translation rule are equivalent, including: respectively passing the first architecture parameterized assembly code block and the second architecture parameterized assembly code block in the important translation rule to a symbolic execution engine; using the symbolic execution engine, respectively symbolizing the first state of the first architecture parameterized assembly code block and the second state of the second architecture parameterized assembly code block to obtain a first symbolic value of the first architecture parameterized assembly code block and a second symbolic value of the second architecture parameterized assembly code block, wherein the first state includes a first register and a first memory address, and the The second state includes a second register and a second memory address; symbolic execution is performed based on the first symbolic value of the first architecture parameterized assembly code block and the second symbolic value of the second architecture parameterized assembly code block to obtain a first final state of the first architecture parameterized assembly code block and a second final state of the second architecture parameterized assembly code block; a first register value and a first memory address value are extracted from the first final state, and a second register value and a second memory address value are extracted from the second final state to construct an equivalence verification formula; an SMT solver is used to solve the equivalence verification formula to determine whether the first final state of the first architecture parameterized assembly code block is equivalent to the second final state of the second architecture parameterized assembly code block.A10. A method as described in A6, further comprising: disassembling multiple binary files to obtain a first architecture sample assembly code block and a second architecture sample assembly code block corresponding to each line of source code; inputting the first architecture sample assembly code block and the second architecture sample assembly code block into a pre-training module to extract the first architecture instruction embedding information corresponding to the first architecture sample assembly code block and the second architecture instruction embedding information corresponding to the second architecture sample assembly code block; training a translation module based on the first architecture sample assembly code block, the first architecture instruction embedding information, the second architecture sample assembly code block, and the second architecture instruction embedding information to obtain the translation model. A11. The method as described in A10, wherein disassembling multiple binary files to obtain the first architecture sample assembly code block and the second architecture sample assembly code block corresponding to each line of source code respectively comprises: obtaining multiple source code files based on multiple programming languages; compiling each of the source code files to generate the first architecture binary file and the second architecture binary file corresponding to the source code file; disassembling the first architecture binary file and the second architecture binary file respectively to obtain the corresponding first architecture assembly code file and the second architecture assembly code file; obtaining each first architecture sample assembly code block from the first architecture assembly code file, and obtaining each second architecture sample assembly code block from the second architecture assembly code file; establishing a mapping relationship between each first architecture sample assembly code block and each second architecture sample assembly code block and each line of source code in the source code file to obtain the first architecture sample assembly code block and the second architecture sample assembly code block corresponding to each line of source code respectively. A12. The method as described in any one of A1-A11, wherein the first architecture is the x86 architecture, and the second architecture is the ARM architecture.

[0118] The various techniques described herein may be implemented in combination with hardware or software, or a combination thereof. Thus, the method and apparatus of the present invention, or some aspects or parts of the method and apparatus of the present invention may be in the form of program codes (i.e., instructions) embedded in a tangible medium, such as a removable hard disk, a USB flash drive, a floppy disk, a CD-ROM, or any other machine-readable storage medium, wherein when the program is loaded into a machine such as a computer and executed by the machine, the machine becomes a device for practicing the present invention.

[0119] In the case where the program code is executed on a programmable computer, the mobile terminal generally includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store the program code; the processor is configured to execute the dynamic binary translation method of the integrated translation rule set of the present invention according to the instructions in the program code stored in the memory.

[0120] By way of example and not limitation, readable media include readable storage media and communication media. Readable storage media stores information such as computer readable instructions, data structures, program modules or other data. Communication media generally embody computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and include any information transfer medium. Any combination of the above is also included within the scope of readable media.

[0121] In the description provided herein, algorithms and displays are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the examples of the present invention. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to implement the content of the present invention described herein, and the above description of specific languages ​​is for the purpose of disclosing the best mode of the present invention.

[0122] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0123] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof.

[0124] Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in the devices described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0125] Unless otherwise specified, the use of ordinal numbers "first", "second", "third", etc. to describe common objects merely indicates that different instances of similar objects are involved and is not intended to imply that the objects so described must have a given order in time, space, order or in any other manner.

Claims

1. A dynamic binary translation method integrating a translation rule set, which is executed in a computing device based on a second architecture processor, wherein the computing device is integrated with a translation rule set, wherein the translation rule set includes a plurality of translation rules, wherein each translation rule includes a first architecture parameterized assembly code block and a corresponding second architecture parameterized assembly code block, and an application is deployed in the computing device, wherein the method includes: Scanning a real-time instruction stream when the application is running to obtain one or more first architecture machine instruction sequences from the real-time instruction stream; De-assembling the first architecture machine instruction sequence into a first architecture assembly instruction sequence; Selecting a translation rule that matches the first architecture assembly instruction sequence from the translation rule set as a target translation rule; Based on the target translation rule, translating the first architecture assembly instruction sequence into a corresponding second architecture assembly instruction sequence; as well as The second architecture assembly instruction sequence is assembled into a second architecture machine instruction sequence so as to execute the second architecture machine instruction sequence through the second architecture processor.

2. The method of claim 1, wherein: Selecting a translation rule that matches the first architecture assembly instruction sequence from the translation rule set as a target translation rule; Based on the target translation rule, translating the first architecture assembly instruction sequence into a corresponding second architecture assembly instruction sequence includes: For each first architecture assembly instruction in the first architecture assembly instruction sequence, determining a first architecture opcode, a first architecture operand type, and a first architecture operand quantity in the first architecture assembly instruction to determine a target instruction mode corresponding to the first architecture assembly instruction; Selecting a translation rule that matches the target instruction pattern from the translation rule set as a target translation rule; Based on the target translation rule, the first architecture assembly instruction is translated into a corresponding second architecture assembly instruction.

3. The method of claim 2, wherein: Determining a first architecture opcode, a first architecture operand type, and a first architecture operand quantity in the first architecture assembly instruction to determine a target instruction mode corresponding to the first architecture assembly instruction includes: Decomposing the first architecture assembly instruction into a plurality of basic elements to determine a first architecture opcode, a first architecture operand type, and a first architecture operand quantity in the first architecture assembly instruction, wherein the plurality of basic elements include a first architecture opcode and one or more first architecture operands; Constructing an instruction mode library corresponding to the first architecture assembly instruction, the instruction mode library comprising a plurality of instruction modes and features of the instruction modes, wherein the features of the instruction modes include an operation code, an operand type, and a number of operands; The first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction are compared with each instruction mode in the instruction mode library to determine a target instruction mode corresponding to the first architecture assembly instruction.

4. The method of claim 3, wherein: Comparing the first architecture opcode, the first architecture operand type, and the first architecture operand quantity in the first architecture assembly instruction with each instruction mode in the instruction mode library to determine a target instruction mode corresponding to the first architecture assembly instruction, including: Comparing the first architecture operation code with the operation codes of each instruction mode in the instruction mode library respectively to obtain one or more first candidate instruction modes matching the first architecture operation code; Comparing the first architecture operand type with the operand types of each of the first candidate instruction modes respectively to obtain one or more second candidate instruction modes matching the first architecture opcode and the first architecture operand type; The first architecture operand quantity is compared with the operand quantity of each of the second candidate instruction modes respectively to obtain a target instruction mode that successfully matches the first architecture opcode, the first architecture operand type and the first architecture operand quantity.

5. The method according to any one of claims 2 to 4, wherein: Based on the target translation rule, translating the first architecture assembly instruction into a corresponding second architecture assembly instruction includes: Parsing the first architecture operand of the first architecture assembly instruction to obtain a parsing result of the first architecture operand, wherein the parsing result includes detailed information of the first architecture operand; Based on the target translation rule and the parsing result of the first architecture operand, the first architecture assembly instruction is translated into one or more corresponding second architecture assembly instructions.

6. The method according to any one of claims 1 to 5, wherein: Also includes: Using the translation model, converting the plurality of first architecture actual assembly code blocks into corresponding plurality of second architecture actual assembly code blocks respectively, so as to establish a mapping relationship between the plurality of first architecture actual assembly code blocks and the plurality of second architecture actual assembly code blocks; Parameterizing the operands in each of the first architecture actual assembly code blocks and the corresponding second architecture actual assembly code blocks to obtain each of the first architecture parameterized assembly code blocks and the corresponding second architecture parameterized assembly code blocks; A translation rule set is generated based on each of the first architecture parameterized assembly code blocks and the corresponding second architecture parameterized assembly code blocks.

7. A dynamic binary translation apparatus, deployed in a computing device based on a second architecture processor, wherein a translation rule set is integrated in the dynamic binary translation apparatus, wherein the translation rule set includes a plurality of translation rules, each of the translation rules includes a first architecture parameterized assembly code block and a corresponding second architecture parameterized assembly code block, wherein an application is deployed in the computing device, and wherein the apparatus comprises: A scanning unit, adapted to scan a real-time instruction stream when the application is running, so as to obtain one or more first architecture machine instruction sequences from the real-time instruction stream; a disassembly unit adapted to disassemble the first architecture machine instruction sequence into a first architecture assembly instruction sequence; A selection unit, adapted to select a translation rule matching the first architecture assembly instruction sequence from the translation rule set as a target translation rule; a translation unit adapted to translate the first architecture assembly instruction sequence into a corresponding second architecture assembly instruction sequence based on the target translation rule; as well as The assembly unit is adapted to assemble the second architecture assembly instruction sequence into a second architecture machine instruction sequence so as to execute the second architecture machine instruction sequence through the second architecture processor.

8. A computing device comprising: at least one processor; and A memory storing program instructions, wherein the program instructions are configured to be processed by the at least one processor, and the program instructions include instructions for processing the method according to any one of claims 1 to 6.

9. A computer program product comprising a computer program / instructions, wherein: When the computer program / instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A readable storage medium storing program instructions, which, when read and processed by a computing device, enables the computing device to process the method according to any one of claims 1 to 6.

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