Binary translation optimization method, binary translator and electronic equipment

Abstract

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, and the method comprises the steps: updating a state mark of a first register in a preset state table according to the write bit width of a narrow write operation to the first register when a narrow write operation instruction is translated; the state mark is used for indicating whether the high bit of the corresponding register needs to be reset or not and recording the effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to read operation from the preset state table; if it is judged that the reading bit width of the reading operation is larger than the effective bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the reading operation instruction; the first zero clearing instruction is used for performing zero clearing on a specified high bit of the second register. According to the method, the target machine code sequence generated by translation can be simplified, redundant operations are greatly reduced, and the execution efficiency of a translation system is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a binary translation optimization method, a binary translator, and an electronic device. Background Technology

[0002] Binary translation can convert source programs running on one architecture platform into target programs running on another architecture platform, thus solving the problem of binary-level applications running across instruction set architectures. Binary translation has become one of the hot research topics in the field of computer technology in recent years.

[0003] In the AArch64 instruction set, the 128-bit vector registers (V0–V31) are used for both scalar floating-point operations and SIMD (Single Instruction Multiple Data) vector operations. The specification mandates that when an instruction is written to the destination register in narrow write form (i.e., a write width less than 128 bits), the untouched high-order bits in the destination register must be immediately cleared to zero. However, architectures such as LoongArch and RISC-V, when handling such narrow write operations, by default retain the original high-order bits or use sign extension, without mandatory clearing.

[0004] To eliminate the aforementioned semantic differences and ensure the correctness of binary translation, traditional dynamic binary translators employ an on-the-fly physical zeroing strategy. This involves generating additional zeroing instructions (such as bitwise AND, insertion, or dedicated zero-extension instructions) after each translation of a narrow-write operation instruction in the AArch64 architecture to force the high-order bits of the target register to be cleared. However, in vector-intensive real-world applications such as audio / video encoding / decoding, machine learning, and scientific computing, the same register is frequently subjected to multiple consecutive narrow-write operations. This zeroing strategy requires generating a zeroing instruction for each narrow-write operation, leading to target code bloat, increased redundant operations, and impacting the execution efficiency of the translation system. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a binary translation optimization method that overcomes or at least partially solves the above problems, which can simplify the target machine code sequence generated by translation, greatly reduce redundant operations, and improve the execution efficiency of the translation system.

[0006] Accordingly, embodiments of the present invention also provide a binary translator and an electronic device to ensure the implementation and application of the above method.

[0007] In a first aspect, embodiments of the present invention disclose a binary translation optimization method, the method comprising: When translating a narrow write operation instruction, the status flag of the first register is updated in the preset status table according to the write bit width of the narrow write operation to the first register; the preset status table records the status flag of each register in the active architecture, and the status flag is used to indicate whether the high bit of the corresponding register needs to be cleared, and to record the effective bit width of the corresponding register; When translating a read operation instruction, the status flag of the second register corresponding to the read operation is obtained from the preset status table; If it is determined that the read bit width of the read operation is greater than the effective bit width indicated by the status flag of the second register, a first clear instruction is inserted before the translation result of the read operation instruction; the first clear instruction is used to clear the specified high bit of the second register.

[0008] Secondly, embodiments of the present invention disclose a binary translator, the binary translator comprising: The state update module is used to update the state flag of the first register in the preset state table when a narrow write operation instruction is translated, based on the write bit width of the first register by the narrow write operation. The preset state table records the state flag of each register in the active architecture. The state flag is used to indicate whether the high bit of the corresponding register needs to be cleared and to record the effective bit width of the corresponding register. The status acquisition module is used to obtain the status flag of the second register corresponding to the read operation from the preset status table when a read operation instruction is translated. The first processing module is configured to insert a first clear instruction before the translation result of the read operation instruction if it is determined that the read bit width of the read operation is greater than the effective bit width indicated by the status flag of the second register; the first clear instruction is used to clear the specified high bits of the second register.

[0009] Thirdly, embodiments of the present invention disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, wherein the executable instruction causes the processor to perform the steps of any of the binary translation optimization methods described above.

[0010] The binary translation optimization method, binary translator, and electronic device provided in this invention have the following advantages: This invention maintains a mapping table (preset state table) for the hardware registers of the source architecture at the translation layer. This table indicates whether the high-order bits of each register in the source architecture need to be cleared, and records the effective bit width of each register. During dynamic translation, for consecutive narrow write operations, no clear instruction is inserted initially. Only when a read operation instruction with a bit width greater than the effective bit width recorded in the preset state table is a clear instruction inserted before the translation result of that read operation instruction is reached. If no read operation instruction with a bit width greater than the effective bit width recorded in the preset state table is encountered, no clear instruction is generated. Compared to traditional translators that generate clear instructions for every narrow write operation, this invention provides a fine-grained, multi-level bit width comparison-based high-order bit delayed clearing method. This method postpones, merges, or even completely discards physical clearing operations as much as possible, thereby maximizing the simplification of the target machine code sequence generated by translation while ensuring semantic correctness. This significantly reduces redundant operations and improves the execution efficiency of the translation system. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the steps of an embodiment of the binary translation optimization method of the present invention; Figure 2 This is a schematic diagram illustrating the use of vector registers with different bit widths in the AArch64 architecture; Figure 3 This is a schematic diagram of a binary translation process according to the present invention; Figure 4 This is a structural block diagram of an embodiment of a binary translator according to the present invention; Figure 5 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0012] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0014] Figure 1 A flowchart illustrating an embodiment of the binary translation optimization method of the present invention is shown. The method may include the following steps: Step 101: When translating a narrow write operation instruction, update the status flag of the first register in the preset status table according to the write bit width of the narrow write operation to the first register; the preset status table records the status flag of each register in the active architecture, and the status flag is used to indicate whether the high bit of the corresponding register needs to be cleared, and to record the effective bit width of the corresponding register. Step 102: When translating a read operation instruction, obtain the status flag of the second register corresponding to the read operation from the preset status table; Step 103: If it is determined that the read bit width of the read operation is greater than the effective bit width indicated by the status flag of the second register, then insert a first clear instruction before the translation result of the read operation instruction; the first clear instruction is used to clear the specified high bits of the second register.

[0015] The binary translation optimization method provided in this invention can be applied to binary translators, such as dynamic binary translators. The binary translator is used to translate binary code from a source architecture to binary code from a target architecture. When the source architecture is AArch64 and the target architecture is LoongArch or RISC-V, due to differences in the high-order processing semantics of narrow-write operations, traditional translators need to insert zero-clear instructions after each narrow-write operation instruction, leading to severe code bloat and performance degradation. This invention provides an optimized zero-clear processing strategy for the above application scenario.

[0016] In this embodiment of the invention, the instructions or instruction groups that implement the function of clearing the high-order bits of the register are collectively referred to as clear instructions, such as the first clear instruction and the second clear instruction in this document. This embodiment of the invention does not limit the specific form of the clear instructions; any instruction that can achieve the function of clearing the specified high-order bits of the register is applicable, including but not limited to bitwise AND instructions, shift instructions, zero-extend instructions, and dedicated high-order bit clear instructions.

[0017] It should be noted that the above examples of using AArch64 as the source architecture and LoongArch or RISC-V as the target architecture are merely illustrative, and the embodiments of this invention do not impose specific limitations on the source and target architectures. As long as there are differences between the source and target architectures in the semantics of high-order bit processing during narrow write operations—for example, the source architecture requires forced zeroing while the target architecture retains the original high-order bit value by default or uses sign extension—the binary translation optimization method provided by this invention is applicable.

[0018] The purpose of this invention is to postpone, merge, or even completely discard the physical zeroing operation as much as possible, thereby simplifying the target machine code sequence generated by translation to the greatest extent possible while ensuring semantic correctness.

[0019] Specifically, in the memory of the binary translator, this embodiment of the invention allocates a data structure in the source architecture to indicate the state to be cleared for each register. This data structure can be used to indicate whether the corresponding register needs to be cleared of its high bits, and at the same time records the effective bit width of the corresponding register, which refers to the bit width of the valid data in the register.

[0020] The embodiments of the present invention do not limit the specific form of this data structure. For example, a mapping table (referred to as a preset state table in the present invention) can be constructed and maintained. Each entry in the mapping table corresponds to a register in the source architecture and is used to record the state flag of the register. The state flag is used to indicate whether the high bits of the corresponding register need to be cleared, and at the same time, it records the effective bit width of the corresponding register.

[0021] Reference Figure 2 This diagram illustrates the use of vector registers with different bit widths in the AArch64 architecture.

[0022] like Figure 2 As shown, the AArch64 architecture provides 128-bit vector / floating-point registers (V0-V31), which are used for both scalar floating-point operations (such as 32-bit single-precision S registers and 64-bit double-precision D registers) and SIMD vector operations of various data widths (such as combinations of 8-bit, 16-bit, 32-bit, and 64-bit elements).

[0023] In the AArch64 architecture, each 128-bit vector register (Vn) supports multiple bit-width alias access methods to achieve a unified register design for scalar floating-point operations and SIMD vector operations. Specifically: Vn: A complete 128-bit vector register used for 128-bit wide SIMD vector operations (such as the Q register).

[0024] Dn: Mapped to the lower 64 bits of Vn, used for 64-bit double-precision floating-point operations or 64-bit vector element operations.

[0025] Sn: Mapped to the lower 32 bits of Vn, used for 32-bit single-precision floating-point operations or 32-bit vector element operations.

[0026] Hn: Mapped to the lower 16 bits of Vn, used for 16-bit half-precision floating-point operations or 16-bit vector element operations.

[0027] Bn: Mapped to the lower 8 bits of Vn, used for 8-bit byte operations or 8-bit vector element operations.

[0028] The AArch64 architecture uses a shared register mechanism. Write operations to narrow-width registers such as S and D are essentially writing to a portion of the 128-bit V register. According to the AArch64 specification, after such a narrow write operation, the unwritten high-order bits in the V register must be automatically cleared by hardware (e.g., ...). Figure 2 (As shown in the mid-to-high position region), to ensure semantic correctness.

[0029] In this embodiment of the invention, the source architecture is AArch64 as an example. The translation optimization process for other source architectures is similar and can be referred to accordingly.

[0030] In this embodiment of the invention, a preset state table is constructed and maintained in the memory of the binary translator. The preset state table is used to record the state flags corresponding to each 128-bit vector register (V0 to V31) in the AArch64 architecture.

[0031] Referring to Table 1, an exemplary description of a status marker according to the present invention is shown.

[0032] Table 1

[0033] Taking the status flag zero64 as an example, it indicates that the high-order bits of the corresponding register need to be cleared, and the width of the valid data in the register is 64 bits, that is, the lower 64 bits of the register are valid data, and the higher 64 bits need to be cleared.

[0034] Furthermore, before translation execution, the preset state table can be constructed and initialized, setting the state flags of all registers in the preset state table to the initial state (e.g., none). Since all registers are initially empty, the initial state indicates that the high-order bits do not need to be cleared.

[0035] It should be noted that the embodiments of the present invention do not limit the register bit width of the source architecture and the target architecture. Table 1 can be extended according to the register bit width of the source architecture. For example, the register bit width of the source architecture can be 32 bits, 64 bits, 128 bits or other fixed widths; the register bit width of the target architecture can also be 32 bits, 64 bits, 128 bits or other fixed widths; the register bit width of the source architecture and the register bit width of the target architecture can be the same or different.

[0036] When the binary translator of this invention translates a narrow write operation instruction, it updates the status flag of the first register in a preset status table according to the write bit width of the first register to be written by the narrow write operation, without inserting a clear instruction at this time. The first register refers to the register to be written to by the narrow write operation.

[0037] The narrow write operation instruction refers to an instruction that writes to a register with a bit width smaller than the register's own bit width. It is understood that a given instruction may contain both read and write operations. The narrow write operation instruction means that while it includes a narrow write operation, it may also include read or other operations.

[0038] Optionally, the narrow write operation may include: writing to the S register or D register in scalar form, and writing to the vector register in a narrow vector form that is not 128 bits wide.

[0039] Taking the AArch64 architecture as an example, its vector registers V0 to V31 are all 128 bits wide. When the instruction writes only a portion of these bits (such as the lower 32 bits, lower 64 bits, etc.), the write operation is called a narrow write operation.

[0040] Specifically, the narrow write operation can include the following two categories: scalar narrow write operation and vector narrow write operation. A scalar narrow write operation involves writing to the S register or D register in scalar form. The S register is mapped to the lower 32 bits of the vector register for single-precision floating-point operations; the D register is mapped to the lower 64 bits of the vector register for double-precision floating-point operations. Writing to the S register or D register is essentially writing a portion of a 128-bit vector register. A vector narrow write operation involves writing to the vector register in a narrow vector form that is not 128 bits wide. For example, using 8-bit, 16-bit, 32-bit, or 64-bit wide SIMD instructions to partially write to the vector register all fall under the category of narrow write operations.

[0041] When translating source architecture instructions one by one, if the binary translator encounters a narrow write operation instruction, it does not generate any target architecture instruction for physical high-order bit clearing. Instead, it updates the status flag of the corresponding register in the preset status table based on the write width of the narrow write operation. If the same register is written to by multiple narrow write operations of different widths consecutively, the status flag of that register in the preset status table will be the write width of the last narrow write operation. In other words, the preset status table always retains the latest status flag of each register.

[0042] In Example 1, register V0 is initially marked as none, indicating that the high-order bits do not need to be cleared. Narrow write operation 1 performs a write operation to register V0 with a write width of 64 bits. At this time, the status flag of register V0 in the preset status table is updated to zero64, indicating that the effective bit width of register V0 is 64 bits. Then, narrow write operation 2 performs a write operation to register V0 with a write width of 32 bits. At this time, the status flag of register V0 in the preset status table is updated to zero32, indicating that the effective bit width of register V0 is 32 bits.

[0043] In Example 2, register V0 is initially marked as none, indicating that the high-order bits do not need to be cleared. Narrow write operation 1 performs a write operation to register V0 with a write width of 32 bits. At this time, the status flag of register V0 in the preset status table is updated to zero32, indicating that the effective bit width of register V0 is 32 bits. Then, narrow write operation 2 performs a write operation to register V0 with a write width of 64 bits. At this time, the status flag of register V0 in the preset status table is updated to zero64, indicating that the effective bit width of register V0 is 64 bits.

[0044] When translating a read operation instruction, the status flag of the second register corresponding to the read operation is obtained from the preset status table. If it is determined that the read bit width of the read operation is greater than the effective bit width indicated by the status flag of the second register, a first clear instruction is inserted before the translation result of the read operation instruction. The first clear instruction is used to clear the specified high-order bits of the second register. The second register refers to the register from which the read operation will read data.

[0045] The translation result refers to the sequence of target architecture instructions generated by translating source architecture instructions. Each source architecture instruction corresponds to a translation result, which may contain one or more target architecture instructions.

[0046] In this embodiment of the invention, no clear instruction is generated for consecutive narrow write operations; only the status flag of the corresponding register in the preset status table is updated. Taking Example 1 above as an example, after narrow write operation 2, when a read operation instruction is translated, it is assumed that the read operation will read 64 bits of data from register V0. At this time, the status flag of the second register (i.e., register V0) corresponding to the read operation is obtained from the preset status table. This status flag indicates that the effective bit width of register V0 is 32 bits. Since the read bit width (64 bits) of register V0 is greater than the effective bit width (32 bits) recorded in the preset status table, a high-bit clear operation needs to be performed on register V0 before the read operation instruction reads the data.

[0047] Specifically, a first clear instruction is inserted before the translation result of the read operation instruction; the first clear instruction is used to clear a specified high-order bit of the second register (such as register V0). The specified high-order bit refers to the remaining high-order bits in the second register excluding the low-order bits occupied by the valid data. Since the valid data in register V0 is currently the lower 32 bits, the specified high-order bit is the high 96 bits of register V0 (128-32=96). That is, the high 96 bits of register V0 need to be cleared.

[0048] Furthermore, the method may further include: after inserting a first clear instruction before the translation result of the read operation instruction, setting the status flag corresponding to the second register to the initial state in the preset state table. Since the first clear instruction is used to clear a specified high-order bit of the second register (such as register V0), after executing the first clear instruction, the high-order bits of the second register have been cleared, and the second register only contains valid data. At this time, the status flag corresponding to the second register can be set to the initial state, indicating that the high-order bits of the second register do not need to be cleared at this time, thus avoiding redundant clearing operations in the future.

[0049] When translating a read operation instruction, the status flag of the second register corresponding to the read operation is obtained from the preset status table; if it is determined that the read operation reads the second register with a bit width less than or equal to the effective bit width indicated by the status flag of the second register, then the read operation instruction can be translated into the target architecture instruction without generating a clear instruction.

[0050] It should be noted that for a source architecture instruction currently translated from binary (referred to as the current instruction), the current instruction may simultaneously include narrow write operations and read operations; that is, the instruction is both a narrow write operation instruction and a read operation instruction. Therefore, in this embodiment of the invention, the current instruction is first determined to be a read operation instruction. If it is a read operation instruction, the read bit width of the read operation is further compared with the effective bit width recorded in the preset state table. If it is necessary to clear the high-order bits of the register, a clear instruction is inserted before the translation result of the current instruction. Further, it is then determined whether the current instruction is a narrow write operation instruction. If it is, the status flag of the corresponding register in the preset state table is updated.

[0051] This invention maintains a mapping table (preset state table) for the hardware registers of the source architecture at the translation layer. This table indicates whether the high-order bits of each register in the source architecture need to be cleared, and records the effective bit width of each register. During dynamic translation, for consecutive narrow write operations, no clear instruction is inserted initially. Only when a read operation instruction with a bit width greater than the effective bit width recorded in the preset state table is a clear instruction inserted before the translation result of that read operation instruction is reached. If no read operation instruction with a bit width greater than the effective bit width recorded in the preset state table is encountered, no clear instruction is generated. Compared to traditional translators that generate clear instructions for every narrow write operation, this invention provides a fine-grained, multi-level bit width comparison-based high-order bit delayed clearing method. This method postpones, merges, or even completely discards physical clearing operations as much as possible, thereby maximizing the simplification of the target machine code sequence generated by translation while ensuring semantic correctness. This significantly reduces redundant operations and improves the execution efficiency of the translation system.

[0052] Redundant operations refer to repeatedly clearing the high bits of the same register multiple times, and most of these operations are unnecessary.

[0053] For example, in Example 2 above, if a traditional clearing strategy is used, after narrow write operation 1 performs a write operation to register V0 (write bit width is 32 bits), the high 96 bits of register V0 are cleared. Then, after narrow write operation 2 performs a write operation to register V0 (write bit width is 64 bits), the high 64 bits of register V0 are cleared again. However, the high 64 bits of register V0 were already zero at this time, making this clearing operation redundant. In this embodiment of the invention, each time a narrow write operation instruction is translated, only the status flag of the corresponding register is updated, and no clearing instruction is inserted. The clearing operations on the high bits of the register are accumulated and delayed until before a certain read operation instruction. The read operation instruction reads a register with a bit width greater than the effective bit width recorded in the preset status table, thereby greatly reducing redundant clearing operations.

[0054] In an optional embodiment of the present invention, the method may further include: When translating a full-width write operation instruction, the status flag of the third register corresponding to the full-width write operation in the preset status table is set to the initial state (e.g., none). The third register refers to the register to be written in the full-width write operation.

[0055] The full-width write operation instruction refers to an instruction that includes a write operation, and the write bit width of the register is equal to the register's own bit width. That is, after a full-width write operation is executed, all bits of the register are overwritten with new data, and there are no unwritten high-order bits. Therefore, the status flag of the corresponding register in the preset status table can be reset to its initial state (e.g., none). This operation means that all previously accumulated delay clearing requirements for this third register are directly cancelled, thus completely eliminating the physical clearing operation that would otherwise have been necessary.

[0056] In an optional embodiment of the present invention, the method may further include: Step S11: When translating to the control flow transfer point, traverse the preset state table and determine whether there is a register to be cleared based on the state flag corresponding to each register; Step S12: If there are registers to be cleared, determine the target location based on the control flow transfer point; Step S13: Insert a second clear instruction at the target position; the second clear instruction is used to clear the specified high-order bits of the register to be cleared.

[0057] The control flow transfer point refers to the location where the execution flow changes during program execution. Control flow transfer includes active transfer (such as jump, function call, etc.) and passive transfer (such as exception, context switch, etc.).

[0058] Upon translating to a control flow transfer point, the preset state table is traversed, and the existence of a register to be cleared is determined based on the state flag corresponding to each register. The register to be cleared refers to a register in the preset state table whose state flag is not in the initial state. If a register to be cleared exists (there may be one or more), the target location corresponding to each register to be cleared is determined based on the control flow transfer point; and a second clear instruction is inserted at the target location; the second clear instruction is used to clear a specified high-order bit of the register to be cleared. The specified high-order bit refers to the remaining high-order bits in the register to be cleared, excluding the low-order bits occupied by valid data.

[0059] In this embodiment of the invention, the high-order bits of all registers to be cleared are uniformly cleared at the control flow transfer point. This ensures that the high-order bits of the registers meet the semantic requirements of the source architecture (such as AArch64) for forced clearing before entering other code blocks, calling external functions, or handling exceptions, thus avoiding cross-code block data dependency errors caused by high-order bits not being cleared.

[0060] Furthermore, by uniformly performing high-bit clearing operations at control flow transfer points, the clearing operations to be processed are delayed and concentrated until the program execution flow switches, thereby further simplifying the target machine code sequence, reducing instruction cache pressure, and improving the overall execution efficiency of the binary translation system while ensuring semantic correctness.

[0061] It is understandable that after performing a high-bit clearing operation on each register to be cleared, the status flag corresponding to that register to be cleared is set to the initial state in the preset status table.

[0062] In an optional embodiment of the present invention, determining the target location based on the control flow transfer point may include: If the control flow transfer is an active transfer, the target location is determined to be before the translation result of the boundary instruction of the current code block; the boundary instruction includes a jump instruction, a function call instruction, or a function return instruction; or, If the control flow transfer is a passive transfer, then the target location is determined to be after the translation result of the last normal instruction before the context saving instruction. The passive transfer includes exception handling, interrupt response, or context switching.

[0063] In specific implementation, the control flow transfer includes active transfer and passive transfer. In the case of active transfer, after executing the boundary instruction of the current code block, the program leaves the current code block and enters another code block. Therefore, before executing the boundary instruction of the current code block, it is necessary to clear the high-order bits of the registers to be cleared in the current code block. Therefore, in the case of active transfer, the target location is determined to be before the translation result of the boundary instruction of the current code block, that is, before the translation result of the boundary instruction of the current code block. The second clear instruction is used to clear the high-order bits of each register to be cleared in the preset state table.

[0064] In passive jumps, it's typically necessary to save the context information before leaving the current code block. Therefore, before saving the context information, a high-order clearing operation needs to be performed on the set of registers to be cleared in the current code block. Thus, in passive jumps, after determining the target location as the translation result of the last normal instruction before the context save instruction, a second clearing instruction is inserted at that location. The normal instructions refer to ordinary arithmetic or memory access instructions other than control flow transfer instructions and exception handling-related instructions.

[0065] Reference Figure 3 The diagram illustrates a binary translation process according to the present invention. Figure 3As shown, the preset state table is initialized first. The binary translator reads a source architecture instruction for translation and determines whether the instruction reads a vector register. If the instruction reads a vector register, the read bit width of the instruction is compared with the effective bit width recorded in the preset state table. If the read bit width is greater than the recorded effective bit width, a clear instruction is inserted before the translation result of the instruction, and the status flag of the register read by the instruction is reset in the preset state table, such as to none. If the instruction does not read a vector register, it determines whether the instruction writes to a vector register. If the instruction does not write to a vector register, it determines whether the current point is a control flow transfer point. If it is a control flow transfer point, the preset state table is traversed to check if there are any registers to be cleared. If there are any registers to be cleared, they are processed uniformly, and the status flags of the cleared registers are reset. If the instruction writes to a vector register, it determines whether the instruction is a full-width write operation instruction. If the instruction is not a full-width write operation instruction, the status flag of the corresponding register in the preset state table is updated according to the write bit width. If the instruction is a full-width write operation instruction, the status flag of the corresponding register in the preset state table is reset.

[0066] In Example 3, the source architecture (AArch64 architecture) instruction snippet is as follows: FMOV S0, S1 B target The first instruction (FMOV S0, S1) writes the value (32 bits) of the floating-point / vector register S1 into register S0. Register S0 is an alias for the lower 32 bits of register V0, and register S1 is an alias for the lower 32 bits of register V1. This instruction has a write width of 32 bits, making it a narrow write operation. Therefore, when translating to the first instruction, the status flag corresponding to register V0 in the preset status table is updated to zero32. No clear instruction is generated at this time.

[0067] The second instruction (B target) is a jump instruction used to unconditionally jump to the target label. Since this is a control flow transfer point, the preset state table is forcibly traversed to check if there is a register to be cleared; if so, a second clear instruction is inserted before the translation result of the second instruction (B target).

[0068] In Example 4, the source architecture (AArch64 architecture) instruction snippet is as follows: fmov d0, x1 fmov s1, w2 fmov s2, w3 fadd s1, s0, s2 fadd s0, s0, s2 fadd d3, d0, d4 ldr q0, [x5] orr v6.16b, v0.16b, v7.16b Initially, State[V0] = none, State[V1] = none, and State[V2] = none. State[Vn] represents the state flag of register Vn in the preset state table.

[0069] The first instruction (fmov d0, x1) is a narrow write operation instruction used to write the lower 64 bits of register V0. The binary translator translates the first instruction into the target architecture instruction and updates the status flag as follows: State[V0]: none -> zero64.

[0070] The second instruction (fmov s1, w2) is a narrow write operation instruction used to write the lower 32 bits of register V1. The binary translator translates the second instruction into the target architecture instruction and updates the status flag as follows: State[V1]: none -> zero32.

[0071] Instruction 3 (fmov s2, w3) is a narrow write operation instruction used to write the lower 32 bits of register V2. The binary translator translates instruction 3 into the target architecture instruction and updates the status flag as follows: State[V2]: none -> zero32.

[0072] The fourth instruction (fadd s1, s0, s2) includes a read operation and a narrow write operation. Specifically, it reads the lower 32 bits of registers V0 and V2, and writes the lower 32 bits of register V1.

[0073] Since State[V0] = zero64 at this time, the read width (32 bits) of register V0 by this instruction is smaller than the effective bit width (64 bits). Therefore, it can be read directly without clearing or updating the status flag of register V0. Similarly, register V2 does not need to be cleared or updated.

[0074] Although the instruction includes a narrow write operation (writing to the lower 32 bits of register V1), since State[V1] = zero32 at this time, the status flag of register V1 does not need to be updated.

[0075] The binary translator translates instruction number 4 into the target architecture instruction, with the status flags as follows: State[V0]: zero64 remains unchanged; State[V2]: zero32 remains unchanged; State[V1]: zero32 -> zero32 (No need to update the state flag).

[0076] Instruction 5 (fadd s0, s0, s2) is a narrow write operation instruction used to perform a 32-bit narrow write operation on register V0. The binary translator translates instruction 5 into the target architecture instruction and updates the state flag as follows: State[V0]: zero64 -> zero32.

[0077] Instruction 6 (fadd d3, d0, d4) is a read operation instruction used to read the lower 64 bits of register V0. Since State[V0] = zero32 at this time, the read bit width (64 bits) is greater than the effective bit width (32 bits). Therefore, the binary translator translates instruction 6 into the target architecture instruction and inserts a clear instruction, such as EmitClear(V0, zero32), before the translation result of instruction 6 to clear the higher 96 bits of register V0; and updates the status flag as follows: State[V0] = none.

[0078] Instruction 7 (ldr q0, [x5]) is a full-width write operation, filling all 128 bits of register V0 at once. The binary translator translates instruction 7 into the target architecture instruction and updates the state flag as follows: State[V0]: none -> none. Since State[V0] was originally none, it doesn't need to be updated.

[0079] Instructions 8 (orr v6.16b, v0.16b, v7.16b) are read operation instructions used to read 128 bits of register V0. Since State[V0] = none, all 128 bits of register V0 are valid, and no clear instruction needs to be generated.

[0080] In Example 4, if the zeroing strategy used in traditional translation methods is adopted, zeroing instructions need to be generated after instructions 1, 2, 3, 4, and 5, requiring a total of 5 zeroing instructions. This embodiment of the invention only requires generating one zeroing instruction before the translation result of instruction 6, greatly reducing the number of target architecture instructions generated during translation, reducing target code bloat, reducing redundant operations, and improving the execution efficiency of the translation system.

[0081] In summary, this invention decouples the physical data modification of registers from the maintenance of their logical states, introducing a global register preset state table to record the boundaries (i.e., effective bit width) of the currently valid data in each register. During the translation of source architecture instructions, it dynamically intercepts high-bit clearing requests (narrow write operations) of registers and updates the preset state table. Based on the actual read and write behavior of subsequent instructions, it triggers physical clearing operations of registers as needed.

[0082] This invention transforms the frequent and scattered real-time physical zeroing operations in traditional zeroing strategies into extremely low-cost state maintenance operations within the translator. A large number of intermediate zeroing operations are merged, delayed, or completely discarded due to encountering full-width write operations, significantly reducing the number of zeroing instructions required and drastically lowering the instruction bloat rate.

[0083] Furthermore, the embodiments of the present invention provide finer-grained bit-width tracking capabilities, breaking through the limitations of traditional Boolean status words, and can perfectly support complex scalar, narrowed vector, and other data operations of different granularities (8 / 16 / 32 / 64 bits) in modern ARM architectures, with a wider optimization coverage.

[0084] Furthermore, the embodiments of the present invention can avoid a large number of redundant zeroing instructions, reduce the computational pressure on the ALU (Arithmetic Logic Unit) in the target hardware microarchitecture and the bottleneck of the instruction decoding front end, improve the overall execution frame rate of the dynamic binary translation system, and significantly improve the execution performance of the translation system.

[0085] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0086] Reference Figure 4 The diagram illustrates a structural block diagram of an embodiment of a binary translator according to the present invention, the binary translator comprising: The state update module 401 is used to update the state flag of the first register in a preset state table when a narrow write operation instruction is translated, based on the write bit width of the first register by the narrow write operation; the preset state table records the state flag of each register in the active architecture, and the state flag is used to indicate whether the high bit of the corresponding register needs to be cleared, and to record the effective bit width of the corresponding register. The status acquisition module 402 is used to obtain the status flag of the second register corresponding to the read operation from the preset status table when the read operation instruction is translated. The first processing module 403 is configured to insert a first clear instruction before the translation result of the read operation instruction if it is determined that the read bit width of the read operation is greater than the effective bit width indicated by the status flag of the second register; the first clear instruction is used to clear the specified high bits of the second register.

[0087] Optionally, the binary translator further includes: The state table traversal module is used to traverse the preset state table when translating to the control flow transfer point, and determine whether there are any registers to be cleared based on the state flags corresponding to each register. The position determination module is used to determine the target position based on the control flow transfer point if there is a register to be cleared; The second processing module is used to insert a second clear instruction at the target position; the second clear instruction is used to clear the specified high-order bits of the register to be cleared.

[0088] Optionally, the location determination module includes: The first determining submodule is used to determine the target location as before the translation result of the boundary instruction of the current code block if the control flow transfer is an active transfer; the boundary instruction includes a jump instruction, a function call instruction, or a function return instruction; or, The second determining submodule is used to determine the target location as after the translation result of the last normal instruction before the context saving instruction if the control flow transfer is a passive transfer. The passive transfer includes exception handling, interrupt response, or context switching.

[0089] Optionally, the binary translator further includes: An initialization module is used to perform an initialization operation on the preset state table, so as to set the state flags of all registers in the preset state table to the initial state; the initial state means that the high bits do not need to be cleared.

[0090] Optionally, the binary translator further includes: The state reset module is used to set the state flag of the third register corresponding to the full-width write operation in the preset state table to the initial state when the full-width write operation instruction is translated.

[0091] Optionally, the narrow write operation includes: writing to the S register or D register in scalar form, and writing to the vector register in a narrow vector form that is not 128 bits wide.

[0092] Optionally, the specified high bit refers to the remaining high bit portion in the register excluding the low bits occupied by valid data.

[0093] The binary translator in this embodiment maintains a mapping table (preset state table) for the hardware registers of the source architecture to indicate whether the high-order bits of each register in the source architecture need to be cleared, and records the effective bit width of each register. During dynamic translation, for consecutive narrow write operations, no clear instruction is inserted until a read operation instruction with a bit width greater than the effective bit width recorded in the preset state table is translated, at which point a clear instruction is inserted before the translation result of that read operation instruction. If no read operation instruction with a bit width greater than the effective bit width recorded in the preset state table is read, then no clear instruction is generated. Compared to traditional translators that generate clear instructions for every narrow write operation, this embodiment provides a fine-grained, high-order bit delayed clearing method based on multi-level bit width comparison, which postpones, merges, or even completely discards physical clearing operations as much as possible, thereby maximizing the simplification of the target machine code sequence generated by translation while ensuring semantic correctness, greatly reducing redundant operations, and improving the execution efficiency of the translation system.

[0094] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0095] Reference Figure 5 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Figure 5 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to perform the steps of the binary translation optimization method of the aforementioned embodiment.

[0096] This invention provides a non-transitory computer-readable storage medium that, when the instructions in the storage medium are executed by a terminal's program or processor, enables the terminal to perform the steps of the binary translation optimization method described in the foregoing embodiments. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0097] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0098] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0099] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0100] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0101] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0102] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A binary translation optimization method, characterized in that, The method includes: When translating a narrow write operation instruction, the status flag of the first register is updated in the preset status table according to the write bit width of the narrow write operation to the first register; the preset status table records the status flag of each register in the active architecture, and the status flag is used to indicate whether the high bit of the corresponding register needs to be cleared, and to record the effective bit width of the corresponding register; When translating a read operation instruction, the status flag of the second register corresponding to the read operation is obtained from the preset status table; If it is determined that the read bit width of the read operation is greater than the effective bit width indicated by the status flag of the second register, a first clear instruction is inserted before the translation result of the read operation instruction; the first clear instruction is used to clear the specified high bit of the second register.

2. The method according to claim 1, characterized in that, The method further includes: When translating to the control flow transfer point, the preset state table is traversed, and it is determined whether there are registers to be cleared based on the state flags corresponding to each register. If there are registers to be cleared, the target location is determined based on the control flow transfer point. Insert a second clear instruction at the target position; the second clear instruction is used to clear the specified high-order bits of the register to be cleared.

3. The method according to claim 2, characterized in that, Determining the target location based on the control flow transfer point includes: If the control flow transfer is an active transfer, the target location is determined to be before the translation result of the boundary instruction of the current code block; the boundary instruction includes a jump instruction, a function call instruction, or a function return instruction; or, If the control flow transfer is a passive transfer, then the target location is determined to be after the translation result of the last normal instruction before the context saving instruction. The passive transfer includes exception handling, interrupt response, or context switching.

4. The method according to claim 1, characterized in that, The method further includes: The preset state table is initialized to set the state flags of all registers in the preset state table to the initial state; the initial state means that the high bits do not need to be cleared.

5. The method according to claim 1, characterized in that, The method further includes: When translating a full-width write operation instruction, the status flag of the third register corresponding to the full-width write operation in the preset status table is set to the initial state.

6. The method according to any one of claims 1 to 5, characterized in that, The narrow write operation includes writing to the S register or D register in scalar form, and writing to the vector register in a narrow vector form that is not 128 bits wide.

7. The method according to any one of claims 1 to 5, characterized in that, The specified high bit refers to the remaining high bit portion of the register excluding the low bits occupied by valid data.

8. A binary translator, characterized in that, The binary translator includes: The state update module is used to update the state flag of the first register in the preset state table when a narrow write operation instruction is translated, based on the write bit width of the first register by the narrow write operation. The preset state table records the state flag of each register in the active architecture. The state flag is used to indicate whether the high bit of the corresponding register needs to be cleared and to record the effective bit width of the corresponding register. The status acquisition module is used to obtain the status flag of the second register corresponding to the read operation from the preset status table when a read operation instruction is translated. The first processing module is configured to insert a first clear instruction before the translation result of the read operation instruction if it is determined that the read bit width of the read operation is greater than the effective bit width indicated by the status flag of the second register; the first clear instruction is used to clear the specified high bits of the second register.

9. The binary translator according to claim 8, characterized in that, The binary translator also includes: The state table traversal module is used to traverse the preset state table when translating to the control flow transfer point, and determine whether there are any registers to be cleared based on the state flags corresponding to each register. The position determination module is used to determine the target position based on the control flow transfer point if there is a register to be cleared; The second processing module is used to insert a second clear instruction at the target position; the second clear instruction is used to clear the specified high-order bits of the register to be cleared.

10. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the steps of the binary translation optimization method as described in any one of claims 1 to 7.

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