Cache allocation method and electronic equipment

Abstract

The invention discloses a cache allocation method and electronic equipment, and relates to the technical field of cache management. For a current scene, the electronic equipment identifies threads and groups the threads into a key thread group and a non-key thread group, and periodically optimizes and adjusts cache upper limits corresponding to the key thread group and the non-key thread group on the basis of a memory stagnation condition generated when a CPU executes a memory access instruction in each period to obtain a target cache upper limit corresponding to each group. Therefore, the memory stagnation generated when the CPU executes the memory access instruction based on the target cache upper limit in the preset period is lower than the memory stagnation generated when other cache upper limits are used in the adjustment process. In this way, it is ensured that the cache resources are reasonably distributed in the key thread group and the non-key thread group, and therefore the overall power consumption of the electronic device is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of cache management technology, and in particular to a cache allocation method and an electronic device. Background Art

[0002] Cache refers to a memory that can exchange data at high speed. Its working principle is: when the CPU requests to read data, it first tries to find it from the cache (usually including multiple levels of cache structure). If the data exists in a certain level of cache, it is directly read and transmitted to the CPU. This process is called cache hit. If the data is not found in the cache (i.e. cache miss), the data is read from the relatively slower memory.

[0003] Cache allocation refers to allocating cache resources to different processor cores, threads or processes according to a certain mechanism or ratio. However, the traditional cache allocation method has the technical problem of unreasonable cache resource allocation leading to high power consumption. Summary of the invention

[0004] The embodiments of the present application provide a cache allocation method and an electronic device, which are used to solve the technical problem of high power consumption caused by unreasonable cache resource allocation.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions: In a first aspect, a cache allocation method is provided, the method comprising: Determine the first thread group and the second thread group divided for the current scene; the importance of the first thread in the first thread group in the current scene is higher than the importance of the second thread in the second thread group in the current scene. Based on the first information corresponding to each preset cycle, periodically optimize and adjust the cache upper limits corresponding to the first thread group and the second thread group, and obtain the first target cache upper limit corresponding to the first thread group and the second target cache upper limit corresponding to the second thread group. The first information corresponding to each cycle is used to characterize the memory stagnation caused by the CPU executing the memory access instruction within the cycle, and the first target cache upper limit is higher than the second target cache upper limit.

[0006] It should be understood that the first thread group is a critical thread group, the second thread group is a non-critical thread group, and the importance of the first thread in the critical thread group in the current scene is greater than the importance of the second thread in the non-critical thread group in the current scene. The first information is the memory stagnation generated when the CPU executes the memory access instruction in each cycle. Based on the first information, the cache upper limits corresponding to the critical thread group and the non-critical thread group are periodically optimized and adjusted to obtain the target cache upper limits corresponding to the critical thread group and the non-critical thread group. The target cache upper limit of the critical thread group is higher than the target cache upper limit of the non-critical thread group.

[0007] In the above cache allocation method, the memory stall caused by the CPU executing the memory access instruction based on the target cache upper limit within the preset cycle is lower than the memory stall caused by using other cache upper limits in the adjustment process. In this way, the reasonable allocation of cache resources in the critical thread group and the non-critical thread group is ensured, thereby reducing the overall power consumption of the electronic device.

[0008] In a possible implementation of the first aspect, the first information corresponding to each cycle is the weighted sum of the second information corresponding to the first thread group and the second thread group respectively in the cycle; the weight corresponding to the first thread group is greater than the weight corresponding to the second thread group; wherein the second information corresponding to each thread group in the first thread group and the second thread group represents a memory stagnation situation when the CPU executes memory access instructions of threads in the thread group within the cycle.

[0009] It should be understood that the second information corresponding to each thread group is the memory stall situation when the CPU executes the memory access instruction of the thread in the corresponding thread group in the cycle. The first information is the weighted sum of the second information corresponding to the critical thread group and the non-critical thread group in the cycle, and the weight corresponding to the critical thread group is greater than the weight corresponding to the non-critical thread group.

[0010] In the above cache allocation method, different weights are assigned to groups with different importance, so as to accurately characterize the importance of each group. On this basis, the optimization target can be the first information, which aims to minimize the memory stagnation caused by the periodic CPU executing the memory access instruction, thereby ensuring the reasonable allocation of cache resources and reducing the power consumption of the electronic device.

[0011] In another possible implementation of the first aspect, the second information corresponding to each thread group is the ratio of the first duration to the first total duration; the first duration represents the duration of memory stagnation caused by the CPU executing memory access instructions of each thread in the thread group during the period, and the first total duration represents the total duration taken by the CPU to execute instructions of each thread in the thread group during the period.

[0012] It should be understood that the first duration is the duration of memory stagnation generated when the CPU executes the memory access instructions of each thread in the thread group within the cycle, and the first total duration is the total duration occupied by the CPU executing the instructions of each thread in the thread group within the cycle. The second information is the ratio of the first duration to the first total duration. In the above cache allocation method, by collecting the first duration and the second duration and calculating the second information, an accurate evaluation of the memory access performance of the CPU executing the thread group is achieved, providing an accurate data basis for periodic optimization and adjustment of the cache upper limit of each group.

[0013] In another possible implementation of the first aspect, based on the first information corresponding to each preset cycle, periodically optimizing and adjusting the cache upper limit corresponding to the first thread group and the second thread group, includes: for each new cycle, optimizing and adjusting the cache upper limit corresponding to the first cycle of the first thread group or the second thread group when the first condition is met. The first condition includes that the first information corresponding to the first cycle is less than the first information corresponding to the second cycle, and / or the difference between the first information corresponding to the first cycle and the first information corresponding to the second cycle is less than or equal to a first threshold; the first threshold is a positive number; the first cycle is the previous cycle of the new cycle, and the second cycle is the previous cycle of the first cycle.

[0014] It should be understood that the first condition includes that the first information decreases, and / or the first information increases but the increase amplitude does not exceed the first threshold. Under the first condition, the cache upper limit corresponding to the first cycle is optimized and adjusted.

[0015] In the above cache allocation method, minimizing the first information is the optimization goal. When the first information decreases, it indicates that the overall memory stagnation phenomenon has been improved, and the current cache upper limit of each group is better. Adjustments are continued on the basis of the first cycle. When the first information increases but the increase does not exceed the first threshold, it indicates that the overall memory stagnation phenomenon has not been improved. However, considering that a small increase in the first information may be due to other realistic factors, adjustments can be continued on the basis of the first cycle. Under the first condition, continuing to adjust and optimize on the basis of the first cycle is conducive to more accurately finding the optimal cache allocation setting solution that minimizes the memory stagnation phenomenon.

[0016] In another possible implementation of the first aspect, optimizing and adjusting the cache upper limit corresponding to the first thread group or the second thread group in the first cycle includes: lowering the cache upper limit corresponding to the first target thread group in the first cycle, and / or raising the cache upper limit corresponding to the second target thread group in the first cycle. The third information corresponding to the first target thread group is less than the third information corresponding to the thread groups other than the first target thread group; the third information corresponding to the second target thread group is greater than the third information corresponding to the thread groups other than the second target thread group; and the third information corresponding to each of the first thread group and the second thread group is the product of the second information corresponding to the thread group and the weight corresponding to the thread group.

[0017] It should be understood that under the first condition, when optimizing and adjusting the cache upper limit corresponding to each thread group, the cache upper limit corresponding to the thread group with the smallest third information may be lowered, and / or the cache upper limit corresponding to the thread group with the largest third information may be raised. The third information is the product of the second information corresponding to the thread group and the weight corresponding to the thread group.

[0018] In the above cache allocation method, the third information comprehensively considers the importance of each group and the memory stagnation when the CPU executes the memory access instructions of the threads in the corresponding thread group within the cycle. By lowering the cache share upper limit of the group with the lowest third information, and / or raising the cache share upper limit of the group with the highest third information, dynamic reallocation of cache resources is achieved, and cache resource utilization is optimized, so that cache resources can more accurately match the actual needs of each group.

[0019] In another possible implementation of the first aspect, based on the first information corresponding to each preset cycle, periodically optimizing and adjusting the cache upper limits corresponding to the first thread group and the second thread group, further includes: for each new cycle, optimizing and adjusting the cache upper limit corresponding to the second cycle of the first thread group or the second thread group when the second condition is met. The second condition includes that the difference between the first information corresponding to the first cycle and the first information corresponding to the second cycle is greater than a first threshold value; and the first threshold value is a positive number.

[0020] It should be understood that the second condition includes that the first information increases, and the increase is greater than the first threshold. Under the first condition, the cache upper limit corresponding to the second cycle is optimized and adjusted. The second cycle is the previous cycle of the first cycle.

[0021] In the above cache allocation method, if the first information increases and the increase is greater than the first threshold, it indicates that the overall memory stagnation phenomenon has intensified, and the cache upper limit settings of each group in the first cycle are unreasonable. It is directly traced back to the second cycle, and a new round of adjustments are made based on the second cycle. Under the second condition, continuing to adjust and optimize based on the second cycle is conducive to more accurately finding the optimal cache allocation setting solution that minimizes the memory stagnation phenomenon.

[0022] In another possible implementation of the first aspect, optimizing and adjusting the cache upper limit corresponding to the first thread group or the second thread group in the second cycle includes: lowering the cache upper limit corresponding to the third target thread group in the second cycle, and / or raising the cache upper limit corresponding to the fourth target thread group in the second cycle. The third information corresponding to the third target thread group is less than the third information corresponding to the thread groups other than the third target thread group; the third information corresponding to the fourth target thread group is greater than the third information corresponding to the thread groups other than the fourth target thread group; and the third information corresponding to each of the first thread group and the second thread group is the product of the second information corresponding to the thread group and the weight corresponding to the thread group.

[0023] It should be understood that under the second condition, when optimizing and adjusting the cache upper limit corresponding to each thread group, the cache upper limit corresponding to the thread group with the smallest third information can be lowered, and / or the cache upper limit corresponding to the thread group with the largest third information can be raised. In this way, the cache resource utilization is optimized so that the cache resources can more accurately match the actual needs of each group.

[0024] In another possible implementation of the first aspect, based on the first information corresponding to each preset cycle, the cache upper limits corresponding to the first thread group and the second thread group are periodically optimized and adjusted to obtain the first target cache upper limit corresponding to the first thread group and the second target cache upper limit corresponding to the second thread group, including: based on the first information corresponding to each preset cycle, the cache upper limits corresponding to the first thread group and the second thread group are periodically optimized and adjusted, and the target cycle is determined in the process of periodic optimization and adjustment, and the cache upper limit corresponding to the first thread group in the target cycle is determined as the first target cache upper limit, and the cache upper limit corresponding to the second thread group in the target cycle is determined as the second target cache upper limit. Wherein, the first information corresponding to the target cycle is less than the first information corresponding to each of N consecutive cycles after the target cycle, and N is a positive integer.

[0025] It should be understood that the target period is determined during the periodic optimization and adjustment process, and the first information corresponding to the target period is less than the first information corresponding to each of N consecutive periods after the target period, where N is a positive integer. The cache upper limit corresponding to each group of the target period is used as the target cache upper limit of each group.

[0026] In the above cache allocation method, the first information of the target cycle is the smallest, and after N consecutive rounds of adjustment, the memory stagnation condition has not been substantially improved. The cache allocation setting scheme of the target cycle can be regarded as the optimal cache allocation setting scheme under the current conditions. The cache upper limit setting of the target cycle ensures the optimal allocation of cache resources in the critical thread group and the non-critical thread group, significantly reducing the overall power consumption of the electronic device.

[0027] In another possible implementation of the first aspect, after allocating a first target cache upper limit to the first thread group and allocating a second target cache upper limit to the second thread group, if the second information of any thread group changes by more than a second threshold for M consecutive cycles, the cache upper limit of each thread group is reset; M is an integer greater than or equal to 2.

[0028] It should be understood that after allocating the target cache upper limit for each group, the second information of each group is monitored. If the second information of any group changes in M ​​consecutive cycles and exceeds the second threshold, the cache upper limit of each thread group is reset. In the above cache allocation method, when the sub-scene changes, it will directly affect the memory access behavior of the thread, thereby causing the fluctuation of the second information. The second information is used as the basis for judging whether the sub-scene has changed, which has a high accuracy. After the sub-scene changes, the electronic device resets the cache upper limit of each group, and uses the method of the present application to dynamically adjust the cache upper limit of each group to ensure rapid adaptation to the demand for cache resources of the new sub-scene.

[0029] In another possible implementation manner of the first aspect, an adjustment granularity of the optimization adjustment is a preset unit granularity.

[0030] In the above cache allocation method, using unit granularity for adjustment can make the adjustment process faster and more efficient. Since the adjustment granularity is pre-set, the electronic device does not need to perform complex calculations or judgments when adjusting, but only needs to perform simple increase or decrease operations according to current needs and the preset unit granularity.

[0031] In another possible implementation of the first aspect, there are multiple first thread groups and multiple second thread groups, the multiple first thread groups include a logical thread group in a game scene and / or a rendering thread group in the game scene, and the multiple second thread groups include an auxiliary thread group and a non-game thread group in the game scene; wherein the auxiliary thread group includes auxiliary threads other than the logical thread group and the rendering thread group and related to the game scene, and the non-game thread group includes threads unrelated to the game scene.

[0032] In the above cache allocation method, since the game logic thread and the game rendering thread need to frequently access and call a large amount of game data during the processing process, they have an extremely high memory access ratio. If the game logic thread and the game rendering thread can improve the hit rate of memory access instructions in the cache, it can effectively reduce the memory stagnation caused by waiting for memory data. In the game scene, optimizing the game logic thread and the game rendering thread can significantly improve the performance of game drawing and effectively reduce power consumption.

[0033] In a second aspect, the present application provides an electronic device, comprising: one or more processors and a memory; the memory and the processor are coupled; the memory is used to store computer program code, the computer program code includes computer instructions, and when the computer instructions are executed by one or more processors, the electronic device executes the method described in the first aspect and any possible design method thereof.

[0034] In a third aspect, the present application provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed on an electronic device, the electronic device executes the method described in the first aspect and any possible design thereof.

[0035] In a fourth aspect, the present application provides a computer program product, which, when executed on a computer, enables the computer to execute the method described in the first aspect and any possible design thereof.

[0036] It can be understood that the beneficial effects that can be achieved by the electronic device described in the second aspect, the computer-readable storage medium described in the third aspect, and the computer program product described in the fourth aspect provided above can be referred to the beneficial effects in the first aspect and any possible design method thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application; Figure 2 A schematic diagram of a software architecture of an electronic device provided in an embodiment of the present application; Figure 3 A schematic diagram for comparing the running time of a game thread within a frame provided by an embodiment of the present application; Figure 4 A schematic diagram of a CPU data reading hierarchy structure provided in an embodiment of the present application; Figure 5 A schematic diagram of a software workflow of an electronic device in a game scenario provided by an embodiment of the present application; Figure 6 A schematic diagram of a cache allocation method provided in an embodiment of the present application; Figure 7 A schematic diagram of weighted sum calculation of memory stall rate provided in an embodiment of the present application; Figure 8 A schematic diagram of adjusting a cache allocation setting scheme provided in an embodiment of the present application Figure 1 ; Fig. 9 A schematic diagram of adjusting a cache allocation setting scheme provided in an embodiment of the present application Figure 2 ; Fig.10 A schematic diagram of adjusting a cache allocation setting scheme provided in an embodiment of the present application Figure 3 ; Fig.11 A schematic diagram of adjusting a cache allocation setting scheme provided in an embodiment of the present application Figure 4 ; Fig.12A schematic diagram of adjusting a cache allocation setting scheme provided in an embodiment of the present application Figure 5 ; Fig.13 A schematic diagram of adjusting a cache allocation setting scheme provided in an embodiment of the present application Figure 6 ; Fig.14 A schematic diagram of a sub-scene change provided in an embodiment of the present application; Fig.15 A schematic diagram of the structure of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "a", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0039] References to "one embodiment" or "some embodiments" etc. described in this specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The term "connection" includes direct connection and indirect connection, unless otherwise specified. "First" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0040] In the embodiments of the present application, the words "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0041] In some schemes, a support vector machine model is used to classify programs based on the degree of interference with other programs when occupying cache and the sensitivity of the program itself to the cache allocation size. After that, a Bayesian optimization algorithm is applied to schedule the resources of the last level cache (LLC) between program categories to search for a cache allocation scheme that maximizes system throughput.

[0042] In some schemes, cache demand is predicted by building a cache behavior prediction model. The model input parameters include the cache service state migration matrix and the initial cache state parameters, and the model output parameters include cache utilization, cache miss rate, and process conflict probability. Based on the model output parameters, a dynamic allocation scheme for shared cache in embedded real-time systems is formulated.

[0043] Both of the above solutions do not take into account the difference in importance of threads in the current scenario, which may lead to unreasonable allocation of cache resources, thereby increasing the overall power consumption of the electronic device.

[0044] In some schemes, cache space is evenly allocated to each thread based on a simple average allocation principle. This cache allocation method may result in insufficient cache resources for critical threads, while non-critical threads occupy too much cache space. When critical threads are performance-limited due to lack of cache resources, the system has to increase the CPU frequency to maintain the target performance level, which leads to a significant increase in power consumption.

[0045] In other schemes, excessive preference is given to critical threads. For example, too much cache space is always allocated to critical threads at a fixed allocation ratio, while the cache space of non-critical threads is compressed. This may cause the running time of these non-critical threads to increase significantly. Even if the CPU frequency remains unchanged, the power consumption will increase due to mutual interference and competition between threads.

[0046] To this end, an embodiment of the present application provides a cache allocation method, which is applied to an electronic device. For the current scenario, the electronic device identifies threads and groups them into critical thread groups and non-critical thread groups. Based on the memory stagnation generated when the CPU executes memory access instructions in each cycle, the cache upper limits corresponding to the critical thread groups and non-critical thread groups are periodically optimized and adjusted to obtain the target cache upper limit corresponding to each group (i.e., each thread group or thread group). In this way, the memory stagnation generated when the CPU executes memory access instructions based on the target cache upper limit within a preset cycle (i.e., the memory stagnation when the CPU executes during the entire cycle) is lower than the memory stagnation generated by other cache upper limits adjusted during the adjustment process. Moreover, the target cache upper limit corresponding to the critical thread group is greater than the target cache upper limit of the non-critical thread group. In this way, the reasonable allocation of cache resources in the critical thread group and the non-critical thread group is ensured, thereby reducing the overall power consumption of the electronic device.

[0047] The cache upper limit can also be called the cache share upper limit. The cache share upper limit refers to the maximum cache resource quota that each group can use in the cache space. For example, in a preset period, the cache share upper limit of the critical thread group A in the cache is 100%, and the cache share upper limit of the non-critical thread group B is 60%, which ensures that 40% of the cache is only used by the critical thread group A. In this way, in most cases, it is ensured that the critical thread group A obtains more cache resources than the non-critical thread group B.

[0048] By way of example, the above-mentioned electronic devices may specifically be mobile phones, tablet computers, televisions (also referred to as smart TVs, smart screens or large-screen devices), laptop computers, ultra-mobile personal computers (UMPCs), handheld computers, cameras (such as digital cameras), camcorders (such as digital video cameras), netbooks, personal digital assistants (PDAs), wearable electronic devices (for example: smart watches, smart bracelets, smart glasses), vehicle-mounted devices, virtual reality devices, and other electronic devices with cache management functions, and the embodiments of the present application do not impose any restrictions on this.

[0049] For ease of understanding, a mobile phone is taken as an example to illustrate the hardware structure and software system of the electronic device to which the method in the embodiment of the present application is applied.

[0050] Figure 1 A schematic diagram of the structure of a mobile phone is shown.

[0051] The mobile phone may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc.

[0052] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the mobile phone. In other embodiments of the present application, the mobile phone may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0053] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0054] The processor 110 can be used to read and execute computer-readable instructions. Optionally, the processor 110 can also include a controller, an arithmetic unit, and a register. Among them, the controller is mainly responsible for decoding instructions and issuing control signals for operations corresponding to the instructions. The arithmetic unit is mainly responsible for saving register operands and intermediate operation results temporarily stored during the execution of instructions. Registers are high-speed storage components with limited storage capacity, which can be used to temporarily store instructions, data, and addresses.

[0055] In a specific implementation, the hardware architecture of the processor 110 can be an application specific integrated circuit (ASIC) architecture, a microprocessor without interlocked piped stages (MIPS) architecture, an ARM (advanced RISC machines) architecture, or a network processor (NP) architecture, etc.

[0056] In some embodiments, the mobile phone may execute the cache allocation method through the processor 110 to ensure the reasonable allocation of cache resources among the critical thread groups and the non-critical thread groups.

[0057] The internal memory 121 can be used to store computer executable program codes, which include instructions. The processor 110 executes various functional applications and data processing of the electronic device 100 by running the instructions stored in the internal memory 121. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0058] The internal memory 121 is provided with a cache for storing instructions and data. In some embodiments, the cache is a high-speed cache memory. The cache can save instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it can be directly called from the cache. Repeated access is avoided, the waiting time of the processor 110 is reduced, and the efficiency of the system is improved. The method in the embodiment of the present application is intended to allocate a reasonable cache upper limit to the thread, so that the cache can be used reasonably and the performance is improved.

[0059] The wireless communication function of the mobile phone can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor.

[0060] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied on mobile phones. In some embodiments, at least some functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 150 can be set in the same device as at least some modules of the processor 110.

[0061] The wireless communication module 160 can provide wireless communication solutions for use on mobile phones, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication technology (NFC), infrared technology (IR), etc.

[0062] The mobile phone can realize audio functions such as music playing and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the earphone interface 170D, and the application processor.

[0063] The key 190 includes a power button, a volume button, etc. The key 190 can be a mechanical key or a touch key. The mobile phone can receive key input and generate key signal input related to the user settings and function control of the mobile phone.

[0064] Motor 191 can generate vibration prompts. Motor 191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback.

[0065] Indicator 192 may be an indicator light, which may be used to indicate charging status, power changes, messages, missed calls, notifications, etc.

[0066] The camera 193 is a physical camera that actually exists. In some embodiments of the present application, the camera 193 of the mobile phone can be multiple, for example, the multiple cameras 193 can include a front camera and a rear camera. The front camera can be one or more, and the rear camera can also be one or more.

[0067] The mobile phone can realize the shooting function through the ISP, the camera 193, the video codec, the GPU, the display screen 194 and the application processor, etc. For example, the application in the mobile phone can access the camera 193 and control the camera 193 to collect images.

[0068] The mobile phone implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0069] Display screen 194 is used to display images, videos, etc.

[0070] The SIM card interface 195 is used to connect a SIM card. The SIM card can be connected to or disconnected from the mobile phone by inserting the SIM card interface 195 or pulling the SIM card out of the SIM card interface 195.

[0071] The software system of the mobile phone can adopt a layered architecture, an event-driven architecture, a micro-kernel architecture, a micro-service architecture, or a cloud architecture. The embodiment of the present invention takes a software system of a layered architecture as an example to exemplify the software structure of the mobile phone.

[0072] Figure 2 It is a software structure block diagram of the mobile phone according to an embodiment of the present invention.

[0073] The layered architecture of the electronic device divides the software into several layers, each with clear roles and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the electronic device may include, for example, an application layer, an application framework layer, a hardware abstraction layer (HAL layer), and a kernel layer. Exemplarily, the application layer may include a series of applications.

[0074] The application layer can include a series of application packages.

[0075] like Figure 2 As shown, the application package may include applications such as camera, call, music, video, game, etc.

[0076] In some other embodiments, the above application package may also include Figure 2 Modules not shown in the figure, such as gallery, calendar, map, navigation, WLAN, Bluetooth and other applications.

[0077] The application framework layer provides an application programming interface (API) and a programming framework for the applications in the application layer. The application framework layer includes some predefined functions.

[0078] like Figure 2As shown, the application framework layer may include game services, content providers, view systems, telephony managers, resource managers, and the like.

[0079] The game service is used to manage the life cycle of the game application, including game start, pause, resume, and stop operations. It coordinates various resources and logic within the game to ensure the smooth operation of the game.

[0080] Content providers are used to store and retrieve data and make it accessible to applications. The data may include videos, images, audio, calls made and received, browsing history and bookmarks, phone books, etc.

[0081] The view system includes visual controls, such as controls for displaying text, controls for displaying images, etc. The view system can be used to build applications. A display interface can be composed of one or more views. For example, a display interface including a text notification icon can include a view for displaying text and a view for displaying images.

[0082] The phone manager is used to provide the communication functions of the mobile phone, such as the management of call status (including answering, hanging up, etc.).

[0083] The resource manager provides various resources for applications, such as localized strings, icons, images, layout files, video files, and so on.

[0084] In other embodiments, the application framework layer may also include Figure 2 Modules not shown in the figure, such as the window manager and notification manager.

[0085] The window manager is used to manage window programs. The window manager can obtain the display screen size, determine whether there is a status bar, lock the screen, capture the screen, etc.

[0086] The notification manager enables applications to display notification information in the status bar. It can be used to convey notification-type messages and can disappear automatically after a short stay without user interaction. For example, the notification manager is used to notify download completion, message reminders, etc. The notification manager can also be a notification that appears in the system top status bar in the form of a chart or scroll bar text, such as notifications of applications running in the background, or a notification that appears on the screen in the form of a dialog window. For example, a text message is displayed in the status bar, a prompt sound is emitted, an electronic device vibrates, an indicator light flashes, etc.

[0087] For example, the hardware abstraction layer (HAL layer) can encapsulate the driver in the kernel layer and provide a calling interface to the application framework layer, shielding the implementation details of the low-level hardware.

[0088] like Figure 2 As shown, the hardware abstraction layer of the electronic device includes at least an identification grouping module and a partitioning calculation module. The identification grouping module is used to identify each thread and group each thread according to the importance of each thread to the target scene. The partitioning calculation module is used to calculate the corresponding cache share upper limit of each group in the cache in the next cycle.

[0089] The kernel layer is the layer between hardware and software. The kernel layer contains at least a data collector and a cache share setting module. The data collector is used to collect target information of each group. The target information of the group represents the memory stagnation caused by the CPU executing the memory access instruction when the thread of the corresponding group is running during the cycle. The cache share setting module is used to set the upper limit of the cache share corresponding to each group in the cache according to the calculation results of the partition calculation module.

[0090] It should be understood that the cache allocation method in the embodiment of the present application can be applied to a variety of stable and continuous scenarios, including but not limited to game scenarios, video playback scenarios, music playback scenarios, and video recording scenarios. In the following, the cache allocation method is introduced by taking the game scenario as an example. The cache allocation methods of other scenarios refer to the game scenario and will not be described one by one.

[0091] In the game scene, the drawing of game frames refers to the process in which the game engine converts the virtual game world into a visible picture on the electronic device screen in real time when the electronic device is running the game. For the drawing of each frame, the game logic thread first calculates the content to be displayed on the screen, and the game rendering thread performs the graphics rendering task based on the calculation results of the game logic thread to generate the final picture. In addition, there may be other auxiliary threads to coordinate the drawing of game frames.

[0092] Figure 3 The figure shows the running time comparison of the game thread in one frame, where the first function refers to the function called during the execution of the game rendering thread. There may be multiple first functions. Figure 3 In the figure, only two different first functions are shown with different patterns for simple illustration. Figure 3 It can be seen that the running time of the game logic thread and the game rendering thread is significantly longer than that of the game auxiliary thread. In other words, the total time of drawing a game frame depends largely on the running time of the game logic thread and the game rendering thread.

[0093] After in-depth research and analysis, the inventor of this application found that since the game logic thread and the game rendering thread need to frequently access and call a large amount of game data during the processing process, they have an extremely high memory access ratio, that is, the proportion of memory access to these two threads when they are running is extremely high. The high memory access requirements of the game logic thread and the game rendering thread cause memory access latency to become an important factor affecting the running time of these two threads.

[0094] For ease of understanding, refer to Figure 4 The hierarchical structure of the CPU when requesting to read data in one embodiment shown. When the CPU initiates a data read request, it will first search in the first-level cache (L1 Cache). If the required data is not found in the first-level cache, it will continue to initiate a search request to the second-level cache (L2 Cache). If the second-level cache also misses the target data, it will further search in the third-level cache (L3 Cache). If the data is still not found in the third-level cache (i.e., a cache miss occurs), the required data will eventually be read from the main memory.

[0095] Since the game logic thread and the game rendering thread need to call a large amount of game data, they will frequently initiate data read requests. If these requests frequently read data from the main memory instead of hitting the cache with a faster access speed, it will cause the so-called "cache stall" phenomenon. Cache stall increases the latency of data access, which in turn affects the running time of these two threads. Therefore, if the game logic thread and the game rendering thread can improve the hit rate of memory access instructions in the cache, it can effectively reduce the memory stall caused by waiting for memory data, thereby increasing the number of instructions per cycle (ipc), and ultimately shortening the execution time of the thread.

[0096] Based on this, in the game scene, optimizing the game logic thread and the game rendering thread can significantly improve the performance of game drawing and effectively reduce power consumption.

[0097] For example, in a game scene, the electronic device can divide the threads into four groups according to their importance to the game scene, namely, the game logic thread group, the game rendering thread group, the game auxiliary thread group, and the non-game thread group. Among them, the game logic thread group and the game rendering thread group belong to the key thread group, and the game auxiliary thread group and the non-game thread group belong to the non-key thread group. The grouping method of game threads is not limited to four groups, and the specific number of groups can be flexibly adjusted according to actual needs, and is not limited here.

[0098] In some embodiments, after the game is started, the electronic device identifies each thread and groups each thread. Specifically, the electronic device can identify the game thread and the non-game thread according to the process number. The game thread includes a game logic thread, a game rendering thread, and a game auxiliary thread. In the game thread, the electronic device further identifies the game logic thread and marks it as a game logic thread group; identifies the game rendering thread and marks it as a game rendering thread group; identifies the game auxiliary thread and marks it as a game auxiliary thread group. The electronic device marks the non-game thread as a non-game thread group.

[0099] Based on the memory stalls generated when the CPU executes memory access instructions in each cycle, the electronic device periodically optimizes and adjusts the cache limits corresponding to the game logic thread group, game rendering thread group, game auxiliary thread group, and non-game thread group to obtain the corresponding target cache limits of the above four groups. In this way, the memory stalls generated when the CPU executes memory access instructions based on the target cache limit in a preset cycle are lower than the memory stalls generated by other cache limits during the adjustment process. Please refer to Figure 5 , combined with the game scenario, the workflow of the mobile phone software is illustrated, which specifically includes the following steps: (1) Start the game application at the application layer.

[0100] (2) The game application passes status information to the game service in the application framework layer.

[0101] This status information is used to indicate that the game application is started.

[0102] (3) The game service passes status information to the game scheduler in the hardware abstraction layer.

[0103] In an embodiment of the present application, the identification grouping module and the division calculation module are set in the game scheduler. In other embodiments, they can also be set in other modules, which is not limited here.

[0104] (4) After the game scheduler's identification and grouping module groups each thread, it sends the grouping results to the data collector at the kernel layer.

[0105] Exemplarily, the identification and grouping module may start to identify each thread after the game application is started, and group each thread according to the importance of each thread to the game scene.

[0106] (5) The data collector collects the memory stall situation (i.e., target information) generated when the CPU executes memory access instructions when each group thread is running in this cycle.

[0107] (6) The data collector sends the target information of each group to the game scheduler.

[0108] (7) The partition calculation module of the game scheduler sends the cache allocation setting plan for the next cycle to the cache share setting module of the kernel layer.

[0109] Specifically, the partitioning calculation module can calculate the cache allocation setting plan for the next cycle (that is, the cache share upper limit corresponding to each group in the cache) according to the target information of each group, and send the cache allocation setting plan for the next cycle to the cache share setting module of the kernel layer. For example, the cache allocation setting plan can be expressed as configuration information such as <group number, cache share upper limit>.

[0110] Furthermore, the cache share setting module may set the upper limit of the cache share corresponding to each group in the cache based on the cache allocation setting scheme.

[0111] In some embodiments, the cache share setting module may set the upper limit of the cache share corresponding to each group in the last level cache (Last Level Cache, LLC) according to the above cache allocation setting scheme.

[0112] It should be understood that Figure 4 In the illustrated embodiment, the third-level cache (L3 Cache) is LLC. In other embodiments, the cache only includes the first-level cache (L1 Cache) and the second-level cache (L2 Cache). In this case, the second-level cache (L2 Cache) is the last-level cache (LLC), and the LLC in other embodiments is understood in the same way.

[0113] For ease of understanding, the cache allocation method of the embodiment of the present application is described in detail in the following embodiment.

[0114] In some embodiments, Figure 6 As shown, the electronic device determines the first thread group and the second thread group divided for the current scene, and the first thread group is more important than the second thread group in the current scene. The first thread group is a critical thread group, and the second thread group is a non-critical thread group.

[0115] Based on the first information corresponding to each preset cycle, the cache upper limits corresponding to the first thread group and the second thread group are periodically optimized and adjusted. The first information is used to characterize the memory stagnation caused by the CPU executing the memory access instruction in the cycle. Figure 6 In the example, the cache limit of the first thread group in cycle n is recorded as a n , the cache limit of the second thread group in cycle n is recorded as b n For example, the cache limit from the first thread group in cycle 1 is recorded as a1, and the cache limit from the second thread group in cycle 1 is recorded as b1. After the cache limits of the first thread group and the second thread group are optimized and adjusted for multiple cycles, the first target cache limit a corresponding to the first thread group is obtained. n+1 The second target cache upper limit b corresponding to the second thread group n+1 Thus, the memory stall generated when the CPU executes the memory access instruction based on the target cache upper limit within the preset cycle is lower than the memory stall generated by using other cache upper limits of the adjustment process.

[0116] In some embodiments, the optimization target may be the first information, aiming to minimize the first information, that is, to minimize the overall memory stall generated when the CPU executes memory access instructions of all threads, thereby ensuring the reasonable allocation of cache resources and reducing the power consumption of the electronic device.

[0117] Specifically, the thread grouping depends on the importance of each thread to the target scenario. The grouping result includes at least one critical thread group and one non-critical thread group.

[0118] For example, in a game scenario, the game logic thread and the game rendering thread are key threads, and the game auxiliary thread and the non-game thread are non-key threads. In this way, in a game scenario, the threads can be divided into four groups: the game logic thread group, the game rendering thread group, the game auxiliary thread group, and the non-game thread group.

[0119] For another example, in a video playback scenario, the importance of threads varies. The video playback rendering thread is an important thread, while the video playback auxiliary thread and the non-video playback thread are non-critical threads. In this way, the threads can be divided into three groups: the video playback rendering thread group, the video playback auxiliary thread group, and the non-video playback thread group. Alternatively, the threads can be divided into two groups: the video playback rendering thread group and the non-critical thread group, where the non-critical thread group includes all threads except the video playback rendering thread.

[0120] The electronic device may calculate the second information corresponding to each group according to the target information of each group. For example, the second information may be a ratio of the first duration to the first total duration. Furthermore, for each period, the electronic device may perform a weighted summation of the second information corresponding to each group in the period to obtain the first information corresponding to the period.

[0121] Specifically, within a preset period, the electronic device collects target information of each group, and the target information may include a first duration and a first total duration. The first duration represents the duration of memory stagnation generated when the CPU executes memory access instructions of each thread in the group within the period, and the first total duration represents the total duration occupied by the CPU when executing instructions of each thread in the group within the period.

[0122] Exemplarily, the first duration may be a memory stall cycle of each group, and the first total duration may be a total instruction cycle.

[0123] A memory stall cycle refers to the number of clock cycles that the CPU is idle while waiting for memory operations (such as data reading) when executing instructions. Total instruction cycles refer to the total number of clock cycles occupied by all instructions executed by the CPU within a preset cycle. Here, "clock cycle" refers to the unit time required for the CPU to perform a basic operation. Exemplarily, for each preset cycle, the target information of each group can be collected through the Performance Monitoring Unit (PMU). PMU is essentially a counter that can be used to collect the memory stall cycle and total cycles of each group.

[0124] In some embodiments of the present application, in each cycle, memory stall cycle and total cycles are collected in groups to obtain the memory stall cycle and total cycles of each group. Specifically, when the thread switches, first check whether the threads before and after the switch (for example, thread A switches to thread B) belong to the same group. If they belong to the same group, the PMU continues to count. If thread B and thread A belong to different groups, the electronic device reads the PMU data, that is, records the memory stall cycle and total cycles of the group where thread A is located in the previous time slice. After that, the PMU is reset and starts counting for the group where thread B is located.

[0125] In a preset cycle, for any group, the memory stall cycle of different time slices is added to get the memory stall cycle of this group, and the total cycles of different time slices is added to get the total cycles of this group. Thus, the memory stall cycle and total cycles of each group are obtained. After a preset cycle ends, the data collected in this preset cycle is read and cleared, and the counting starts again in the next preset cycle.

[0126] In some embodiments, the electronic device may assign different weights to different groups, thereby accurately representing the importance of each group. Furthermore, for each cycle, the electronic device may perform weighted summation of the second information corresponding to each group in the cycle to obtain the first information corresponding to the cycle. The second information corresponding to each group represents the memory stagnation when the CPU executes the memory access instruction of the thread in the thread group in the cycle. For example, the second information may be the ratio of the first duration to the first total duration.

[0127] Specifically, the electronic device may multiply the second information corresponding to each thread group in the cycle by the weight of the thread group to obtain the third information of each thread group. Furthermore, the electronic device may add the third information of each thread group to obtain the first information corresponding to the cycle.

[0128] In some embodiments, for any cycle and any thread group, the first duration is a memory stall cycle, the first total duration is a total instruction cycle, the second information is a ratio of a memory stall cycle to total cycles (i.e., a memory stall rate), and the third information is a product of a memory stall rate and a weight of a corresponding thread group (i.e., a weighted memory stall rate). The electronic device sums the third information of each group to obtain the first information (i.e., a weighted sum of memory stall rates).

[0129] On this basis, the optimization target can be the weighted sum of memory stall rates, aiming to minimize the sum of weighted memory stall rates of each group, thereby ensuring the reasonable allocation of cache resources and reducing the power consumption of electronic devices.

[0130] For the same preset cycle, the weighted memory stall rates of each group are added together to obtain the weighted sum of the memory stall rates of the corresponding preset cycle. For any group, the weighted memory stall rate may be the product of the memory stall rate and the corresponding group weight coefficient; the memory stall rate may be calculated based on the memory stall cycle and total cycles, for example, the memory stall rate may be memory stall cycle / total cycles.

[0131] For example, Figure 7 As shown in the figure, for the target scenario, the threads are divided into 4 groups, namely group 1 to group 4. The corresponding weight coefficients are set according to the importance of the threads in the group. The weight coefficients of group 1 to group 4 are weight coefficient a, weight coefficient b, weight coefficient c and weight coefficient d respectively. Within a preset period, for any group, the electronic device calculates the memory stall rate of this group based on the collected memory stall cycle and total cycles. The memory stall rate of this group is multiplied by the corresponding weight coefficient to obtain the weighted memory stall rate of this group. The weighted memory stall rates of each group are added together to obtain the weighted sum of the memory stall rates.

[0132] The electronic device can dynamically adjust the cache allocation setting scheme based on a preset period to ensure reasonable and timely optimization of cache resources.

[0133] For the current preset cycle, the electronic device calculates the memory stall rate, the weighted memory stall rate, and the weighted sum of the memory stall rates of each group. For the next preset cycle, the electronic device can adjust the cache allocation setting scheme according to the weighted memory stall rate of each group and the weighted sum of the memory stall rates. For example, the cache share upper limit of the group with the lowest weighted stall rate can be lowered, and / or the cache share upper limit of the group with the highest weighted stall rate can be raised.

[0134] By lowering the upper limit of the cache share of the group with the lowest weighted memory stall rate, and / or raising the upper limit of the cache share of the group with the highest weighted memory stall rate, dynamic reallocation of cache resources is achieved, and cache resource utilization is optimized, so that cache resources can more accurately match the actual needs of each group.

[0135] Each time the electronic device lowers or raises the upper limit of the cache share, it can be adjusted according to the pre-set unit granularity. The unit granularity can be set according to demand. For example, if a more detailed cache resource allocation adjustment is sought, the unit granularity can be set to a smaller value, such as 2% or 5%; if the simplicity of adjustment operation and reduction of adjustment frequency are sought, the unit granularity can be set to a larger value, such as 10% or 15%.

[0136] Using unit granularity for adjustment can make the adjustment process faster and more efficient. Since the adjustment granularity is pre-set, the electronic device does not need to perform complex calculations or judgments when adjusting, but only needs to perform simple increase or decrease operations based on current needs and the preset unit granularity.

[0137] Figure 8 and Fig. 9 Two adjustment methods for cache allocation setting schemes are shown.

[0138] Figure 8 and Fig. 9 In the embodiment, in cycle 1, the upper limits of the cache shares of groups 1 to 4 are A, B, C and D respectively. For cycle 1, the electronic device calculates the weighted memory stall rates of groups 1 to 4. Assuming that the weighted memory stall rate of group 1 is the highest and the weighted memory stall rate of group 4 is the lowest, it indicates that the cache resources of group 1 are less than those of other groups, or the cache resources of group 4 are more than those of other groups.

[0139] In some embodiments, Figure 8 As shown, the electronic device can reduce the upper limit of the cache share of group 4 in the next preset cycle (ie, cycle 2). For example, the adjusted upper limit of the cache share of group 4 is D-10%.

[0140] In other embodiments, Fig. 9 As shown, the electronic device can increase the upper limit of the cache share of group 1 in cycle 2. For example, the adjusted upper limit of the cache share of group 1 is A+5%.

[0141] The electronic device calculates the difference in the weighted sum of memory stall rates between two preset cycles, and adjusts the upper limit of the cache share of each group in the next preset cycle according to the above difference. Taking the weighted sum of memory stall rates as the optimization target, the memory access efficiency of each group is comprehensively considered, and the allocation of cache resources is dynamically optimized through continuous monitoring of multiple cycles, which greatly improves the overall memory stall phenomenon.

[0142] If the weighted sum of memory stagnation rates decreases, it means that the overall memory stagnation phenomenon has been improved, and the current cache allocation setting scheme is better. The electronic device can continue to adjust based on the current cache allocation setting scheme. That is, lower the upper limit of the cache share of the group with the lowest current weighted memory stagnation rate, and / or increase the upper limit of the cache share of the group with the highest current weighted memory stagnation rate. If the weighted sum of memory stagnation rates increases, but the increase does not exceed the preset first threshold, it means that the overall memory stagnation phenomenon has not been improved. In some embodiments, considering that a small increase in memory stagnation rate may be due to instantaneous load changes, in order to avoid system instability caused by excessive adjustment, the electronic device continues to adjust based on the current cache allocation setting scheme. That is, based on the current cache allocation setting scheme, lower the upper limit of the cache share of the group with the lowest current weighted memory stagnation rate, and / or increase the upper limit of the cache share of the group with the highest current weighted memory stagnation rate.

[0143] In other embodiments, when the weighted sum of memory stall rates increases but the increase does not exceed a preset first threshold, the electronic device may also choose to go back to the previous cache allocation setting scheme and perform a new round of adjustments based on this.

[0144] If the weighted sum of memory stagnation rates increases, and the increase is greater than the preset first threshold, it means that the overall memory stagnation phenomenon has intensified, and the current cache allocation setting plan is significantly unreasonable. The electronic device directly goes back to the previous cache allocation setting plan and makes a new round of adjustments on this basis.

[0145] When the electronic device goes back to the previous cache allocation setting scheme and performs a new round of adjustments on the previous cache allocation setting scheme, in order to avoid returning to the current unreasonable cache allocation setting scheme during the adjustment process, the electronic device may change the adjustment method, such as changing the adjustment granularity or the adjustment object, in the new round of adjustments.

[0146] In some embodiments, a target period is determined during the periodic optimization and adjustment process, and the target period is the period with the minimum weighted sum of historical memory stall rates. The weighted sum of memory stall rates corresponding to each of N consecutive periods (N is a preset positive integer) after the target period is not less than the weighted sum of memory stall rates corresponding to the target period, which means that despite the gradual adjustment of N periods, the memory stall condition has not been substantially improved.

[0147] In this case, given that the weighted sum of the memory stall rate corresponding to the cache allocation setting scheme of the target cycle is at the lowest level, the scheme is considered to be the optimal configuration scheme under the current operating conditions. Therefore, the electronic device adopts the cache allocation setting scheme corresponding to the target cycle, that is, the target cache upper limit of each group is set to the cache upper limit of each group in the target cycle, so as to reduce the overall power consumption of the electronic device.

[0148] After allocating the target cache limit to each group, if the memory stall rate of any group changes by more than the preset second threshold for M consecutive cycles (M is a preset integer greater than or equal to 2), it is considered that the sub-scenario has changed. It should be understood that the cycle cannot be too short, and it is necessary to ensure that the memory stall rate of each group is basically stable when the sub-scenario remains unchanged.

[0149] Among them, the sub-scene refers to a smaller scene that can be further subdivided according to the specific activity content, environmental characteristics or behavior patterns in the target scene. For example, the game scene includes sub-scenes such as free movement sub-scenes, material picking sub-scenes and fighting sub-scenes. After the sub-scene changes, the electronic device can reset the cache upper limit of each group, and then use the method of the above embodiment to dynamically adjust the cache upper limit of each group. The memory stall rate of each group is an important indicator reflecting the memory access efficiency of the thread. When the sub-scene changes, it will directly affect the memory access behavior of the thread, and then cause the fluctuation of the memory stall rate. Using the memory stall rate as a basis for judging whether the sub-scene has changed has a high accuracy. After the sub-scene changes, the cache upper limit of each group is reset, and the cache upper limit of each group is dynamically adjusted using the method of the present application to ensure rapid adaptation to the demand for cache resources in the new sub-scene.

[0150] For ease of understanding, the following embodiments introduce a method for adjusting the upper limit of the cache share of the present application.

[0151] In some embodiments, Figures 10 to 12 As shown, in cycle 1, the upper limits of the cache shares of groups 1 to 4 are A, B, C and D respectively, and in the next preset cycle (i.e., cycle 2), the upper limits of the cache shares of groups 1 to 4 are A+5%, B, C and D respectively.

[0152] In some embodiments, Fig.10 As shown, the difference in the weighted sum of memory stall rates between two consecutive cycles is counted. If the weighted sum 1 of the memory stall rate in cycle 1 is greater than the weighted sum 2 of the memory stall rate in cycle 2, that is, the weighted sum of the memory stall rate decreases, the cache allocation setting scheme of cycle 2 is better. For the next cycle (i.e., cycle 3), the electronic device continues to adjust the upper limit of the cache share of each group based on the cache allocation setting scheme of cycle 2. Exemplarily, in cycle 3, the upper limits of the cache shares of groups 1 to 4 are A+5%+5% (i.e., A+10%), B, C, and D, respectively.

[0153] In some embodiments, Fig.11 As shown, the difference in the weighted sum of memory stall rates between two consecutive cycles is counted. If the weighted sum 1 of the memory stall rate in cycle 1 is less than the weighted sum 2 of the memory stall rate in cycle 2, that is, the weighted sum of the memory stall rate increases, and the increase is greater than the first threshold, it means that the current cache allocation setting scheme is unreasonable. Then, for the next preset cycle (i.e., preset cycle 3), the electronic device uses the preset cache allocation setting scheme of cycle 1, that is, in cycle 3, the cache upper limits of groups 1 to 4 are reset to A, B, C, and D, respectively.

[0154] like Fig.11 As shown, for cycle 4, in order to avoid returning to the unreasonable cache allocation setting scheme of cycle 2 during the adjustment process, the electronic device can change the adjustment method in the new round of adjustment. For example, the electronic device can change the adjustment method of "raising the upper limit of the cache share of the group with the highest weighted stagnation rate" to "lowering the upper limit of the cache share of the group with the lowest weighted stagnation rate". In this way, in cycle 4, the cache upper limits of groups 1 to 4 are A, B, C and D-5% respectively. For another example, the electronic device can reduce the adjustment granularity. For example, the adjustment method of "raising the upper limit of the cache share of the group with the highest weighted stagnation rate with a granularity of 5%" can be changed to "raising the upper limit of the cache share of the group with the highest weighted stagnation rate with a granularity of 3%".

[0155] In some embodiments, Fig.12As shown, the electronic device can count the difference in the weighted sum of memory stall rates between two consecutive preset cycles. If the weighted sum 1 of the memory stall rate of the preset cycle 1 is less than or equal to the weighted sum 2 of the memory stall rate of the preset cycle 2, and the increase is less than or equal to the first threshold (that is, the weighted sum of the memory stall rate increases, and the increase is less than or equal to the first threshold), then for the next preset cycle (that is, the preset cycle 3), the electronic device can continue to make adjustments based on the cache allocation setting scheme of cycle 2. For example, in cycle 3, the upper limits of the cache shares of groups 1 to 4 are A+5%+5% (that is, A+10%), B, C and D respectively. In some embodiments, the target cycle is determined in the process of periodic optimization and adjustment, and the cache upper limit corresponding to each group in the target cycle is determined as the target cache upper limit of each group.

[0156] like Fig.13 As shown, in cycle Y, the upper limits of cache shares of groups 1 to 4 are A, B, C and D respectively; in cycle Y+1, the upper limits of cache shares of groups 1 to 4 are A+5%, B, C and D respectively. Compared with the cycles before cycle Y, the weighted sum of memory stall rates in cycle Y is the smallest. Assuming that the weighted sum of memory stall rates corresponding to cycle Y is y, the weighted sum of memory stall rates corresponding to each cycle thereafter is continuously recorded, and the weighted sum of memory stall rates corresponding to cycle Y+1 is y+1, and so on, the weighted sum of memory stall rates corresponding to cycle Y+N (N is a preset positive integer) is y+n, and if y+1 to y+n are not less than y, cycle Y is the target cycle. In cycles Y+N+1 and thereafter, the electronic device sets the target cache upper limit of each group to the cache upper limit corresponding to each group in cycle Y. That is, the upper limits of cache shares of groups 1 to 4 are A, B, C and D respectively.

[0157] After allocating a target cache limit for each group, the electronic device can record the memory stall rate of each group. Fig.14 As shown, assuming that in cycle 8, the electronic device allocates a target cache upper limit for groups 1 to 4, then for subsequent cycles, the memory stall rate is continuously observed for groups 1 to 4. In cycle a, the memory stall rate of group b is recorded as memory stall rate ab. For example, in cycle 8, the memory stall rate of group 1 is recorded as memory stall rate 8-1.

[0158] If the memory stall rate of any group changes for a plurality of M consecutive cycles and exceeds the second threshold, for example, Fig.14As shown, if the difference in memory stall rate of group 4 for three consecutive cycles exceeds the second threshold, it is considered that the sub-scenario has changed. The electronic device resets the cache share upper limit of each group in cycle 12, and dynamically adjusts the cache upper limit of each group according to the method of the present application.

[0159] An embodiment of the present application also provides an electronic device, which may include: one or more processors and a memory; the memory and the processor are coupled; the memory is used to store computer program code, the computer program code includes computer instructions, and when the computer instructions are executed by one or more processors, the electronic device can perform the various functions or steps performed in the above method embodiment.

[0160] The present application also provides a chip system, such as Fig.15 As shown, the chip system 1500 includes at least one processor 1501 and at least one interface circuit 1502. The processor 1501 and the interface circuit 1502 can be interconnected through lines. For example, the interface circuit 1502 can be used to receive signals from other devices (such as a memory of an electronic device). For another example, the interface circuit 1502 can be used to send signals to other devices (such as the processor 1501). Exemplarily, the interface circuit 1502 can read the instructions stored in the memory and send the instructions to the processor 1501. When the instruction is executed by the processor 1501, the electronic device can execute the various steps in the above embodiments. Of course, the chip system can also include other discrete devices, which are not specifically limited in the embodiments of the present application.

[0161] An embodiment of the present application further provides a computer storage medium, which includes computer instructions. When the computer instructions are executed on the above electronic device, the electronic device executes each step in the above method embodiment.

[0162] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute each step in the above method embodiment.

[0163] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0164] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0165] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0166] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0167] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0168] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A cache allocation method, characterized in that: Applied to electronic equipment, the method comprises: Determine a first thread group and a second thread group divided for a current scene; the importance of a first thread in the first thread group in the current scene is higher than the importance of a second thread in the second thread group in the current scene; Based on the first information corresponding to each preset period, periodically optimize and adjust the cache upper limits corresponding to the first thread group and the second thread group, respectively, to obtain a first target cache upper limit corresponding to the first thread group and a second target cache upper limit corresponding to the second thread group; The first information corresponding to each of the cycles is used to characterize a memory stagnation situation generated when the CPU executes a memory access instruction within the cycle, and the first target cache upper limit is higher than the second target cache upper limit.

2. The cache allocation method according to claim 1, characterized in that: The first information corresponding to each of the cycles is a weighted sum of the second information corresponding to the first thread group and the second thread group in the cycle; the weight corresponding to the first thread group is greater than the weight corresponding to the second thread group; The second information corresponding to each thread group in the first thread group and the second thread group represents a memory stagnation situation when the CPU executes memory access instructions of threads in the thread group within the cycle.

3. The cache allocation method according to claim 2, characterized in that: The second information corresponding to each thread group is the ratio of the first duration to the first total duration; the first duration represents the duration of memory stagnation caused by the CPU executing memory access instructions of each thread in the thread group during the cycle, and the first total duration represents the total duration taken by the CPU to execute instructions of each thread in the thread group during the cycle.

4. The cache allocation method according to claim 2 or 3, characterized in that: The periodically optimizing and adjusting the cache upper limits corresponding to the first thread group and the second thread group based on the first information corresponding to each preset period includes: For each new cycle, when a first condition is met, optimizing and adjusting the cache upper limit corresponding to the first cycle of the first thread group or the second thread group; Among them, the first condition includes that the first information corresponding to the first cycle is less than the first information corresponding to the second cycle, and / or the difference between the first information corresponding to the first cycle and the first information corresponding to the second cycle is less than or equal to a first threshold; the first threshold is a positive number; the first cycle is the previous cycle of the new cycle, and the second cycle is the previous cycle of the first cycle.

5. The cache allocation method according to claim 4, characterized in that: The optimizing and adjusting the cache upper limit corresponding to the first thread group or the second thread group in the first cycle includes: Lowering the cache upper limit corresponding to the first cycle for the first target thread group, and / or raising the cache upper limit corresponding to the first cycle for the second target thread group; Among them, the third information corresponding to the first target thread group is smaller than the third information corresponding to thread groups other than the first target thread group; the third information corresponding to the second target thread group is larger than the third information corresponding to thread groups other than the second target thread group; the third information corresponding to each thread group in the first thread group and the second thread group is the product of the second information corresponding to the thread group and the weight corresponding to the thread group.

6. The cache allocation method according to claim 2 or 3, characterized in that: The periodically optimizing and adjusting the cache upper limits corresponding to the first thread group and the second thread group based on the first information corresponding to each preset period, further includes: For each new cycle, when a second condition is met, optimizing and adjusting the cache upper limit corresponding to the first thread group or the second thread group in the second cycle; The second condition includes that the difference between the first information corresponding to the first period and the first information corresponding to the second period is greater than a first threshold; and the first threshold is a positive number.

7. The cache allocation method according to claim 6, characterized in that: The optimizing and adjusting the cache upper limit corresponding to the first thread group or the second thread group in the second cycle includes: Lowering the cache upper limit corresponding to the third target thread group in the second cycle, and / or raising the cache upper limit corresponding to the fourth target thread group in the second cycle; Among them, the third information corresponding to the third target thread group is smaller than the third information corresponding to the thread groups other than the third target thread group; the third information corresponding to the fourth target thread group is larger than the third information corresponding to the thread groups other than the fourth target thread group; the third information corresponding to each thread group in the first thread group and the second thread group is the product of the second information corresponding to the thread group and the weight corresponding to the thread group.

8. The cache allocation method according to claim 1, characterized in that: The step of periodically optimizing and adjusting the cache upper limits corresponding to the first thread group and the second thread group based on the first information corresponding to each preset period, and obtaining the first target cache upper limit corresponding to the first thread group and the second target cache upper limit corresponding to the second thread group, includes: Based on the first information corresponding to each preset period, periodically optimize and adjust the cache upper limits corresponding to the first thread group and the second thread group, determine a target period in the process of periodic optimization and adjustment, and determine the cache upper limit corresponding to the first thread group in the target period as the first target cache upper limit, and determine the cache upper limit corresponding to the second thread group in the target period as the second target cache upper limit; The first information corresponding to the target period is smaller than the first information corresponding to each of N consecutive periods after the target period, where N is a positive integer.

9. The cache allocation method according to claim 1, characterized in that: The method further comprises: After allocating the first target cache upper limit to the first thread group and allocating the second target cache upper limit to the second thread group, if the second information of any thread group changes by more than a second threshold value for M consecutive cycles, the cache upper limit of each thread group is reset; M is an integer greater than or equal to 2.

10. The cache allocation method according to claim 1, characterized in that: The optimization adjustment granularity is the preset unit granularity.

11. The cache allocation method according to claim 1, characterized in that: There are multiple first thread groups and multiple second thread groups, wherein the multiple first thread groups include a logical thread group in a game scene and / or a rendering thread group in the game scene, and the multiple second thread groups include an auxiliary thread group and a non-game thread group in the game scene; wherein the auxiliary thread group includes auxiliary threads other than the logical thread group and the rendering thread group and related to the game scene, and the non-game thread group includes threads unrelated to the game scene.

12. An electronic device, characterized in that: The electronic device comprises: one or more processors and a memory; the memory is coupled to the processor; the memory is used to store computer program code, the computer program code comprises computer instructions, and when the computer instructions are executed by the one or more processors, the electronic device executes the method as described in any one of claims 1-11.

13. A computer-readable storage medium, wherein instructions are stored in the computer-readable storage medium, characterized in that: When the instructions are executed on an electronic device, the electronic device is caused to execute the method as claimed in any one of claims 1 to 11.

14. A computer program product, characterized in that When the computer program product is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 11.

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