CRC-32 check code generation method based on RISC-V instruction set extension

Abstract

The invention relates to a CRC-32 check code generation method based on RISC-V instruction set extension, and the method comprises the steps: defining an instruction set, and adding a CRC-32 instruction in an RISC-V instruction set; a CRC (Cyclic Redundancy Check) calculation unit is added in the RISC-V processor and is used for calculating and processing the arithmetic logic of the CRC-32; a tool chain of the RISC-V is correspondingly modified so as to support compiling and generation of a CRC-32 instruction; 1) initializing; 2) reading data in blocks; (3) the CRC-32 instruction is executed; 4) updating the data blocks until all the data blocks are processed; and 5) outputting a result: after all data blocks are processed, performing bit-by-bit negation to obtain a final CRC-32 check code. By using the CRC-32 instruction, the speed of a cryptographic algorithm can be increased, the size of an application program is reduced, and a user can directly call the application program, so that the development efficiency is improved.

Description

Technical Field

[0001] The invention relates to a CRC-32 check code generation method based on RISC-V instruction set extension, belonging to the technical field of CRC-32 check code generation. Background Art

[0002] CRC-32 checksums are widely used in data transmission and storage to detect data integrity. Currently, when calculating CRC-32 checksums, using high-level languages ​​will generate more instructions due to a large number of repeated operations, which reduces efficiency. Using FPGA to implement CRC-32 checksum generation is the fastest, but its versatility is limited. Traditional CRC-32 checksum generation algorithms are usually byte-by-byte, involving table lookup, shift, and XOR operations. The calculation process has high performance requirements, especially when processing big data, and the calculation efficiency is low. Therefore, using instructions to implement the CRC-32 checksum algorithm takes into account both versatility and hardware acceleration performance.

[0003] RISC-V is a modular and open instruction set architecture that allows users to customize extended instructions. Extended instructions can enhance the performance of specific computing tasks, thereby improving performance and efficiency in certain specific scenarios. Summary of the invention

[0004] In view of the deficiencies of the prior art, the present invention provides a CRC-32 check code generation method based on RISC-V instruction set extension;

[0005] The purpose of the present invention is to address the problem that the generation of CRC-32 check code in the above-mentioned prior art can only be achieved through hardware circuit design or software, and to integrate the calculation process of CRC-32 into special hardware instructions through the RISC-V instruction set extension method.

[0006] The present invention designs acceleration instructions specifically for the CRC-32 check code generation process by extending the RISC-V instruction set, thereby improving the speed and efficiency of the calculation of the CRC-32 check code generation.

[0007] Terminology explanation:

[0008] 1. ALU, Arithmetic Logic Unit, is a component in the processor that performs arithmetic and logical operations. It is responsible for performing operations such as addition, subtraction, multiplication, division, and bit operations. In the present invention, ALU will be used to assist in the calculation of CRC-32, especially when performing bit operations and shift operations.

[0009] 2. Memory refers to the hardware used to store data and programs in a computer system. In the present invention, Memory will be used to store the data to be calculated for CRC-32 and the pre-calculated CRC-32 value.

[0010] 3. Registers are fast storage areas inside the processor, used to temporarily store data during instruction execution. In the present invention, Registers are used to store intermediate results and states during CRC-32 calculation.

[0011] 4. CRC, Cyclic Redundancy Check, is a commonly used, division-based verification technique used to detect errors in data transmission or storage. CRC-32 is a type of CRC that uses a 32-bit polynomial to generate a checksum to ensure data integrity.

[0012] In order to achieve the above object, the present invention has the following technical solutions:

[0013] A CRC-32 check code generation method based on RISC-V instruction set extension, comprising:

[0014] Defining the instruction set means: adding CRC-32 instructions to the RISC-V instruction set;

[0015] Add a CRC calculation unit in the RISC-V processor, which is used to calculate and process the operation logic of CRC-32;

[0016] Modify the RISC-V toolchain accordingly to support the compilation and generation of CRC-32 instructions;

[0017] 1) Initialization: Initialize the CRC register to 0xFFFFFFFF;

[0018] 2) Read data in blocks: Load data into register rs2 block by block according to the bit width of the data to be processed, and load the current CRC register value into register rs1;

[0019] 3) Execute CRC-32 instruction: Execute CRC-32 instruction on register rs1 and register rs2, and update CRC register after calculation; after each instruction execution, the content of CRC register is updated, including the new CRC calculation result;

[0020] 4) Update data block: Repeat steps 2) and 3) for the next block of data until all data blocks are processed;

[0021] 5) Output result: After all data blocks are processed, the final value in the CRC register is bitwise inverted with 0xFFFFFFFF to obtain the final CRC-32 checksum.

[0022] Preferably, according to the present invention, different CRC-32 instructions are designed for different data types, as follows:

[0023] When the data type is to process byte data, the CRC-32 instruction is CRC32_B;

[0024] When the data type is to process half-word data, the CRC-32 instruction is CRC32_H;

[0025] When the data type is word data, the CRC-32 instruction is CRC32_W;

[0026] When the data type is to process double-word data, the CRC-32 instruction is CRC32_D;

[0027] Each instruction operation form is as follows:

[0028] CRC32_B rd,rs1,rs2, means: calculate the CRC32 value of 8-bit data;

[0029] CRC32_H rd,rs1,rs2, means: calculate the CRC32 value of 16-bit data;

[0030] CRC32_W rd,rs1,rs2, means: calculate the CRC32 value of 32-bit data;

[0031] CRC32_D rd,rs1,rs2, means: calculate the CRC32 value of 64-bit data;

[0032] Among them, the target register rd is used to store the final CRC32 value; the register rs1 is used to store the original data; the register rs2 is used to store the current CRC32 accumulated value.

[0033] Further preferably, the format of the CRC-32 instruction is:

[0034] For the CRC-32 instruction, the R-type instruction is used to process the data in the register; the R-type instruction has three operands, two source registers and one target register; the two source registers include register rs1 and register rs2, and the target register is the CRC register.

[0035] Preferably, according to the present invention, the RISC-V processor includes an instruction register, a decoding unit, an ALU, a memory, registers, a CRC operation unit and a lookup register; the instruction register, the decoding unit, the ALU and the memory are connected in sequence; the instruction register, the registers, the CRC operation unit and the lookup register are connected in sequence, the decoding unit is connected to the registers, and the memory is connected to the CRC operation unit;

[0036] Instruction register: stores the intermediate CRC results and accumulates and updates them each time an instruction is executed; decoding unit: used to parse the instructions obtained from the instruction memory and extract the key information required to execute the instruction; ALU: used to assist in the calculation of CRC-32; Memory: used to store the data to be calculated CRC-32 and the pre-calculated CRC-32 value; Registers: used to store the intermediate results and status during the CRC-32 calculation process; CRC operation unit: used to calculate and process the operation logic of CRC-32; lookup register: used to store the pre-calculated CRC32 value of each byte.

[0037] Preferably, according to the present invention, the RISC-V tool chain is modified accordingly to support the compilation and generation of CRC-32 instructions; including:

[0038] Modify the assembler: add support for CRC-32 instructions to the assembler;

[0039] Modify the compiler: add built-in CRC-32 instruction support in GCC or LLVM compiler;

[0040] Modify the linker: Make sure that the linker correctly handles the object code format of the CRC-32 instruction and that the generated binary program correctly executes the extended instruction.

[0041] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the above-mentioned CRC-32 check code generation method based on RISC-V instruction set extension are implemented.

[0042] A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the above-mentioned CRC-32 check code generation method based on the RISC-V instruction set extension are implemented.

[0043] The beneficial effects of the present invention are:

[0044] The present invention enables the RISC-V processor to have CRC-32 check code generation instructions. Compared with pure software implementation, the use of these instructions can improve the speed of cryptographic algorithms and reduce the size of application programs. Users can call them directly to improve development efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic diagram of the architecture of the RISC-V processor;

[0046] Figure 2 A flowchart of a process for executing a CRC-32 checksum generation instruction in a RISC-V processor;

[0047] Figure 3 A flowchart showing the detailed process of generating a CRC-32 checksum. DETAILED DESCRIPTION

[0048] The present invention will be further defined below in conjunction with the accompanying drawings and embodiments, but is not limited thereto.

[0049] Example 1

[0050] A CRC-32 check code generation method based on RISC-V instruction set extension, comprising:

[0051] Defining the instruction set means adding dedicated CRC-32 instructions to the RISC-V instruction set; these instructions can directly complete the CRC-32 calculation by operating the data in the register.

[0052] Modify the hardware: To implement a custom CRC-32 instruction, you need to add a dedicated CRC calculation unit to the RISC-V processor. The CRC calculation unit is used to calculate and process the CRC-32 operation logic;

[0053] Modify the software: In order to use the customized CRC-32 instructions, modify the RISC-V tool chain (such as GCC, LLVM) accordingly to support the compilation and generation of CRC-32 instructions;

[0054] 1) Initialization: Initialize the CRC register to 0xFFFFFFFF;

[0055] 2) Read data in blocks: Load data into register rs2 block by block according to the bit width of the data to be processed (8, 16, 32 or 64 bits), and load the current CRC register value (initial 0xFFFFFFFF) into register rs1;

[0056] 3) Execute CRC-32 instruction: Execute CRC-32 instruction on register rs1 and register rs2, and update CRC register after calculation; after each instruction execution, the content of CRC register is updated, including the new CRC calculation result;

[0057] 4) Update data block: Repeat steps 2) and 3) for the next block of data until all data blocks are processed;

[0058] 5) Output result: After all data blocks are processed, the final value in the CRC register is bitwise inverted with 0xFFFFFFFF to obtain the final CRC-32 checksum.

[0059] Example 2

[0060] The difference between the CRC-32 check code generation method based on RISC-V instruction set extension described in Example 1 is that:

[0061] Different CRC-32 instructions are designed for different data types, as follows:

[0062] When the data type is to process byte data (8 bits), the CRC-32 instruction is CRC32_B;

[0063] When the data type is to process half-word data (16 bits), the CRC-32 instruction is CRC32_H;

[0064] When the data type is word data (32 bits), the CRC-32 instruction is CRC32_W;

[0065] When the data type is to process double-word data (64 bits), the CRC-32 instruction is CRC32_D;

[0066] Each instruction operation form is as follows:

[0067] CRC32_B rd,rs1,rs2, means: calculate the CRC32 value of 8-bit data;

[0068] CRC32_H rd,rs1,rs2, means: calculate the CRC32 value of 16-bit data;

[0069] CRC32_W rd,rs1,rs2, means: calculate the CRC32 value of 32-bit data;

[0070] CRC32_D rd,rs1,rs2, means: calculate the CRC32 value of 64-bit data;

[0071] Among them, the target register rd is used to store the final CRC32 value; the register rs1 is used to store the original data; the register rs2 is used to store the current CRC32 accumulated value.

[0072] The format of the CRC-32 instruction is:

[0073] RISC-V instructions are usually of three types: R-type, I-type, S-type, etc. For CRC-32 instructions, R-type instructions are used to process data in registers; R-type instructions have three operands, two source registers and one target register; the two source registers include register rs1 and register rs2, and the target register is the CRC register.

[0074] As shown in Table 1:

[0075] funct7 rs2 rs1 funct3 rd opcode

[0076] Among them, funct7: specifies the function category and identifies the CRC-32 operation type. rs2: source register 2, used to store the data to be calculated. rs1: source register 1, used to store the current CRC value. funct3: used to distinguish the bit width of the operation data (8 bits, 16 bits, 32 bits, 64 bits). rd: destination register, stores the calculated CRC value. opcode: specifies the operation type, and a specific value can be assigned to the CRC-32 operation.

[0077] like Figure 1 As shown, the RISC-V processor includes an instruction register, a decoding unit, an ALU, a memory, registers, a CRC operation unit and a lookup table register (LUT); the instruction register, the decoding unit, the ALU and the memory are connected in sequence; the instruction register, the registers, the CRC operation unit and the lookup table register are connected in sequence, the decoding unit is connected to the registers, and the memory is connected to the CRC operation unit;

[0078] Instruction register: stores the intermediate CRC results and accumulates and updates them each time an instruction is executed; decoding unit: used to parse the instructions obtained from the instruction memory and extract the key information required to execute the instruction; ALU: used to assist in the calculation of CRC-32, especially when performing bit operations and shift operations; Memory: used to store the data to be calculated for CRC-32 and the pre-calculated CRC-32 value; Registers: used to store the intermediate results and status during the CRC-32 calculation process; CRC operation unit: used to calculate and process the operation logic of CRC-32; lookup register: used to store the pre-calculated CRC32 value of each byte.

[0079] Specific implementation steps:

[0080] Register read: When the instruction is executed, the input data is read from the source register rs1.

[0081] Table lookup operation: Based on the byte value of the input data, the corresponding CRC-32 value is found from the LUT.

[0082] XOR operation: XOR the found value with the current CRC accumulation value (from the rs2 register).

[0083] Shift operation: Update the updated CRC value by shifting.

[0084] Result storage: Store the calculated final CRC value into the destination register rd.

[0085] Modify the RISC-V toolchain accordingly to support the compilation and generation of CRC-32 instructions; including:

[0086] Modify the assembler: add support for CRC-32 instructions to the assembler; enable it to recognize and parse CRC-32 extended instructions.

[0087] Modify the compiler: Add built-in CRC-32 instruction support in the GCC or LLVM compiler; developers can call these instructions directly by using inline assembly or compiler built-in functions.

[0088] Modify the linker: Make sure that the linker correctly handles the object code format of the CRC-32 instruction and that the generated binary program correctly executes the extended instruction.

[0089] like Figure 2 As shown, the CRC-32 checksum generation instruction is executed in the RISC-V processor; including:

[0090] 1) Start: Start from the start node;

[0091] 2) Get instructions from the instruction register: The RISC-V processor reads the next instruction to be executed from the instruction register;

[0092] 3) Determine whether the instruction is a CRC calculation instruction: The decoding unit checks whether the current instruction is an extended instruction specifically for CRC-32 calculation. If not, turn to execute a normal instruction. If yes, go to step 4).

[0093] 4) Start the CRC-32 operation logic: The RISC-V processor will start the CRC-32 operation logic and start performing the CRC-32 operation.

[0094] 5) Store the CRC-32 result to the register file: After the calculation is completed, the CRC-32 calculation result is stored in the specified register in the register file.

[0095] 6) Update program counter: The program counter of the RISC-V processor is updated to point to the next instruction to be executed.

[0096] 7) Get the next instruction from the instruction register: The RISC-V processor reads the next instruction from the instruction register again, and the process returns to step 3) to continue to determine the instruction type.

[0097] like Figure 3 As shown in the figure, the detailed process of generating CRC-32 checksum includes:

[0098] 1) Start: Start from the start node;

[0099] 2) Initialize the CRC register: Set the initial value of the CRC register, usually a predefined constant. (The most common CRC-32 polynomial is the initial value 0xFFFFFFFF defined in the IEEE 802.3 standard.)

[0100] 3) Read data register: read data from the data source into the data register.

[0101] 4) Whether all data has been processed: Check whether all data has been processed. If all data has been processed, the process turns to CRC-32 calculation completion. If not all data has been processed, the process continues to the next step.

[0102] 5) XOR the data bit with the highest bit of the CRC register: XOR the current highest bit in the data register with the highest bit of the CRC register.

[0103] 6) Shift the CRC register one bit to the left: Shift all bits in the CRC register one bit to the left to prepare for the XOR operation of the next bit of data.

[0104] 7) Store the XOR result in the highest bit of the CRC register: Store the XOR result in step 5 in the highest bit of the CRC register.

[0105] 8) Read the next bit of data: Read the next bit of data from the data register and prepare for the next round of XOR operation.

[0106] 9) Return to step 4): The process returns to step 4) and continues to check whether all data has been processed.

[0107] 10) CRC-32 calculation completed: When all data bits have been processed, the CRC-32 calculation is completed.

[0108] 11) Store the result in a register: Store the final CRC-32 value in a register or output it to a specified location.

[0109] 12) Return to the main process: The process ends and returns to the main program or performs subsequent operations.

[0110] Example 3

[0111] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the CRC-32 check code generation method based on the RISC-V instruction set extension described in Example 1 or 2 are implemented.

[0112] Example 4

[0113] A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the CRC-32 check code generation method based on the RISC-V instruction set extension described in Example 1 or 2 are implemented.

Claims

1. A CRC-32 check code generation method based on RISC-V instruction set extension, characterized in that: include: Defining the instruction set means: adding CRC-32 instructions to the RISC-V instruction set; Add a CRC calculation unit in the RISC-V processor, which is used to calculate and process the operation logic of CRC-32; Modify the RISC-V toolchain accordingly to support the compilation and generation of CRC-32 instructions; 1) Initialization; 2) Read data in blocks: Load data into register rs2 block by block according to the bit width of the data to be processed, and load the current CRC register value into register rs1; 3) Execute CRC-32 instruction: Execute CRC-32 instruction on register rs1 and register rs2, and update CRC register after calculation; after each instruction execution, the content of CRC register is updated, including the new CRC calculation result; 4) Update data block: Repeat steps 2) and 3) for the next block of data until all data blocks are processed; 5) Output result: After all data blocks are processed, the final value in the CRC register is bitwise inverted with 0xFFFFFFFF to obtain the final CRC-32 checksum.

2. A CRC-32 check code generation method based on RISC-V instruction set extension according to claim 1, characterized in that, Different CRC-32 instructions are designed for different data types, as follows: When the data type is to process byte data, the CRC-32 instruction is CRC32_B; When the data type is to process half-word data, the CRC-32 instruction is CRC32_H; When the data type is word data, the CRC-32 instruction is CRC32_W; When the data type is to process double-word data, the CRC-32 instruction is CRC32_D; Each instruction operation form is as follows: CRC32_B rd,rs1,rs2, means: calculate the CRC32 value of 8-bit data; CRC32_H rd,rs1,rs2, means: calculate the CRC32 value of 16-bit data; CRC32_W rd,rs1,rs2, means: calculate the CRC32 value of 32-bit data; CRC32_D rd,rs1,rs2, means: calculate the CRC32 value of 64-bit data; Among them, the target register rd is used to store the final CRC32 value; the register rs1 is used to store the original data; the register rs2 is used to store the current CRC32 accumulated value.

3. A CRC-32 check code generation method based on RISC-V instruction set extension according to claim 1, characterized in that, The format of the CRC-32 instruction is: For the CRC-32 instruction, the R-type instruction is used to process the data in the register; the R-type instruction has three operands, two source registers and one target register; the two source registers include register rs1 and register rs2, and the target register is the CRC register.

4. A CRC-32 check code generation method based on RISC-V instruction set extension according to claim 1, characterized in that: The RISC-V processor includes an instruction register, a decoding unit, an ALU, a memory, registers, a CRC operation unit and a lookup table register; the instruction register, the decoding unit, the ALU and the memory are connected in sequence; the instruction register, the registers, the CRC operation unit and the lookup table register are connected in sequence, the decoding unit is connected to the registers, and the memory is connected to the CRC operation unit; Instruction register: saves the intermediate CRC result and accumulates and updates it each time an instruction is executed; Decoding unit: used to parse the instructions obtained from the instruction memory and extract the key information required to execute the instruction; ALU: used to assist in the calculation of CRC-32; Memory: used to store the data to be calculated for CRC-32 and the pre-calculated CRC-32 value; Registers: used to store the intermediate results and status during the CRC-32 calculation process; CRC operation unit: used to calculate and process the operation logic of CRC-32; Lookup register: used to store the pre-calculated CRC32 value of each byte.

5. A CRC-32 check code generation method based on RISC-V instruction set extension according to any one of claims 1 to 4, characterized in that: Modify the RISC-V toolchain accordingly to support the compilation and generation of CRC-32 instructions; including: Modify the assembler: add support for CRC-32 instructions to the assembler; Modify the compiler: add built-in CRC-32 instruction support in GCC or LLVM compiler; Modify the linker: Make sure that the linker correctly handles the object code format of the CRC-32 instruction and that the generated binary program correctly executes the extended instruction.

6. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the CRC-32 check code generation method based on the RISC-V instruction set extension described in any one of claims 1 to 5 are implemented.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the CRC-32 check code generation method based on the RISC-V instruction set extension described in any one of claims 1 to 5 are implemented.

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