A parallel testing system and method for electronic equipment products based on greedy strategy

Abstract

The present invention discloses a parallel testing system and method for electronic equipment products based on a greedy strategy, and relates to the field of electronic equipment testing. The present invention can uniformly control the management, scheduling and execution of the entire test process. After the tester inputs basic information such as test items and available test instruments, multiple test items are allocated to multiple threads according to a certain parallel test task scheduling strategy to form an optimal parallel test sequence, and the effect of the test process and the test performance analysis can be displayed on the client. At the same time, the relevant test information and test process are uniformly managed through a database, and the reusability is greatly enhanced. By loading different configuration files, parallel testing of different test tasks can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of electronic equipment testing, and in particular to a system and method for parallel testing of electronic equipment products based on a greedy strategy. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

[0003] With the continuous development of electronic equipment production, there have been problems such as rapid expansion of scale, tight debugging resources, and insufficient flexibility. How to improve test efficiency has become an important issue that needs to be solved urgently. Electronic equipment testing usually still adopts the traditional sequential test mode, that is, testing all test items one by one in sequence. As a result, the average idle time of the test instrument may account for more than 50% of the entire test time, which will bring many problems: on the one hand, it will cause a large number of test instruments to wait, reducing the utilization rate of test instruments; on the other hand, it will cause the test items to be delayed and the test time will be greatly extended; and the test scheduling scheme of the existing automatic test system is largely set according to user experience, and there are problems such as low efficiency and lack of flexibility.

[0004] For a new type of product, it is necessary to test several test items of this model product. For a single test item, different types and numbers of test instruments are required to test it. In product testing, usually, testing a test item only requires a test interface of this model product to access the test instrument. However, there is also a special intercommunication situation, that is, some test items require another product of the same model for auxiliary testing, such as requiring another product as the signal sending or receiving end to perform signal interaction testing.

[0005] In view of the above test scenarios, in the actual test instrument allocation process, multiple test groups may often use the same test instrument, but the test instrument resources are limited. As a result, after the test instrument is allocated, other test items cannot start testing due to insufficient test instruments in the test group, and thus are stuck in waiting. In addition, different products have different test times, making it impossible to predict the waiting time for other products, thus affecting test efficiency. Summary of the invention

[0006] The purpose of the present invention is to provide a parallel testing system and method for electronic equipment products based on a greedy strategy to solve the problems of low test efficiency caused by the serial sequential testing in the existing test methods. The system can uniformly control the management, scheduling and execution of the entire test process. After the tester inputs the basic information such as the test items and the available test instruments, the parallel testing system will distribute multiple test items to multiple threads according to a certain parallel test task scheduling strategy to form an optimal parallel test sequence, and can display the effect of the test process and the test performance analysis on the client. At the same time, the relevant test information and test process are uniformly managed through the database, and the reusability is greatly enhanced. By loading different configuration files, the parallel testing of different test tasks can be realized.

[0007] The technical solution of the present invention is as follows:

[0008] A parallel testing method for electronic equipment products based on a greedy strategy, comprising:

[0009] Step S1: Arrange all test items in the queue to be tested in descending order according to the test time;

[0010] Step S2: adding the test item ranked first to the test queue as the first item, and updating the remaining available test instruments;

[0011] Step S3: traverse the remaining test items, if the remaining available test instruments can meet the test requirements of the current test item, add the test item to the test queue, and update the remaining available test instruments again until the termination condition is reached;

[0012] Step S4: Based on the test queue, start this round of parallel testing;

[0013] Step S5: Based on the remaining test items in the queue to be tested, repeat steps S2 to S4 to finally complete the testing of all test items.

[0014] Furthermore, each test item includes: test time, test instrument requirement vector, and interoperability identification.

[0015] Furthermore, the step S2 comprises:

[0016] Step S21: adding the test item ranked first to the test queue as the first item;

[0017] Step S22: updating the test instrument state vector according to the test instrument requirement vector of the added test item.

[0018] Furthermore, the step S21 includes:

[0019] If the test instrument state vector cannot satisfy the test instrument requirement vector, the test item is skipped and the next test item is added to the test queue.

[0020] Furthermore, the step S22 includes:

[0021] The test instrument requirement vector is deducted from the test instrument state vector to obtain the remaining test instrument state vector, thus completing the test instrument state vector update.

[0022] Furthermore, the step S3 comprises:

[0023] Step S31: traverse the remaining test items, and if the updated test instrument state vector can satisfy the test instrument requirement vector of the next test item, add the test item to the test queue;

[0024] Step S32: Update the test instrument state vector again;

[0025] Step S33: Repeat steps S31 to S33 until the termination condition is reached.

[0026] Furthermore, the termination conditions include:

[0027] The upper limit of the number of parallel paths is reached or the updated test instrument state vector cannot meet the test instrument requirement vectors of the remaining test items.

[0028] Furthermore, let the upper limit of the number of parallel paths be N;

[0029] If the intercommunication mark of the added test item is displayed as intercommunication, the number of parallel paths occupied is 2;

[0030] If the intercommunication flag of the added test item is displayed as non-intercommunication, the number of parallel paths occupied is 1.

[0031] Furthermore, the step S31 further includes:

[0032] If the updated test instrument state vector can satisfy the test instrument requirement vector of the current test item, but the test item conflicts with the test instruments used by the test items in the test queue, the test item is skipped and the next test item is selected in sequence.

[0033] The present invention also proposes a parallel testing system for electronic equipment products based on a greedy strategy, comprising: an instrument layer, a scheduling layer, and a product layer;

[0034] The test layer has multiple test instruments; the product layer has multiple products; the scheduling layer is provided with a parallel test scheduling algorithm module and a product test connection scheduling control module; the parallel test scheduling algorithm module can execute a parallel testing method for electronic equipment products based on a greedy strategy to build a test queue; the product test connection scheduling control module maps the test instruments, products and test items in a one-to-one-to-one or multiple-to-one-to-one mapping according to the test queue to complete the parallel testing of the product.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The present invention can uniformly control the management, scheduling and execution of the entire test process. After the tester inputs basic information such as test items and available test instruments, the parallel test system allocates multiple test items to multiple threads according to a certain parallel test task scheduling strategy to form an optimal parallel test sequence, and can display the effect of the test process and test performance analysis on the client. At the same time, the relevant test information and test process are uniformly managed through the database, and the reusability is greatly enhanced. By loading different configuration files, parallel testing of different test tasks can be achieved.

[0037] 3. The present invention can improve the utilization rate of test instruments, shorten the overall test time, and realize the planning and scheduling of test instrument resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a flow chart of a parallel testing method for electronic equipment products based on a greedy strategy;

[0039] Figure 2 Schematic diagram of parallel testing process based on greedy strategy;

[0040] Figure 3 This is a block diagram of a parallel testing system for electronic equipment products based on a greedy strategy;

[0041] Figure 4 This is a time comparison chart for different test methods;

[0042] Figure 5 This is a comparison chart of test time based on generated data;

[0043] Figure 6 This is a time efficiency analysis chart based on test data. DETAILED DESCRIPTION

[0044] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0045] The features and performance of the present invention are further described in detail below in conjunction with the embodiments.

[0046] Embodiment 1

[0047] First of all, it should be explained that the core idea of ​​the greedy strategy is to always make the best choice at the moment when solving a problem. Its characteristic is that it is carried out step by step, often based on the current situation and making the best choice according to a certain optimization measure, without considering various possible overall situations, saving a lot of time that must be spent on exhausting all possibilities to find the optimal solution. The greedy strategy adopts a top-down, iterative way to make successive greedy choices. Each time a greedy choice is made, the problem is simplified into a smaller sub-problem. Through each step of greedy choice, an optimal solution to the problem can be obtained.

[0048] Therefore, the core idea of ​​the parallel testing method proposed in the present invention is as follows: Figure 2 As shown, according to the current relationship between the test equipment and the product, the test groups to be tested are divided into multiple rounds for testing. Each round consists of multiple test groups for parallel testing. In each round of iteration, combined with constraints such as the number of parallel paths and whether they are interoperable, multiple test groups with independent relationships (that is, the test instruments used have no conflicts) are selected from the test groups to be tested to perform test operations, and then enter the next round, and repeat the selection and testing operations until all product test items are tested. In each round, this method has an optimal solution, that is, maximizing concurrent efficiency. Thereby shortening the test time and improving the test efficiency overall.

[0049] See also Figure 1 This embodiment proposes a parallel testing method for electronic equipment products based on a greedy strategy, which specifically includes the following steps:

[0050] Step S1: Arrange all test items in the queue to be tested in descending order according to the test time;

[0051] Step S2: adding the test item ranked first to the test queue as the first item, and updating the remaining available test instruments;

[0052] Step S3: traverse the remaining test items, if the remaining available test instruments can meet the test requirements of the current test item, add the test item to the test queue, and update the remaining available test instruments again until the termination condition is reached;

[0053] Step S4: Based on the test queue, start this round of parallel testing;

[0054] Step S5: Based on the remaining test items in the queue to be tested, repeat steps S2 to S4 to finally complete the testing of all test items.

[0055] In this embodiment, specifically, each test item includes: test time, test equipment requirement vector, and intercommunication identifier.

[0056] In this embodiment, specifically, step S2 includes:

[0057] Step S21: adding the test item ranked first to the test queue as the first item;

[0058] Step S22: updating the test instrument state vector according to the test instrument requirement vector of the added test item.

[0059] In this embodiment, specifically, step S21 includes:

[0060] If the test instrument state vector cannot satisfy the test instrument requirement vector, the test item is skipped and the next test item is added to the test queue.

[0061] In this embodiment, specifically, step S22 includes:

[0062] The test instrument requirement vector is deducted from the test instrument state vector to obtain the remaining test instrument state vector, thus completing the test instrument state vector update.

[0063] In this embodiment, specifically, step S3 includes:

[0064] Step S31: traverse the remaining test items, and if the updated test instrument state vector can satisfy the test instrument requirement vector of the next test item, add the test item to the test queue;

[0065] Step S32: Update the test instrument state vector again;

[0066] Step S33: Repeat steps S31 to S33 until the termination condition is reached.

[0067] In this embodiment, specifically, the termination condition includes:

[0068] The upper limit of the number of parallel paths is reached or the updated test instrument state vector cannot meet the test instrument requirement vectors of the remaining test items.

[0069] In this embodiment, specifically, the upper limit of the number of parallel paths is set to N;

[0070] If the intercommunication mark of the added test item is displayed as intercommunication, the number of parallel paths occupied is 2;

[0071] If the intercommunication flag of the added test item is displayed as non-intercommunication, the number of parallel paths occupied is 1.

[0072] In this embodiment, specifically, step S31 further includes:

[0073] If the updated test instrument state vector can satisfy the test instrument requirement vector of the current test item, but the test item conflicts with the test instruments used by the test items in the test queue, the test item is skipped and the next test item is selected in sequence.

[0074] See also Figure 3 ,This embodiment also proposes a parallel testing system for electronic equipment products based on ,greedy strategy, including: an instrument layer, a scheduling layer, and a product layer;

[0075] The test layer has multiple test instruments; the product layer has multiple products; the scheduling layer is provided with a parallel test scheduling algorithm module and a product test connection scheduling control module; the parallel test scheduling algorithm module can execute a parallel testing method for electronic equipment products based on a greedy strategy to build a test queue; the product test connection scheduling control module maps the test instruments, products and test items in a one-to-one-to-one or multiple-to-one-to-one mapping according to the test queue to complete the parallel testing of the product.

[0076] Embodiment 2

[0077] This embodiment is based on the electronic equipment product parallel testing method based on the greedy strategy proposed in the first embodiment, and is specifically programmed to form the following two algorithms.

[0078]

[0079] According to the returned test queue, each test item is executed in parallel. After k rounds, all test items are tested. Therefore, Algorithm 2 describes the parallel testing process.

[0080]

[0081] The main parameters related to the above algorithm are described as follows:

[0082] (1)α i ={t i ,u i ,f i ,ε i}; i = 1, ..., n, represents n test items of the product, each test item includes its test time t i , the test equipment requirement vector u of the test item i , this test item is an interoperable identifier f i ;

[0083] (2)Ω={ω i}, i=1,…,m represents the test instrument state set, ω i represents the available quantity of the i-th test instrument;

[0084] (3)U i = {u j}, i = 1, ..., n; j = 1, ..., m represents the instrument requirement vector of the i-th test item, which contains m elements and represents the number of j-th test instruments required;

[0085] uj

[0086] (4) F = {f i |f i =0,1; i=1,2,...,n} indicates whether the test item needs to be interoperable. fi can only be 0 or 1. 0 means that the i-th test item does not need auxiliary products for interoperability, and 1 means that the i-th test item needs auxiliary products for interoperability.

[0087] (5)Φ={U i |1≤i≤m} represents the queue consisting of untested items.

[0088] Specifically, Table 1 summarizes the relevant parameters and their meanings.

[0089] Table 1 Related parameters and their meanings

[0090]

[0091]

[0092] Embodiment 3

[0093] This embodiment is based on the practical application of a parallel testing method for electronic equipment products based on a greedy strategy proposed in the first embodiment.

[0094] Specifically, the test data used in this embodiment is 46 test items of a certain electronic equipment product, and the constraint condition is set to 4-way parallel. Figure 4The final test time comparison of serial test, random parallel test and the parallel test method proposed in this patent is shown;

[0095] from Figure 4 It can be seen that the test time using the serial test method is 433.67 minutes, the test time using the random parallel test method is 261.21 minutes, and the test time using the parallel test method proposed in this patent is 167.58 minutes, and the time efficiency is improved by 61%, which shows the effectiveness and efficiency of the patent method.

[0096] At the same time, the bottleneck factors of the actual application of this method were further analyzed. 200 simulation data were generated based on the actual production data, each containing 100 test items for testing. The test time results are as follows: Figure 5 As shown;

[0097] Due to random data, the test time fluctuates greatly, with the average serial test time being 2551.94 minutes and the average parallel test time being 1006.99 minutes. Eliminating only the limit on the number of test instruments reduces the average parallel time to 976.53 minutes, with little change; eliminating only the limit on intercommunication reduces the average parallel time to 705.03 minutes, with a significant reduction. After eliminating the limit on intercommunication and the number of test instruments, the test is 4-way full parallel, and the average parallel time is 656.14 minutes. From the above data, it can be analyzed that the limit on the number of test instruments has little impact on the test, while the limit on intercommunication has a relatively large impact on the test.

[0098] Time efficiency Figure 6 As shown in the figure, the average time efficiency of the original conditional parallelism can reach 61%; after eliminating the limit on the number of test instruments, the efficiency of each group of tests is improved, but the change is small, and the average value reaches 62%; after eliminating the interconnection restriction, 4-way parallelism can be achieved most of the time, and only a small part can only have 2 or 3-way parallelism due to the limit on the number of test instruments. At this time, the average efficiency improvement can reach 72%; after eliminating the limit on the number of test instruments and the interconnection restriction, 4-way full parallelism can be achieved, and the average efficiency improvement is 74%, which is very close to the theoretical value of 75%.

[0099] In general, the method proposed in this patent can efficiently test each test item of the product, automatically and intelligently handle the equipment resource conflicts that may occur in parallel testing, and automatically generate a scheduling plan for parallel testing of multiple test items using the current test items and instrument mapping conditions, so as to achieve parallel testing of multiple products, complete the transition from serial to parallel test mode, greatly improve test efficiency and test quality, and reduce the cost of electronic equipment testing. At the same time, this method can be easily extended to the testing of different test items for multiple products, thus combining high efficiency and scalability.

[0100] The above-mentioned embodiments only express the specific implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the protection scope of the present application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the technical solution concept of the present application, and these all belong to the protection scope of the present application.

[0101] This background section is provided to generally present the context of the invention, and the work of the presently named inventors, the work to the extent described in this background section, and aspects of this section that did not constitute prior art at the time of application are neither explicitly nor implicitly admitted to be prior art to the present invention.

Claims

1. A parallel testing method for electronic equipment products based on a greedy strategy, characterized in that: include: Step S1: Arrange all test items in the queue to be tested in descending order according to the test time; Step S2: adding the test item ranked first to the test queue as the first item, and updating the remaining available test instruments; Step S3: traverse the remaining test items, if the remaining available test instruments can meet the test requirements of the current test item, add the test item to the test queue, and update the remaining available test instruments again until the termination condition is reached; Step S4: Based on the test queue, start this round of parallel testing; Step S5: Based on the remaining test items in the queue to be tested, repeat steps S2 to S4 to finally complete the testing of all test items.

2. The method for parallel testing of electronic equipment products based on a greedy strategy according to claim 1, characterized in that: Each test item includes: test time, test instrument requirement vector, and interoperability identification.

3. The method for parallel testing of electronic equipment products based on a greedy strategy according to claim 2, characterized in that: The step S2 comprises: Step S21: adding the test item ranked first to the test queue as the first item; Step S22: updating the test instrument state vector according to the test instrument requirement vector of the added test item.

4. The method for parallel testing of electronic equipment products based on a greedy strategy according to claim 3, characterized in that: The step S21 comprises: If the test instrument state vector cannot satisfy the test instrument requirement vector, the test item is skipped and the next test item is added to the test queue.

5. The method for parallel testing of electronic equipment products based on a greedy strategy according to claim 3, characterized in that: The step S22 comprises: The test instrument requirement vector is deducted from the test instrument state vector to obtain the remaining test instrument state vector, thus completing the test instrument state vector update.

6. The method for parallel testing of electronic equipment products based on a greedy strategy according to claim 3, characterized in that: The step S3 comprises: Step S31: traverse the remaining test items, and if the updated test instrument state vector can satisfy the test instrument requirement vector of the next test item, add the test item to the test queue; Step S32: Update the test instrument state vector again; Step S33: Repeat steps S31 to S33 until the termination condition is reached.

7. The method for parallel testing of electronic equipment products based on a greedy strategy according to claim 6, characterized in that: The termination conditions include: The upper limit of the number of parallel paths is reached or the updated test instrument state vector cannot satisfy the test instrument requirement vectors of the remaining test items.

8. The method for parallel testing of electronic equipment products based on a greedy strategy according to claim 7 is characterized in that: The upper limit of the number of parallel paths is N; If the intercommunication mark of the added test item is displayed as intercommunication, the number of parallel paths occupied is 2; If the intercommunication flag of the added test item is displayed as non-intercommunication, the number of parallel paths occupied is 1.

9. The method for parallel testing of electronic equipment products based on a greedy strategy according to claim 6, characterized in that: The step S31 further includes: If the updated test instrument state vector can satisfy the test instrument requirement vector of the current test item, but the test item conflicts with the test instruments used by the test items in the test queue, the test item is skipped and the next test item is selected in sequence.

10. A parallel testing system for electronic equipment products based on a greedy strategy, characterized in that: include: Instrument layer, scheduling layer, product layer; The testing layer has a plurality of testing instruments; The product layer has multiple products; the scheduling layer is provided with a parallel test scheduling algorithm module and a product test connection scheduling control module; the parallel test scheduling algorithm module can execute a parallel testing method for electronic equipment products based on a greedy strategy to build a test queue; the product test connection scheduling control module maps test instruments, products and test items in a one-to-one-to-one or multiple-to-one-to-one mapping according to the test queue to complete parallel testing of products.

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