Risc-v based secure branch predictor and method of operation

Abstract

The application discloses a RISC-V based security branch predictor and a running method thereof. The security branch predictor comprises an attack module and a defense module. The attack module is used to simulate attack training on an initial condition branch instruction in the security branch predictor by using a side channel attack program to obtain a target condition branch instruction. The defense module is used to generate a target state update value according to the target condition branch instruction, and update a current saturation counter state corresponding to the target condition branch instruction according to the target state update value, so as to optimize the security branch predictor based on the updated current saturation counter state. The current saturation counter state is stored in a branch history table in the security branch predictor. The application can effectively avoid the perception of the saturation counter state by an attacker, reduce the risk of malicious attacks and data leakage, improve the security and reliability of the system, and can be widely applied to the technical field of data security.

Description

Technical Field

[0001] This application relates to the field of data security technology, and in particular to a RISC-V-based secure branch predictor and its operation method. Background Technology

[0002] RISC-V is an open-source instruction set architecture based on a reduced instruction set architecture. RISC-V is designed to provide a flexible, scalable, high-performance, and low-power processor architecture. However, microarchitecture side-channel attacks are a type of attack that exploits the processor's microarchitecture state. Branch predictor-based side-channel attacks are a variant of microarchitecture side-channel attacks, primarily targeting the branch history table (BHT) of the branch predictor to steal security-critical information. This type of attack poses a significant threat to system security and also carries the risk of data leakage.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The embodiments of this application aim to at least partially address one of the technical problems in the related art. Therefore, the main objective of the embodiments of this application is to propose a secure branch predictor and its operation method based on RISC-V, which can effectively prevent attackers from perceiving the state of the saturation counter, reduce the risk of malicious attacks and data leakage, and improve the security and reliability of the system.

[0005] To achieve the above objectives, one aspect of this application proposes a RISC-V-based secure branch predictor, which is a prediction module on a RISC-V processor. The secure branch predictor includes an attack module and a defense module, wherein:

[0006] The attack module is used to simulate attack training on the initial conditional branch instruction in the secure branch predictor using a side-channel attack program in order to obtain the target conditional branch instruction.

[0007] The defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the safe branch predictor based on the updated current saturation counter state; wherein, the current saturation counter state is stored in the branch history table in the safe branch predictor.

[0008] In some embodiments, the defense module includes a storage unit, a state machine unit, and a random number generation unit, wherein:

[0009] The storage unit is used to store the first confidence data corresponding to the target conditional branch instruction; wherein, the first confidence data includes a first confidence state and a first confidence level;

[0010] The state machine unit is used to update the first confidence data to obtain the second confidence data corresponding to the target conditional branch instruction; wherein, the second confidence data includes a second confidence state and a second confidence level;

[0011] The random number generation unit is used to generate the target state update value based on the second confidence data.

[0012] In some embodiments, the target state update value is used to update the current jump direction value of the target conditional branch instruction, so as to update the current jump direction of the target conditional branch instruction.

[0013] In some embodiments, the RI SC-V processor includes an instruction fetch unit, an instruction decoding unit, and a branch jump unit, wherein the instruction fetch unit includes the safe branch predictor, wherein:

[0014] The instruction extraction unit is used to pre-decode the target conditional branch instruction to obtain target conditional branch instruction information, and read the current saturation counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, so as to predict the current predicted jump direction of the target conditional branch instruction according to the current saturation counter state, and transmit the current predicted jump direction to the branch jump unit.

[0015] The instruction decoding unit is used to obtain pre-decoded instruction information from the instruction extraction unit, and analyze the pre-decoded instruction information to obtain target instruction information, so as to transmit the target instruction information to the branch jump unit;

[0016] The branch jump unit is used to perform branch calculations based on the target instruction information to obtain the target jump direction, and compare the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

[0017] To achieve the above objectives, another aspect of this application proposes a method for operating a RI SC-V-based security branch predictor, applied to the RI SC-V-based security branch predictor as described above. The security branch predictor is a prediction module on a RI SC-V processor, and includes an attack module and a defense module. The method includes the following steps:

[0018] The attack module uses a side-channel attack program to simulate and train the initial conditional branch instruction in the secure branch predictor to obtain the target conditional branch instruction.

[0019] The defense module generates a target status update value based on the target conditional branch instruction.

[0020] The defense module updates the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, and optimizes the safe branch predictor based on the updated current saturation counter state; wherein, the current saturation counter state is stored in the branch history table in the safe branch predictor;

[0021] The optimized secure branch predictor predicts the conditional branch instructions to be predicted on the RI SC-V processor to obtain the target secure branch prediction result.

[0022] In some embodiments, the RI SC-V processor includes an instruction extraction unit, an instruction decoding unit, and a branch jump unit. The instruction extraction unit includes the secure branch predictor. Before the defense module generates the target state update value based on the target conditional branch instruction, the method further includes:

[0023] The target conditional branch instruction is input into the instruction extraction unit of the RI SC-V processor, and the instruction extraction unit pre-decodes the target conditional branch instruction to obtain the target conditional branch instruction information corresponding to the target conditional branch instruction.

[0024] The instruction extraction unit reads the current saturation counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, predicts the current predicted jump direction of the target conditional branch instruction according to the current saturation counter state, and transmits the current predicted jump direction to the branch jump unit.

[0025] The instruction decoding unit obtains the pre-decoded instruction information from the instruction extraction unit, analyzes the pre-decoded instruction information to obtain the target instruction information, and then transmits the target instruction information to the branch jump unit.

[0026] The branch jump unit calculates the target jump direction based on the target instruction information, and compares the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

[0027] In some embodiments, the defense module includes a storage unit, a state machine unit, and a random number generation unit. The storage unit stores first confidence data corresponding to the target conditional branch instruction. The first confidence data includes a first confidence state and a first confidence level. Generating a target state update value based on the target conditional branch instruction through the defense module includes:

[0028] The state machine unit updates the first confidence data based on the first confidence state and the target jump direction output by the branch jump unit to obtain the second confidence data corresponding to the target conditional branch instruction; wherein, the second confidence data includes a second confidence state and a second confidence level;

[0029] The target state update value is generated by the random number generation unit based on the second confidence data.

[0030] In some embodiments, the step of updating the current saturation counter state corresponding to the target conditional branch instruction by the defense module according to the target state update value, and optimizing the safe branch predictor based on the updated current saturation counter state, includes:

[0031] The defense module updates the current jump direction value of the target conditional branch instruction according to the target state update value, and updates the current jump direction of the target conditional branch instruction according to the current jump direction value;

[0032] The defense module updates the current saturation counter state corresponding to the target conditional branch instruction according to the updated current jump direction, and optimizes the safe branch predictor based on the updated current saturation counter state.

[0033] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method described above.

[0034] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods described above.

[0035] The embodiments of this application include at least the following beneficial effects: This application provides a secure branch predictor and its operation method based on RI SC-V. The secure branch predictor is a prediction module on an RI SC-V processor. The secure branch predictor includes an attack module and a defense module, wherein: the attack module is used to simulate attack training on the initial conditional branch instruction in the secure branch predictor using a side-channel attack program to obtain the target conditional branch instruction; the defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the secure branch predictor based on the updated current saturation counter state; wherein, the current saturation counter state is stored in the branch history table in the secure branch predictor. This application embodiment simulates side-channel attacks through an attack module, enabling the defense module to learn and adapt to the simulated attack patterns. This allows the RI SC-V processor to improve its defense against actual side-channel attacks based on a secure branch predictor. By selectively updating the current saturation counter state in the branch history table, attackers can be effectively prevented from perceiving the saturation counter state, reducing the risk of malicious attacks and data leakage, and improving the security and reliability of the system. Even in the presence of side-channel attacks, it can maintain high prediction accuracy. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of the RI SC-V-based secure branch predictor provided in the embodiments of this application;

[0037] Figure 2 This is a schematic diagram of the overall architecture of the secure branch predictor provided in the embodiments of this application;

[0038] Figure 3 This is a schematic diagram of the signal transmission process in the branch predictor provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the defense process of the security branch predictor provided in the embodiments of this application;

[0040] Figure 5 This is a schematic diagram of the state machine transition process provided in the embodiments of this application;

[0041] Figure 6 This is a flowchart of the steps of the operation method of the RI SC-V-based security branch predictor provided in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0044] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0045] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0047] Currently, in the field of chip instruction set architecture, RISC-V has received widespread attention due to the promotion of open source and the continuous development of the RISC-V ecosystem. RISC-V is an open-source instruction set architecture (ISA) based on Reduced Instruction Set Computing (RISC). RISC-V is designed to provide a flexible, scalable, high-performance, and low-power processor architecture that can be used in various fields, such as embedded systems, servers, and high-performance computing. However, RISC-V may be vulnerable to microarchitecture side-channel attacks. Microarchitecture side-channel attacks are a method of exploiting the processor's microarchitecture state to steal security-critical information. These attacks can not only steal encryption keys, monitor device input, extract browser browsing history, and crack Address Space Layout Randomization (ALSR), but also assist transient execution attacks such as Spectre and Meltdown by transmitting sensitive information obtained "transiently" through changes in the microarchitecture state to the attacker. Many performance enhancements found in current processors have not been thoroughly analyzed for security vulnerabilities, leading to various attacks. Predictors, particularly branch predictors, have been identified as sources of security vulnerabilities. Among these, the Spectre attack induces the victim to perform speculative operations that would not occur during the strict serialization of program instructions, and then leaks the victim's confidential information to the attacker through a covert channel. The Spectre-V1 attack, a variant of the Spectre attack, exploits incorrect predictions of conditional branches, primarily targeting the branch history table (BHT) of the branch predictor to steal security-critical information. This attack poses a significant threat to system security and also exposes the attacker to data breaches.

[0048] In view of this, this application provides a secure branch predictor and its operation method based on RISC-V. The secure branch predictor is a prediction module on a RISC-V processor. The secure branch predictor includes an attack module and a defense module. The attack module is used to simulate attack training on the initial conditional branch instructions in the secure branch predictor using a side-channel attack program to obtain the target conditional branch instructions. The defense module is used to generate a target state update value based on the target conditional branch instructions and update the current saturation counter state corresponding to the target conditional branch instructions based on the target state update value, so as to optimize the secure branch predictor based on the updated current saturation counter state. The current saturation counter state is stored in the branch history table in the secure branch predictor. This application provides a secure branch predictor that improves the RISC-V processor's defense capability against actual side-channel attacks by simulating side-channel attacks through the attack module, enabling the defense module to learn and adapt to the simulated attack mode. By selectively updating the current saturation counter state in the branch history table, attackers can be effectively prevented from perceiving the saturation counter state, reducing the risk of malicious attacks and data leakage, improving the security and reliability of the system, and maintaining high prediction accuracy even in the presence of side-channel attacks.

[0049] The RISC-V-based secure branch predictor and its operation method provided in this application relate to the field of data security technology. The RISC-V-based secure branch predictor operation method provided in this application can be applied to a terminal, a server, or software running on a terminal or server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, or in-vehicle terminal, but is not limited to these. The server can be configured as an independent physical server, a server cluster composed of multiple physical servers, or a distributed system. It can also be configured as a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network. The software can be an application implementing the RISC-V-based secure branch predictor operation method, but is not limited to the above forms.

[0050] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframes, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0051] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the RISC-V-based secure branch predictor provided in the embodiments of this application; Figure 1 The secure branch predictor in the text is a prediction module on a RISC-V processor. The secure branch predictor includes an attack module and a defense module, wherein:

[0052] The attack module is used to simulate attack training on the initial conditional branch instruction in the secure branch predictor using a side-channel attack program in order to obtain the target conditional branch instruction.

[0053] The defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the safe branch predictor based on the updated current saturation counter state; wherein, the current saturation counter state is stored in the branch history table in the safe branch predictor.

[0054] In practical applications, the branch predictor is a prediction module on a RISC-V processor. Similarly, the secure branch predictor provided in this embodiment is also a prediction module on a RISC-V processor. However, the secure branch predictor in this embodiment differs from traditional branch predictors. The secure branch predictor in this embodiment includes an attack module and a defense module. The attack module is used to simulate attack training on the initial conditional branch instruction in the secure branch predictor using a side-channel attack program to obtain the target conditional branch instruction. The defense module is used to generate a target state update value based on the target conditional branch instruction and update the current saturation counter state corresponding to the target conditional branch instruction based on the target state update value, so as to optimize the secure branch predictor based on the updated current saturation counter state. The current saturation counter state is stored in the branch history table in the secure branch predictor.

[0055] For a detailed implementation, please refer to Figure 2 , Figure 2 This is a schematic diagram of the overall architecture of the secure branch predictor provided in this application embodiment; the overall architecture of the secure branch predictor designed in this application embodiment for defending against Spectre-V1 attacks on a RISC-V processor is as follows. Figure 2 As shown, Defend BHT refers to the modified BHT based on the defense method proposed in the embodiments of this application, which is part of the RISC-V processor core. The RISC-V processor core is connected to peripherals via the AXI bus. The peripherals include a UART serial port and memory. The memory stores the side-channel attack program mentioned in the embodiments of this application, and the UART serial port is used to output the program running results. The system consists of two parts: attack and defense. The attack part mainly uses Spectre-V1 code adapted to the RISC-V instruction set, which is placed in the memory of the RISC-V processor's SoC (System on Chip). After the SoC boots up, it reads the program from this memory, initializes the RISC-V processor, and then executes the attack program code. The defense part mainly modifies the BHT (Branch History Table) of the RISC-V processor's branch predictor. By recording the confidence level of each conditional branch instruction jump state, the system then probabilistically adjusts the conditional branch instruction based on the confidence level to update the BHT state. This makes the BHT state invisible to attackers to a certain extent, preventing attackers from maliciously training the conditional branch instruction state. This ensures that the original functions of the RISC-V processor are not affected while protecting the RISC-V processor from Spectre-V1 attacks.

[0056] It is worth mentioning that the design of the secure branch predictor in this application embodiment is mainly aimed at the defense against Spectre-V1 attacks. However, the secure branch predictor in this application embodiment can also effectively mitigate other attacks related to speculative execution, thereby preventing security threats such as unauthorized access and data leakage. It has a certain degree of adaptability and can be widely used in various fields, such as cloud computing and network security. That is, it can be implemented in processors that use the same type of branch predictor, providing reliability and security for various user scenarios.

[0057] For side-channel attack programs, they are compiled into executable files using a compilation toolchain. The executable files are then converted into binary files using the toolchain and stored in the memory of the RISC-V processor's SoC. After the SoC starts up, the program is read from this memory, the RISC-V processor is initialized, and the attack program code is executed. The toolchain used in this application embodiment is the standard toolchain of the RISC-V architecture. The compiled executable file also contains the processor initialization program. The processor initialization program is placed in the SoC's memory, and the executable file in the memory is executed after power-on.

[0058] This application primarily targets the Spectre-V1 attack, which targets conditional branch instructions in the following form:

[0059] if (x < 16) {

[0060] sec = array1[x];

[0061] temp = array2[sec*512];}

[0062] Specifically, the simulation test process based on the Spectre-V1 attack simulation test code is as follows: Spectre-V1 uses speculative execution of conditional branch instructions. When a conditional branch instruction is speculatively executed, a subsequent load instruction will be executed, mapping the secret data sec to the address of array array2 and retrieving the value and putting it into the cache. When the conditional branch instruction is executed incorrectly, the state of the cache will not be restored, which should not happen under normal circumstances. The Spectre-V1 attack then traverses all addresses in the cache and restores the value of sec according to the different read and write times, thus reading the sec content that should not have been read in the first place.

[0063] In this embodiment, the Spectre-V1 attack requires malicious training of a conditional branch instruction, training its state to 11, representing the Taken state. Specifically, the RI SC-V processor's branch predictor uses a 2-bit saturation counter with four states: 00 (Strong Not Taken), 01 (Weak Not Taken), 10 (Weak Taken), and 11 (Strong Taken). In the Spectre-V1 attack code, to ensure that the conditional branch instruction makes incorrect predictions when executed with incorrect conditions, it is executed at least four times with correct conditions before using incorrect conditions. This ensures that the saturation counter value in the corresponding BHT of the conditional branch instruction in the branch predictor is 11, i.e., the Strong Taken state.

[0064] The initial conditional branch instruction is the original conditional branch instruction without any processing. However, in this embodiment, a side-channel attack program is required to simulate the attack training of the initial conditional branch instruction in order to obtain the target conditional branch instruction. After the simulated attack training, the target conditional branch instruction obtained in the branch predictor has a saturation counter value of 11 in the corresponding BHT (branch history table in the secure branch predictor), which is the Strong Taken state.

[0065] In some embodiments, the target state update value is used to update the current jump direction value of the target conditional branch instruction, so as to update the current jump direction of the target conditional branch instruction.

[0066] Optionally, the RI SC-V processor includes an instruction fetch unit, an instruction decoding unit, and a branch jump unit, wherein the instruction fetch unit includes the safe branch predictor.

[0067] In some embodiments, the instruction extraction unit is used to pre-decode the target conditional branch instruction to obtain target conditional branch instruction information, and read the current saturation counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, so as to predict the current predicted jump direction of the target conditional branch instruction according to the current saturation counter state, and transmit the current predicted jump direction to the branch jump unit; the instruction decoding unit is used to obtain the pre-decoded instruction information in the instruction extraction unit, and analyze the pre-decoded instruction information to obtain target instruction information, so as to transmit the target instruction information to the branch jump unit; the branch jump unit is used to perform branch calculation according to the target instruction information to obtain the target jump direction, and compare the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

[0068] In the secure branch predictor of the RI SC-V processor, the components related to conditional branch instructions are the Instruction Fetch Unit (IFU), the Instruction Decode Unit (IDU), and the Branch Jump Unit (BJU). The secure branch predictor is part of the Instruction Fetch Unit; the Instruction Fetch Unit, Instruction Decode Unit, and Branch Jump Unit are all part of the RI SC-V processor and are sub-units of the processor's top-level module.

[0069] The pre-decoding operation in the instruction fetch unit is used to determine whether an instruction is a branch instruction, thereby deciding whether to use the prediction result output by the branch predictor. If there is no branch instruction, the prediction result output by the branch predictor is not used. The instruction decoding unit obtains the pre-decoding instruction information from the instruction fetch unit. Based on this information, the instruction decoding unit can decode the specific operations required for the branch instruction, as well as the register indices or immediate values ​​used by the instruction. The instruction decoding unit can also decode the execution unit corresponding to the instruction. The instruction fetch unit directly transmits the prediction information to the branch jump unit for prediction result checking to update the BHT; therefore, the prediction information obtained by the instruction fetch unit does not need to be transmitted to the instruction decoding unit.

[0070] Please see Figure 3 , Figure 3 This is a schematic diagram of the signal transmission process in the branch predictor provided in the embodiments of this application; as shown Figure 3 As shown, Figure 3 This describes the information flow during the execution of conditional branch instructions in a RI SC-V processor, but does not include the modified BHT provided in the embodiments of this application. Figure 3 In this context, BHT refers to unmodified BHT. Figure 3 All the modules mentioned are in Figure 2 In the RI SC-V processor core, such as Figure 3As shown, the information flow transmission process for conditional branch instruction execution in the RI SC-V processor is as follows: First, the Program Counter (PC) generation section generates a PC value, retrieves the corresponding instruction from the Instruction Cache (I Cache), and performs pre-decoding. If it is a conditional branch instruction, the prediction information of the corresponding instruction is obtained from the BHT based on the pre-decoding information. Both the I Cache and BHT are located in the Instruction Cache Unit (I FU). The prediction information is then passed to the Execution Unit (BJU). Simultaneously, the Instruction Decoder (IDU) passes the decoded complete instruction information to the BJU. The BJU performs branch calculations based on this information, including whether to perform a jump and the calculation of the jump address, and checks the previous prediction. The BJU outputs the execution information to the corresponding execution unit. If the BJU finds that the previous prediction is incorrect, it triggers an instruction flow change, instructing the PC generation section to generate a new PC value and updating the saturation counter state of the corresponding conditional branch instruction in the BHT. If the prediction is correct, only the saturation counter state of the corresponding conditional branch instruction in the BHT is updated.

[0071] In its implementation, when an instruction enters the RISC-V processor, it is first pre-decoded in the Instruction Fetch Unit (IFU). If the instruction is a conditional branch instruction, the IFU will retrieve the conditional branch instruction information (i.e., the target conditional branch instruction information). This information includes the source register, the specific conditional branch instruction type (such as Branch if Equal (BEQ), Branch if Not Equal (BNE), and Branch if Less), etc. The process involves several steps: First, the instruction fetch unit (BLT) reads the saturation counter state of the corresponding conditional branch instruction from the branch history table (BHT) in the safe branch predictor based on the information of these conditional branch instructions. Then, it predicts the jump direction of the conditional branch instruction based on the saturation counter state and passes the predicted jump direction information to the instruction decode unit (IDU). The instruction decode unit obtains instruction information such as the value of the source register and passes it to the branch jump unit (BJU). The branch jump unit obtains the final jump direction of the conditional branch instruction and compares it with the prediction result (the jump direction of the conditional branch instruction) in the instruction fetch unit to determine whether pipeline redirection is needed. The final jump direction result is then returned to the instruction fetch unit, which updates the corresponding saturation counter state in the branch history table (BHT) based on the final jump direction result and confidence level of the conditional branch instruction. This ensures a more accurate prediction result for the next prediction, improving processor performance.

[0072] Optionally, the defense module includes a storage unit, a state machine unit, and a random number generation unit.

[0073] Specifically, as mentioned earlier, the attack code first trains a conditional branch instruction using condition values ​​that satisfy the branch condition, training its corresponding saturation counter state to 11, i.e., the StrongTaken state. Then, it executes the conditional branch instruction with condition values ​​that do not satisfy the branch condition, reading values ​​that shouldn't be read based on the processor's inferred execution characteristics. The defense module will simulate interference in the training process based on this characteristic.

[0074] In some embodiments, the storage unit is used to store first confidence data corresponding to the target conditional branch instruction; wherein the first confidence data includes a first confidence state and a first confidence level; the state machine unit is used to update the first confidence data to obtain second confidence data corresponding to the target conditional branch instruction; wherein the second confidence data includes a second confidence state and a second confidence level; and the random number generation unit is used to generate a target state update value based on the second confidence data.

[0075] Specifically, in the architecture of the defense module, the storage unit is designed to store the confidence state and confidence level output by the state machine unit. The confidence state and confidence level are in one-to-one correspondence. The storage unit output value[5:2] represents the confidence state of the corresponding BHT entry, and value[1:0] represents the confidence level of the corresponding BHT entry. The confidence level records the number of times a conditional branch instruction has undergone the aforementioned malicious training, while the confidence state records the intermediate behavior of the malicious training. The confidence state and confidence level are input together into the state machine unit for updating. For example, the initial stage (or intermediate stage) of the target conditional branch instruction corresponds to a first confidence state and a first confidence level. Firstly, the first confidence state and first confidence level corresponding to the target conditional branch instruction are input into the state machine unit for updating, which yields the second confidence state and second confidence level corresponding to the target conditional branch instruction. The second confidence state and second confidence level are the latest confidence state and confidence level.

[0076] In the architecture of the defense module, the state machine unit is designed to update the confidence state and confidence level of a conditional branch instruction. After receiving the confidence state and confidence level output from the storage unit, the state machine unit updates the corresponding confidence state and confidence level of the conditional branch instruction by using state machine jumps, based on the current confidence state and the jump direction of the conditional branch instruction in this execution output by the branch jump unit (BJU).

[0077] Please participate Figure 4 , Figure 4 This is a schematic diagram of the defense process of the security branch predictor provided in the embodiments of this application; as shown Figure 4 As shown, Figure 4In this context, `value` refers to the output value of the storage unit, which includes the current state (`value[5:2]`) and the current confidence (`confidence[1:0]`). `confidence` refers to the confidence level of the current conditional branch instruction, such as... Figure 4 As shown, the secure branch predictor updates the saturation counter of the conditional branch instruction in the BHT based on the execution result of the BJU. The defense mentioned in this embodiment is performed during this process. Specifically, based on the conditional branch instruction information, the state and confidence corresponding to the conditional branch instruction are read from the storage unit that stores the conditional branch instruction state and confidence, and passed to the state machine unit. At the same time, the state machine unit obtains the branch jump result output from the BJU, obtains the new state and confidence based on the branch jump result, and uses it to update the value in the storage unit. Simultaneously, the confidence is passed to the random number generation unit. The random number generation unit dynamically adjusts the inversion probability based on the confidence, determines the update value of the BHT based on the branch jump result and the inversion probability, and finally updates the saturation counter state of the corresponding conditional branch instruction in the BHT.

[0078] The state machine unit contains nine states: P1, P2, P3, P4, M1, M2, M3, M4, and IDLE. The initial state is IDLE, and the initial confidence level is 0. Please refer to [link / reference]. Figure 5 , Figure 5 This is a schematic diagram of the state machine transition process provided in the embodiments of this application; it should be noted that, Figure 5 The section on "confidence level change" provides a comprehensive explanation of the confidence level change within the "state transition" section. Specifically, for example... Figure 5 As shown, the specific implementation process of updating the confidence state and confidence level of the corresponding conditional branch instruction using state machine jumps is as follows:

[0079] When the jump direction of the input conditional branch instruction is a jump, the confidence state transitions from IDLE to P1, the state machine unit outputs confidence state P1, and the confidence level is 0; if it is a no-jump, the confidence state transitions from IDLE to M1, the state machine unit outputs confidence state M1, and the confidence level is 0. When the conditional branch instruction is executed again, if the jump direction of the input conditional branch instruction is a jump and the input confidence state is P1, the confidence state transitions to P2, and the confidence level remains unchanged; if the jump direction of the input conditional branch instruction is a jump and the input confidence state is M1, the confidence state transitions to P1, and the confidence level remains unchanged; if the jump direction of the input conditional branch instruction is a no-jump and the input confidence state is P1, the confidence state transitions to M1, and the confidence level remains unchanged; if the input conditional branch instruction... If the jump direction of the conditional branch instruction is no jump and the input confidence state is M1, the confidence state jumps to M2, and the confidence level remains unchanged. If the jump direction of the input conditional branch instruction is a jump and the input confidence state is P2, the confidence state jumps to P3, and the confidence level remains unchanged. If the jump direction of the input conditional branch instruction is a jump and the input confidence state is M2, the confidence state jumps to P1, and the confidence level remains unchanged. If the jump direction of the input conditional branch instruction is no jump and the input confidence state is M1, the confidence state jumps to M2, and the confidence level remains unchanged. If the input confidence state is P2, the confidence state jumps to M1, and the confidence level remains unchanged. If the jump direction of the input conditional branch instruction is no jump and the input confidence state is M2, the confidence state jumps to M3, and the confidence level remains unchanged. If the jump direction of the input conditional branch instruction is a jump and the input confidence state is P3, the confidence state jumps to P4, and the confidence level remains unchanged. If the jump direction of the input conditional branch instruction is a jump and the input confidence state is M3, the confidence state jumps to P1. If the input conditional branch instruction does not jump in the current execution direction and the input confidence state is P3, the confidence state jumps to M1, and the confidence remains unchanged; if the input conditional branch instruction does not jump in the current execution direction and the input confidence state is M3, the confidence state jumps to M4, and the confidence remains unchanged; if the input conditional branch instruction jumps in the current execution direction and the input confidence state is P4, the confidence state remains at P4, and the confidence remains unchanged.If the conditional branch instruction being executed in this instance results in a jump, and the input confidence state is M4, the confidence state jumps to P1, and the confidence level is incremented by 1 from the original confidence level input to the state machine unit. If the conditional branch instruction being executed in this instance results in a non-jump, and the input confidence state is P4, the confidence state jumps to M1, and the confidence level is incremented by 1 from the original confidence level input to the state machine unit. If the conditional branch instruction being executed in this instance results in a non-jump, and the input confidence state is M4, the confidence state remains unchanged at M4, and the confidence level remains unchanged.

[0080] In the specific implementation, the updated confidence state and confidence level output by the state machine unit will be returned to the storage unit to update the value in the storage unit; at the same time, the confidence level will also be transmitted to the random number generation unit to adjust the probability of the random number generation unit generating 0 or 1.

[0081] In the architecture of the defense module, the random number generation unit is designed to generate a random number that is approximately uniformly distributed. A reference value is set within the random number generation unit. When the generated random number is less than this reference value, the unit inverts the jump direction of the input conditional branch instruction and outputs it, updating the saturation counter state in the BHT entry of that conditional branch instruction. As the confidence level of the input random number generation unit changes, the reference value also changes; that is, the probability of inverting the value representing the jump direction also changes, and this probability is related to the confidence level of the conditional branch instruction.

[0082] Specifically, the jump direction value output by the random number generation unit is output to the BHT entry, replacing the original jump direction value and updating the saturation counter state corresponding to the conditional branch instruction. Since the probability of the jump direction used for updating is inverted, the saturation counter state corresponding to the conditional branch instruction in the BHT is unpredictable to the attacker, i.e., invisible, thus reducing the risk of Spectre-V1 attacks.

[0083] In this embodiment, the secure branch predictor is a prediction module on the RI SC-V processor. The secure branch predictor includes an attack module and a defense module. The attack module simulates a side-channel attack to train the initial conditional branch instruction in the secure branch predictor, obtaining a target conditional branch instruction. The defense module generates a target state update value based on the target conditional branch instruction and updates the current saturation counter state corresponding to the target conditional branch instruction based on the target state update value, thereby optimizing the secure branch predictor based on the updated current saturation counter state. The current saturation counter state is stored in the branch history table of the secure branch predictor. This embodiment simulates a side-channel attack through the attack module, enabling the defense module to learn and adapt to the simulated attack mode. This improves the RI SC-V processor's defense against actual side-channel attacks based on the secure branch predictor. By specifically updating the current saturation counter state in the branch history table, attackers can be effectively prevented from perceiving the saturation counter state, reducing the risk of malicious attacks and data leakage, improving system security and reliability, and maintaining high prediction accuracy even in the presence of side-channel attacks.

[0084] It is readily understood that this application embodiment, targeting the Branch Predictor (BHT) section of the RI SC-V processor, designs a scheme that identifies and records potential malicious training of conditional branch instructions. When malicious training is suspected, the value of the corresponding saturation counter used to update the BHT is probabilistically inverted. This effectively prevents attackers from perceiving the state of the saturation counter, reducing the risk of malicious attacks and data leakage, and improving system security and reliability. In other words, this application embodiment provides a secure branch predictor design for defending against Spectre-V1 attacks on the RI SC-V processor. While ensuring that the original functions of the RI SC-V processor are not affected, it can protect the RI SC-V processor from Spectre-V1 attacks. Furthermore, the secure branch predictor design provided in this application embodiment can also effectively mitigate other speculative execution attacks, preventing unauthorized access and data leakage, among other security threats.

[0085] Please see Figure 6 , Figure 6 This is an optional flowchart of the operation method of the RI SC-V-based security branch predictor provided in the embodiments of this application, which is applied to, for example... Figure 1 A RI SC-V-based security branch predictor, wherein the security branch predictor is a prediction module on a RI SC-V processor, and the security branch predictor includes an attack module and a defense module. Figure 6 The method may include, but is not limited to, steps S601 to S604.

[0086] Step S601: The attack module uses a side-channel attack program to simulate and train the initial conditional branch instruction in the secure branch predictor to obtain the target conditional branch instruction.

[0087] Step S602: The defense module generates a target state update value according to the target conditional branch instruction;

[0088] Optionally, the RI SC-V processor includes an instruction fetch unit, an instruction decode unit, and a branch jump unit, wherein the instruction fetch unit includes a safe branch predictor.

[0089] In some embodiments, before step S602, the method may further include: inputting the target conditional branch instruction into the instruction extraction unit of the RI SC-V processor; pre-decoding the target conditional branch instruction through the instruction extraction unit to obtain target conditional branch instruction information corresponding to the target conditional branch instruction; reading the current saturation counter state corresponding to the target conditional branch instruction in the branch history table through the instruction extraction unit based on the target conditional branch instruction information, predicting the current predicted jump direction of the target conditional branch instruction based on the current saturation counter state, and transmitting the current predicted jump direction to the branch jump unit; obtaining the pre-decoded instruction information from the instruction extraction unit through the instruction decoding unit, analyzing the pre-decoded instruction information to obtain target instruction information, and transmitting the target instruction information to the branch jump unit; performing branch calculations based on the target instruction information through the branch jump unit to obtain the target jump direction, and comparing the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

[0090] Optionally, the defense module includes a storage unit, a state machine unit, and a random number generation unit. The storage unit stores the first confidence data corresponding to the target conditional branch instruction; wherein, the first confidence data includes a first confidence state and a first confidence level.

[0091] In some embodiments, step S602 may include: updating the first confidence data by the state machine unit according to the first confidence state and the target jump direction output by the branch jump unit to obtain the second confidence data corresponding to the target conditional branch instruction; wherein, the second confidence data includes the second confidence state and the second confidence level; and generating a target state update value by the random number generation unit according to the second confidence data.

[0092] Step S603: The defense module updates the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, and optimizes the safe branch predictor based on the updated current saturation counter state; wherein, the current saturation counter state is stored in the branch history table in the safe branch predictor;

[0093] In some embodiments, step S603 may include: updating the current jump direction value of the target conditional branch instruction according to the target state update value through the defense module, and updating the current jump direction of the target conditional branch instruction according to the current jump direction value; updating the current saturation counter state corresponding to the target conditional branch instruction according to the updated current jump direction through the defense module, and optimizing the safe branch predictor based on the updated current saturation counter state.

[0094] Step S604: The optimized safe branch predictor predicts the conditional branch instruction to be predicted on the RISC-V processor to obtain the target safe branch prediction result.

[0095] In the specific implementation, the attack module uses a side-channel attack program to simulate and train the initial conditional branch instruction in the secure branch predictor to obtain the target conditional branch instruction. The defense module generates a target state update value based on the target conditional branch instruction and updates the current saturation counter state corresponding to the target conditional branch instruction based on this update value. The secure branch predictor is then optimized based on the updated current saturation counter state. Finally, the optimized secure branch predictor predicts the conditional branch instruction to be predicted on the RISC-V processor to obtain the target secure branch prediction result. By designing a scheme to identify and record potential malicious training scenarios for conditional branch instructions, the secure branch predictor is trained to obtain the optimized version. When malicious training is suspected, the optimized secure branch predictor inverts the probability when updating the corresponding saturation counter value in the BHT, effectively preventing attackers from perceiving the saturation counter state, reducing the risk of malicious attacks and data leakage, and improving the system's security and reliability.

[0096] Steps S601 to S604, as illustrated in this embodiment, involve the attack module using a side-channel attack program to simulate an attack training on the initial conditional branch instruction in the secure branch predictor to obtain the target conditional branch instruction; the defense module generating a target state update value based on the target conditional branch instruction; the defense module updating the current saturation counter state corresponding to the target conditional branch instruction based on the target state update value, and optimizing the secure branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in the branch history table in the secure branch predictor; and the optimized secure branch predictor predicts the conditional branch instruction to be predicted on the RISC-V processor to obtain the target secure branch prediction result. This application embodiment simulates side-channel attacks through an attack module, enabling the defense module to learn and adapt to the simulated attack patterns. This allows the RISC-V processor to improve its defense against actual side-channel attacks based on a secure branch predictor. By specifically updating the current saturation counter state in the branch history table, attackers can be effectively prevented from sensing the saturation counter state, reducing the risk of malicious attacks and data leakage, and improving the system's security and reliability. Finally, predicting the conditional branch instructions to be predicted based on the optimized secure branch predictor can reduce the risk of malicious attacks and data leakage, and maintain high prediction accuracy even in the presence of side-channel attacks.

[0097] It should be noted that this embodiment only provides a brief illustrative description of the general flow of the operation method of the RISC-V-based secure branch predictor. For detailed descriptions of each step, please refer to the relevant content in the aforementioned RISC-V-based secure branch predictor embodiment. It will not be repeated here. It is understood that the present invention does not limit this.

[0098] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method for operating a RISC-V-based secure branch predictor. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0099] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0100] Please see Figure 7 , Figure 7 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes:

[0101] The processor 701 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0102] The memory 702 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 702 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 702 and is called and executed by the processor 701 to run the RISC-V-based safe branch predictor operation method of the embodiments of this application.

[0103] The input / output interface 703 is used to implement information input and output;

[0104] The communication interface 704 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0105] Bus 705 transmits information between various components of the device (e.g., processor 701, memory 702, input / output interface 703, and communication interface 704);

[0106] The processor 701, memory 702, input / output interface 703, and communication interface 704 are connected to each other within the device via bus 705.

[0107] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for operating a RISC-V-based secure branch predictor.

[0108] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0109] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0110] This application provides a secure branch predictor and its operation method based on RI SC-V. The secure branch predictor is a prediction module on the RI SC-V processor, comprising an attack module and a defense module. The attack module simulates a side-channel attack to train the initial conditional branch instruction in the secure branch predictor, obtaining a target conditional branch instruction. The defense module generates a target state update value based on the target conditional branch instruction and updates the current saturation counter state corresponding to the target conditional branch instruction based on the target state update value, thereby optimizing the secure branch predictor based on the updated current saturation counter state. The current saturation counter state is stored in a branch history table within the secure branch predictor. This application simulates a side-channel attack through the attack module, enabling the defense module to learn and adapt to the simulated attack mode. This improves the RI SC-V processor's defense against actual side-channel attacks based on the secure branch predictor. By specifically updating the current saturation counter state in the branch history table, attackers can be effectively prevented from perceiving the saturation counter state, reducing the risk of malicious attacks and data leakage, and improving system security and reliability. Even in the presence of side-channel attacks, high prediction accuracy is maintained.

[0111] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0112] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0113] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0114] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0115] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0116] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0117] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0118] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0119] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0120] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0121] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A RISC-V-based secure branch predictor, wherein the secure branch predictor is a prediction module on a RISC-V processor, characterized in that, The security branch predictor includes an attack module and a defense module, wherein: The attack module is used to simulate attack training on the initial conditional branch instruction in the secure branch predictor using a side-channel attack program in order to obtain the target conditional branch instruction. The defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the safe branch predictor based on the updated current saturation counter state; wherein, the current saturation counter state is stored in the branch history table in the safe branch predictor; The defense module includes a storage unit, a state machine unit, and a random number generation unit, wherein: The storage unit is used to store the first confidence data corresponding to the target conditional branch instruction; wherein, the first confidence data includes a first confidence state and a first confidence level; The state machine unit is used to obtain the branch jump result output by the branch jump unit in the RISC-V processor, and update the first confidence data according to the branch jump result to obtain the second confidence data corresponding to the target conditional branch instruction; wherein, the second confidence data includes a second confidence state and a second confidence level; The random number generation unit is used to dynamically adjust the inversion probability according to the second confidence level, and to determine the target state update value according to the branch jump result and the adjusted inversion probability; wherein, the current saturation counter state updated based on the target state update value stored in the branch history table cannot be predicted by the attacker, and the inversion probability is used to characterize the probability of the value of the conditional branch instruction jump direction being inverted.

2. The RISC-V-based secure branch predictor according to claim 1, characterized in that, The target state update value is used to update the current jump direction value of the target conditional branch instruction, so as to update the current jump direction of the target conditional branch instruction.

3. The RISC-V-based secure branch predictor according to claim 1, characterized in that, The RISC-V processor includes an instruction fetch unit, an instruction decoding unit, and a branch jump unit. The instruction fetch unit includes the safe branch predictor, wherein: The instruction extraction unit is used to pre-decode the target conditional branch instruction to obtain target conditional branch instruction information, and read the current saturation counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, so as to predict the current predicted jump direction of the target conditional branch instruction according to the current saturation counter state, and transmit the current predicted jump direction to the branch jump unit. The instruction decoding unit is used to obtain pre-decoded instruction information from the instruction extraction unit, and analyze the pre-decoded instruction information to obtain target instruction information, so as to transmit the target instruction information to the branch jump unit; The branch jump unit is used to perform branch calculations based on the target instruction information to obtain the target jump direction, and compare the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

4. A method for operating a RISC-V-based secure branch predictor, applied to the RISC-V-based secure branch predictor as described in any one of claims 1-3, wherein the secure branch predictor is a prediction module on a RISC-V processor, characterized in that, The security branch predictor includes an attack module and a defense module, and the method includes the following steps: The attack module uses a side-channel attack program to simulate and train the initial conditional branch instruction in the secure branch predictor to obtain the target conditional branch instruction. The defense module generates a target status update value based on the target conditional branch instruction. The defense module updates the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, and optimizes the safe branch predictor based on the updated current saturation counter state; wherein, the current saturation counter state is stored in the branch history table in the safe branch predictor; The optimized safe branch predictor predicts the conditional branch instructions to be predicted on the RISC-V processor to obtain the target safe branch prediction result. The defense module includes a storage unit, a state machine unit, and a random number generation unit. The storage unit stores first confidence data corresponding to the target conditional branch instruction. The first confidence data includes a first confidence state and a first confidence level. Generating a target state update value based on the target conditional branch instruction through the defense module includes: The branch jump result output by the branch jump unit in the RISC-V processor is obtained through the state machine unit, and the first confidence data is updated according to the branch jump result to obtain the second confidence data corresponding to the target conditional branch instruction; wherein, the second confidence data includes a second confidence state and a second confidence level; The random number generation unit dynamically adjusts the inversion probability based on the second confidence level, and determines the target state update value based on the branch jump result and the adjusted inversion probability; wherein, the current saturation counter state updated based on the target state update value stored in the branch history table cannot be predicted by the attacker, and the inversion probability is used to characterize the probability of the value of the conditional branch instruction jump direction being inverted.

5. The method according to claim 4, characterized in that, The RISC-V processor includes an instruction fetching unit, an instruction decoding unit, and a branch jump unit. The instruction fetching unit includes the secure branch predictor. Before the defense module generates the target state update value based on the target conditional branch instruction, the method further includes: The target conditional branch instruction is input into the instruction extraction unit of the RISC-V processor, and the instruction extraction unit pre-decodes the target conditional branch instruction to obtain the target conditional branch instruction information corresponding to the target conditional branch instruction. The instruction extraction unit reads the current saturation counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, predicts the current predicted jump direction of the target conditional branch instruction according to the current saturation counter state, and transmits the current predicted jump direction to the branch jump unit. The instruction decoding unit obtains the pre-decoded instruction information from the instruction extraction unit, analyzes the pre-decoded instruction information to obtain the target instruction information, and then transmits the target instruction information to the branch jump unit. The branch jump unit calculates the target jump direction based on the target instruction information, and compares the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

6. The method according to claim 4, characterized in that, The step of updating the current saturation counter state corresponding to the target conditional branch instruction by the defense module according to the target state update value, and optimizing the safe branch predictor based on the updated current saturation counter state, includes: The defense module updates the current jump direction value of the target conditional branch instruction according to the target state update value, and updates the current jump direction of the target conditional branch instruction according to the current jump direction value; The defense module updates the current saturation counter state corresponding to the target conditional branch instruction according to the updated current jump direction, and optimizes the safe branch predictor based on the updated current saturation counter state.

7. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method according to any one of claims 4 to 6.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 4 to 6.

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