Radiation-resistant chip design method, device, computer equipment and storage medium

Abstract

In order to solve the problems of large area consumption, long cycle, high cost and low radiation resistance performance in the design of radiation-resistant chips in the prior art, the present invention proposes a radiation-resistant chip design method, device, computer equipment and storage medium. The method includes: finding the maximum distance between Tap Cell and standard cell; finding the insertion distance of SEL-resistant Tap Cell by establishing a device-level SEL simulation model containing Tap Cell; finding the insertion spacing of both SEL-resistant and SET-resistant Tap Cell by establishing a cell-level SET simulation model, and using it as a basis for re-layout of Tap Cell and standard cell in the layout to complete the chip layout design. This design method utilizes the property that the insertion spacing of Tap Cell causes differences in SEL and SET sensitivity, which improves the radiation resistance of the designed chip while taking into account the cost and cycle of the design.

Description

Technical Field

[0001] The present invention relates to the field of chip design, in particular to the field of radiation-resistant chip design, and specifically to a radiation-resistant chip design method, device, computer equipment and storage medium. Background Art

[0002] The radiation environment in space is composed of galactic cosmic rays, solar cosmic rays, and the Earth's radiation belt. Taking galactic cosmic rays as an example, regardless of whether the solar activity is the highest or lowest year, its composition always contains different types of high-energy heavy ions. The electronic systems and equipment of spacecraft are extremely vulnerable to the bombardment of these high-energy heavy ions when operating in orbit, which in turn causes single event latchup (SEL) and single event transient (SET), which seriously threaten the reliability of aerospace equipment, reduce the service life of aerospace equipment, and even damage the spacecraft. Specifically, the thyristor conduction phenomenon caused by SEL will cause a continuous large current. If it is not effectively contained, it will directly burn the aerospace chip; the transient pulse caused by SET will not only cause chip soft errors, but also spread through the layers inside the chip, and may also propagate to the timing storage unit, causing the chip output to flip abnormally, and a single event upset (SEU) will occur, causing irreparable losses. Therefore, aerospace chips must be designed to be radiation-resistant to prevent single-particle latch-up (hereinafter referred to as anti-SEL) and single-particle transient (hereinafter referred to as anti-SET) phenomena and improve their reliability in space environments.

[0003] Traditional radiation-resistant chip design starts from the bottom layer of the chip and reinforces the standard cells. Specifically, for SEL, standard cells are often protected by increasing well contacts and substrate contacts, increasing the distance between PMOS and NMOS tubes, etc.; for SET, standard cells can be mitigated by using technologies such as guard rings, ring gates, and checkerboard reinforcement. However, the above radiation-resistant strategies have increased the commercial library area of ​​the original process manufacturer to varying degrees. In addition, the reinforcement design of standard cells will inevitably lead to layout modifications, so it is necessary to re-extract the library exchange format (lef) files and library logic description (lib) files of all cells, resulting in unnecessary manpower and material investment. Under the condition of ensuring the chip's radiation resistance, whether it is the increase in the commercial library area or the modification of the layout of the reinforcement design that brings more manpower and material investment, it has increased the development cycle and cost.

[0004] On the other hand, in advanced process nodes, where integration is high and tape-out is expensive, area becomes the primary consideration. Advanced process nodes bring lower supply voltages and higher operating frequencies, so SET must be effectively protected, and the phenomenon of single-particle hard damage such as unrecoverable SEL burning the chip must also be avoided.

[0005] Tap Cell is a special physical unit. Its main function is to reduce the parasitic resistance of the substrate by applying bias voltage to the substrate at a fixed interval, so that the chip cannot meet the conduction requirements, thereby cutting off the positive feedback loop of the latch effect and eliminating the latch effect. As a unit that comes with the commercial library, Tap Cell not only provides VDD and VSS potentials for the body end of the MOS tube, but also has more flexibility in reinforcement design. Summary of the invention

[0006] In view of this, in order to solve the problems of long design cycle, high cost and low radiation resistance in the prior art, the present invention provides a radiation-resistant chip design method, device, computer equipment and storage medium. The radiation-resistant chip design method can effectively improve the chip's radiation resistance and has the characteristics of small area overhead, short cycle and low cost.

[0007] A method for designing a radiation-resistant chip, comprising:

[0008] Step S110: Determine the Tap Cell layout insertion rule during chip backend design based on the process design file provided by the process manufacturer, and obtain the maximum distance value between the Tap Cell and the standard cell based on the Tap Cell layout insertion rule. ;

[0009] Step S120: Building a device-level SEL simulation model containing Tap Cells and using the maximum distance value , find the Tap Cell insertion distance that meets the anti-SEL requirements ;

[0010] Step S130: Building a unit-level SET simulation model containing Tap Cells and using the Tap Cells to insert distance , obtain the Tap Cell insertion spacing that meets both SEL and SET requirements ;

[0011] Step S140: insert the spacing according to the Tap Cell Tap Cells are staggered in the chip layout, and EDA tools are used to complete the layout and routing of other standard cells in the chip layout to form the overall chip layout design.

[0012] Specifically, the process design file includes design rules or design guidelines.

[0013] Specifically, in step S120, a device-level SEL simulation model containing Tap Cell is constructed, and the maximum distance value is used. , find the Tap Cell insertion distance that meets the anti-SEL requirements The process includes:

[0014] Step S121: By extracting the device parameters of the commercial netlist, the device-level SEL simulation model containing the Tap Cell is constructed; the device-level SEL simulation model is an inverter, and the device parameters of the commercial netlist extracted include the worst parameter conditions of the transistor: the distance L between the PMOS tube and the NMOS tube is the smallest, the length of the active area of ​​the PMOS tube is He Kuan Take the maximum, the length of the active area of ​​the NMOS tube He Kuan Also take the maximum;

[0015] Step S122: Using the maximum distance value , the device-level SEL simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion distance that meets the anti-SEL requirements .

[0016] Specifically, in step S130, a unit-level SET simulation model containing Tap Cell is constructed, and the Tap Cell insertion distance is used. , obtain the Tap Cell insertion spacing that meets both SEL and SET requirements The process includes:

[0017] Step S131: constructing the cell-level SET simulation model containing Tap Cells, wherein the cell-level SET simulation model satisfies: a standard cell is surrounded by staggered Tap Cells; and when P-well and N-well are not considered, the model is symmetrical left and right and up and down;

[0018] Step S132: Using the Tap Cell to insert the distance , the unit-level SET simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion spacing that meets both the anti-SEL and anti-SET requirements .

[0019] Preferably, use the variable represents the distance between the Tap Cell and the standard cell, then in step S122, the maximum distance value is used , the device-level SEL simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion distance that meets the anti-SEL requirements The process includes:

[0020] Set the SEL threshold to , set the maximum distance value As The initial value of the search step and set the search step size for one operation ;

[0021] Search step size as described Reduce the distance between Tap Cell and standard cell and update the ;

[0022] The SEL threshold is used to determine the latching condition of the standard unit of the simulation chip at this time: if the source current of the PMOS tube in the standard unit of the simulation chip decreases over time until it disappears, it is determined that the SEL threshold meets the standard; if the source current of the PMOS tube in the standard unit of the simulation chip does not change significantly over time, it is determined that the SEL threshold does not meet the standard, and the process returns to the previous step and continues to search by step length. Execute the next operation until the SEL threshold is reached;

[0023] When the SEL threshold is reached, the operation ends. The value of is the Tap Cell insertion distance that meets the anti-SEL requirement. .

[0024] Preferably, use the variable represents the distance between two Tap Cells, then in step S132, the distance is inserted using the Tap Cell , the unit-level SET simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion spacing that meets both the anti-SEL and anti-SET requirements The process includes:

[0025] Set the SET threshold to , set the Tap Cell insertion distance The four times value of The initial value of the search step and set the search step size for one operation ;

[0026] by After the transient pulse width simulation is performed on all standard cells, the transient sensitivity is sorted according to the pulse width. The larger the pulse width, the stronger the sensitivity and the worse the anti-SET performance. The standard cell with the largest pulse width is taken as the most sensitive cell, and only the most sensitive cell is subjected to subsequent SET simulation.

[0027] Search step size as described Reduce the distance between the two Tap Cells and update the ;

[0028] The SET threshold is used to determine whether the simulation chip meets the SET resistance requirement at this time: if the most sensitive unit in the simulation chip is at any position between two Tap Cells, the transient pulse width generated is less than , then it is determined that the SET threshold meets the standard; if the most sensitive unit in the simulation chip is at any position between two Tap Cells, the transient pulse width generated is not all less than , it is determined that the SET threshold has not been met, and the search is continued at the previous step. Execute the next operation until the SET threshold is reached;

[0029] When the SET threshold is reached, the operation ends. The value of is the Tap Cell insertion spacing that meets both the SEL and SET requirements. .

[0030] Furthermore, the simulation software is simulation software that implements corresponding simulation functions in a semiconductor device simulation tool.

[0031] The present invention provides a radiation-resistant chip design device, which designs a radiation-resistant chip using the steps of the above method, and the device includes the following modules:

[0032] The first module is used to determine the TapCell layout insertion rules during chip backend design based on the process design files provided by the process manufacturer, and obtain the maximum distance value between the Tap Cell and the standard cell based on the Tap Cell layout insertion rules. ;

[0033] The second module is used to build a device-level SEL simulation model containing Tap Cell and use the maximum distance value , find the Tap Cell insertion distance that meets the anti-SEL requirements ;

[0034] The third module is used to build a unit-level SET simulation model containing Tap Cell and use the TapCell to insert the distance , obtain the Tap Cell insertion spacing that meets both SEL and SET requirements ;

[0035] The fourth module is used to insert the spacing according to the Tap Cell TapCells are staggered in the chip layout, and EDA tools are used to complete the layout and routing of other standard cells in the chip layout to form the layout design of the entire chip.

[0036] The present invention also protects a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the aforementioned radiation-resistant chip design method when executing the computer program.

[0037] In addition, the present invention protects a storage medium having a computer program stored thereon, which implements the steps of the aforementioned radiation-resistant chip design method when executed by a processor.

[0038] In summary, the present invention provides a method, device, computer equipment and storage medium for designing a radiation-resistant chip. Compared with the prior art, the design method of the present invention is based on the design rules or design guidelines of the process manufacturer, and utilizes the properties of the different Tap Cell insertion distances that cause differences in the SEL and SET sensitivities of the standard cells, to find the Tap Cell insertion spacing that meets both the anti-SEL and anti-SET requirements, and feeds back the Tap Cell insertion spacing setting to the chip layout and design, so that the anti-radiation performance of the chip is improved while taking into account the design cost and design cycle, and is easy to implement computer program-aided design. Therefore, the method of the present invention ensures that the anti-radiation performance of the chip design is improved, and also has the characteristics of short cycle, low cost and flexible configuration, and can be applied to aviation, aerospace and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a process of designing a radiation-resistant chip based on Tap Cell provided in the first embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of a device-level SEL simulation model in the second embodiment of the present invention, wherein: is the length of the active area of ​​the PMOS tube. is the width of the active area of ​​the PMOS tube, is the length of the active area of ​​the NMOS tube, is the width of the active area of ​​the NMOS tube, D represents the current outflow end of the PMOS tube or NMOS tube, and S represents the current inflow end of the PMOS tube or NMOS tube;

[0041] Figure 3 This is a schematic diagram of a unit-level SET simulation model in the second embodiment of the present invention, wherein: is the distance between the Tap Cell and the standard cell, is the distance between two Tap Cells;

[0042] Figure 4 is a curve diagram of the change of the PMOS source current when SEL occurs or not in the second embodiment of the present invention, wherein (a) is the change of the PMOS source current over time when SEL does not occur, and (b) is the change of the PMOS source current over time when SEL occurs;

[0043] Figure 5 FIG. 1 is a schematic diagram of transient pulse width variation of a buffer unit under different Tap Cell insertion spacings under a 55 nm process node provided in the second embodiment of the present invention, wherein the dotted line is the Tap Cell insertion spacing of The curve of the transient pulse width change of the buffer unit when the solid line is the insertion spacing of the Tap Cell The transient pulse width change curve of the Buffer unit when

[0044] Figure 6 The flowchart of the algorithm implemented by a computer program according to the steps of the method for designing a radiation-resistant chip described in the second embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0046] In a first embodiment, the present invention provides a method for designing a radiation-resistant chip, such as Figure 1 As shown, the method comprises the following steps:

[0047] Step S110: Determine the Tap Cell layout insertion rule during chip backend design based on the process design file provided by the process manufacturer, and obtain the maximum distance value between the Tap Cell and the standard cell based on the Tap Cell layout insertion rule. ;

[0048] Step S120: Building a device-level SEL simulation model containing Tap Cells and using the maximum distance value , find the Tap Cell insertion distance that meets the anti-SEL requirements ;

[0049] Step S130: Building a unit-level SET simulation model containing Tap Cells and using the Tap Cells to insert distance , obtain the Tap Cell insertion spacing that meets both SEL and SET requirements ;

[0050] Step S140: insert the spacing according to the Tap Cell Tap Cells are staggered in the chip layout, and EDA tools are used to complete the layout and routing of other standard cells in the chip layout to form the overall chip layout design.

[0051] Specifically, in step S110, the process design file includes design rules or design guidelines.

[0052] In the second embodiment of the present invention, the device-level SEL simulation model is selected as follows: Figure 2 The inverter shown. And because SEL is a local effect, SEL sensitivity is closely related to the size of the active area and the distance between the PMOS tube and the NMOS tube. The active area size includes: the length of the active area of ​​the PMOS tube He Kuan , the length of the active area of ​​the NMOS tube He Kuan Therefore, in step S120, a device-level SEL simulation model containing Tap Cell is constructed, and the maximum distance value is used. , find the Tap Cell insertion distance that meets the anti-SEL requirements The process includes:

[0053] Step S121: By extracting the device parameters of the commercial netlist, the device-level SEL simulation model containing Tap Cell is constructed; the device-level SEL simulation model is an inverter, and the device parameters of the commercial netlist extracted include the worst parameter conditions of the transistor: the distance L between the PMOS tube and the NMOS tube is the smallest, the length of the active area of ​​the PMOS tube is He Kuan Take the maximum, the length of the active area of ​​the NMOS tube He Kuan Also take the maximum;

[0054] Step S122: Using the maximum distance value , the device-level SEL simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion distance that meets the anti-SEL requirements .

[0055] Further, in step S130, a unit-level SET simulation model containing Tap Cell is constructed, and the Tap Cell insertion distance is used , obtain the Tap Cell insertion spacing that meets both SEL and SET requirements The process includes:

[0056] Step S131: Building the unit-level SET simulation model containing Tap Cell, such as Figure 3 As shown, the cell-level SET simulation model satisfies: the standard cell is surrounded by staggered Tap Cells; when the P-well and N-well are not considered, the model is symmetrical left and right and up and down;

[0057] Step S132: Using the Tap Cell to insert the distance , the unit-level SET simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion spacing that meets both the anti-SEL and anti-SET requirements .

[0058] Preferably, use the variable represents the distance between the Tap Cell and the standard cell, then in step S122, the maximum distance value is used , through simulation software similar to semiconductor simulation tools, the device-level SEL simulation model containing Tap Cell is simulated and solved to find the Tap Cell insertion distance that meets the anti-SEL requirements The process includes:

[0059] Set the SEL threshold to , set the maximum distance value As The initial value of the search step and set the search step size for one operation ;

[0060] Search step size as described Reduce the distance between Tap Cell and standard cell and update the ;

[0061] The SEL threshold is used to determine the latching status of the standard cell of the simulation chip at this time: Figure 4 As shown in (a) in FIG. 1 , if the source current of the PMOS tube in the standard unit of the simulation chip decreases over time until it disappears, indicating that SEL does not occur, then it is determined that the SEL threshold meets the standard; Figure 4As shown in (b), if the source current of the PMOS tube in the standard unit of the simulation chip does not decrease significantly over time, it is determined that the SEL threshold fails to meet the standard, and the search step is continued according to the previous step. Execute the next operation until the SEL threshold is reached;

[0062] When the SEL threshold is reached, the operation ends. The value of is the Tap Cell insertion distance that meets the anti-SEL requirement. .

[0063] Furthermore, under different Tap Cell insertion spacing values, the transient pulse width of the standard cell varies with the Changes due to changes such as Figure 5 shown. Figure 5 Specifically, the transient pulse width variation under a 55 nm process node is given. By changing the Tap Cell insertion spacing , causing the transient pulse width of the Buffer unit to increase as It can be seen that the maximum transient pulse width of the standard unit is generally between two Tap Cells, and as the distance between Tap Cells decreases, the maximum transient pulse width also decreases.

[0064] Using variables represents the distance between two Tap Cells. According to the above-mentioned law that the transient pulse width changes with the change of the Tap Cell insertion spacing, preferably, in step S132, the Tap Cell insertion distance is used. , through simulation software similar to that in semiconductor device simulation tools, the cell-level SET simulation model containing Tap Cell is simulated and solved to find the Tap Cell insertion spacing that meets both the anti-SEL and anti-SET requirements The process includes:

[0065] Set the SET threshold to , set the Tap Cell insertion distance The four times value of The initial value of the search step and set the search step size for one operation ;

[0066] by The initial value of the transient pulse width is used to simulate all standard cells, and then the transient sensitivity is sorted according to the pulse width. The larger the pulse width, the stronger the sensitivity and the worse the anti-SET performance. The standard cell with the largest pulse width is taken as the most sensitive cell, and only the most sensitive cell is subjected to subsequent SET simulation.

[0067] Search step size as described Reduce the distance between the two Tap Cells and update the ;

[0068] The SET threshold is used to determine whether the simulation chip meets the SET resistance requirement at this time: if the most sensitive unit in the simulation chip is at any position between two Tap Cells, the transient pulse width generated is less than , then it is determined that the SET threshold meets the standard; if the most sensitive unit in the simulation chip is at any position between two Tap Cells, the transient pulse width generated is not all less than , it is determined that the SET threshold has not been met, and the search is continued at the previous step. Execute the next operation until the SET threshold is reached;

[0069] When the SET threshold is reached, the operation ends. That is, the Tap Cell insertion spacing that meets both the SEL and SET requirements. .

[0070] The radiation-resistant chip design methods described in the first embodiment and the second embodiment are based on the existing advanced commercial process. Instead of changing the original commercial cell library, the different properties of the SEL and SET sensitivities of the standard cell caused by the different Tap Cell insertion distances are used to find the Tap Cell insertion spacing that meets the requirements of both anti-SEL and anti-SET. Then, the insertion spacing information is fed back to the standard cell layout design, which can significantly improve the chip's radiation resistance and achieve the purpose of meeting practical engineering applications. Compared with the previous radiation-resistant chip design method that reinforces the commercial cell itself, it avoids the circuit design and layout drawing process of the radiation-resistant standard cell one by one, is easy to implement computer program-aided design, has the characteristics of flexible configuration, and greatly saves labor costs and time costs, shortens the design cycle, and improves design efficiency. The radiation-resistant chip method in the present invention has the characteristics of high flexibility, small area overhead, low cost, and short cycle, and also has a significant improvement in the chip's radiation resistance performance, and can be applied to multiple application fields such as aviation and aerospace.

[0071] In another embodiment of the present invention, a radiation-resistant chip design device is provided, wherein the device is used to design a radiation-resistant chip using the above method, and the device specifically includes the following modules:

[0072] The first module is used to determine the TapCell layout insertion rules during chip backend design based on the process design files provided by the process manufacturer, and obtain the maximum distance value between the Tap Cell and the standard cell based on the Tap Cell layout insertion rules. ;

[0073] The second module is used to build a device-level SEL simulation model containing Tap Cell and use the maximum distance value , find the Tap Cell insertion distance that meets the anti-SEL requirements ;

[0074] The third module is used to build a unit-level SET simulation model containing Tap Cell and use the TapCell to insert the distance , obtain the Tap Cell insertion spacing that meets both SEL and SET requirements ;

[0075] The fourth module is used to insert the spacing according to the Tap Cell TapCells are staggered in the chip layout, and EDA tools are used to complete the layout and routing of other standard cells in the chip layout to form the layout design of the entire chip.

[0076] In one embodiment, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the aforementioned radiation-resistant chip design method when executing the computer program. The computer device may be a server. The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store sample data. The network interface of the computer device is used to communicate with an external terminal via a network connection.

[0077] Preferably, according to the steps of the radiation-resistant chip design method described in the second embodiment, the algorithm flow implemented by the computer program is as follows: Figure 6 shown.

[0078] On the other hand, in one embodiment, the present invention protects a storage medium having a computer program stored thereon, wherein the computer program implements the steps of the aforementioned radiation-resistant chip design method when executed by a processor.

[0079] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0080] Matters not covered by the present invention are known technologies.

[0081] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A method for designing a radiation-resistant chip, characterized in that: include: Step S110: Determine the Tap Cell layout insertion rule during chip backend design based on the process design file provided by the process manufacturer, and obtain the maximum distance value between the Tap Cell and the standard cell based on the Tap Cell layout insertion rule. ; Step S120: Building a device-level SEL simulation model containing Tap Cells and using the maximum distance value , find the Tap Cell insertion distance that meets the anti-SEL requirements ; Step S130: Building a unit-level SET simulation model containing Tap Cells and using the Tap Cells to insert distance , obtain the Tap Cell insertion spacing that meets both SEL and SET requirements ; Step S140: insert the spacing according to the Tap Cell Tap Cells are staggered in the chip layout, and EDA tools are used to complete the layout and routing of other standard cells in the chip layout to form the overall chip layout design.

2. The method for designing a radiation-resistant chip according to claim 1, characterized in that: The process design file includes design rules or design guidelines.

3. The method for designing a radiation-resistant chip according to claim 2, characterized in that: In step S120, a device-level SEL simulation model containing Tap Cell is constructed and the maximum distance value is used. , find the Tap Cell insertion distance that meets the anti-SEL requirements The process includes: Step S121: By extracting the device parameters of the commercial netlist, the device-level SEL simulation model containing the Tap Cell is constructed; the device-level SEL simulation model is an inverter, and the device parameters of the commercial netlist extracted include the worst parameter conditions of the transistor: the distance L between the PMOS tube and the NMOS tube is the smallest, the length of the active area of ​​the PMOS tube is He Kuan Take the maximum, the length of the active area of ​​the NMOS tube He Kuan Also take the maximum; Step S122: Using the maximum distance value , the device-level SEL simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion distance that meets the anti-SEL requirements .

4. The method for designing a radiation-resistant chip according to claim 3, characterized in that: In step S130, a unit-level SET simulation model containing Tap Cell is constructed, and the Tap Cell insertion distance is used. , obtain the Tap Cell insertion spacing that meets both SEL and SET requirements The process includes: Step S131: constructing the cell-level SET simulation model containing Tap Cells, wherein the cell-level SET simulation model satisfies: a standard cell is surrounded by staggered Tap Cells; and when P-well and N-well are not considered, the model is symmetrical left and right and up and down; Step S132: Using the Tap Cell to insert the distance , the unit-level SET simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion spacing that meets both the anti-SEL and anti-SET requirements .

5. The method for designing a radiation-resistant chip according to claim 4, characterized in that: Using variables represents the distance between the Tap Cell and the standard cell, then in step S122, the maximum distance value is used , the device-level SEL simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion distance that meets the anti-SEL requirements The process includes: Set the SEL threshold to , set the maximum distance value As The initial value of the search step and set the search step size for one operation ; Search step size as described Reduce the distance between Tap Cell and standard cell and update the ; The SEL threshold is used to determine the latching condition of the standard unit of the simulation chip at this time: if the source current of the PMOS tube in the standard unit of the simulation chip decreases over time until it disappears, it is determined that the SEL threshold meets the standard; if the source current of the PMOS tube in the standard unit of the simulation chip does not decrease significantly over time, it is determined that the SEL threshold does not meet the standard, and the search step is continued. Execute the next operation until the SEL threshold is reached; When the SEL threshold is reached, the operation ends. The value of is the Tap Cell insertion distance that meets the anti-SEL requirement. .

6. The method for designing a radiation-resistant chip according to claim 5, characterized in that: Using variables represents the distance between two Tap Cells, then in step S132, the distance is inserted using the Tap Cell , the unit-level SET simulation model containing Tap Cell is simulated and solved by simulation software to find the Tap Cell insertion spacing that meets both the anti-SEL and anti-SET requirements The process includes: Set the SET threshold to , set the Tap Cell insertion distance The four times value of The initial value of the search step and set the search step size for one operation ; by After the transient pulse width simulation is performed on all standard cells, the transient sensitivity is sorted according to the pulse width. The larger the pulse width, the stronger the sensitivity and the worse the anti-SET performance. The standard cell with the largest pulse width is taken as the most sensitive cell, and only the most sensitive cell is subjected to subsequent SET simulation. Search step size as described Reduce the distance between the two Tap Cells and update the ; The SET threshold is used to determine whether the simulation chip meets the SET resistance requirement at this time: if the most sensitive unit in the simulation chip is at any position between two Tap Cells, the transient pulse width generated is less than , then it is determined that the SET threshold meets the standard; if the most sensitive unit in the simulation chip is at any position between two Tap Cells, the transient pulse width generated is not all less than , it is determined that the SET threshold has not been met, and the search is continued at the previous step. Execute the next operation until the SET threshold is reached; When the SET threshold is reached, the operation ends. The value of is the Tap Cell insertion spacing that meets both the SEL and SET requirements. .

7. The method for designing a radiation-resistant chip according to claim 6, characterized in that: The simulation software is simulation software that realizes corresponding simulation functions in semiconductor device simulation tools.

8. A radiation-resistant chip design device, characterized in that: The device designs a radiation-resistant chip using the steps of the method according to any one of claims 1 to 7, and the device comprises the following modules: The first module is used to determine the Tap Cell layout insertion rules during chip backend design based on the process design file provided by the process manufacturer, and obtain the maximum distance value between the Tap Cell and the standard cell based on the Tap Cell layout insertion rules ; The second module is used to build a device-level SEL simulation model containing Tap Cell and use the maximum distance value , find the Tap Cell insertion distance that meets the anti-SEL requirements ; The third module is used to build a unit-level SET simulation model containing Tap Cells and use the Tap Cells to insert distance , obtain the Tap Cell insertion spacing that meets both SEL and SET requirements ; The fourth module is used to insert the spacing according to the Tap Cell Tap Cells are staggered in the chip layout, and EDA tools are used to complete the layout and routing of other standard cells in the chip layout to form the overall chip layout design.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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