Gate driving circuit, display panel and display device

Abstract

The application discloses a gate driving circuit, a display panel and a display device. The gate driving circuit comprises a plurality of shift registers connected in cascade, and each shift register comprises an input module, an output module, a first control module, a second control module and a third control module. The input module controls the voltage of a first node and the voltage of a second node based on the signals of a trigger signal end and a first clock end. The first control module controls the voltage of a third node based on the signals of the first clock end and the first node. The second control module controls the voltage of a fourth node based on the signals of the first node, the third node, a first power supply end, a second power supply end, the first clock end and a second clock end. The third control module controls the voltage of the second node based on the signals of the first node, the third node, the first power supply end and the second clock end. The output module controls the voltage of a first output end based on the second node, the fourth node, the first power supply end and the second power supply end.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] The gate drive circuit is one of the essential circuits for driving the display panel. The gate drive circuit typically includes multiple cascaded shift registers, which are electrically connected to the sub-pixels of the display panel. The signals output by the shift registers are used to control the state of the transistors in the sub-pixels, thereby driving the sub-pixels to emit light.

[0003] The stability of the signal output by the shift register affects the light emission effect of the sub-pixels. Therefore, how to optimize the performance of the shift register is an important problem faced by those skilled in the art. Summary of the Invention

[0004] This disclosure provides a gate driving circuit, a display panel, and a display device, which can improve the stability of the gate driving circuit and thus optimize its performance.

[0005] In a first aspect, embodiments of this disclosure provide a gate driving circuit, including a plurality of cascaded shift registers. Each shift register includes: an input module, an output module, a first control module, a second control module, and a third control module. The input module controls the voltage of a first node and the voltage of a second node based on signals from a trigger signal terminal and a first clock terminal. The first control module controls the voltage of a third node based on signals from the first clock terminal and the first node. The second control module controls the voltage of a fourth node based on signals from the first node, the third node, a first power supply terminal, a second power supply terminal, a first clock terminal, and a second clock terminal. The third control module controls the voltage of a second node based on signals from the first node, the third node, the first power supply terminal, and the second clock terminal. The output module controls the voltage of a first output terminal based on signals from the second node, the fourth node, the first power supply terminal, and the second power supply terminal.

[0006] In a second aspect, embodiments of this disclosure provide a display panel including the gate driving circuit described in the first aspect embodiment.

[0007] Thirdly, embodiments of this disclosure provide a display device including a display panel as described in the second aspect of the embodiments.

[0008] According to the embodiments of this disclosure, the third node controls the second control circuit and the third control circuit, which simplifies the connection relationship of the third node. The third node no longer directly controls the second node, and the third node will not directly interfere with the potential of the second node, thereby reducing the signal interference of the second node, improving circuit stability, and thus optimizing the performance of the gate drive circuit. Attached Figure Description

[0009] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0010] Figure 1 This diagram illustrates a structural schematic of a display panel provided in an embodiment of the present disclosure.

[0011] Figure 2 This diagram illustrates a structural schematic of a pixel driving circuit provided in an embodiment of the present disclosure.

[0012] Figure 3 This diagram illustrates another structural schematic of the pixel driving circuit provided in an embodiment of the present disclosure; Figure 4 This diagram illustrates a structural schematic of a gate drive circuit provided in an embodiment of the present disclosure.

[0013] Figure 5 This diagram illustrates a structural schematic of a shift register provided in an embodiment of the present disclosure;

[0014] Figure 6 This diagram illustrates one structure of a shift register in a comparative example.

[0015] Figure 7 This diagram illustrates another structural schematic of the shift register provided in an embodiment of the present disclosure;

[0016] Figure 8 This diagram illustrates yet another structural schematic of the shift register provided in an embodiment of the present disclosure;

[0017] Figure 9 This diagram illustrates yet another structural schematic of the shift register provided in an embodiment of the present disclosure;

[0018] Figure 10 This diagram illustrates yet another structural schematic of the shift register provided in an embodiment of the present disclosure;

[0019] Figure 11 This diagram illustrates a timing schematic of a shift register provided in an embodiment of the present disclosure.

[0020] Figure 12 This diagram illustrates yet another structural schematic of the shift register provided in an embodiment of the present disclosure;

[0021] Figure 13 This diagram illustrates another structural schematic of the gate drive circuit provided in an embodiment of the present disclosure;

[0022] Figure 14 This diagram illustrates yet another structural schematic of the shift register provided in an embodiment of the present disclosure;

[0023] Figure 15 This diagram illustrates another timing schematic of the shift register provided in an embodiment of the present disclosure;

[0024] Figure 16 This diagram illustrates another structural schematic of the display panel provided in an embodiment of the present disclosure;

[0025] Figure 17 This diagram illustrates a structural schematic of a display device provided in an embodiment of the present disclosure;

[0026] Figure 18 This illustration shows another structural schematic diagram of the display device provided in an embodiment of the present disclosure. Detailed Implementation

[0027] The features and exemplary embodiments of various aspects of this disclosure will now be described in detail. To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are configured only to explain this disclosure and are not configured to limit this disclosure. For those skilled in the art, this disclosure can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this disclosure by illustrating examples.

[0028] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0029] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0030] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0031] In embodiments of this disclosure, the term "electrical connection" can refer to a direct electrical connection between two components, or an electrical connection between two components via one or more other components. The term "drive" can refer to "control" or "operation." The display panel can be a display device or a module / part of a display device.

[0032] In this embodiment, a transistor is a device that includes at least three terminals: a gate, a source, and a drain. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the area through which current primarily flows. In this embodiment, when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged; that is, the "source" and "drain" can be interchanged. In this embodiment, for any transistor, one of the "source" and "drain" is referred to as the first terminal of the transistor, and the other is referred to as the second terminal of the transistor, with the gate being the control terminal of the transistor. In embodiments of this disclosure, at least a portion of the signal has a high voltage and a low voltage; one of the high voltage and the low voltage can serve as the gate voltage of the signal, which enables the controlled transistor to conduct; the other of the high voltage and the low voltage can serve as the cutoff voltage of the signal, which enables the controlled transistor to cut off. For example, for a signal controlling a P-type transistor (which can be applied to the gate of the P-type transistor), its gate voltage is a low voltage and its cutoff voltage is a high voltage. As another example, for a signal controlling an N-type transistor (which can be applied to the gate of the N-type transistor), its gate voltage is a high voltage and its cutoff voltage is a low voltage. In this document, "voltage" can also be referred to as "level" or "potential." "Cutoff" can also be referred to as "off" or "turn-off."

[0033] Various modifications and variations can be made to this disclosure without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this disclosure is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this disclosure can be combined with each other without contradiction.

[0034] This disclosure provides a gate driving circuit, a display panel, and a display device. The embodiments of this disclosure will be described below with reference to the accompanying drawings.

[0035] This disclosure provides a display panel. For example... Figure 1 As shown, the display panel 100 is provided with an array of sub-pixels 20. Each sub-pixel 20 includes a light-emitting element 21 and a pixel driving circuit 22 for driving the light-emitting element.

[0036] See Figure 1 The display panel 100 has multiple scan lines GL extending along a first direction X in the display area AA. Taking the first direction X as the row direction, each scan line GL corresponds to a sub-pixel row. The pixel driving circuit 22 of each sub-pixel in the sub-pixel row is electrically connected to the corresponding scan line GL. The display panel 100 also has multiple data lines DL extending along a second direction Y in the display area AA, which intersects with the first direction X. Taking the second direction Y as the column direction, each data line DL corresponds to a sub-pixel column. The pixel driving circuit 22 of each sub-pixel in the sub-pixel column is electrically connected to the corresponding data line DL. Thus, the pixel driving circuit 22 of each sub-pixel is connected to both the scan line GL and the data line DL. A scan signal is applied to the scan line GL to control the state of the pixel driving circuit 22.

[0037] Understandably, in Figure 1 The example only illustrates one type of scan line GL corresponding to the sub-pixel row; as needed, the display panel 100 can be configured with multiple different scan lines GL corresponding to the sub-pixel rows. A data voltage Vdata for driving the pixel driving circuit 22 can be loaded onto the data line DL. The pixel driving circuit 22 can drive the light-emitting element 21 according to the written data voltage Vdata, thereby controlling the brightness of the light-emitting element 21. It is understood that the pixel driving circuit 22 can also control the brightness of the light-emitting element 21 according to other signals.

[0038] For example, the pixel driving circuit 22 includes at least a data writing transistor, a driving transistor, and a storage capacitor. The gate of the driving transistor can be electrically connected to one electrode plate of the storage capacitor. The source of the data writing transistor can be electrically connected to the data line DL, and the gate of the data writing transistor can be electrically connected to a write control line for loading a data writing signal (a scan signal). The pixel driving circuit 22 is configured such that when a gate voltage of the data writing signal is applied to the write control line, the data writing transistor is turned on, thereby causing the driving voltage on the data line DL to be written to the gate of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the light-emitting element 21 to emit light under the control of the voltage on its gate. It is understood that the pixel driving circuit 22 of this disclosure embodiment may also include other transistors or capacitors to give the pixel driving circuit 22 better driving performance. For example, the pixel driving circuit 22 can be a 7T1C (7 transistors and one capacitor), an 8T1C (8 transistors and one capacitor), or other architecture pixel driving circuits.

[0039] As an example, the pixel driving circuit 22 is as follows: Figure 2 In the 7T1C architecture shown, transistor T2 writes the data signal from data line DL to driving transistor T3, which generates the driving current. Transistor T4 compensates for the threshold voltage of driving transistor T3. Transistor T5 transmits the reset signal from the first reset signal line Vref1 to the gate of driving transistor T3. Transistor T7 transmits the reset signal from the second reset signal line Vref2 to the first electrode of light-emitting element 21. Transistors T1 and T6 control whether light-emitting element 21 emits light. Additionally, S1-S3 and Emit are all scan signals; Emit can also be called the light-emitting control signal.

[0040] As another example, pixel driving circuit 22 is as follows Figure 3 The 13T2C architecture shown includes a pixel driving circuit 22 comprising a PAM module and a PWM module. The PWM module is electrically connected to the PAM module, and the PAM module is electrically connected to the first electrode of the light-emitting element 21. Furthermore, PAM_S1, PAM_S2, PAM_EM, PWM_S1, PWM_S2, and PWM_EM are all scanning signals; PAM_EM and PWM_EM can also be referred to as light-emitting control signals.

[0041] For example, the light-emitting element 21 can be a current-driven self-emitting element, such as any one of organic light-emitting diode (OLED), polymer light-emitting diode (PLED), quantum dot light-emitting diode (QLED), micro light-emitting diode (Micro LED), mini light-emitting diode (MiNi LED), etc.

[0042] In this embodiment, the light-emitting element 21 may include a variety of light-emitting elements 21 of different colors, such as a red sub-pixel for emitting red light, a blue sub-pixel for emitting blue light, and a green sub-pixel for emitting green light.

[0043] See Figure 4 The display panel 100 also includes a gate driving circuit 10, which is electrically connected to the sub-pixel 20. The gate driving circuit 10 provides scanning signals to the pixel driving circuit 22. For example, multiple gate driving circuits can be provided to provide different scanning signals, depending on the needs of the pixel driving circuit 22. Alternatively, some scanning signals can share a single gate driving circuit.

[0044] For example, the gate drive circuit 10 can drive the gate to... Figure 2 The pixel driving circuit shown provides the signal Emit. For example, the gate driving circuit 10 can also provide... Figure 3 The pixel driving circuit shown provides the signal PWM_EM, or the gate driving circuit 10 can provide the signal PWM_EM. Figure 3 The pixel driving circuit shown provides the signal PAM_EM, or the gate driving circuit 10 can provide the signal PAM_EM to the pixel driving circuit shown. Figure 3 The pixel driving circuit shown provides the signals PWM_EM and PAM_EM.

[0045] As an example, the gate drive circuit 10 is located in the bezel area of ​​the display panel, which is a non-display area.

[0046] As another example, the gate drive circuit 10 is located in the display area of ​​the display panel to achieve narrow bezels or even bezel-less designs.

[0047] For example, depending on the needs of the pixel driving circuit, the scan signal may include, but is not limited to, one or more of the following signals: a light emission control signal for controlling the output drive current of the pixel driving circuit, a write control signal for controlling the data voltage written to the pixel driving circuit, and a reset control signal for controlling the reset of the pixel driving circuit, etc. For example, the scan signal includes... Figure 2 The signal Emit is shown. For example, the scan signal includes... Figure 3 The signal PWM_EM shown, or the scan signal, includes Figure 3 The signal PAM_EM shown, or the scan signal, includes Figure 3 The signals PWM_EM and PAM_EM are shown.

[0048] See Figure 5 The gate drive circuit 10 provided in this embodiment includes a plurality of cascaded shift registers (VSRs). The shift registers (VSRs) include an input module 11, an output module 12, a first control module 13, a second control module 14, and a third control module 15.

[0049] Input module 11 controls the voltage of the first node N1 and the voltage of the second node N2 based on the signals of the trigger signal terminal STV and the first clock terminal CK; first control module 13 controls the voltage of the third node N3 based on the signals of the first clock terminal CK and the first node N1; second control module 14 controls the voltage of the fourth node N4 based on the signals of the first node N1, the third node N3, the first power supply terminal VGH, the second power supply terminal VGL, the first clock terminal CK and the second clock terminal XCK; third control module 15 controls the voltage of the second node N2 based on the signals of the first node N1, the third node N3, the first power supply terminal VGH and the second clock terminal XCK; output module 12 controls the voltage of the first output terminal OUT1 based on the signals of the second node N2, the fourth node N4, the first power supply terminal VGH and the second power supply terminal VGL.

[0050] Understandably, input module 11 is electrically connected to trigger signal terminal STV, first clock terminal CK, first node N1, and second node N2; first control module 13 is electrically connected to first clock terminal CK, first node N1, and third node N3; second control module 14 is electrically connected to first node N1, third node N3, first power supply terminal VGH, second power supply terminal VGL, first clock terminal CK, second clock terminal XCK, and fourth node N4; third control module 15 is electrically connected to first node N1, third node N3, first power supply terminal VGH, second clock terminal XCK, and second node N2; and output module 12 is electrically connected to second node N2, fourth node N4, first power supply terminal VGH, second power supply terminal VGL, and first output terminal OUT1.

[0051] The trigger signal terminal STV provides the trigger signal. When the trigger signal is a gate voltage, the shift register is triggered to operate. In the cascaded shift registers, the trigger signal terminal STV of the first-stage shift register is electrically connected to the driver chip, and the trigger signal terminal STV of the (i+1)th-stage shift register is electrically connected to the first output terminal OUT1 of the i-th-stage shift register, where i is an integer greater than 0. In other words, the signal output from the first output terminal OUT1 of the i-th-stage shift register serves as the trigger signal for the (i+1)th-stage shift register.

[0052] The first clock terminal CK and the second clock terminal XCK are used to provide clock signals, which include alternating high and low voltage signals. The first clock signal at the first clock terminal CK and the second clock signal at the second clock terminal XCK are inverted.

[0053] The first power supply terminal VGH is used to provide a high voltage signal, and the second power supply terminal VGL is used to provide a low voltage signal.

[0054] The input module 11, output module 12, first control module 13, second control module 14, and third control module 15 cooperate to enable the first output terminal OU1 to output a scanning signal. This scanning signal is used to drive the pixel driving circuit, thereby controlling the light-emitting effect of the sub-pixels. The output module 12 is controlled by the second node N2. The voltage stability of the second node N2 affects the stability of the signal output by the first output terminal OU1. In other words, the voltage stability of the second node N2 affects the light-emitting effect of the sub-pixels.

[0055] To better illustrate the beneficial effects of the embodiments of this application, please refer to the comparison. Figure 6 and Figure 5 , Figure 6 Middle node N2' and Figure 3 The second node N2 is equivalent to, Figure 6 Middle node N3' and Figure 5 The third node N3 in the middle is equivalent to, Figure 6 Middle node N4' and Figure 5 The fourth node N4 in the middle is equivalent to, Figure 6 The gate of transistor M11' is connected to node N2', and node N2' is controlled by node N3'. Node N3' also needs to control transistors M4' and M9'. Therefore, it is susceptible to disturbances from transistors M4' and M9', which can interfere with the potential of node N2' and lead to a decrease in circuit stability.

[0056] According to the embodiments of this disclosure, the third node controls the second control circuit and the third control circuit, which simplifies the connection relationship of the third node. The third node no longer directly controls the second node, and the third node will not directly interfere with the potential of the second node, thereby reducing the signal interference of the second node, improving circuit stability, and thus optimizing the performance of the gate drive circuit.

[0057] In some embodiments, such as Figure 7 As shown, the second control module includes a first sub-control module 141 and a second sub-control module 142. The first sub-control module 141 controls the voltage of the fifth node N5 based on the signals of the third node N3, the first power supply terminal VGH, the first clock terminal CK, and the second clock terminal XCK; the second sub-control module 142 controls the voltage of the fourth node N4 based on the signals of the first node N1, the fifth node N5, the first power supply terminal VGH, and the second power supply terminal VGL.

[0058] Understandably, the first sub-control module 141 is electrically connected to the third node N3, the first power supply terminal VGH, the first clock terminal CK, the second clock terminal XCK, and the fifth node N5. The second sub-control module 142 is electrically connected to the first node N1, the fifth node N5, the first power supply terminal VGH, the second power supply terminal VGL, and the fourth node N4.

[0059] In this embodiment, the second control module is divided into a first sub-control module 141 and a second sub-control module 142. The signal of the third node N3 affects the voltage of the fifth node N5, and the signals of the fifth node N5 and the first node N1 affect the voltage of the fourth node N4. In this way, the control accuracy can be improved.

[0060] In some embodiments, such as Figure 8 As shown, the shift register also includes a pull-up module 16, which controls the voltage of the first node N1 based on the signals of the fifth node N5 and the first power supply terminal VGH.

[0061] For example, when the fifth node N5 is at a low voltage, the pull-up module 16 is turned on, and the high voltage of the first power supply terminal VGH is transmitted to the first node N1. In this way, when the fifth node N5 is at a low voltage, the pull-up module 16 is used to lock the potential of the first node N1, thereby increasing the potential stability of the first node N1.

[0062] In some embodiments, such as Figure 9 As shown, the shift register also includes a reset module 17, which controls the voltage of the first node N1 based on the signals of the first power supply terminal VGH and the reset signal terminal RST.

[0063] For example, when the reset signal terminal RST is low, the reset module 17 is turned on, and the high voltage of the first power supply terminal VGH is transmitted to the first node N1.

[0064] By setting up a reset module, it is possible to ensure that the circuit can be restored to a known and definite state in the initial state or in an error state, thereby increasing the reliability of the circuit.

[0065] In some embodiments, such as Figure 9 As shown, the input module 11 includes a first sub-input module 111 and a second sub-input module 112. The first sub-input module 111 controls the voltage of the second node N2 based on the signals of the trigger signal terminal STV and the first clock terminal CK; the second sub-input module 112 controls the voltage of the first node N1 based on the signals of the trigger signal terminal STV and the first clock terminal CK.

[0066] For example, when the signal at the first clock terminal CK is low voltage, the first sub-input module 111 and the second sub-input module 112 are turned on, the signal at the trigger signal terminal STV is transmitted to the second node N2 through the first sub-input module 111, and the signal at the trigger signal terminal STV is transmitted to the first node N1 through the second sub-input module 112.

[0067] In this embodiment, different sub-input modules are used to transmit the STV signal to the first node N1 and the second node N2 respectively, thereby realizing input control of the first node N1 and the second node N2 respectively, thus avoiding the voltage of the first node N1 from interfering with the voltage of the second node N2, and further improving the potential stability of the second node N2.

[0068] In some embodiments, such as Figure 10 As shown, the first sub-input module 111 includes a first transistor M1. The first terminal of the first transistor M1 is electrically connected to the trigger signal terminal STV, the second terminal of the first transistor M1 is electrically connected to the second node N2, and the gate of the first transistor M1 is electrically connected to the first clock terminal CK. The second sub-input module 112 includes a second transistor M2. The first terminal of the second transistor M2 is electrically connected to the trigger signal terminal STV, the second terminal of the second transistor M2 is electrically connected to the first node N1, and the gate of the second transistor M2 is electrically connected to the first clock terminal CK.

[0069] For example, when the first clock signal on the first clock terminal CK is low voltage, the first transistor M1 and the second transistor M2 are turned on, the trigger signal on the trigger signal terminal STV is transmitted to the second node N2 through the first transistor M1, and the trigger signal on the trigger signal terminal STV is transmitted to the first node N1 through the second transistor M2.

[0070] For example, such as Figure 10As shown, the first transistor M1 is a dual-gate transistor, or the channel length of the first transistor M1 is greater than the channel length of the second transistor M2. Using a dual-gate transistor or a transistor with a longer channel length as the first transistor can reduce leakage current, thereby further ensuring the potential stability of the second node. In this paper, a dual-gate transistor includes two sub-transistors connected in series, with their gates electrically connected. For example, taking the first transistor M1 as an example with two sub-transistors, the first terminal of the first sub-transistor is electrically connected to the trigger signal terminal STV, the second terminal of the first sub-transistor is electrically connected to the first terminal of the second sub-transistor, the second terminal of the second sub-transistor is electrically connected to the second node N2, and the gates of the first and second sub-transistors are electrically connected to the first clock terminal.

[0071] In some embodiments, such as Figure 10 As shown, the first control module 13 includes a third transistor M3 and a fourth transistor M4; the first terminal of the third transistor M3 is electrically connected to the first clock terminal CK, the second terminal of the third transistor M3 is electrically connected to the third node N3, and the gate of the third transistor M3 is electrically connected to the first node N1; the first terminal and the gate of the fourth transistor M4 are electrically connected to the first clock terminal CK, and the second terminal of the fourth transistor M4 is electrically connected to the third node N3.

[0072] For example, when the first node N1 is at a low voltage, the third transistor M3 is turned on, and the first clock signal on the first clock terminal CK is transmitted to the third node N3 through the third transistor M3. When the first clock signal on the first clock terminal CK is at a low voltage, the fourth transistor M4 is turned on, and the first clock signal on the first clock terminal CK is transmitted to the third node N3 through the fourth transistor M4.

[0073] For example, such as Figure 10 As shown, at least one of the third transistor M3 and the fourth transistor M4 is a dual-gate transistor, or, at least one of the third transistor M3 and the fourth transistor M4 has a channel length greater than the channel length of the second transistor M2. For example, Figure 8 The diagram illustrates that both the third transistor M3 and the fourth transistor M4 are dual-gate transistors.

[0074] The third transistor M3 and / or the fourth transistor M4 are dual-gate transistors or transistors with long channel lengths, which can reduce leakage current and thus ensure the potential stability of the third node.

[0075] In some embodiments, such as Figure 10As shown, the third control module 15 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a first capacitor C1. The first terminal and gate of the fifth transistor M5 are electrically connected to the sixth node N6, and the second terminal of the fifth transistor M5 is electrically connected to the second node N2. The first terminal of the sixth transistor M6 is electrically connected to the first power supply terminal VGH, and the second terminal of the sixth transistor M6 is electrically connected to the first terminal of the first capacitor C1. The gate of the sixth transistor M6 is electrically connected to the third node N3. The first terminal of the seventh transistor M7 is electrically connected to the second clock terminal XCK, and the second terminal of the seventh transistor M7 is electrically connected to the first terminal of the first capacitor C1. The gate of the seventh transistor M7 is electrically connected to the sixth node N6. The second terminal of the first capacitor C1 is electrically connected to the sixth node N6, and the sixth node N6 is electrically connected to the first node N1.

[0076] For example, when the sixth node N6 is at a low voltage, the fifth transistor M5 and the seventh transistor M7 are turned on. When the third node N3 is at a low level, the sixth transistor M6 is turned on.

[0077] When the voltage at the first terminal of the first capacitor C1 changes from high to low, the coupling effect of the first capacitor C1 will cause the potential of the sixth node N6 to decrease, thereby enabling the fifth transistor M5 to conduct more fully and keeping the potential of the second node N2 at a low level.

[0078] In some embodiments, such as Figure 10 As shown, the sixth node N6 is electrically connected to the first node N1 through the eighth transistor M8, and the gate of the eighth transistor M8 is electrically connected to the second power supply terminal VGL.

[0079] The eighth transistor M8 can be kept on by the second power supply terminal VGL.

[0080] In this embodiment, the eighth transistor M8 can isolate the first node N1 and the sixth node N6, so that the voltage of the first node N1 can be maintained relatively stably. For example, the voltage of the first node N1 will not drop below the voltage of the second power supply terminal VGL, thereby reducing the bias stress applied to the transistor connected to the first node N1.

[0081] For example, the channel length of the eighth transistor can be greater than the channel length of the transistors in the output module. This reduces the leakage current of the eighth transistor, thereby better isolating the first node N1 and the sixth node N6.

[0082] In some embodiments, such as Figure 10As shown, the first sub-control module 141 includes a ninth transistor M9, a tenth transistor M10, and a second capacitor C2; the first terminal of the ninth transistor M9 is electrically connected to the second clock terminal XCK, the second terminal of the ninth transistor M9 is electrically connected to the fifth node N5, and the gate of the ninth transistor M9 is electrically connected to the third node N3; the first terminal of the tenth transistor M10 is electrically connected to the first power supply terminal VGH, the second terminal of the tenth transistor M10 is electrically connected to the fifth node N5, and the gate of the tenth transistor M10 is electrically connected to the first clock terminal CK; the first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the fifth node N5.

[0083] For example, when the third node N3 is at a low voltage, the ninth transistor M9 is turned on, and the second clock signal at the second clock terminal XCK is transmitted to the fifth node N5. When the first clock signal at the first clock terminal CK is at a low voltage, the tenth transistor M10 is turned on, and the high voltage at the first power supply terminal VGH is transmitted to the fifth node N5. The two terminals of the second capacitor C2 are connected to the third node N3 and the fifth node N5 respectively. If the voltage of either the third node N3 or the fifth node N5 jumps, the voltage of the other node will also jump under the coupling effect of the second capacitor C2.

[0084] For example, the ninth transistor M9 is a dual-gate transistor, or the channel length of the ninth transistor M9 is greater than the channel length of the transistors in the output module, in order to reduce the possibility of leakage current in the ninth transistor M9, thereby improving the potential stability of the fifth node N5.

[0085] In some embodiments, such as Figure 10 As shown, the second sub-control module 142 includes an eleventh transistor M11 and a twelfth transistor M12; the first terminal of the eleventh transistor M11 is electrically connected to the second power supply terminal VGL, the second terminal of the eleventh transistor M11 is electrically connected to the fourth node N4, and the gate of the eleventh transistor M11 is electrically connected to the fifth node N5; the first terminal of the twelfth transistor M12 is electrically connected to the first power supply terminal VGH, the second terminal of the twelfth transistor M12 is electrically connected to the fourth node N4, and the gate of the twelfth transistor M12 is electrically connected to the first node N1.

[0086] For example, when the fifth node N5 is at a low voltage, the eleventh transistor M11 is turned on, and the low voltage of the second power supply terminal VGL is transmitted to the fourth node N4. When the first node N1 is at a low voltage, the twelfth transistor M12 is turned on, and the high voltage of the first power supply terminal VGH is transmitted to the fourth node N4, thereby locking the potential of the fourth node N4.

[0087] In some embodiments, such as Figure 10As shown, the output module 12 includes a thirteenth transistor M13, a fourteenth transistor M14, a third capacitor C3, and a fourth capacitor C4. The first terminal of the thirteenth transistor M13 is electrically connected to the first power supply terminal VGH, the second terminal of the thirteenth transistor M13 is electrically connected to the first output terminal OUT1, and the gate of the thirteenth transistor M13 is electrically connected to the fourth node N4. The first terminal of the fourteenth transistor M14 is electrically connected to the second power supply terminal VGL, the second terminal of the fourteenth transistor M14 is electrically connected to the first output terminal OUT1, and the gate of the fourteenth transistor M14 is electrically connected to the second node N2. The third capacitor C3 is electrically connected between the first power supply terminal VGH and the fourth node N4. The fourth capacitor C4 is electrically connected between the second node N2 and the first output terminal OUT1.

[0088] For example, when the fourth node N4 is at a low voltage, the thirteenth transistor M13 is turned on, and the high voltage of the first power supply terminal VGH is transmitted to the first output terminal OU1, which outputs a high voltage. When the second node N2 is at a low voltage, the fourteenth transistor M14 is turned on, and the voltage of the second power supply terminal VGL is transmitted to the first output terminal OU1, which outputs the voltage of the second power supply terminal VGL.

[0089] For example, the channel width-to-length ratios of the thirteenth transistor M13 and the fourteenth transistor M14 are the same, and the channel width-to-length ratio of the thirteenth transistor M13 is greater than the channel width-to-length ratio of any one of the transistors in the input module 11, the first control module 13, the second control module 14, the third control module 15, the pull-up module 16, and the reset module 17. In this way, the driving capability of the signal output by the first output terminal OU1 can be guaranteed.

[0090] In some embodiments, such as Figure 10 As shown, the pull-up module 16 includes a fifteenth transistor M15. The first terminal of the fifteenth transistor M15 is electrically connected to the first power supply terminal VGH, the second terminal of the fifteenth transistor M15 is electrically connected to the first node N1, and the gate of the fifteenth transistor M15 is electrically connected to the fifth node N5.

[0091] For example, when the fifth node N5 is at a low voltage, the fifteenth transistor M15 is turned on, and the high voltage of the first power supply terminal VGH is transmitted to the first node N1, thereby locking the potential of the first node N1 and improving the potential stability of the first node N1.

[0092] In some embodiments, such as Figure 10 As shown, the reset module 17 includes a sixteenth transistor M16. The first terminal of the sixteenth transistor M16 is electrically connected to the first power supply terminal VGH, the second terminal of the sixteenth transistor M16 is electrically connected to the first node N1, and the gate of the sixteenth transistor M16 is electrically connected to the reset signal terminal RST.

[0093] For example, when the reset signal at the reset signal terminal RST is low, the sixteenth transistor M16 is turned on, and the high voltage at the first power supply terminal VGH is transmitted to the first node N1, resetting the potential of the first node N1.

[0094] It should be noted that the above example uses P-type transistors as an example. In other examples, the transistors in the shift register can be N-type transistors; or, some transistors in the shift register can be P-type transistors and others can be N-type transistors.

[0095] The following references Figure 10 and Figure 11 Taking P-type transistors as an example, the working process of the shift register is explained:

[0096] The shift register operates through stages t1 to t9. In Table 1, "0" indicates a low voltage is applied to the transistor's gate, meaning the transistor is turned on; "1" indicates a high voltage is applied to the transistor's gate, meaning the transistor is turned off. Here, "low voltage" and "high voltage" are relative terms. "Low voltage" refers to the voltage that controls the transistor's on-state, and "high voltage" refers to the voltage that controls its off-state. The specific values ​​of the "low voltage" and "high voltage" can vary between different transistors.

[0097] Table 1

[0098]

[0099]

[0100] At each stage, the first power supply terminal VGH maintains a high voltage, while the second power supply terminal VGL maintains a low voltage.

[0101] In the first stage t1, the reset signal terminal RST is low, the trigger signal terminal STV is high, the first clock terminal CK is low, the second clock terminal XCK is high, the first node N1, the second node N2, the fifth node N5, and the sixth node N6 are high, the third node N3 and the fourth node N4 are low, and the first output terminal OUT1 outputs a high voltage.

[0102] In the second stage t2, the reset signal terminal RST is high, the trigger signal terminal STV is low, the first clock terminal CK is high, the second clock terminal XCK is low, the first node N1, the second node N2, and the sixth node N6 are high, the third node N3, the fourth node N4, and the fifth node N5 are low, and the first output terminal OUT1 outputs a high voltage.

[0103] In the third stage t3, the reset signal terminal RST is high, the trigger signal terminal STV is low, the first clock terminal CK is low, the second clock terminal XCK is high, the first node N1, the second node N2, the third node N3, the fifth node N5, and the sixth node N6 are low, the fourth node N4 is high, and the first output terminal OUT1 outputs a low voltage.

[0104] In the fourth stage t4, the reset signal terminal RST is high, the trigger signal terminal STV is low, the first clock terminal CK is high, the second clock terminal XCK is low, the first node N1, the second node N2, and the sixth node N6 are low, the third node N3, the fourth node N4, and the fifth node N5 are high, and the first output terminal OUT1 outputs a low voltage.

[0105] Understandably, in the third stage t3, the sixth transistor M6 and the seventh transistor M7 are turned on, and the first terminal of the first capacitor C1 is at a high voltage; in the fourth stage t4, the seventh transistor M7 is turned on, and the first terminal of the first capacitor C1 jumps to a low voltage, causing the sixth node N6 to jump to an even lower voltage. Since the eighth transistor M8 isolates the sixth node N6 from the first node N1, the voltage of the first node N1 will not jump to a lower voltage.

[0106] The working process of the fifth stage t5 is the same as that of the third stage t3, and will not be described again here.

[0107] The operation of stage t6 is the same as that of stage t4, and will not be described again here. It should be noted that in stage t6, the voltage of the trigger signal terminal STV may be slightly increased due to coupling with other signals, but this will not affect the normal operation of the shift register.

[0108] In stage t7, the reset signal RST is high, the trigger signal STV is high, the first clock signal CK is low, the second clock signal XCK is high, nodes N1, N2, N4, N5, and N6 are high, node N3 is low, and the first output OUT1 outputs a low voltage. Similarly, in stage t7, the voltage at the first output OUT1 may be slightly increased due to coupling from other signals, but this will not affect the normal operation of the shift register.

[0109] In stage 8 t8, the reset signal terminal RST is high, the trigger signal terminal STV is high, the first clock terminal CK is high, the second clock terminal XCK is low, the first node N1, the second node N2, and the sixth node N6 are high, the third node N3, the fourth node N4, and the fifth node N5 are low, and the first output terminal OUT1 outputs a high voltage.

[0110] In the ninth stage t9, the reset signal terminal RST is high, the trigger signal terminal STV is high, the first clock terminal CK is low, the second clock terminal XCK is high, the first node N1, the second node N2, the fifth node N5, and the sixth node N6 are high, the third node N3 and the fourth node N4 are low, and the first output terminal OUT1 outputs a high voltage.

[0111] After stage t9, stage 8 t8 and stage 9 t9 are executed repeatedly.

[0112] In some embodiments, such as Figure 12 As shown, the shift register also includes a gating module 18, which controls the voltage of the second output terminal OUT2 based on the signals of the first output terminal OUT1, the second power supply terminal VGL, the fourth node N4, the third power supply terminal VD, and the start signal terminal IN.

[0113] Understandably, the gating module 18 is electrically connected to the first output terminal OUT1, the second power supply terminal VGL, the fourth node N4, the third power supply terminal VD, the start signal terminal IN, and the second output terminal OUT2.

[0114] For example, the signal at the third power supply terminal VD is a fixed high voltage. For example, the voltage at the third power supply terminal VD may be equal to the voltage at the first power supply terminal VGH. Of course, in other examples, the voltage at the third power supply terminal VD may not be equal to the voltage at the first power supply terminal VGH.

[0115] For example, such as Figure 13 As shown, when the shift register includes a gating module, the first output terminal OUT1 serves as a cascade signal terminal. The first output terminal OUT1 of the i-th stage shift register is electrically connected to the trigger signal terminal STV of the (i+1)-th stage shift register, where i is an integer greater than 0. For example, the first output terminal OUT1 of the first stage shift register VSR(1) is electrically connected to the trigger signal terminal STV of the second stage shift register VSR(2), the first output terminal OUT1 of the second stage shift register VSR(2) is electrically connected to the trigger signal terminal STV of the third stage shift register VSR(3), the first output terminal OUT1 of the third stage shift register VSR(3) is electrically connected to the trigger signal terminal STV of the fourth stage shift register VSR(4), and so on. The second output terminal OU2 serves as a driving signal terminal. The second output terminal OU2 is electrically connected to the sub-pixel through the scan line GL, and the signal output by the second output terminal OU2 is used to drive the sub-pixel.

[0116] As an example, such as Figure 3As shown, the pixel driving circuit includes an amplitude modulation module and a pulse width modulation module. The pulse width modulation module is connected to the sweep frequency signal SWEEP. The signal waveform of the start signal terminal IN includes a slanted waveform, so that the second output terminal OUT2 outputs the sweep frequency signal SWEEP to control the pulse width modulation module.

[0117] As another example, the signal waveform at the start signal terminal IN includes a square wave waveform, causing the second output terminal OUT2 to output a scanning signal to control the amplitude modulation module.

[0118] In some embodiments, such as Figure 14 As shown, the gating module 18 includes a seventeenth transistor M17, an eighteenth transistor M18, a fifth capacitor C5, and a sixth capacitor C6. The first terminal of the seventeenth transistor M17 is electrically connected to the third power supply terminal VD, the second terminal of the seventeenth transistor M17 is electrically connected to the second output terminal OUT2, and the gate of the seventeenth transistor M17 is electrically connected to the fourth node N4. The first terminal of the eighteenth transistor M18 is electrically connected to the start signal terminal IN, the second terminal of the eighteenth transistor M18 is electrically connected to the second output terminal OUT2, and the gate of the eighteenth transistor M18 is electrically connected to the first output terminal OUT1. The fifth capacitor C5 is electrically connected between the first output terminal OUT1 and the second power supply terminal VGL. The sixth capacitor C6 is electrically connected between the second output terminal OUT2 and the gate of the eighteenth transistor M18.

[0119] For example, when the fourth node N4 is at a low voltage, the seventeenth transistor M17 is turned on, and the high voltage of the third power supply terminal VD is transmitted to the second output terminal OUT2. When the first output terminal OUT1 is at a low voltage, the eighteenth transistor M18 is turned on, and the signal of the start signal terminal IN is transmitted to the second output terminal OUT2.

[0120] In some embodiments, the channel width-to-length ratio of the seventeenth transistor M17 is greater than the channel width-to-length ratio of the transistors in the output module 12; and / or, the channel width-to-length ratio of the eighteenth transistor M18 is greater than the channel width-to-length ratio of the transistors in the output module 12. In this way, the driving capability of the signal output by the second output terminal OU2 can be guaranteed.

[0121] For example, the seventeenth transistor M17 and the eighteenth transistor M18 have the same channel width-to-length ratio, the thirteenth transistor M13 and the fourteenth transistor M14 have the same channel width-to-length ratio, the channel width of the seventeenth transistor M17 is greater than the channel width of the thirteenth transistor M13, and the channel length of the seventeenth transistor M17 is greater than the channel length of the thirteenth transistor M13.

[0122] In some embodiments, such as Figure 14As shown, the gating module 18 also includes a nineteenth transistor M19. The gate of the eighteenth transistor M18 is electrically connected to the first output terminal OUT1 through the nineteenth transistor M19, and the gate of the nineteenth transistor M19 is electrically connected to the second power supply terminal VGL.

[0123] The nineteenth transistor M19 can be kept on by the first power supply terminal VGL.

[0124] In this embodiment, the nineteenth transistor M19 isolates the gate of the first output terminal OUT1 from that of the eighteenth transistor M18, thus maintaining the voltage of the first output terminal OUT1 relatively stably. For example, the voltage of the first output terminal OUT1 will not drop below the voltage of the second power supply terminal VGL, thereby reducing the bias stress applied to the transistor connected to the first output terminal OUT1.

[0125] For example, the channel length of the nineteenth transistor may be greater than the channel length of the transistor in the output module.

[0126] The following references Figure 14 and Figure 15 Taking a shift register as an example where all transistors are P-type transistors and the signal waveform at the start signal terminal IN includes a bevel waveform:

[0127] The shift register's operation still includes stages 1 to 9 (t1). Compared to Table 1, Table 2 also shows the gate voltages of transistors M17, M18, and M19 in each stage. Similarly, in Table 2, "0" indicates a low voltage is applied to the transistor's gate, and the transistor is turned on; "1" indicates a high voltage is applied to the transistor's gate, and the transistor is turned off. Here, "low voltage" and "high voltage" are relative; "low voltage" refers to the voltage controlling the transistor's on-state, and "high voltage" refers to the voltage controlling the transistor's off-state. The specific values ​​of the "low voltage" and "high voltage" applied to different transistors can vary.

[0128] Table 2

[0129] t1 t2 t3 t4 t5 t6 t7 t8 t9 M1 0 1 0 1 0 1 0 1 0 M2 0 1 0 1 0 1 0 1 0 M3 1 1 0 0 0 0 1 1 1 M4 0 1 0 1 0 1 0 1 0 M5 1 1 0 0 0 0 1 1 1 M6 0 0 0 1 0 1 0 0 0 M7 1 1 0 0 0 0 1 1 1 M8 0 0 0 0 0 0 0 0 0 M9 0 0 0 1 0 1 0 0 0 M10 0 1 0 1 0 1 0 1 0 M11 1 0 1 1 1 1 1 0 1 M12 1 1 0 0 0 0 1 1 1 M13 0 0 1 1 1 1 1 0 0 M14 1 1 0 0 0 0 1 1 1 M15 1 0 1 1 1 1 1 0 1 M16 0 1 1 1 1 1 1 1 1 M17 0 0 1 1 1 1 1 0 0 M18 1 1 0 0 0 0 0 1 1 M19 0 0 0 0 0 0 0 0 0

[0130] At each stage, the first power supply terminal VGH maintains a high voltage, the second power supply terminal VGL maintains a low voltage, and the third power supply terminal VD maintains a high voltage. For example, the voltage value of the third power supply terminal VD is the same as the voltage value of the first power supply terminal VGH.

[0131] Figure 15 and Figure 11 The similarities will not be repeated here; the differences include:

[0132] In the first stage t1 and the second stage t2, the first output terminal OUT1 outputs a high voltage, the fourth node N4 is at a low voltage, the seventeenth transistor M17 is turned on, and the high voltage of the third power supply terminal VD is transmitted to the second output terminal OUT2, which then outputs a high voltage.

[0133] During the third stage t3 to the seventh stage t7, the first output terminal OUT1 outputs a low voltage, the fourth node N4 is at a high voltage, the eighteenth transistor M18 is turned on, and the beveled waveform signal at the start signal terminal IN is transmitted to the second output terminal OUT2, which outputs a beveled waveform signal. For example, the voltage of this beveled waveform signal is greater than or equal to 0.

[0134] In the eighth stage t8 and the ninth stage t9, the first output terminal OUT1 outputs a high voltage, the fourth node N4 is at a low voltage, the seventeenth transistor M17 is turned on, and the high voltage of the third power supply terminal VD is transmitted to the second output terminal OUT2, and the second output terminal OUT2 outputs a high voltage.

[0135] After stage t9, stage 8 t8 and stage 9 t9 are executed repeatedly.

[0136] In some embodiments, such as Figure 16 As shown, the sub-pixel 20 includes a light-emitting element 21 and a pixel driving circuit 22 for driving the light-emitting element 21. The pixel driving circuit 22 includes a PWM (Pulse Width Modulation) module and a PAM (Pulse Amplitude Modulation) module. The combination of the PWM module and the PAM module can control the driving current intensity and the duration of the driving current to control the light-emitting state of the light-emitting element.

[0137] The PWM module and the PAM module are connected. The pixel circuit generates drive current under the control of the PWM module and the PAM module. The PAM module is used to control the amplitude of the drive current, and the PWM module is used to adjust the pulse width of the voltage applied to the first electrode of the light-emitting element.

[0138] The PWM module adjusts the pulse width of the voltage applied to the first electrode of the light-emitting element. In other words, the PWM module adjusts the actual emission period of the drive current applied to the light-emitting element. Simultaneously, it maintains a constant drive current to adjust the grayscale or brightness of the light-emitting element, rather than simply adjusting the magnitude of the drive current. Therefore, the PAM module can provide drive current to the light-emitting element so that it is driven with optimal luminous efficiency, and adjust the grayscale or brightness of the light-emitting element by adjusting its emission duty cycle (i.e., the emission period) through the PWM module.

[0139] The gate driving circuit 10 includes a first gate driving circuit 10_PWM, a second gate driving circuit 10_PAM, and a third gate driving circuit 10_SWEEP. The first gate driving circuit 10_PWM includes, as follows: Figure 5 , Figure 7 , Figure 8 , Figure 9 , Figure 10 The shift register shown in any of the attached figures, the second gate drive circuit 10_PAM includes Figure 12 or Figure 14 The shift register shown includes the third gate drive circuit 10_SWEEP. Figure 12 or Figure 14 The shift register is shown. In other words, the first gate drive circuit 10_PWM does not include a gating module, while the second gate drive circuit 10_PAM and the third gate drive circuit 10_SWEEP do include gating modules.

[0140] The second gate drive circuit 10_PAM is electrically connected to the PAM module, and the first gate drive circuit 10_PWM and the third gate drive circuit 10_SWEEP are electrically connected to the PWM module. The first output terminal OU1 of the first gate drive circuit 10_PWM is used to output the first light emission control signal Emit1, the second output terminal OUT of the second gate drive circuit 10_PAM is used to output the second light emission control signal Emit2, and the second output terminal OUT of the third gate drive circuit 10_SWEEP is used to output the sweep frequency signal SWEEP.

[0141] For ease of distinction, the start signal terminal of the second gate drive circuit 10_PAM is labeled IN_PAM, and the start signal terminal of the third gate drive circuit 10_SWEEP is labeled IN_SWEEP. The signal timing of the start signal terminals IN_PAM and IN_SWEEP of the second and third gate drive circuits is different.

[0142] For example, the start signal terminal IN_PAM of the second gate drive circuit 10_PAM is a square wave signal, and the signal waveform of the start signal terminal IN_SWEEP of the third gate drive circuit 10_SWEEP includes a beveled waveform.

[0143] In the absence of a gating module in the shift register, the signal output from the first output terminal of the shift register can only be adjusted according to the row time as the minimum change. The gating time of the PAM module in the pixel driving circuit is related to the light-emitting effect of the light-emitting element. The second gate driving circuit 10_PAM includes a gating module. Thus, by adjusting the signal waveform of the start signal terminal IN_PAM of the second gate driving circuit 10_PAM, a 1:N adjustment can be achieved on the second output terminal OUT2 of the second gate driving circuit 10_PAM. This results in higher adjustment precision for the second light-emitting control signal Emit2 output by the second gate driving circuit 10_PAM. Here, 1:N refers to the first row of sub-pixels to the Nth row of sub-pixels, where N is an integer greater than 1.

[0144] This disclosure also provides a display device, including the display panel provided in this disclosure. Please refer to... Figure 17 , Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 17 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of the present disclosure. Figure 17 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this disclosure does not impose specific limitations on these. The display device provided in this embodiment has the beneficial effects of the display panel provided in this embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0145] The display device provided in this embodiment of the invention can be a splicing display device, such as a borderless splicing display device. The splicing display device includes at least two of the above-mentioned display panels 100, so as to be suitable for large-screen display devices with display functions.

[0146] At least two display panels 100 may be arranged along the first direction X, or at least two display panels 100 may be arranged along the second direction Y, but are not limited thereto, and the embodiments of the present invention do not make specific limitations in this regard.

[0147] The display device 1000 provided in this embodiment of the invention can be Figure 17 The phone shown can also be Figure 18 The splicing display device shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, etc. The embodiments disclosed herein do not impose any special limitations on this.

[0148] The embodiments described above in this disclosure are not exhaustive and do not limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this disclosure, thereby enabling those skilled in the art to make good use of this disclosure and modifications based on it. This disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A gate drive circuit characterized by comprising: The shift register comprises a plurality of shift registers in cascade, and the shift register comprises an input module, an output module, a first control module, a second control module and a third control module. The input module controls the voltage of the first node and the voltage of the second node based on the signals of the trigger signal end and the first clock end. The first control module controls the voltage of the third node based on the signals of the first clock end and the first node. The second control module controls the voltage of the fourth node based on the signals of the first node, the third node, the first power supply end, the second power supply end, the first clock end and the second clock end. The third control module controls the voltage of the second node based on the signals of the first node, the third node, the first power supply end and the second clock end. The output module controls the voltage of the first output end based on the signals of the second node, the fourth node, the first power supply end and the second power supply end.

2. The gate drive circuit according to claim 1, characterized by The second control module comprises a first sub-control module and a second sub-control module. The first sub-control module controls the voltage of the fifth node based on the signals of the third node, the first power supply end, the first clock end and the second clock end. The second sub-control module controls the voltage of the fourth node based on the signals of the first node, the fifth node, the first power supply end and the second power supply end.

3. The gate drive circuit according to claim 2, characterized by The shift register further comprises a pull-up module, which controls the voltage of the first node based on the signals of the fifth node and the first power supply end.

4. The gate drive circuit according to claim 1, characterized by The shift register further comprises a reset module, which controls the voltage of the first node based on the signals of the first power supply end and a reset signal end.

5. The gate drive circuit according to claim 1, characterized by The input module comprises a first sub-input module and a second sub-input module. The first sub-input module controls the voltage of the second node based on the signals of the trigger signal end and the first clock end. The second sub-input module controls the voltage of the first node based on the signals of the trigger signal end and the first clock end.

6. The gate drive circuit according to claim 5, characterized by The first sub-input module comprises a first transistor, a first electrode of the first transistor is electrically connected with the trigger signal end, a second electrode of the first transistor is electrically connected with the second node, and a gate electrode of the first transistor is electrically connected with the first clock end. The second sub-input module comprises a second transistor, a first electrode of the second transistor is electrically connected with the trigger signal end, a second electrode of the second transistor is electrically connected with the first node, and a gate electrode of the second transistor is electrically connected with the first clock end.

7. The gate drive circuit according to claim 1, wherein The first control module comprises a third transistor and a fourth transistor. A first electrode of the third transistor is electrically connected with the first clock end, a second electrode of the third transistor is electrically connected with the third node, and a gate electrode of the third transistor is electrically connected with the first node. A first electrode and a gate electrode of the fourth transistor are electrically connected with the first clock end, and a second electrode of the fourth transistor is electrically connected with the third node.

8. The gate drive circuit according to claim 1, characterized by The third control module comprises a fifth transistor, a sixth transistor, a seventh transistor and a first capacitor. The first electrode and the gate electrode of the fifth transistor are electrically connected with the sixth node, and the second electrode of the fifth transistor is electrically connected with the second node; The first electrode of the sixth transistor is electrically connected with the first power supply end, the second electrode of the sixth transistor is electrically connected with the first electrode of the first capacitor, and the gate electrode of the sixth transistor is electrically connected with the third node; The first electrode of the seventh transistor is electrically connected with the second clock end, the second electrode of the seventh transistor is electrically connected with the first electrode of the first capacitor, and the gate electrode of the seventh transistor is electrically connected with the sixth node; The second electrode of the first capacitor is electrically connected with the sixth node, and the sixth node is electrically connected with the first node.

9. The gate drive circuit according to claim 8, characterized in that The sixth node is electrically connected with the first node through an eighth transistor, and the gate electrode of the eighth transistor is electrically connected with the second power supply end.

10. The gate drive circuit according to claim 2, characterized by The first sub-control module comprises a ninth transistor, a tenth transistor and a second capacitor; The first electrode of the ninth transistor is electrically connected with the second clock end, the second electrode of the ninth transistor is electrically connected with the fifth node, and the gate electrode of the ninth transistor is electrically connected with the third node; The first electrode of the tenth transistor is electrically connected with the first power supply end, the second electrode of the tenth transistor is electrically connected with the fifth node, and the gate electrode of the tenth transistor is electrically connected with the first clock end; The first electrode of the second capacitor is electrically connected with the third node, and the second electrode of the second capacitor is electrically connected with the fifth node.

11. The gate drive circuit according to claim 2, characterized by The second sub-control module comprises an eleventh transistor and a twelfth transistor; The first electrode of the eleventh transistor is electrically connected with the second power supply end, the second electrode of the eleventh transistor is electrically connected with the fourth node, and the gate electrode of the eleventh transistor is electrically connected with the fifth node; The first electrode of the twelfth transistor is electrically connected with the first power supply end, the second electrode of the twelfth transistor is electrically connected with the fourth node, and the gate electrode of the twelfth transistor is electrically connected with the first node.

12. The gate drive circuit according to claim 1, characterized by The output module comprises a thirteenth transistor, a fourteenth transistor, a third capacitor and a fourth capacitor; The first electrode of the thirteenth transistor is electrically connected with the first power supply end, the second electrode of the thirteenth transistor is electrically connected with the first output end, and the gate electrode of the thirteenth transistor is electrically connected with the fourth node; The first electrode of the fourteenth transistor is electrically connected with the second power supply end, the second electrode of the fourteenth transistor is electrically connected with the first output end, and the gate electrode of the fourteenth transistor is electrically connected with the second node; The third capacitor is electrically connected between the first power supply end and the fourth node; The fourth capacitor is electrically connected between the second node and the first output end.

13. The gate drive circuit according to claim 3, characterized by The pull-up module comprises a fifteenth transistor, the first electrode of the fifteenth transistor is electrically connected with the first power supply end, the second electrode of the fifteenth transistor is electrically connected with the first node, and the gate electrode of the fifteenth transistor is electrically connected with the fifth node.

14. The gate drive circuit according to claim 4, characterized by The reset module comprises a sixteenth transistor, a first electrode of the sixteenth transistor is electrically connected with the first power supply end, a second electrode of the sixteenth transistor is electrically connected with the first node, and a gate electrode of the sixteenth transistor is electrically connected with the reset signal end.

15. The gate drive circuit of claim 1, wherein The shift register further comprises: The gating module controls the voltage of the second output end based on signals of the first output end, the second power supply end, the fourth node, a third power supply end and a start signal end.

16. The gate drive circuit of claim 15, wherein, The gating module comprises a seventeenth transistor, an eighteenth transistor, a fifth capacitor and a sixth capacitor; a first electrode of the seventeenth transistor is electrically connected with the third power supply end, a second electrode of the seventeenth transistor is electrically connected with the second output end, and a gate electrode of the seventeenth transistor is electrically connected with the fourth node; a first electrode of the eighteenth transistor is electrically connected with the start signal end, a second electrode of the eighteenth transistor is electrically connected with the second output end, and a gate electrode of the eighteenth transistor is electrically connected with the first output end; the fifth capacitor is electrically connected between the first output end and the second power supply end; the sixth capacitor is electrically connected between the second output end and the gate electrode of the eighteenth transistor.

17. The gate drive circuit of claim 16, wherein, The gating module further comprises a nineteenth transistor, the gate electrode of the eighteenth transistor is electrically connected with the first output end through the nineteenth transistor, and a gate electrode of the nineteenth transistor is electrically connected with the second power supply end.

18. The gate drive circuit according to claim 16, wherein, a channel width-length ratio of the seventeenth transistor is greater than a channel width-length ratio of a transistor in the output module; and / or, a channel width-length ratio of the eighteenth transistor is greater than a channel width-length ratio of a transistor in the output module.

19. A display panel, characterized by comprises: a sub-pixel; and the gate drive circuit according to any one of claims 1-18, which is electrically connected with the sub-pixel.

20. The display panel of claim 19, wherein, The sub-pixel comprises a pulse amplitude modulation module and a pulse width modulation module; The gate drive circuit comprises a first gate drive circuit, a second gate drive circuit and a third gate drive circuit, the first gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 14, the second gate drive circuit and the third gate drive circuit comprise the gate drive circuit according to any one of claims 15 to 18; the second gate drive circuit is electrically connected with the pulse amplitude modulation module, and the first gate drive circuit and the third gate drive circuit are electrically connected with the pulse width modulation module; signals of a start signal end of the second gate drive circuit and a start signal end of the third gate drive circuit are different in time sequence.

21. A display device comprising: comprises the display panel according to claim 19 or 20.

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